11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 16ef289982SUlf Hansson #include <linux/io.h> 171c6a0718SPierre Ossman #include <linux/interrupt.h> 18613b152cSRussell King #include <linux/kernel.h> 19000bc9d5SLee Jones #include <linux/slab.h> 201c6a0718SPierre Ossman #include <linux/delay.h> 211c6a0718SPierre Ossman #include <linux/err.h> 221c6a0718SPierre Ossman #include <linux/highmem.h> 23019a5f56SNicolas Pitre #include <linux/log2.h> 2470be208fSUlf Hansson #include <linux/mmc/pm.h> 251c6a0718SPierre Ossman #include <linux/mmc/host.h> 2634177802SLinus Walleij #include <linux/mmc/card.h> 27d2762090SUlf Hansson #include <linux/mmc/slot-gpio.h> 281c6a0718SPierre Ossman #include <linux/amba/bus.h> 291c6a0718SPierre Ossman #include <linux/clk.h> 30bd6dee6fSJens Axboe #include <linux/scatterlist.h> 319ef986a6SLinus Walleij #include <linux/of.h> 3234e84f39SLinus Walleij #include <linux/regulator/consumer.h> 33c8ebae37SRussell King #include <linux/dmaengine.h> 34c8ebae37SRussell King #include <linux/dma-mapping.h> 35c8ebae37SRussell King #include <linux/amba/mmci.h> 361c3be369SRussell King #include <linux/pm_runtime.h> 37258aea76SViresh Kumar #include <linux/types.h> 38a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 391c6a0718SPierre Ossman 401c6a0718SPierre Ossman #include <asm/div64.h> 411c6a0718SPierre Ossman #include <asm/io.h> 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #include "mmci.h" 449cb15142SSrinivas Kandagatla #include "mmci_qcom_dml.h" 451c6a0718SPierre Ossman 461c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 471c6a0718SPierre Ossman 481c6a0718SPierre Ossman static unsigned int fmax = 515633; 491c6a0718SPierre Ossman 504956e109SRabin Vincent static struct variant_data variant_arm = { 518301bb68SRabin Vincent .fifosize = 16 * 4, 528301bb68SRabin Vincent .fifohalfsize = 8 * 4, 5308458ef6SRabin Vincent .datalength_bits = 16, 547d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 55dc6500bfSSrinivas Kandagatla .f_max = 100000000, 567878289bSUlf Hansson .reversed_irq_handling = true, 576ea9cdf3SPatrice Chotard .mmcimask1 = true, 587f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 5911dfb970SPatrice Chotard .opendrain = MCI_ROD, 604956e109SRabin Vincent }; 614956e109SRabin Vincent 62768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 63768fbc18SPawel Moll .fifosize = 128 * 4, 64768fbc18SPawel Moll .fifohalfsize = 64 * 4, 65768fbc18SPawel Moll .datalength_bits = 16, 667d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 67dc6500bfSSrinivas Kandagatla .f_max = 100000000, 686ea9cdf3SPatrice Chotard .mmcimask1 = true, 697f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 7011dfb970SPatrice Chotard .opendrain = MCI_ROD, 71768fbc18SPawel Moll }; 72768fbc18SPawel Moll 733a37298aSPawel Moll static struct variant_data variant_arm_extended_fifo_hwfc = { 743a37298aSPawel Moll .fifosize = 128 * 4, 753a37298aSPawel Moll .fifohalfsize = 64 * 4, 763a37298aSPawel Moll .clkreg_enable = MCI_ARM_HWFCEN, 773a37298aSPawel Moll .datalength_bits = 16, 783a37298aSPawel Moll .pwrreg_powerup = MCI_PWR_UP, 79dc6500bfSSrinivas Kandagatla .f_max = 100000000, 806ea9cdf3SPatrice Chotard .mmcimask1 = true, 817f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 8211dfb970SPatrice Chotard .opendrain = MCI_ROD, 833a37298aSPawel Moll }; 843a37298aSPawel Moll 854956e109SRabin Vincent static struct variant_data variant_u300 = { 868301bb68SRabin Vincent .fifosize = 16 * 4, 878301bb68SRabin Vincent .fifohalfsize = 8 * 4, 8849ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 89e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 9008458ef6SRabin Vincent .datalength_bits = 16, 915db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 92c7354133SSrinivas Kandagatla .st_sdio = true, 937d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 94dc6500bfSSrinivas Kandagatla .f_max = 100000000, 954d1a3a0dSUlf Hansson .signal_direction = true, 96f4670daeSUlf Hansson .pwrreg_clkgate = true, 971ff44433SUlf Hansson .pwrreg_nopower = true, 986ea9cdf3SPatrice Chotard .mmcimask1 = true, 997f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 10011dfb970SPatrice Chotard .opendrain = MCI_OD, 1014956e109SRabin Vincent }; 1024956e109SRabin Vincent 10334fd4213SLinus Walleij static struct variant_data variant_nomadik = { 10434fd4213SLinus Walleij .fifosize = 16 * 4, 10534fd4213SLinus Walleij .fifohalfsize = 8 * 4, 10634fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 107f5abc767SLinus Walleij .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 10834fd4213SLinus Walleij .datalength_bits = 24, 1095db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 110c7354133SSrinivas Kandagatla .st_sdio = true, 11134fd4213SLinus Walleij .st_clkdiv = true, 11234fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 113dc6500bfSSrinivas Kandagatla .f_max = 100000000, 11434fd4213SLinus Walleij .signal_direction = true, 115f4670daeSUlf Hansson .pwrreg_clkgate = true, 1161ff44433SUlf Hansson .pwrreg_nopower = true, 1176ea9cdf3SPatrice Chotard .mmcimask1 = true, 1187f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 11911dfb970SPatrice Chotard .opendrain = MCI_OD, 12034fd4213SLinus Walleij }; 12134fd4213SLinus Walleij 1224956e109SRabin Vincent static struct variant_data variant_ux500 = { 1238301bb68SRabin Vincent .fifosize = 30 * 4, 1248301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1254956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 12649ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 127e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 128e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 12908458ef6SRabin Vincent .datalength_bits = 24, 1305db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 131c7354133SSrinivas Kandagatla .st_sdio = true, 132b70a67f9SLinus Walleij .st_clkdiv = true, 1337d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 134dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1354d1a3a0dSUlf Hansson .signal_direction = true, 136f4670daeSUlf Hansson .pwrreg_clkgate = true, 13701259620SUlf Hansson .busy_detect = true, 13849adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 13949adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 14049adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 1411ff44433SUlf Hansson .pwrreg_nopower = true, 1426ea9cdf3SPatrice Chotard .mmcimask1 = true, 1437f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 14411dfb970SPatrice Chotard .opendrain = MCI_OD, 1454956e109SRabin Vincent }; 146b70a67f9SLinus Walleij 1471784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1481784b157SPhilippe Langlais .fifosize = 30 * 4, 1491784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1501784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1511784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 152e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 153e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 1545db3eee7SLinus Walleij .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 1551784b157SPhilippe Langlais .datalength_bits = 24, 1565db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 157c7354133SSrinivas Kandagatla .st_sdio = true, 1581784b157SPhilippe Langlais .st_clkdiv = true, 1591784b157SPhilippe Langlais .blksz_datactrl16 = true, 1607d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 161dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1624d1a3a0dSUlf Hansson .signal_direction = true, 163f4670daeSUlf Hansson .pwrreg_clkgate = true, 16401259620SUlf Hansson .busy_detect = true, 16549adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 16649adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 16749adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 1681ff44433SUlf Hansson .pwrreg_nopower = true, 1696ea9cdf3SPatrice Chotard .mmcimask1 = true, 1707f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 17111dfb970SPatrice Chotard .opendrain = MCI_OD, 1721784b157SPhilippe Langlais }; 1731784b157SPhilippe Langlais 1742a9d6c80SPatrice Chotard static struct variant_data variant_stm32 = { 1752a9d6c80SPatrice Chotard .fifosize = 32 * 4, 1762a9d6c80SPatrice Chotard .fifohalfsize = 8 * 4, 1772a9d6c80SPatrice Chotard .clkreg = MCI_CLK_ENABLE, 1782a9d6c80SPatrice Chotard .clkreg_enable = MCI_ST_UX500_HWFCEN, 1792a9d6c80SPatrice Chotard .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 1802a9d6c80SPatrice Chotard .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 1812a9d6c80SPatrice Chotard .datalength_bits = 24, 1822a9d6c80SPatrice Chotard .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 1832a9d6c80SPatrice Chotard .st_sdio = true, 1842a9d6c80SPatrice Chotard .st_clkdiv = true, 1852a9d6c80SPatrice Chotard .pwrreg_powerup = MCI_PWR_ON, 1862a9d6c80SPatrice Chotard .f_max = 48000000, 1872a9d6c80SPatrice Chotard .pwrreg_clkgate = true, 1882a9d6c80SPatrice Chotard .pwrreg_nopower = true, 1892a9d6c80SPatrice Chotard }; 1902a9d6c80SPatrice Chotard 19155b604aeSSrinivas Kandagatla static struct variant_data variant_qcom = { 19255b604aeSSrinivas Kandagatla .fifosize = 16 * 4, 19355b604aeSSrinivas Kandagatla .fifohalfsize = 8 * 4, 19455b604aeSSrinivas Kandagatla .clkreg = MCI_CLK_ENABLE, 19555b604aeSSrinivas Kandagatla .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 19655b604aeSSrinivas Kandagatla MCI_QCOM_CLK_SELECT_IN_FBCLK, 19755b604aeSSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 19855b604aeSSrinivas Kandagatla .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 1995db3eee7SLinus Walleij .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 20055b604aeSSrinivas Kandagatla .blksz_datactrl4 = true, 20155b604aeSSrinivas Kandagatla .datalength_bits = 24, 20255b604aeSSrinivas Kandagatla .pwrreg_powerup = MCI_PWR_UP, 20355b604aeSSrinivas Kandagatla .f_max = 208000000, 20455b604aeSSrinivas Kandagatla .explicit_mclk_control = true, 20555b604aeSSrinivas Kandagatla .qcom_fifo = true, 2069cb15142SSrinivas Kandagatla .qcom_dml = true, 2076ea9cdf3SPatrice Chotard .mmcimask1 = true, 2087f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 20911dfb970SPatrice Chotard .opendrain = MCI_ROD, 21029aba07aSUlf Hansson .init = qcom_variant_init, 21155b604aeSSrinivas Kandagatla }; 21255b604aeSSrinivas Kandagatla 21349adc0caSLinus Walleij /* Busy detection for the ST Micro variant */ 21401259620SUlf Hansson static int mmci_card_busy(struct mmc_host *mmc) 21501259620SUlf Hansson { 21601259620SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 21701259620SUlf Hansson unsigned long flags; 21801259620SUlf Hansson int busy = 0; 21901259620SUlf Hansson 22001259620SUlf Hansson spin_lock_irqsave(&host->lock, flags); 22149adc0caSLinus Walleij if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 22201259620SUlf Hansson busy = 1; 22301259620SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 22401259620SUlf Hansson 22501259620SUlf Hansson return busy; 22601259620SUlf Hansson } 22701259620SUlf Hansson 228a6a6464aSLinus Walleij /* 229653a761eSUlf Hansson * Validate mmc prerequisites 230653a761eSUlf Hansson */ 231653a761eSUlf Hansson static int mmci_validate_data(struct mmci_host *host, 232653a761eSUlf Hansson struct mmc_data *data) 233653a761eSUlf Hansson { 234653a761eSUlf Hansson if (!data) 235653a761eSUlf Hansson return 0; 236653a761eSUlf Hansson 237653a761eSUlf Hansson if (!is_power_of_2(data->blksz)) { 238653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), 239653a761eSUlf Hansson "unsupported block size (%d bytes)\n", data->blksz); 240653a761eSUlf Hansson return -EINVAL; 241653a761eSUlf Hansson } 242653a761eSUlf Hansson 243653a761eSUlf Hansson return 0; 244653a761eSUlf Hansson } 245653a761eSUlf Hansson 246f829c042SUlf Hansson static void mmci_reg_delay(struct mmci_host *host) 247f829c042SUlf Hansson { 248f829c042SUlf Hansson /* 249f829c042SUlf Hansson * According to the spec, at least three feedback clock cycles 250f829c042SUlf Hansson * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 251f829c042SUlf Hansson * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 252f829c042SUlf Hansson * Worst delay time during card init is at 100 kHz => 30 us. 253f829c042SUlf Hansson * Worst delay time when up and running is at 25 MHz => 120 ns. 254f829c042SUlf Hansson */ 255f829c042SUlf Hansson if (host->cclk < 25000000) 256f829c042SUlf Hansson udelay(30); 257f829c042SUlf Hansson else 258f829c042SUlf Hansson ndelay(120); 259f829c042SUlf Hansson } 260f829c042SUlf Hansson 261653a761eSUlf Hansson /* 262a6a6464aSLinus Walleij * This must be called with host->lock held 263a6a6464aSLinus Walleij */ 2647437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 2657437cfa5SUlf Hansson { 2667437cfa5SUlf Hansson if (host->clk_reg != clk) { 2677437cfa5SUlf Hansson host->clk_reg = clk; 2687437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 2697437cfa5SUlf Hansson } 2707437cfa5SUlf Hansson } 2717437cfa5SUlf Hansson 2727437cfa5SUlf Hansson /* 2737437cfa5SUlf Hansson * This must be called with host->lock held 2747437cfa5SUlf Hansson */ 2757437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 2767437cfa5SUlf Hansson { 2777437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 2787437cfa5SUlf Hansson host->pwr_reg = pwr; 2797437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 2807437cfa5SUlf Hansson } 2817437cfa5SUlf Hansson } 2827437cfa5SUlf Hansson 2837437cfa5SUlf Hansson /* 2847437cfa5SUlf Hansson * This must be called with host->lock held 2857437cfa5SUlf Hansson */ 2869cc639a2SUlf Hansson static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 2879cc639a2SUlf Hansson { 28849adc0caSLinus Walleij /* Keep busy mode in DPSM if enabled */ 28949adc0caSLinus Walleij datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 29001259620SUlf Hansson 2919cc639a2SUlf Hansson if (host->datactrl_reg != datactrl) { 2929cc639a2SUlf Hansson host->datactrl_reg = datactrl; 2939cc639a2SUlf Hansson writel(datactrl, host->base + MMCIDATACTRL); 2949cc639a2SUlf Hansson } 2959cc639a2SUlf Hansson } 2969cc639a2SUlf Hansson 2979cc639a2SUlf Hansson /* 2989cc639a2SUlf Hansson * This must be called with host->lock held 2999cc639a2SUlf Hansson */ 300a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 301a6a6464aSLinus Walleij { 3024956e109SRabin Vincent struct variant_data *variant = host->variant; 3034956e109SRabin Vincent u32 clk = variant->clkreg; 304a6a6464aSLinus Walleij 305c58a8509SUlf Hansson /* Make sure cclk reflects the current calculated clock */ 306c58a8509SUlf Hansson host->cclk = 0; 307c58a8509SUlf Hansson 308a6a6464aSLinus Walleij if (desired) { 3093f4e6f7bSSrinivas Kandagatla if (variant->explicit_mclk_control) { 3103f4e6f7bSSrinivas Kandagatla host->cclk = host->mclk; 3113f4e6f7bSSrinivas Kandagatla } else if (desired >= host->mclk) { 312a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 313399bc486SLinus Walleij if (variant->st_clkdiv) 314399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 315a6a6464aSLinus Walleij host->cclk = host->mclk; 316b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 317b70a67f9SLinus Walleij /* 318b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 319b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 320b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 321b70a67f9SLinus Walleij * frequency 322b70a67f9SLinus Walleij */ 323b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 324b70a67f9SLinus Walleij if (clk >= 256) 325b70a67f9SLinus Walleij clk = 255; 326b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 327a6a6464aSLinus Walleij } else { 328b70a67f9SLinus Walleij /* 329b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 330b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 331b70a67f9SLinus Walleij */ 332a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 333a6a6464aSLinus Walleij if (clk >= 256) 334a6a6464aSLinus Walleij clk = 255; 335a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 336a6a6464aSLinus Walleij } 3374380c14fSRabin Vincent 3384380c14fSRabin Vincent clk |= variant->clkreg_enable; 339a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 340a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 341a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 342a6a6464aSLinus Walleij } 343a6a6464aSLinus Walleij 344c58a8509SUlf Hansson /* Set actual clock for debug */ 345c58a8509SUlf Hansson host->mmc->actual_clock = host->cclk; 346c58a8509SUlf Hansson 3479e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 348771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 349771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 350e1412d85SSrinivas Kandagatla clk |= variant->clkreg_8bit_bus_enable; 3519e6c82cdSLinus Walleij 3526dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 3536dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 354e8740644SSrinivas Kandagatla clk |= variant->clkreg_neg_edge_enable; 3556dbb6ee0SUlf Hansson 3567437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 357a6a6464aSLinus Walleij } 358a6a6464aSLinus Walleij 3591c6a0718SPierre Ossman static void 3601c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 3611c6a0718SPierre Ossman { 3621c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 3631c6a0718SPierre Ossman 3641c6a0718SPierre Ossman BUG_ON(host->data); 3651c6a0718SPierre Ossman 3661c6a0718SPierre Ossman host->mrq = NULL; 3671c6a0718SPierre Ossman host->cmd = NULL; 3681c6a0718SPierre Ossman 3691c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 3701c6a0718SPierre Ossman } 3711c6a0718SPierre Ossman 3722686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 3732686b4b4SLinus Walleij { 3742686b4b4SLinus Walleij void __iomem *base = host->base; 3756ea9cdf3SPatrice Chotard struct variant_data *variant = host->variant; 3762686b4b4SLinus Walleij 3772686b4b4SLinus Walleij if (host->singleirq) { 3782686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 3792686b4b4SLinus Walleij 3802686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 3812686b4b4SLinus Walleij mask0 |= mask; 3822686b4b4SLinus Walleij 3832686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 3842686b4b4SLinus Walleij } 3852686b4b4SLinus Walleij 3866ea9cdf3SPatrice Chotard if (variant->mmcimask1) 3872686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 3886ea9cdf3SPatrice Chotard 3896ea9cdf3SPatrice Chotard host->mask1_reg = mask; 3902686b4b4SLinus Walleij } 3912686b4b4SLinus Walleij 3921c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 3931c6a0718SPierre Ossman { 3949cc639a2SUlf Hansson mmci_write_datactrlreg(host, 0); 3952686b4b4SLinus Walleij mmci_set_mask1(host, 0); 3961c6a0718SPierre Ossman host->data = NULL; 3971c6a0718SPierre Ossman } 3981c6a0718SPierre Ossman 3994ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 4004ce1d6cbSRabin Vincent { 4014ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 4024ce1d6cbSRabin Vincent 4034ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 4044ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 4054ce1d6cbSRabin Vincent else 4064ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 4074ce1d6cbSRabin Vincent 4084ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 4094ce1d6cbSRabin Vincent } 4104ce1d6cbSRabin Vincent 411c8ebae37SRussell King /* 412c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 413c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 414c8ebae37SRussell King * no custom DMA interfaces are supported. 415c8ebae37SRussell King */ 416c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 417c3be1efdSBill Pemberton static void mmci_dma_setup(struct mmci_host *host) 418c8ebae37SRussell King { 419c8ebae37SRussell King const char *rxname, *txname; 420c8ebae37SRussell King 4211fd83f0eSLee Jones host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 4221fd83f0eSLee Jones host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 423c8ebae37SRussell King 42458c7ccbfSPer Forlin /* initialize pre request cookie */ 42558c7ccbfSPer Forlin host->next_data.cookie = 1; 42658c7ccbfSPer Forlin 4271fd83f0eSLee Jones /* 4281fd83f0eSLee Jones * If only an RX channel is specified, the driver will 4291fd83f0eSLee Jones * attempt to use it bidirectionally, however if it is 4301fd83f0eSLee Jones * is specified but cannot be located, DMA will be disabled. 4311fd83f0eSLee Jones */ 4321fd83f0eSLee Jones if (host->dma_rx_channel && !host->dma_tx_channel) 4331fd83f0eSLee Jones host->dma_tx_channel = host->dma_rx_channel; 434c8ebae37SRussell King 435c8ebae37SRussell King if (host->dma_rx_channel) 436c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 437c8ebae37SRussell King else 438c8ebae37SRussell King rxname = "none"; 439c8ebae37SRussell King 440c8ebae37SRussell King if (host->dma_tx_channel) 441c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 442c8ebae37SRussell King else 443c8ebae37SRussell King txname = "none"; 444c8ebae37SRussell King 445c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 446c8ebae37SRussell King rxname, txname); 447c8ebae37SRussell King 448c8ebae37SRussell King /* 449c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 450c8ebae37SRussell King * the parameters of the DMA engine device. 451c8ebae37SRussell King */ 452c8ebae37SRussell King if (host->dma_tx_channel) { 453c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 454c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 455c8ebae37SRussell King 456c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 457c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 458c8ebae37SRussell King } 459c8ebae37SRussell King if (host->dma_rx_channel) { 460c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 461c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 462c8ebae37SRussell King 463c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 464c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 465c8ebae37SRussell King } 4669cb15142SSrinivas Kandagatla 46729aba07aSUlf Hansson if (host->ops && host->ops->dma_setup) 46829aba07aSUlf Hansson host->ops->dma_setup(host); 469c8ebae37SRussell King } 470c8ebae37SRussell King 471c8ebae37SRussell King /* 4726e0ee714SBill Pemberton * This is used in or so inline it 473c8ebae37SRussell King * so it can be discarded. 474c8ebae37SRussell King */ 475c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 476c8ebae37SRussell King { 477c8ebae37SRussell King if (host->dma_rx_channel) 478c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 4798c3a05b4SUlf Hansson if (host->dma_tx_channel) 480c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 481c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 482c8ebae37SRussell King } 483c8ebae37SRussell King 484653a761eSUlf Hansson static void mmci_dma_data_error(struct mmci_host *host) 485653a761eSUlf Hansson { 486653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 487653a761eSUlf Hansson dmaengine_terminate_all(host->dma_current); 488e13934bdSLinus Walleij host->dma_in_progress = false; 489653a761eSUlf Hansson host->dma_current = NULL; 490653a761eSUlf Hansson host->dma_desc_current = NULL; 491653a761eSUlf Hansson host->data->host_cookie = 0; 492653a761eSUlf Hansson } 493653a761eSUlf Hansson 494c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 495c8ebae37SRussell King { 496653a761eSUlf Hansson struct dma_chan *chan; 497653a761eSUlf Hansson 498feeef096SHeiner Kallweit if (data->flags & MMC_DATA_READ) 499653a761eSUlf Hansson chan = host->dma_rx_channel; 500feeef096SHeiner Kallweit else 501653a761eSUlf Hansson chan = host->dma_tx_channel; 502653a761eSUlf Hansson 503feeef096SHeiner Kallweit dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 504feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 505653a761eSUlf Hansson } 506653a761eSUlf Hansson 507653a761eSUlf Hansson static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 508653a761eSUlf Hansson { 509c8ebae37SRussell King u32 status; 510c8ebae37SRussell King int i; 511c8ebae37SRussell King 512c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 513c8ebae37SRussell King for (i = 0; ; i++) { 514c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 515c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 516c8ebae37SRussell King break; 517c8ebae37SRussell King udelay(10); 518c8ebae37SRussell King } 519c8ebae37SRussell King 520c8ebae37SRussell King /* 521c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 522c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 523c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 524c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 525c8ebae37SRussell King */ 526c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 527653a761eSUlf Hansson mmci_dma_data_error(host); 528c8ebae37SRussell King if (!data->error) 529c8ebae37SRussell King data->error = -EIO; 530c8ebae37SRussell King } 531c8ebae37SRussell King 53258c7ccbfSPer Forlin if (!data->host_cookie) 533653a761eSUlf Hansson mmci_dma_unmap(host, data); 534c8ebae37SRussell King 535c8ebae37SRussell King /* 536c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 537c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 538c8ebae37SRussell King */ 539c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 540c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 541c8ebae37SRussell King mmci_dma_release(host); 542c8ebae37SRussell King } 543653a761eSUlf Hansson 544e13934bdSLinus Walleij host->dma_in_progress = false; 545653a761eSUlf Hansson host->dma_current = NULL; 546653a761eSUlf Hansson host->dma_desc_current = NULL; 547c8ebae37SRussell King } 548c8ebae37SRussell King 549653a761eSUlf Hansson /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 550653a761eSUlf Hansson static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 551653a761eSUlf Hansson struct dma_chan **dma_chan, 552653a761eSUlf Hansson struct dma_async_tx_descriptor **dma_desc) 553c8ebae37SRussell King { 554c8ebae37SRussell King struct variant_data *variant = host->variant; 555c8ebae37SRussell King struct dma_slave_config conf = { 556c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 557c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 558c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 559c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 560c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 561c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 562258aea76SViresh Kumar .device_fc = false, 563c8ebae37SRussell King }; 564c8ebae37SRussell King struct dma_chan *chan; 565c8ebae37SRussell King struct dma_device *device; 566c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 567c8ebae37SRussell King int nr_sg; 5689cb15142SSrinivas Kandagatla unsigned long flags = DMA_CTRL_ACK; 569c8ebae37SRussell King 570c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 57105f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 572c8ebae37SRussell King chan = host->dma_rx_channel; 573c8ebae37SRussell King } else { 57405f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 575c8ebae37SRussell King chan = host->dma_tx_channel; 576c8ebae37SRussell King } 577c8ebae37SRussell King 578c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 579c8ebae37SRussell King if (!chan) 580c8ebae37SRussell King return -EINVAL; 581c8ebae37SRussell King 582c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 58358c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 584c8ebae37SRussell King return -EINVAL; 585c8ebae37SRussell King 586c8ebae37SRussell King device = chan->device; 587feeef096SHeiner Kallweit nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 588feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 589c8ebae37SRussell King if (nr_sg == 0) 590c8ebae37SRussell King return -EINVAL; 591c8ebae37SRussell King 5929cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 5939cb15142SSrinivas Kandagatla flags |= DMA_PREP_INTERRUPT; 5949cb15142SSrinivas Kandagatla 595c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 59616052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 5979cb15142SSrinivas Kandagatla conf.direction, flags); 598c8ebae37SRussell King if (!desc) 599c8ebae37SRussell King goto unmap_exit; 600c8ebae37SRussell King 601653a761eSUlf Hansson *dma_chan = chan; 602653a761eSUlf Hansson *dma_desc = desc; 603c8ebae37SRussell King 60458c7ccbfSPer Forlin return 0; 60558c7ccbfSPer Forlin 60658c7ccbfSPer Forlin unmap_exit: 607feeef096SHeiner Kallweit dma_unmap_sg(device->dev, data->sg, data->sg_len, 608feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 60958c7ccbfSPer Forlin return -ENOMEM; 61058c7ccbfSPer Forlin } 61158c7ccbfSPer Forlin 612653a761eSUlf Hansson static inline int mmci_dma_prep_data(struct mmci_host *host, 613653a761eSUlf Hansson struct mmc_data *data) 614653a761eSUlf Hansson { 615653a761eSUlf Hansson /* Check if next job is already prepared. */ 616653a761eSUlf Hansson if (host->dma_current && host->dma_desc_current) 617653a761eSUlf Hansson return 0; 618653a761eSUlf Hansson 619653a761eSUlf Hansson /* No job were prepared thus do it now. */ 620653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &host->dma_current, 621653a761eSUlf Hansson &host->dma_desc_current); 622653a761eSUlf Hansson } 623653a761eSUlf Hansson 624653a761eSUlf Hansson static inline int mmci_dma_prep_next(struct mmci_host *host, 625653a761eSUlf Hansson struct mmc_data *data) 626653a761eSUlf Hansson { 627653a761eSUlf Hansson struct mmci_host_next *nd = &host->next_data; 628653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 629653a761eSUlf Hansson } 630653a761eSUlf Hansson 63158c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 63258c7ccbfSPer Forlin { 63358c7ccbfSPer Forlin int ret; 63458c7ccbfSPer Forlin struct mmc_data *data = host->data; 63558c7ccbfSPer Forlin 636653a761eSUlf Hansson ret = mmci_dma_prep_data(host, host->data); 63758c7ccbfSPer Forlin if (ret) 63858c7ccbfSPer Forlin return ret; 63958c7ccbfSPer Forlin 64058c7ccbfSPer Forlin /* Okay, go for it. */ 641c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 642c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 643c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 644e13934bdSLinus Walleij host->dma_in_progress = true; 64558c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 64658c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 647c8ebae37SRussell King 6489cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 6499cb15142SSrinivas Kandagatla dml_start_xfer(host, data); 6509cb15142SSrinivas Kandagatla 651c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 652c8ebae37SRussell King 653c8ebae37SRussell King /* Trigger the DMA transfer */ 6549cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 655c8ebae37SRussell King 656c8ebae37SRussell King /* 657c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 658c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 659c8ebae37SRussell King * call mmci_data_end() 660c8ebae37SRussell King */ 661c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 662c8ebae37SRussell King host->base + MMCIMASK0); 663c8ebae37SRussell King return 0; 664c8ebae37SRussell King } 66558c7ccbfSPer Forlin 66658c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 66758c7ccbfSPer Forlin { 66858c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 66958c7ccbfSPer Forlin 670653a761eSUlf Hansson WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 671653a761eSUlf Hansson WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 67258c7ccbfSPer Forlin 67358c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 67458c7ccbfSPer Forlin host->dma_current = next->dma_chan; 67558c7ccbfSPer Forlin next->dma_desc = NULL; 67658c7ccbfSPer Forlin next->dma_chan = NULL; 67758c7ccbfSPer Forlin } 67858c7ccbfSPer Forlin 679d3c6aac3SLinus Walleij static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 68058c7ccbfSPer Forlin { 68158c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 68258c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 68358c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 68458c7ccbfSPer Forlin 68558c7ccbfSPer Forlin if (!data) 68658c7ccbfSPer Forlin return; 68758c7ccbfSPer Forlin 688653a761eSUlf Hansson BUG_ON(data->host_cookie); 68958c7ccbfSPer Forlin 690653a761eSUlf Hansson if (mmci_validate_data(host, data)) 691653a761eSUlf Hansson return; 692653a761eSUlf Hansson 693653a761eSUlf Hansson if (!mmci_dma_prep_next(host, data)) 69458c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 69558c7ccbfSPer Forlin } 69658c7ccbfSPer Forlin 69758c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 69858c7ccbfSPer Forlin int err) 69958c7ccbfSPer Forlin { 70058c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 70158c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 70258c7ccbfSPer Forlin 703653a761eSUlf Hansson if (!data || !data->host_cookie) 70458c7ccbfSPer Forlin return; 70558c7ccbfSPer Forlin 706653a761eSUlf Hansson mmci_dma_unmap(host, data); 707653a761eSUlf Hansson 708653a761eSUlf Hansson if (err) { 709653a761eSUlf Hansson struct mmci_host_next *next = &host->next_data; 710653a761eSUlf Hansson struct dma_chan *chan; 711653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) 71258c7ccbfSPer Forlin chan = host->dma_rx_channel; 713653a761eSUlf Hansson else 71458c7ccbfSPer Forlin chan = host->dma_tx_channel; 71558c7ccbfSPer Forlin dmaengine_terminate_all(chan); 716653a761eSUlf Hansson 717b5c16a60SSrinivas Kandagatla if (host->dma_desc_current == next->dma_desc) 718b5c16a60SSrinivas Kandagatla host->dma_desc_current = NULL; 719b5c16a60SSrinivas Kandagatla 720e13934bdSLinus Walleij if (host->dma_current == next->dma_chan) { 721e13934bdSLinus Walleij host->dma_in_progress = false; 722b5c16a60SSrinivas Kandagatla host->dma_current = NULL; 723e13934bdSLinus Walleij } 724b5c16a60SSrinivas Kandagatla 725653a761eSUlf Hansson next->dma_desc = NULL; 726653a761eSUlf Hansson next->dma_chan = NULL; 727b5c16a60SSrinivas Kandagatla data->host_cookie = 0; 72858c7ccbfSPer Forlin } 72958c7ccbfSPer Forlin } 73058c7ccbfSPer Forlin 731c8ebae37SRussell King #else 732c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 73358c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 73458c7ccbfSPer Forlin { 73558c7ccbfSPer Forlin } 736c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 737c8ebae37SRussell King { 738c8ebae37SRussell King } 739c8ebae37SRussell King 740c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 741c8ebae37SRussell King { 742c8ebae37SRussell King } 743c8ebae37SRussell King 744c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 745c8ebae37SRussell King { 746c8ebae37SRussell King } 747c8ebae37SRussell King 748653a761eSUlf Hansson static inline void mmci_dma_finalize(struct mmci_host *host, 749653a761eSUlf Hansson struct mmc_data *data) 750653a761eSUlf Hansson { 751653a761eSUlf Hansson } 752653a761eSUlf Hansson 753c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 754c8ebae37SRussell King { 755c8ebae37SRussell King } 756c8ebae37SRussell King 757c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 758c8ebae37SRussell King { 759c8ebae37SRussell King return -ENOSYS; 760c8ebae37SRussell King } 76158c7ccbfSPer Forlin 76258c7ccbfSPer Forlin #define mmci_pre_request NULL 76358c7ccbfSPer Forlin #define mmci_post_request NULL 76458c7ccbfSPer Forlin 765c8ebae37SRussell King #endif 766c8ebae37SRussell King 7671c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 7681c6a0718SPierre Ossman { 7698301bb68SRabin Vincent struct variant_data *variant = host->variant; 7701c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 7711c6a0718SPierre Ossman unsigned long long clks; 7721c6a0718SPierre Ossman void __iomem *base; 7731c6a0718SPierre Ossman int blksz_bits; 7741c6a0718SPierre Ossman 77564de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 7761c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 7771c6a0718SPierre Ossman 7781c6a0718SPierre Ossman host->data = data; 779528320dbSRabin Vincent host->size = data->blksz * data->blocks; 78051d4375dSRussell King data->bytes_xfered = 0; 7811c6a0718SPierre Ossman 7821c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 783c4a35769SSrinivas Kandagatla do_div(clks, NSEC_PER_SEC); 7841c6a0718SPierre Ossman 7851c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 7861c6a0718SPierre Ossman 7871c6a0718SPierre Ossman base = host->base; 7881c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 7891c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 7901c6a0718SPierre Ossman 7911c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 7921c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 7931c6a0718SPierre Ossman 7941784b157SPhilippe Langlais if (variant->blksz_datactrl16) 7951784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 796ff783233SSrinivas Kandagatla else if (variant->blksz_datactrl4) 797ff783233SSrinivas Kandagatla datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 7981784b157SPhilippe Langlais else 7991c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 800c8ebae37SRussell King 801c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 8021c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 803c8ebae37SRussell King 804c7354133SSrinivas Kandagatla if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 80506c1a121SUlf Hansson u32 clk; 806c7354133SSrinivas Kandagatla 8075df014dfSSrinivas Kandagatla datactrl |= variant->datactrl_mask_sdio; 8087258db7eSUlf Hansson 809c8ebae37SRussell King /* 81070ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 81170ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 81270ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 81370ac0935SUlf Hansson * depends on the rate of MCLK. 81406c1a121SUlf Hansson */ 815c7354133SSrinivas Kandagatla if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 81670ac0935SUlf Hansson (host->size < 8 || 81770ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 81806c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 81906c1a121SUlf Hansson else 82006c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 82106c1a121SUlf Hansson 82206c1a121SUlf Hansson mmci_write_clkreg(host, clk); 82306c1a121SUlf Hansson } 82406c1a121SUlf Hansson 8256dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 8266dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 827e17dca2bSSrinivas Kandagatla datactrl |= variant->datactrl_mask_ddrmode; 8286dbb6ee0SUlf Hansson 82906c1a121SUlf Hansson /* 830c8ebae37SRussell King * Attempt to use DMA operation mode, if this 831c8ebae37SRussell King * should fail, fall back to PIO mode 832c8ebae37SRussell King */ 833c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 834c8ebae37SRussell King return; 835c8ebae37SRussell King 836c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 837c8ebae37SRussell King mmci_init_sg(host, data); 838c8ebae37SRussell King 839c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 8401c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 8411c6a0718SPierre Ossman 8421c6a0718SPierre Ossman /* 843c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 844c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 845c4d877c1SRussell King * is available. 8461c6a0718SPierre Ossman */ 847c4d877c1SRussell King if (host->size < variant->fifohalfsize) 8481c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 8491c6a0718SPierre Ossman } else { 8501c6a0718SPierre Ossman /* 8511c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 8521c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 8531c6a0718SPierre Ossman */ 8541c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 8551c6a0718SPierre Ossman } 8561c6a0718SPierre Ossman 8579cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 8581c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 8592686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 8601c6a0718SPierre Ossman } 8611c6a0718SPierre Ossman 8621c6a0718SPierre Ossman static void 8631c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 8641c6a0718SPierre Ossman { 8651c6a0718SPierre Ossman void __iomem *base = host->base; 8661c6a0718SPierre Ossman 86764de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 8681c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 8691c6a0718SPierre Ossman 8701c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 8711c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 8726adb2a80SSrinivas Kandagatla mmci_reg_delay(host); 8731c6a0718SPierre Ossman } 8741c6a0718SPierre Ossman 8751c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 8761c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 8771c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 8781c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 8791c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 8801c6a0718SPierre Ossman } 8811c6a0718SPierre Ossman if (/*interrupt*/0) 8821c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 8831c6a0718SPierre Ossman 884ae7b0061SSrinivas Kandagatla if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 885ae7b0061SSrinivas Kandagatla c |= host->variant->data_cmd_enable; 886ae7b0061SSrinivas Kandagatla 8871c6a0718SPierre Ossman host->cmd = cmd; 8881c6a0718SPierre Ossman 8891c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 8901c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 8911c6a0718SPierre Ossman } 8921c6a0718SPierre Ossman 8931c6a0718SPierre Ossman static void 8941c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 8951c6a0718SPierre Ossman unsigned int status) 8961c6a0718SPierre Ossman { 8971cb9da50SUlf Hansson /* Make sure we have data to handle */ 8981cb9da50SUlf Hansson if (!data) 8991cb9da50SUlf Hansson return; 9001cb9da50SUlf Hansson 901f20f8f21SLinus Walleij /* First check for errors */ 9027f7b5503SPatrice Chotard if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT | 9037f7b5503SPatrice Chotard host->variant->start_err | 904b63038d6SUlf Hansson MCI_TXUNDERRUN | MCI_RXOVERRUN)) { 9058cb28155SLinus Walleij u32 remain, success; 906f20f8f21SLinus Walleij 907c8ebae37SRussell King /* Terminate the DMA transfer */ 908653a761eSUlf Hansson if (dma_inprogress(host)) { 909c8ebae37SRussell King mmci_dma_data_error(host); 910653a761eSUlf Hansson mmci_dma_unmap(host, data); 911653a761eSUlf Hansson } 912c8ebae37SRussell King 913c8afc9d5SRussell King /* 914c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 915c8afc9d5SRussell King * the data counter gives the number of bytes transferred 916c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 917c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 918c8afc9d5SRussell King * matters for FIFO overruns only. 919c8afc9d5SRussell King */ 920f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 9218cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 9228cb28155SLinus Walleij 923c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 924c8afc9d5SRussell King status, success); 9258cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 9268cb28155SLinus Walleij /* Last block was not successful */ 927c8afc9d5SRussell King success -= 1; 92817b0429dSPierre Ossman data->error = -EILSEQ; 9298cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 93017b0429dSPierre Ossman data->error = -ETIMEDOUT; 931757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 932757df746SLinus Walleij data->error = -ECOMM; 933c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 93417b0429dSPierre Ossman data->error = -EIO; 935c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 936c8afc9d5SRussell King if (success > host->variant->fifosize) 937c8afc9d5SRussell King success -= host->variant->fifosize; 938c8afc9d5SRussell King else 939c8afc9d5SRussell King success = 0; 9408cb28155SLinus Walleij data->error = -EIO; 9414ce1d6cbSRabin Vincent } 94251d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 9431c6a0718SPierre Ossman } 944f20f8f21SLinus Walleij 9458cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 9468cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 947f20f8f21SLinus Walleij 948ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 949c8ebae37SRussell King if (dma_inprogress(host)) 950653a761eSUlf Hansson mmci_dma_finalize(host, data); 9511c6a0718SPierre Ossman mmci_stop_data(host); 9521c6a0718SPierre Ossman 9538cb28155SLinus Walleij if (!data->error) 9548cb28155SLinus Walleij /* The error clause is handled above, success! */ 95551d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 956f20f8f21SLinus Walleij 957024629c6SUlf Hansson if (!data->stop || host->mrq->sbc) { 9581c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 9591c6a0718SPierre Ossman } else { 9601c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 9611c6a0718SPierre Ossman } 9621c6a0718SPierre Ossman } 9631c6a0718SPierre Ossman } 9641c6a0718SPierre Ossman 9651c6a0718SPierre Ossman static void 9661c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 9671c6a0718SPierre Ossman unsigned int status) 9681c6a0718SPierre Ossman { 9691c6a0718SPierre Ossman void __iomem *base = host->base; 97049adc0caSLinus Walleij bool sbc; 971ad82bfeaSUlf Hansson 972ad82bfeaSUlf Hansson if (!cmd) 973ad82bfeaSUlf Hansson return; 974ad82bfeaSUlf Hansson 975ad82bfeaSUlf Hansson sbc = (cmd == host->mrq->sbc); 976ad82bfeaSUlf Hansson 97749adc0caSLinus Walleij /* 97849adc0caSLinus Walleij * We need to be one of these interrupts to be considered worth 97949adc0caSLinus Walleij * handling. Note that we tag on any latent IRQs postponed 98049adc0caSLinus Walleij * due to waiting for busy status. 98149adc0caSLinus Walleij */ 98249adc0caSLinus Walleij if (!((status|host->busy_status) & 98349adc0caSLinus Walleij (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 984ad82bfeaSUlf Hansson return; 9858d94b54dSUlf Hansson 98649adc0caSLinus Walleij /* 98749adc0caSLinus Walleij * ST Micro variant: handle busy detection. 98849adc0caSLinus Walleij */ 98949adc0caSLinus Walleij if (host->variant->busy_detect) { 99049adc0caSLinus Walleij bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 99149adc0caSLinus Walleij 99249adc0caSLinus Walleij /* We are busy with a command, return */ 99349adc0caSLinus Walleij if (host->busy_status && 99449adc0caSLinus Walleij (status & host->variant->busy_detect_flag)) 9958d94b54dSUlf Hansson return; 9968d94b54dSUlf Hansson 99749adc0caSLinus Walleij /* 99849adc0caSLinus Walleij * We were not busy, but we now got a busy response on 99949adc0caSLinus Walleij * something that was not an error, and we double-check 100049adc0caSLinus Walleij * that the special busy status bit is still set before 100149adc0caSLinus Walleij * proceeding. 100249adc0caSLinus Walleij */ 10038d94b54dSUlf Hansson if (!host->busy_status && busy_resp && 10048d94b54dSUlf Hansson !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 100549adc0caSLinus Walleij (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 10065cad24d8SJean-Nicolas Graux 10075cad24d8SJean-Nicolas Graux /* Clear the busy start IRQ */ 10085cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 10095cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 10105cad24d8SJean-Nicolas Graux 10115cad24d8SJean-Nicolas Graux /* Unmask the busy end IRQ */ 101249adc0caSLinus Walleij writel(readl(base + MMCIMASK0) | 101349adc0caSLinus Walleij host->variant->busy_detect_mask, 10148d94b54dSUlf Hansson base + MMCIMASK0); 101549adc0caSLinus Walleij /* 101649adc0caSLinus Walleij * Now cache the last response status code (until 101749adc0caSLinus Walleij * the busy bit goes low), and return. 101849adc0caSLinus Walleij */ 101949adc0caSLinus Walleij host->busy_status = 102049adc0caSLinus Walleij status & (MCI_CMDSENT|MCI_CMDRESPEND); 10218d94b54dSUlf Hansson return; 10228d94b54dSUlf Hansson } 10238d94b54dSUlf Hansson 102449adc0caSLinus Walleij /* 102549adc0caSLinus Walleij * At this point we are not busy with a command, we have 10265cad24d8SJean-Nicolas Graux * not received a new busy request, clear and mask the busy 10275cad24d8SJean-Nicolas Graux * end IRQ and fall through to process the IRQ. 102849adc0caSLinus Walleij */ 10298d94b54dSUlf Hansson if (host->busy_status) { 10305cad24d8SJean-Nicolas Graux 10315cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 10325cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 10335cad24d8SJean-Nicolas Graux 103449adc0caSLinus Walleij writel(readl(base + MMCIMASK0) & 103549adc0caSLinus Walleij ~host->variant->busy_detect_mask, 10368d94b54dSUlf Hansson base + MMCIMASK0); 10378d94b54dSUlf Hansson host->busy_status = 0; 10388d94b54dSUlf Hansson } 103949adc0caSLinus Walleij } 10401c6a0718SPierre Ossman 10411c6a0718SPierre Ossman host->cmd = NULL; 10421c6a0718SPierre Ossman 10431c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 104417b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 10451c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 104617b0429dSPierre Ossman cmd->error = -EILSEQ; 10479047b435SRussell King - ARM Linux } else { 10489047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 10499047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 10509047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 10519047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 10521c6a0718SPierre Ossman } 10531c6a0718SPierre Ossman 1054024629c6SUlf Hansson if ((!sbc && !cmd->data) || cmd->error) { 10553b6e3c73SUlf Hansson if (host->data) { 10563b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 1057653a761eSUlf Hansson if (dma_inprogress(host)) { 10583b6e3c73SUlf Hansson mmci_dma_data_error(host); 1059653a761eSUlf Hansson mmci_dma_unmap(host, host->data); 1060653a761eSUlf Hansson } 10611c6a0718SPierre Ossman mmci_stop_data(host); 10623b6e3c73SUlf Hansson } 1063024629c6SUlf Hansson mmci_request_end(host, host->mrq); 1064024629c6SUlf Hansson } else if (sbc) { 1065024629c6SUlf Hansson mmci_start_command(host, host->mrq->cmd, 0); 10661c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 10671c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 10681c6a0718SPierre Ossman } 10691c6a0718SPierre Ossman } 10701c6a0718SPierre Ossman 10719c34b73dSSrinivas Kandagatla static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 10729c34b73dSSrinivas Kandagatla { 10739c34b73dSSrinivas Kandagatla return remain - (readl(host->base + MMCIFIFOCNT) << 2); 10749c34b73dSSrinivas Kandagatla } 10759c34b73dSSrinivas Kandagatla 10769c34b73dSSrinivas Kandagatla static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 10779c34b73dSSrinivas Kandagatla { 10789c34b73dSSrinivas Kandagatla /* 10799c34b73dSSrinivas Kandagatla * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 10809c34b73dSSrinivas Kandagatla * from the fifo range should be used 10819c34b73dSSrinivas Kandagatla */ 10829c34b73dSSrinivas Kandagatla if (status & MCI_RXFIFOHALFFULL) 10839c34b73dSSrinivas Kandagatla return host->variant->fifohalfsize; 10849c34b73dSSrinivas Kandagatla else if (status & MCI_RXDATAAVLBL) 10859c34b73dSSrinivas Kandagatla return 4; 10869c34b73dSSrinivas Kandagatla 10879c34b73dSSrinivas Kandagatla return 0; 10889c34b73dSSrinivas Kandagatla } 10899c34b73dSSrinivas Kandagatla 10901c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 10911c6a0718SPierre Ossman { 10921c6a0718SPierre Ossman void __iomem *base = host->base; 10931c6a0718SPierre Ossman char *ptr = buffer; 10949c34b73dSSrinivas Kandagatla u32 status = readl(host->base + MMCISTATUS); 109526eed9a5SLinus Walleij int host_remain = host->size; 10961c6a0718SPierre Ossman 10971c6a0718SPierre Ossman do { 10989c34b73dSSrinivas Kandagatla int count = host->get_rx_fifocnt(host, status, host_remain); 10991c6a0718SPierre Ossman 11001c6a0718SPierre Ossman if (count > remain) 11011c6a0718SPierre Ossman count = remain; 11021c6a0718SPierre Ossman 11031c6a0718SPierre Ossman if (count <= 0) 11041c6a0718SPierre Ossman break; 11051c6a0718SPierre Ossman 1106393e5e24SUlf Hansson /* 1107393e5e24SUlf Hansson * SDIO especially may want to send something that is 1108393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 1109393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 1110393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 1111393e5e24SUlf Hansson */ 1112393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 1113393e5e24SUlf Hansson if (count < 4) { 1114393e5e24SUlf Hansson unsigned char buf[4]; 11154b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 1116393e5e24SUlf Hansson memcpy(ptr, buf, count); 1117393e5e24SUlf Hansson } else { 11184b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1119393e5e24SUlf Hansson count &= ~0x3; 1120393e5e24SUlf Hansson } 1121393e5e24SUlf Hansson } else { 11224b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1123393e5e24SUlf Hansson } 11241c6a0718SPierre Ossman 11251c6a0718SPierre Ossman ptr += count; 11261c6a0718SPierre Ossman remain -= count; 112726eed9a5SLinus Walleij host_remain -= count; 11281c6a0718SPierre Ossman 11291c6a0718SPierre Ossman if (remain == 0) 11301c6a0718SPierre Ossman break; 11311c6a0718SPierre Ossman 11321c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11331c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 11341c6a0718SPierre Ossman 11351c6a0718SPierre Ossman return ptr - buffer; 11361c6a0718SPierre Ossman } 11371c6a0718SPierre Ossman 11381c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 11391c6a0718SPierre Ossman { 11408301bb68SRabin Vincent struct variant_data *variant = host->variant; 11411c6a0718SPierre Ossman void __iomem *base = host->base; 11421c6a0718SPierre Ossman char *ptr = buffer; 11431c6a0718SPierre Ossman 11441c6a0718SPierre Ossman do { 11451c6a0718SPierre Ossman unsigned int count, maxcnt; 11461c6a0718SPierre Ossman 11478301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 11488301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 11491c6a0718SPierre Ossman count = min(remain, maxcnt); 11501c6a0718SPierre Ossman 115134177802SLinus Walleij /* 115234177802SLinus Walleij * SDIO especially may want to send something that is 115334177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 115434177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 115534177802SLinus Walleij * So compensate by adding +3 on the count, a single 115634177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 115734177802SLinus Walleij * 32bit writes etc. 115834177802SLinus Walleij */ 11594b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 11601c6a0718SPierre Ossman 11611c6a0718SPierre Ossman ptr += count; 11621c6a0718SPierre Ossman remain -= count; 11631c6a0718SPierre Ossman 11641c6a0718SPierre Ossman if (remain == 0) 11651c6a0718SPierre Ossman break; 11661c6a0718SPierre Ossman 11671c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11681c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 11691c6a0718SPierre Ossman 11701c6a0718SPierre Ossman return ptr - buffer; 11711c6a0718SPierre Ossman } 11721c6a0718SPierre Ossman 11731c6a0718SPierre Ossman /* 11741c6a0718SPierre Ossman * PIO data transfer IRQ handler. 11751c6a0718SPierre Ossman */ 11761c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 11771c6a0718SPierre Ossman { 11781c6a0718SPierre Ossman struct mmci_host *host = dev_id; 11794ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 11808301bb68SRabin Vincent struct variant_data *variant = host->variant; 11811c6a0718SPierre Ossman void __iomem *base = host->base; 11821c6a0718SPierre Ossman u32 status; 11831c6a0718SPierre Ossman 11841c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11851c6a0718SPierre Ossman 118664de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 11871c6a0718SPierre Ossman 11881c6a0718SPierre Ossman do { 11891c6a0718SPierre Ossman unsigned int remain, len; 11901c6a0718SPierre Ossman char *buffer; 11911c6a0718SPierre Ossman 11921c6a0718SPierre Ossman /* 11931c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 11941c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 11951c6a0718SPierre Ossman * definition it is more than half empty. 11961c6a0718SPierre Ossman * 11971c6a0718SPierre Ossman * For read, check for data available. 11981c6a0718SPierre Ossman */ 11991c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 12001c6a0718SPierre Ossman break; 12011c6a0718SPierre Ossman 12024ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 12034ce1d6cbSRabin Vincent break; 12044ce1d6cbSRabin Vincent 12054ce1d6cbSRabin Vincent buffer = sg_miter->addr; 12064ce1d6cbSRabin Vincent remain = sg_miter->length; 12071c6a0718SPierre Ossman 12081c6a0718SPierre Ossman len = 0; 12091c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 12101c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 12111c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 12121c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 12131c6a0718SPierre Ossman 12144ce1d6cbSRabin Vincent sg_miter->consumed = len; 12151c6a0718SPierre Ossman 12161c6a0718SPierre Ossman host->size -= len; 12171c6a0718SPierre Ossman remain -= len; 12181c6a0718SPierre Ossman 12191c6a0718SPierre Ossman if (remain) 12201c6a0718SPierre Ossman break; 12211c6a0718SPierre Ossman 12221c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 12231c6a0718SPierre Ossman } while (1); 12241c6a0718SPierre Ossman 12254ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 12264ce1d6cbSRabin Vincent 12271c6a0718SPierre Ossman /* 1228c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 1229c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 12301c6a0718SPierre Ossman */ 1231c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 12322686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 12331c6a0718SPierre Ossman 12341c6a0718SPierre Ossman /* 12351c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 12361c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 12371c6a0718SPierre Ossman * the chip itself has disabled the data path, and 12381c6a0718SPierre Ossman * stops us racing with our data end IRQ. 12391c6a0718SPierre Ossman */ 12401c6a0718SPierre Ossman if (host->size == 0) { 12412686b4b4SLinus Walleij mmci_set_mask1(host, 0); 12421c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 12431c6a0718SPierre Ossman } 12441c6a0718SPierre Ossman 12451c6a0718SPierre Ossman return IRQ_HANDLED; 12461c6a0718SPierre Ossman } 12471c6a0718SPierre Ossman 12481c6a0718SPierre Ossman /* 12491c6a0718SPierre Ossman * Handle completion of command and data transfers. 12501c6a0718SPierre Ossman */ 12511c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 12521c6a0718SPierre Ossman { 12531c6a0718SPierre Ossman struct mmci_host *host = dev_id; 12541c6a0718SPierre Ossman u32 status; 12551c6a0718SPierre Ossman int ret = 0; 12561c6a0718SPierre Ossman 12571c6a0718SPierre Ossman spin_lock(&host->lock); 12581c6a0718SPierre Ossman 12591c6a0718SPierre Ossman do { 12601c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 12612686b4b4SLinus Walleij 12622686b4b4SLinus Walleij if (host->singleirq) { 12636ea9cdf3SPatrice Chotard if (status & host->mask1_reg) 12642686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 12652686b4b4SLinus Walleij 12662686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 12672686b4b4SLinus Walleij } 12682686b4b4SLinus Walleij 12698d94b54dSUlf Hansson /* 12705cad24d8SJean-Nicolas Graux * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 12715cad24d8SJean-Nicolas Graux * enabled) in mmci_cmd_irq() function where ST Micro busy 12725cad24d8SJean-Nicolas Graux * detection variant is handled. Considering the HW seems to be 12735cad24d8SJean-Nicolas Graux * triggering the IRQ on both edges while monitoring DAT0 for 12745cad24d8SJean-Nicolas Graux * busy completion and that same status bit is used to monitor 12755cad24d8SJean-Nicolas Graux * start and end of busy detection, special care must be taken 12765cad24d8SJean-Nicolas Graux * to make sure that both start and end interrupts are always 12775cad24d8SJean-Nicolas Graux * cleared one after the other. 12788d94b54dSUlf Hansson */ 12791c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 12805cad24d8SJean-Nicolas Graux if (host->variant->busy_detect) 12815cad24d8SJean-Nicolas Graux writel(status & ~host->variant->busy_detect_mask, 12825cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 12835cad24d8SJean-Nicolas Graux else 12841c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 12851c6a0718SPierre Ossman 128664de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 12871c6a0718SPierre Ossman 12887878289bSUlf Hansson if (host->variant->reversed_irq_handling) { 12897878289bSUlf Hansson mmci_data_irq(host, host->data, status); 12907878289bSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 12917878289bSUlf Hansson } else { 1292ad82bfeaSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 12931cb9da50SUlf Hansson mmci_data_irq(host, host->data, status); 12947878289bSUlf Hansson } 12951c6a0718SPierre Ossman 129649adc0caSLinus Walleij /* 129749adc0caSLinus Walleij * Don't poll for busy completion in irq context. 129849adc0caSLinus Walleij */ 129949adc0caSLinus Walleij if (host->variant->busy_detect && host->busy_status) 130049adc0caSLinus Walleij status &= ~host->variant->busy_detect_flag; 13018d94b54dSUlf Hansson 13021c6a0718SPierre Ossman ret = 1; 13031c6a0718SPierre Ossman } while (status); 13041c6a0718SPierre Ossman 13051c6a0718SPierre Ossman spin_unlock(&host->lock); 13061c6a0718SPierre Ossman 13071c6a0718SPierre Ossman return IRQ_RETVAL(ret); 13081c6a0718SPierre Ossman } 13091c6a0718SPierre Ossman 13101c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 13111c6a0718SPierre Ossman { 13121c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 13139e943021SLinus Walleij unsigned long flags; 13141c6a0718SPierre Ossman 13151c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 13161c6a0718SPierre Ossman 1317653a761eSUlf Hansson mrq->cmd->error = mmci_validate_data(host, mrq->data); 1318653a761eSUlf Hansson if (mrq->cmd->error) { 1319255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1320255d01afSPierre Ossman return; 1321255d01afSPierre Ossman } 1322255d01afSPierre Ossman 13239e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 13241c6a0718SPierre Ossman 13251c6a0718SPierre Ossman host->mrq = mrq; 13261c6a0718SPierre Ossman 132758c7ccbfSPer Forlin if (mrq->data) 132858c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 132958c7ccbfSPer Forlin 13301c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 13311c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 13321c6a0718SPierre Ossman 1333024629c6SUlf Hansson if (mrq->sbc) 1334024629c6SUlf Hansson mmci_start_command(host, mrq->sbc, 0); 1335024629c6SUlf Hansson else 13361c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 13371c6a0718SPierre Ossman 13389e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 13391c6a0718SPierre Ossman } 13401c6a0718SPierre Ossman 13411c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 13421c6a0718SPierre Ossman { 13431c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 13447d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1345a6a6464aSLinus Walleij u32 pwr = 0; 1346a6a6464aSLinus Walleij unsigned long flags; 1347db90f91fSLee Jones int ret; 13481c6a0718SPierre Ossman 1349bc521818SUlf Hansson if (host->plat->ios_handler && 1350bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1351bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1352bc521818SUlf Hansson 13531c6a0718SPierre Ossman switch (ios->power_mode) { 13541c6a0718SPierre Ossman case MMC_POWER_OFF: 1355599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1356599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1357237fb5e6SLee Jones 13587c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1359237fb5e6SLee Jones regulator_disable(mmc->supply.vqmmc); 13607c0136efSUlf Hansson host->vqmmc_enabled = false; 13617c0136efSUlf Hansson } 1362237fb5e6SLee Jones 13631c6a0718SPierre Ossman break; 13641c6a0718SPierre Ossman case MMC_POWER_UP: 1365599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1366599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1367599c1d5cSUlf Hansson 13687d72a1d4SUlf Hansson /* 13697d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 13707d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 13717d72a1d4SUlf Hansson * configured in the variant data. 13727d72a1d4SUlf Hansson */ 13737d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 13747d72a1d4SUlf Hansson 13751c6a0718SPierre Ossman break; 13761c6a0718SPierre Ossman case MMC_POWER_ON: 13777c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1378db90f91fSLee Jones ret = regulator_enable(mmc->supply.vqmmc); 1379db90f91fSLee Jones if (ret < 0) 1380db90f91fSLee Jones dev_err(mmc_dev(mmc), 1381db90f91fSLee Jones "failed to enable vqmmc regulator\n"); 13827c0136efSUlf Hansson else 13837c0136efSUlf Hansson host->vqmmc_enabled = true; 1384db90f91fSLee Jones } 1385237fb5e6SLee Jones 13861c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 13871c6a0718SPierre Ossman break; 13881c6a0718SPierre Ossman } 13891c6a0718SPierre Ossman 13904d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 13914d1a3a0dSUlf Hansson /* 13924d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 13934d1a3a0dSUlf Hansson * indicating signal direction for the signals in 13944d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 13954d1a3a0dSUlf Hansson */ 13964593df29SUlf Hansson pwr |= host->pwr_reg_add; 13974d1a3a0dSUlf Hansson 13984d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 13994d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 14004d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 14014d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 14024d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 14034d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 14044d1a3a0dSUlf Hansson } 14054d1a3a0dSUlf Hansson 1406f9bb304cSPatrice Chotard if (variant->opendrain) { 1407f9bb304cSPatrice Chotard if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 140811dfb970SPatrice Chotard pwr |= variant->opendrain; 1409f9bb304cSPatrice Chotard } else { 1410f9bb304cSPatrice Chotard /* 1411f9bb304cSPatrice Chotard * If the variant cannot configure the pads by its own, then we 1412f9bb304cSPatrice Chotard * expect the pinctrl to be able to do that for us 1413f9bb304cSPatrice Chotard */ 1414f9bb304cSPatrice Chotard if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1415f9bb304cSPatrice Chotard pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1416f9bb304cSPatrice Chotard else 1417f9bb304cSPatrice Chotard pinctrl_select_state(host->pinctrl, host->pins_default); 1418f9bb304cSPatrice Chotard } 14191c6a0718SPierre Ossman 1420f4670daeSUlf Hansson /* 1421f4670daeSUlf Hansson * If clock = 0 and the variant requires the MMCIPOWER to be used for 1422f4670daeSUlf Hansson * gating the clock, the MCI_PWR_ON bit is cleared. 1423f4670daeSUlf Hansson */ 1424f4670daeSUlf Hansson if (!ios->clock && variant->pwrreg_clkgate) 1425f4670daeSUlf Hansson pwr &= ~MCI_PWR_ON; 1426f4670daeSUlf Hansson 14273f4e6f7bSSrinivas Kandagatla if (host->variant->explicit_mclk_control && 14283f4e6f7bSSrinivas Kandagatla ios->clock != host->clock_cache) { 14293f4e6f7bSSrinivas Kandagatla ret = clk_set_rate(host->clk, ios->clock); 14303f4e6f7bSSrinivas Kandagatla if (ret < 0) 14313f4e6f7bSSrinivas Kandagatla dev_err(mmc_dev(host->mmc), 14323f4e6f7bSSrinivas Kandagatla "Error setting clock rate (%d)\n", ret); 14333f4e6f7bSSrinivas Kandagatla else 14343f4e6f7bSSrinivas Kandagatla host->mclk = clk_get_rate(host->clk); 14353f4e6f7bSSrinivas Kandagatla } 14363f4e6f7bSSrinivas Kandagatla host->clock_cache = ios->clock; 14373f4e6f7bSSrinivas Kandagatla 1438a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1439a6a6464aSLinus Walleij 1440a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 14417437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1442f829c042SUlf Hansson mmci_reg_delay(host); 1443a6a6464aSLinus Walleij 1444a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 14451c6a0718SPierre Ossman } 14461c6a0718SPierre Ossman 144789001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 144889001446SRussell King { 144989001446SRussell King struct mmci_host *host = mmc_priv(mmc); 145029719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 1451d2762090SUlf Hansson unsigned int status = mmc_gpio_get_cd(mmc); 145289001446SRussell King 1453d2762090SUlf Hansson if (status == -ENOSYS) { 14544b8caec0SRabin Vincent if (!plat->status) 14554b8caec0SRabin Vincent return 1; /* Assume always present */ 14564b8caec0SRabin Vincent 145729719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 1458d2762090SUlf Hansson } 145974bc8093SRussell King return status; 146089001446SRussell King } 146189001446SRussell King 14620f3ed7f7SUlf Hansson static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 14630f3ed7f7SUlf Hansson { 14640f3ed7f7SUlf Hansson int ret = 0; 14650f3ed7f7SUlf Hansson 14660f3ed7f7SUlf Hansson if (!IS_ERR(mmc->supply.vqmmc)) { 14670f3ed7f7SUlf Hansson 14680f3ed7f7SUlf Hansson switch (ios->signal_voltage) { 14690f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_330: 14700f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14710f3ed7f7SUlf Hansson 2700000, 3600000); 14720f3ed7f7SUlf Hansson break; 14730f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_180: 14740f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14750f3ed7f7SUlf Hansson 1700000, 1950000); 14760f3ed7f7SUlf Hansson break; 14770f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_120: 14780f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14790f3ed7f7SUlf Hansson 1100000, 1300000); 14800f3ed7f7SUlf Hansson break; 14810f3ed7f7SUlf Hansson } 14820f3ed7f7SUlf Hansson 14830f3ed7f7SUlf Hansson if (ret) 14840f3ed7f7SUlf Hansson dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 14850f3ed7f7SUlf Hansson } 14860f3ed7f7SUlf Hansson 14870f3ed7f7SUlf Hansson return ret; 14880f3ed7f7SUlf Hansson } 14890f3ed7f7SUlf Hansson 149001259620SUlf Hansson static struct mmc_host_ops mmci_ops = { 14911c6a0718SPierre Ossman .request = mmci_request, 149258c7ccbfSPer Forlin .pre_req = mmci_pre_request, 149358c7ccbfSPer Forlin .post_req = mmci_post_request, 14941c6a0718SPierre Ossman .set_ios = mmci_set_ios, 1495d2762090SUlf Hansson .get_ro = mmc_gpio_get_ro, 149689001446SRussell King .get_cd = mmci_get_cd, 14970f3ed7f7SUlf Hansson .start_signal_voltage_switch = mmci_sig_volt_switch, 14981c6a0718SPierre Ossman }; 14991c6a0718SPierre Ossman 150078f87df2SUlf Hansson static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 150178f87df2SUlf Hansson { 15024593df29SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 150378f87df2SUlf Hansson int ret = mmc_of_parse(mmc); 1504000bc9d5SLee Jones 150578f87df2SUlf Hansson if (ret) 150678f87df2SUlf Hansson return ret; 1507000bc9d5SLee Jones 15084593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat0", NULL)) 15094593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA0DIREN; 15104593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat2", NULL)) 15114593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA2DIREN; 15124593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat31", NULL)) 15134593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA31DIREN; 15144593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat74", NULL)) 15154593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA74DIREN; 15164593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-cmd", NULL)) 15174593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_CMDDIREN; 15184593df29SUlf Hansson if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 15194593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_FBCLKEN; 15204593df29SUlf Hansson 1521000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 152278f87df2SUlf Hansson mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1523000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 152478f87df2SUlf Hansson mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1525000bc9d5SLee Jones 152678f87df2SUlf Hansson return 0; 1527000bc9d5SLee Jones } 1528000bc9d5SLee Jones 1529c3be1efdSBill Pemberton static int mmci_probe(struct amba_device *dev, 1530aa25afadSRussell King const struct amba_id *id) 15311c6a0718SPierre Ossman { 15326ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1533000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 15344956e109SRabin Vincent struct variant_data *variant = id->data; 15351c6a0718SPierre Ossman struct mmci_host *host; 15361c6a0718SPierre Ossman struct mmc_host *mmc; 15371c6a0718SPierre Ossman int ret; 15381c6a0718SPierre Ossman 1539000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1540000bc9d5SLee Jones if (!plat && !np) { 1541000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1542000bc9d5SLee Jones return -EINVAL; 15431c6a0718SPierre Ossman } 15441c6a0718SPierre Ossman 1545b9b52918SLee Jones if (!plat) { 1546b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1547b9b52918SLee Jones if (!plat) 1548b9b52918SLee Jones return -ENOMEM; 1549b9b52918SLee Jones } 1550b9b52918SLee Jones 15511c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1552ef289982SUlf Hansson if (!mmc) 1553ef289982SUlf Hansson return -ENOMEM; 15541c6a0718SPierre Ossman 155578f87df2SUlf Hansson ret = mmci_of_parse(np, mmc); 155678f87df2SUlf Hansson if (ret) 155778f87df2SUlf Hansson goto host_free; 155878f87df2SUlf Hansson 15591c6a0718SPierre Ossman host = mmc_priv(mmc); 15604ea580f1SRabin Vincent host->mmc = mmc; 1561012b7d33SRussell King 1562f9bb304cSPatrice Chotard /* 1563f9bb304cSPatrice Chotard * Some variant (STM32) doesn't have opendrain bit, nevertheless 1564f9bb304cSPatrice Chotard * pins can be set accordingly using pinctrl 1565f9bb304cSPatrice Chotard */ 1566f9bb304cSPatrice Chotard if (!variant->opendrain) { 1567f9bb304cSPatrice Chotard host->pinctrl = devm_pinctrl_get(&dev->dev); 1568f9bb304cSPatrice Chotard if (IS_ERR(host->pinctrl)) { 1569f9bb304cSPatrice Chotard dev_err(&dev->dev, "failed to get pinctrl"); 1570310eb252SWei Yongjun ret = PTR_ERR(host->pinctrl); 1571f9bb304cSPatrice Chotard goto host_free; 1572f9bb304cSPatrice Chotard } 1573f9bb304cSPatrice Chotard 1574f9bb304cSPatrice Chotard host->pins_default = pinctrl_lookup_state(host->pinctrl, 1575f9bb304cSPatrice Chotard PINCTRL_STATE_DEFAULT); 1576f9bb304cSPatrice Chotard if (IS_ERR(host->pins_default)) { 1577f9bb304cSPatrice Chotard dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1578310eb252SWei Yongjun ret = PTR_ERR(host->pins_default); 1579f9bb304cSPatrice Chotard goto host_free; 1580f9bb304cSPatrice Chotard } 1581f9bb304cSPatrice Chotard 1582f9bb304cSPatrice Chotard host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1583f9bb304cSPatrice Chotard MMCI_PINCTRL_STATE_OPENDRAIN); 1584f9bb304cSPatrice Chotard if (IS_ERR(host->pins_opendrain)) { 1585f9bb304cSPatrice Chotard dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1586310eb252SWei Yongjun ret = PTR_ERR(host->pins_opendrain); 1587f9bb304cSPatrice Chotard goto host_free; 1588f9bb304cSPatrice Chotard } 1589f9bb304cSPatrice Chotard } 1590f9bb304cSPatrice Chotard 1591012b7d33SRussell King host->hw_designer = amba_manf(dev); 1592012b7d33SRussell King host->hw_revision = amba_rev(dev); 159364de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 159464de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1595012b7d33SRussell King 1596665ba56fSUlf Hansson host->clk = devm_clk_get(&dev->dev, NULL); 15971c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 15981c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 15991c6a0718SPierre Ossman goto host_free; 16001c6a0718SPierre Ossman } 16011c6a0718SPierre Ossman 1602ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 16031c6a0718SPierre Ossman if (ret) 1604665ba56fSUlf Hansson goto host_free; 16051c6a0718SPierre Ossman 16069c34b73dSSrinivas Kandagatla if (variant->qcom_fifo) 16079c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 16089c34b73dSSrinivas Kandagatla else 16099c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_get_rx_fifocnt; 16109c34b73dSSrinivas Kandagatla 16111c6a0718SPierre Ossman host->plat = plat; 16124956e109SRabin Vincent host->variant = variant; 16131c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1614c8df9a53SLinus Walleij /* 1615c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1616c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1617c8df9a53SLinus Walleij * (if possible). 1618c8df9a53SLinus Walleij */ 1619dc6500bfSSrinivas Kandagatla if (host->mclk > variant->f_max) { 1620dc6500bfSSrinivas Kandagatla ret = clk_set_rate(host->clk, variant->f_max); 1621c8df9a53SLinus Walleij if (ret < 0) 1622c8df9a53SLinus Walleij goto clk_disable; 1623c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 162464de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 162564de0289SLinus Walleij host->mclk); 1626c8df9a53SLinus Walleij } 1627ef289982SUlf Hansson 1628c8ebae37SRussell King host->phybase = dev->res.start; 1629ef289982SUlf Hansson host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1630ef289982SUlf Hansson if (IS_ERR(host->base)) { 1631ef289982SUlf Hansson ret = PTR_ERR(host->base); 16321c6a0718SPierre Ossman goto clk_disable; 16331c6a0718SPierre Ossman } 16341c6a0718SPierre Ossman 1635ed9067fdSUlf Hansson if (variant->init) 1636ed9067fdSUlf Hansson variant->init(host); 1637ed9067fdSUlf Hansson 16387f294e49SLinus Walleij /* 16397f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 16407f294e49SLinus Walleij * clock divider equations which means that the minimum divider 16417f294e49SLinus Walleij * differs too. 16423f4e6f7bSSrinivas Kandagatla * on Qualcomm like controllers get the nearest minimum clock to 100Khz 16437f294e49SLinus Walleij */ 16447f294e49SLinus Walleij if (variant->st_clkdiv) 16457f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 16463f4e6f7bSSrinivas Kandagatla else if (variant->explicit_mclk_control) 16473f4e6f7bSSrinivas Kandagatla mmc->f_min = clk_round_rate(host->clk, 100000); 16487f294e49SLinus Walleij else 16497f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1650808d97ccSLinus Walleij /* 165178f87df2SUlf Hansson * If no maximum operating frequency is supplied, fall back to use 165278f87df2SUlf Hansson * the module parameter, which has a (low) default value in case it 165378f87df2SUlf Hansson * is not specified. Either value must not exceed the clock rate into 16545080a08dSUlf Hansson * the block, of course. 1655808d97ccSLinus Walleij */ 165678f87df2SUlf Hansson if (mmc->f_max) 16573f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16583f4e6f7bSSrinivas Kandagatla min(variant->f_max, mmc->f_max) : 16593f4e6f7bSSrinivas Kandagatla min(host->mclk, mmc->f_max); 1660808d97ccSLinus Walleij else 16613f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16623f4e6f7bSSrinivas Kandagatla fmax : min(host->mclk, fmax); 16633f4e6f7bSSrinivas Kandagatla 16643f4e6f7bSSrinivas Kandagatla 166564de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 166664de0289SLinus Walleij 1667599c1d5cSUlf Hansson /* Get regulators and the supported OCR mask */ 16689369c97cSBjorn Andersson ret = mmc_regulator_get_supply(mmc); 166951006952SWolfram Sang if (ret) 16709369c97cSBjorn Andersson goto clk_disable; 16719369c97cSBjorn Andersson 1672599c1d5cSUlf Hansson if (!mmc->ocr_avail) 16731c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 1674599c1d5cSUlf Hansson else if (plat->ocr_mask) 1675599c1d5cSUlf Hansson dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1676599c1d5cSUlf Hansson 16779dd8a8b8SUlf Hansson /* We support these capabilities. */ 16789dd8a8b8SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 16799dd8a8b8SUlf Hansson 168049adc0caSLinus Walleij /* 168149adc0caSLinus Walleij * Enable busy detection. 168249adc0caSLinus Walleij */ 16838d94b54dSUlf Hansson if (variant->busy_detect) { 16848d94b54dSUlf Hansson mmci_ops.card_busy = mmci_card_busy; 168549adc0caSLinus Walleij /* 168649adc0caSLinus Walleij * Not all variants have a flag to enable busy detection 168749adc0caSLinus Walleij * in the DPSM, but if they do, set it here. 168849adc0caSLinus Walleij */ 168949adc0caSLinus Walleij if (variant->busy_dpsm_flag) 169049adc0caSLinus Walleij mmci_write_datactrlreg(host, 169149adc0caSLinus Walleij host->variant->busy_dpsm_flag); 16928d94b54dSUlf Hansson mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 16938d94b54dSUlf Hansson mmc->max_busy_timeout = 0; 16948d94b54dSUlf Hansson } 16958d94b54dSUlf Hansson 16968d94b54dSUlf Hansson mmc->ops = &mmci_ops; 16978d94b54dSUlf Hansson 169870be208fSUlf Hansson /* We support these PM capabilities. */ 169978f87df2SUlf Hansson mmc->pm_caps |= MMC_PM_KEEP_POWER; 170070be208fSUlf Hansson 17011c6a0718SPierre Ossman /* 17021c6a0718SPierre Ossman * We can do SGIO 17031c6a0718SPierre Ossman */ 1704a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 17051c6a0718SPierre Ossman 17061c6a0718SPierre Ossman /* 170708458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 170808458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 170908458ef6SRabin Vincent * single request. 17101c6a0718SPierre Ossman */ 171108458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 17121c6a0718SPierre Ossman 17131c6a0718SPierre Ossman /* 17141c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 17151c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 17161c6a0718SPierre Ossman */ 17171c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 17181c6a0718SPierre Ossman 17191c6a0718SPierre Ossman /* 17201c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 17211c6a0718SPierre Ossman */ 17228f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 17231c6a0718SPierre Ossman 17241c6a0718SPierre Ossman /* 17258f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 17268f7f6b7eSWill Deacon * the maximum request size. 17271c6a0718SPierre Ossman */ 17288f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 17291c6a0718SPierre Ossman 17301c6a0718SPierre Ossman spin_lock_init(&host->lock); 17311c6a0718SPierre Ossman 17321c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 17336ea9cdf3SPatrice Chotard 17346ea9cdf3SPatrice Chotard if (variant->mmcimask1) 17351c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 17366ea9cdf3SPatrice Chotard 17371c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 17381c6a0718SPierre Ossman 1739ce437aa4SLinus Walleij /* 1740ce437aa4SLinus Walleij * If: 1741ce437aa4SLinus Walleij * - not using DT but using a descriptor table, or 1742ce437aa4SLinus Walleij * - using a table of descriptors ALONGSIDE DT, or 1743ce437aa4SLinus Walleij * look up these descriptors named "cd" and "wp" right here, fail 17449ef986a6SLinus Walleij * silently of these do not exist 1745ce437aa4SLinus Walleij */ 1746ce437aa4SLinus Walleij if (!np) { 174789168b48SLinus Walleij ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1748ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1749ce437aa4SLinus Walleij goto clk_disable; 1750ce437aa4SLinus Walleij 175189168b48SLinus Walleij ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1752ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1753ce437aa4SLinus Walleij goto clk_disable; 1754ce437aa4SLinus Walleij } 175589001446SRussell King 1756ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1757ef289982SUlf Hansson DRIVER_NAME " (cmd)", host); 17581c6a0718SPierre Ossman if (ret) 1759ef289982SUlf Hansson goto clk_disable; 17601c6a0718SPierre Ossman 1761dfb85185SRussell King if (!dev->irq[1]) 17622686b4b4SLinus Walleij host->singleirq = true; 17632686b4b4SLinus Walleij else { 1764ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1765ef289982SUlf Hansson IRQF_SHARED, DRIVER_NAME " (pio)", host); 17661c6a0718SPierre Ossman if (ret) 1767ef289982SUlf Hansson goto clk_disable; 17682686b4b4SLinus Walleij } 17691c6a0718SPierre Ossman 17708cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 17711c6a0718SPierre Ossman 17721c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 17731c6a0718SPierre Ossman 1774c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1775c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1776c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1777c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1778c8ebae37SRussell King 1779c8ebae37SRussell King mmci_dma_setup(host); 17801c6a0718SPierre Ossman 17812cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 17822cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 17831c3be369SRussell King 17848c11a94dSRussell King mmc_add_host(mmc); 17858c11a94dSRussell King 17866f2d3c89SUlf Hansson pm_runtime_put(&dev->dev); 17871c6a0718SPierre Ossman return 0; 17881c6a0718SPierre Ossman 17891c6a0718SPierre Ossman clk_disable: 1790ac940938SJulia Lawall clk_disable_unprepare(host->clk); 17911c6a0718SPierre Ossman host_free: 17921c6a0718SPierre Ossman mmc_free_host(mmc); 17931c6a0718SPierre Ossman return ret; 17941c6a0718SPierre Ossman } 17951c6a0718SPierre Ossman 17966e0ee714SBill Pemberton static int mmci_remove(struct amba_device *dev) 17971c6a0718SPierre Ossman { 17981c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 17991c6a0718SPierre Ossman 18001c6a0718SPierre Ossman if (mmc) { 18011c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 18026ea9cdf3SPatrice Chotard struct variant_data *variant = host->variant; 18031c6a0718SPierre Ossman 18041c3be369SRussell King /* 18051c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 18061c3be369SRussell King * version here so that we can access the primecell. 18071c3be369SRussell King */ 18081c3be369SRussell King pm_runtime_get_sync(&dev->dev); 18091c3be369SRussell King 18101c6a0718SPierre Ossman mmc_remove_host(mmc); 18111c6a0718SPierre Ossman 18121c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 18136ea9cdf3SPatrice Chotard 18146ea9cdf3SPatrice Chotard if (variant->mmcimask1) 18151c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 18161c6a0718SPierre Ossman 18171c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 18181c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 18191c6a0718SPierre Ossman 1820c8ebae37SRussell King mmci_dma_release(host); 1821ac940938SJulia Lawall clk_disable_unprepare(host->clk); 18221c6a0718SPierre Ossman mmc_free_host(mmc); 18231c6a0718SPierre Ossman } 18241c6a0718SPierre Ossman 18251c6a0718SPierre Ossman return 0; 18261c6a0718SPierre Ossman } 18271c6a0718SPierre Ossman 1828571dce4fSUlf Hansson #ifdef CONFIG_PM 18291ff44433SUlf Hansson static void mmci_save(struct mmci_host *host) 18301ff44433SUlf Hansson { 18311ff44433SUlf Hansson unsigned long flags; 18321ff44433SUlf Hansson 18331ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18341ff44433SUlf Hansson 18351ff44433SUlf Hansson writel(0, host->base + MMCIMASK0); 183642dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18371ff44433SUlf Hansson writel(0, host->base + MMCIDATACTRL); 18381ff44433SUlf Hansson writel(0, host->base + MMCIPOWER); 18391ff44433SUlf Hansson writel(0, host->base + MMCICLOCK); 184042dcc89aSUlf Hansson } 18411ff44433SUlf Hansson mmci_reg_delay(host); 18421ff44433SUlf Hansson 18431ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18441ff44433SUlf Hansson } 18451ff44433SUlf Hansson 18461ff44433SUlf Hansson static void mmci_restore(struct mmci_host *host) 18471ff44433SUlf Hansson { 18481ff44433SUlf Hansson unsigned long flags; 18491ff44433SUlf Hansson 18501ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18511ff44433SUlf Hansson 185242dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18531ff44433SUlf Hansson writel(host->clk_reg, host->base + MMCICLOCK); 18541ff44433SUlf Hansson writel(host->datactrl_reg, host->base + MMCIDATACTRL); 18551ff44433SUlf Hansson writel(host->pwr_reg, host->base + MMCIPOWER); 185642dcc89aSUlf Hansson } 18571ff44433SUlf Hansson writel(MCI_IRQENABLE, host->base + MMCIMASK0); 18581ff44433SUlf Hansson mmci_reg_delay(host); 18591ff44433SUlf Hansson 18601ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18611ff44433SUlf Hansson } 18621ff44433SUlf Hansson 18638259293aSUlf Hansson static int mmci_runtime_suspend(struct device *dev) 18648259293aSUlf Hansson { 18658259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18668259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18678259293aSUlf Hansson 18688259293aSUlf Hansson if (mmc) { 18698259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 1870e36bd9c6SUlf Hansson pinctrl_pm_select_sleep_state(dev); 18711ff44433SUlf Hansson mmci_save(host); 18728259293aSUlf Hansson clk_disable_unprepare(host->clk); 18738259293aSUlf Hansson } 18748259293aSUlf Hansson 18758259293aSUlf Hansson return 0; 18768259293aSUlf Hansson } 18778259293aSUlf Hansson 18788259293aSUlf Hansson static int mmci_runtime_resume(struct device *dev) 18798259293aSUlf Hansson { 18808259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18818259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18828259293aSUlf Hansson 18838259293aSUlf Hansson if (mmc) { 18848259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 18858259293aSUlf Hansson clk_prepare_enable(host->clk); 18861ff44433SUlf Hansson mmci_restore(host); 1887e36bd9c6SUlf Hansson pinctrl_pm_select_default_state(dev); 18888259293aSUlf Hansson } 18898259293aSUlf Hansson 18908259293aSUlf Hansson return 0; 18918259293aSUlf Hansson } 18928259293aSUlf Hansson #endif 18938259293aSUlf Hansson 189448fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 1895f3737fa3SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1896f3737fa3SUlf Hansson pm_runtime_force_resume) 18976ed23b80SRafael J. Wysocki SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 189848fa7003SUlf Hansson }; 189948fa7003SUlf Hansson 190088411deaSArvind Yadav static const struct amba_id mmci_ids[] = { 19011c6a0718SPierre Ossman { 19021c6a0718SPierre Ossman .id = 0x00041180, 1903768fbc18SPawel Moll .mask = 0xff0fffff, 19044956e109SRabin Vincent .data = &variant_arm, 19051c6a0718SPierre Ossman }, 19061c6a0718SPierre Ossman { 1907768fbc18SPawel Moll .id = 0x01041180, 1908768fbc18SPawel Moll .mask = 0xff0fffff, 1909768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1910768fbc18SPawel Moll }, 1911768fbc18SPawel Moll { 19123a37298aSPawel Moll .id = 0x02041180, 19133a37298aSPawel Moll .mask = 0xff0fffff, 19143a37298aSPawel Moll .data = &variant_arm_extended_fifo_hwfc, 19153a37298aSPawel Moll }, 19163a37298aSPawel Moll { 19171c6a0718SPierre Ossman .id = 0x00041181, 19181c6a0718SPierre Ossman .mask = 0x000fffff, 19194956e109SRabin Vincent .data = &variant_arm, 19201c6a0718SPierre Ossman }, 1921cc30d60eSLinus Walleij /* ST Micro variants */ 1922cc30d60eSLinus Walleij { 1923cc30d60eSLinus Walleij .id = 0x00180180, 1924cc30d60eSLinus Walleij .mask = 0x00ffffff, 19254956e109SRabin Vincent .data = &variant_u300, 1926cc30d60eSLinus Walleij }, 1927cc30d60eSLinus Walleij { 192834fd4213SLinus Walleij .id = 0x10180180, 192934fd4213SLinus Walleij .mask = 0xf0ffffff, 193034fd4213SLinus Walleij .data = &variant_nomadik, 193134fd4213SLinus Walleij }, 193234fd4213SLinus Walleij { 1933cc30d60eSLinus Walleij .id = 0x00280180, 1934cc30d60eSLinus Walleij .mask = 0x00ffffff, 19350bcb7efdSLinus Walleij .data = &variant_nomadik, 19364956e109SRabin Vincent }, 19374956e109SRabin Vincent { 19384956e109SRabin Vincent .id = 0x00480180, 19391784b157SPhilippe Langlais .mask = 0xf0ffffff, 19404956e109SRabin Vincent .data = &variant_ux500, 1941cc30d60eSLinus Walleij }, 19421784b157SPhilippe Langlais { 19431784b157SPhilippe Langlais .id = 0x10480180, 19441784b157SPhilippe Langlais .mask = 0xf0ffffff, 19451784b157SPhilippe Langlais .data = &variant_ux500v2, 19461784b157SPhilippe Langlais }, 19472a9d6c80SPatrice Chotard { 19482a9d6c80SPatrice Chotard .id = 0x00880180, 19492a9d6c80SPatrice Chotard .mask = 0x00ffffff, 19502a9d6c80SPatrice Chotard .data = &variant_stm32, 19512a9d6c80SPatrice Chotard }, 195255b604aeSSrinivas Kandagatla /* Qualcomm variants */ 195355b604aeSSrinivas Kandagatla { 195455b604aeSSrinivas Kandagatla .id = 0x00051180, 195555b604aeSSrinivas Kandagatla .mask = 0x000fffff, 195655b604aeSSrinivas Kandagatla .data = &variant_qcom, 195755b604aeSSrinivas Kandagatla }, 19581c6a0718SPierre Ossman { 0, 0 }, 19591c6a0718SPierre Ossman }; 19601c6a0718SPierre Ossman 19619f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 19629f99835fSDave Martin 19631c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 19641c6a0718SPierre Ossman .drv = { 19651c6a0718SPierre Ossman .name = DRIVER_NAME, 196648fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 19671c6a0718SPierre Ossman }, 19681c6a0718SPierre Ossman .probe = mmci_probe, 19690433c143SBill Pemberton .remove = mmci_remove, 19701c6a0718SPierre Ossman .id_table = mmci_ids, 19711c6a0718SPierre Ossman }; 19721c6a0718SPierre Ossman 19739e5ed094Sviresh kumar module_amba_driver(mmci_driver); 19741c6a0718SPierre Ossman 19751c6a0718SPierre Ossman module_param(fmax, uint, 0444); 19761c6a0718SPierre Ossman 19771c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 19781c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1979