11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 18000bc9d5SLee Jones #include <linux/slab.h> 191c6a0718SPierre Ossman #include <linux/delay.h> 201c6a0718SPierre Ossman #include <linux/err.h> 211c6a0718SPierre Ossman #include <linux/highmem.h> 22019a5f56SNicolas Pitre #include <linux/log2.h> 231c6a0718SPierre Ossman #include <linux/mmc/host.h> 2434177802SLinus Walleij #include <linux/mmc/card.h> 251c6a0718SPierre Ossman #include <linux/amba/bus.h> 261c6a0718SPierre Ossman #include <linux/clk.h> 27bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2889001446SRussell King #include <linux/gpio.h> 299a597016SLee Jones #include <linux/of_gpio.h> 3034e84f39SLinus Walleij #include <linux/regulator/consumer.h> 31c8ebae37SRussell King #include <linux/dmaengine.h> 32c8ebae37SRussell King #include <linux/dma-mapping.h> 33c8ebae37SRussell King #include <linux/amba/mmci.h> 341c3be369SRussell King #include <linux/pm_runtime.h> 35258aea76SViresh Kumar #include <linux/types.h> 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #include <asm/div64.h> 381c6a0718SPierre Ossman #include <asm/io.h> 391c6a0718SPierre Ossman #include <asm/sizes.h> 401c6a0718SPierre Ossman 411c6a0718SPierre Ossman #include "mmci.h" 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman static unsigned int fmax = 515633; 461c6a0718SPierre Ossman 474956e109SRabin Vincent /** 484956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 494956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 504380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 5108458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 528301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 538301bb68SRabin Vincent * is asserted (likewise for RX) 548301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 558301bb68SRabin Vincent * is asserted (likewise for RX) 5634177802SLinus Walleij * @sdio: variant supports SDIO 57b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 581784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 597d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 604d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 614956e109SRabin Vincent */ 624956e109SRabin Vincent struct variant_data { 634956e109SRabin Vincent unsigned int clkreg; 644380c14fSRabin Vincent unsigned int clkreg_enable; 6508458ef6SRabin Vincent unsigned int datalength_bits; 668301bb68SRabin Vincent unsigned int fifosize; 678301bb68SRabin Vincent unsigned int fifohalfsize; 6834177802SLinus Walleij bool sdio; 69b70a67f9SLinus Walleij bool st_clkdiv; 701784b157SPhilippe Langlais bool blksz_datactrl16; 717d72a1d4SUlf Hansson u32 pwrreg_powerup; 724d1a3a0dSUlf Hansson bool signal_direction; 734956e109SRabin Vincent }; 744956e109SRabin Vincent 754956e109SRabin Vincent static struct variant_data variant_arm = { 768301bb68SRabin Vincent .fifosize = 16 * 4, 778301bb68SRabin Vincent .fifohalfsize = 8 * 4, 7808458ef6SRabin Vincent .datalength_bits = 16, 797d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 804956e109SRabin Vincent }; 814956e109SRabin Vincent 82768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 83768fbc18SPawel Moll .fifosize = 128 * 4, 84768fbc18SPawel Moll .fifohalfsize = 64 * 4, 85768fbc18SPawel Moll .datalength_bits = 16, 867d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 87768fbc18SPawel Moll }; 88768fbc18SPawel Moll 894956e109SRabin Vincent static struct variant_data variant_u300 = { 908301bb68SRabin Vincent .fifosize = 16 * 4, 918301bb68SRabin Vincent .fifohalfsize = 8 * 4, 9249ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 9308458ef6SRabin Vincent .datalength_bits = 16, 9434177802SLinus Walleij .sdio = true, 957d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 964d1a3a0dSUlf Hansson .signal_direction = true, 974956e109SRabin Vincent }; 984956e109SRabin Vincent 994956e109SRabin Vincent static struct variant_data variant_ux500 = { 1008301bb68SRabin Vincent .fifosize = 30 * 4, 1018301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1024956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 10349ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 10408458ef6SRabin Vincent .datalength_bits = 24, 10534177802SLinus Walleij .sdio = true, 106b70a67f9SLinus Walleij .st_clkdiv = true, 1077d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1084d1a3a0dSUlf Hansson .signal_direction = true, 1094956e109SRabin Vincent }; 110b70a67f9SLinus Walleij 1111784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1121784b157SPhilippe Langlais .fifosize = 30 * 4, 1131784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1141784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1151784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1161784b157SPhilippe Langlais .datalength_bits = 24, 1171784b157SPhilippe Langlais .sdio = true, 1181784b157SPhilippe Langlais .st_clkdiv = true, 1191784b157SPhilippe Langlais .blksz_datactrl16 = true, 1207d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1214d1a3a0dSUlf Hansson .signal_direction = true, 1221784b157SPhilippe Langlais }; 1231784b157SPhilippe Langlais 124a6a6464aSLinus Walleij /* 125a6a6464aSLinus Walleij * This must be called with host->lock held 126a6a6464aSLinus Walleij */ 1277437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 1287437cfa5SUlf Hansson { 1297437cfa5SUlf Hansson if (host->clk_reg != clk) { 1307437cfa5SUlf Hansson host->clk_reg = clk; 1317437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 1327437cfa5SUlf Hansson } 1337437cfa5SUlf Hansson } 1347437cfa5SUlf Hansson 1357437cfa5SUlf Hansson /* 1367437cfa5SUlf Hansson * This must be called with host->lock held 1377437cfa5SUlf Hansson */ 1387437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 1397437cfa5SUlf Hansson { 1407437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 1417437cfa5SUlf Hansson host->pwr_reg = pwr; 1427437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 1437437cfa5SUlf Hansson } 1447437cfa5SUlf Hansson } 1457437cfa5SUlf Hansson 1467437cfa5SUlf Hansson /* 1477437cfa5SUlf Hansson * This must be called with host->lock held 1487437cfa5SUlf Hansson */ 149a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 150a6a6464aSLinus Walleij { 1514956e109SRabin Vincent struct variant_data *variant = host->variant; 1524956e109SRabin Vincent u32 clk = variant->clkreg; 153a6a6464aSLinus Walleij 154a6a6464aSLinus Walleij if (desired) { 155a6a6464aSLinus Walleij if (desired >= host->mclk) { 156a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 157399bc486SLinus Walleij if (variant->st_clkdiv) 158399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 159a6a6464aSLinus Walleij host->cclk = host->mclk; 160b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 161b70a67f9SLinus Walleij /* 162b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 163b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 164b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 165b70a67f9SLinus Walleij * frequency 166b70a67f9SLinus Walleij */ 167b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 168b70a67f9SLinus Walleij if (clk >= 256) 169b70a67f9SLinus Walleij clk = 255; 170b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 171a6a6464aSLinus Walleij } else { 172b70a67f9SLinus Walleij /* 173b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 174b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 175b70a67f9SLinus Walleij */ 176a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 177a6a6464aSLinus Walleij if (clk >= 256) 178a6a6464aSLinus Walleij clk = 255; 179a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 180a6a6464aSLinus Walleij } 1814380c14fSRabin Vincent 1824380c14fSRabin Vincent clk |= variant->clkreg_enable; 183a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 184a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 185a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 186a6a6464aSLinus Walleij } 187a6a6464aSLinus Walleij 1889e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 189771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 190771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 191771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 1929e6c82cdSLinus Walleij 1937437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 194a6a6464aSLinus Walleij } 195a6a6464aSLinus Walleij 1961c6a0718SPierre Ossman static void 1971c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 1981c6a0718SPierre Ossman { 1991c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 2001c6a0718SPierre Ossman 2011c6a0718SPierre Ossman BUG_ON(host->data); 2021c6a0718SPierre Ossman 2031c6a0718SPierre Ossman host->mrq = NULL; 2041c6a0718SPierre Ossman host->cmd = NULL; 2051c6a0718SPierre Ossman 2061c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2072cd976c4SUlf Hansson 2082cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 2092cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 2101c6a0718SPierre Ossman } 2111c6a0718SPierre Ossman 2122686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 2132686b4b4SLinus Walleij { 2142686b4b4SLinus Walleij void __iomem *base = host->base; 2152686b4b4SLinus Walleij 2162686b4b4SLinus Walleij if (host->singleirq) { 2172686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 2182686b4b4SLinus Walleij 2192686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 2202686b4b4SLinus Walleij mask0 |= mask; 2212686b4b4SLinus Walleij 2222686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 2232686b4b4SLinus Walleij } 2242686b4b4SLinus Walleij 2252686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 2262686b4b4SLinus Walleij } 2272686b4b4SLinus Walleij 2281c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 2291c6a0718SPierre Ossman { 2301c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 2312686b4b4SLinus Walleij mmci_set_mask1(host, 0); 2321c6a0718SPierre Ossman host->data = NULL; 2331c6a0718SPierre Ossman } 2341c6a0718SPierre Ossman 2354ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 2364ce1d6cbSRabin Vincent { 2374ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 2384ce1d6cbSRabin Vincent 2394ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 2404ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 2414ce1d6cbSRabin Vincent else 2424ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 2434ce1d6cbSRabin Vincent 2444ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 2454ce1d6cbSRabin Vincent } 2464ce1d6cbSRabin Vincent 247c8ebae37SRussell King /* 248c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 249c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 250c8ebae37SRussell King * no custom DMA interfaces are supported. 251c8ebae37SRussell King */ 252c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 253c8ebae37SRussell King static void __devinit mmci_dma_setup(struct mmci_host *host) 254c8ebae37SRussell King { 255c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 256c8ebae37SRussell King const char *rxname, *txname; 257c8ebae37SRussell King dma_cap_mask_t mask; 258c8ebae37SRussell King 259c8ebae37SRussell King if (!plat || !plat->dma_filter) { 260c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 261c8ebae37SRussell King return; 262c8ebae37SRussell King } 263c8ebae37SRussell King 26458c7ccbfSPer Forlin /* initialize pre request cookie */ 26558c7ccbfSPer Forlin host->next_data.cookie = 1; 26658c7ccbfSPer Forlin 267c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 268c8ebae37SRussell King dma_cap_zero(mask); 269c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 270c8ebae37SRussell King 271c8ebae37SRussell King /* 272c8ebae37SRussell King * If only an RX channel is specified, the driver will 273c8ebae37SRussell King * attempt to use it bidirectionally, however if it is 274c8ebae37SRussell King * is specified but cannot be located, DMA will be disabled. 275c8ebae37SRussell King */ 276c8ebae37SRussell King if (plat->dma_rx_param) { 277c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 278c8ebae37SRussell King plat->dma_filter, 279c8ebae37SRussell King plat->dma_rx_param); 280c8ebae37SRussell King /* E.g if no DMA hardware is present */ 281c8ebae37SRussell King if (!host->dma_rx_channel) 282c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 283c8ebae37SRussell King } 284c8ebae37SRussell King 285c8ebae37SRussell King if (plat->dma_tx_param) { 286c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 287c8ebae37SRussell King plat->dma_filter, 288c8ebae37SRussell King plat->dma_tx_param); 289c8ebae37SRussell King if (!host->dma_tx_channel) 290c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 291c8ebae37SRussell King } else { 292c8ebae37SRussell King host->dma_tx_channel = host->dma_rx_channel; 293c8ebae37SRussell King } 294c8ebae37SRussell King 295c8ebae37SRussell King if (host->dma_rx_channel) 296c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 297c8ebae37SRussell King else 298c8ebae37SRussell King rxname = "none"; 299c8ebae37SRussell King 300c8ebae37SRussell King if (host->dma_tx_channel) 301c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 302c8ebae37SRussell King else 303c8ebae37SRussell King txname = "none"; 304c8ebae37SRussell King 305c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 306c8ebae37SRussell King rxname, txname); 307c8ebae37SRussell King 308c8ebae37SRussell King /* 309c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 310c8ebae37SRussell King * the parameters of the DMA engine device. 311c8ebae37SRussell King */ 312c8ebae37SRussell King if (host->dma_tx_channel) { 313c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 314c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 315c8ebae37SRussell King 316c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 317c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 318c8ebae37SRussell King } 319c8ebae37SRussell King if (host->dma_rx_channel) { 320c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 321c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 322c8ebae37SRussell King 323c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 324c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 325c8ebae37SRussell King } 326c8ebae37SRussell King } 327c8ebae37SRussell King 328c8ebae37SRussell King /* 329c8ebae37SRussell King * This is used in __devinit or __devexit so inline it 330c8ebae37SRussell King * so it can be discarded. 331c8ebae37SRussell King */ 332c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 333c8ebae37SRussell King { 334c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 335c8ebae37SRussell King 336c8ebae37SRussell King if (host->dma_rx_channel) 337c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 338c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 339c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 340c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 341c8ebae37SRussell King } 342c8ebae37SRussell King 343c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 344c8ebae37SRussell King { 345c8ebae37SRussell King struct dma_chan *chan = host->dma_current; 346c8ebae37SRussell King enum dma_data_direction dir; 347c8ebae37SRussell King u32 status; 348c8ebae37SRussell King int i; 349c8ebae37SRussell King 350c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 351c8ebae37SRussell King for (i = 0; ; i++) { 352c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 353c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 354c8ebae37SRussell King break; 355c8ebae37SRussell King udelay(10); 356c8ebae37SRussell King } 357c8ebae37SRussell King 358c8ebae37SRussell King /* 359c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 360c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 361c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 362c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 363c8ebae37SRussell King */ 364c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 365c8ebae37SRussell King dmaengine_terminate_all(chan); 366c8ebae37SRussell King if (!data->error) 367c8ebae37SRussell King data->error = -EIO; 368c8ebae37SRussell King } 369c8ebae37SRussell King 370c8ebae37SRussell King if (data->flags & MMC_DATA_WRITE) { 371c8ebae37SRussell King dir = DMA_TO_DEVICE; 372c8ebae37SRussell King } else { 373c8ebae37SRussell King dir = DMA_FROM_DEVICE; 374c8ebae37SRussell King } 375c8ebae37SRussell King 37658c7ccbfSPer Forlin if (!data->host_cookie) 377c8ebae37SRussell King dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 378c8ebae37SRussell King 379c8ebae37SRussell King /* 380c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 381c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 382c8ebae37SRussell King */ 383c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 384c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 385c8ebae37SRussell King mmci_dma_release(host); 386c8ebae37SRussell King } 387c8ebae37SRussell King } 388c8ebae37SRussell King 389c8ebae37SRussell King static void mmci_dma_data_error(struct mmci_host *host) 390c8ebae37SRussell King { 391c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 392c8ebae37SRussell King dmaengine_terminate_all(host->dma_current); 393c8ebae37SRussell King } 394c8ebae37SRussell King 39558c7ccbfSPer Forlin static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 39658c7ccbfSPer Forlin struct mmci_host_next *next) 397c8ebae37SRussell King { 398c8ebae37SRussell King struct variant_data *variant = host->variant; 399c8ebae37SRussell King struct dma_slave_config conf = { 400c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 401c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 402c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 403c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 404c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 405c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 406258aea76SViresh Kumar .device_fc = false, 407c8ebae37SRussell King }; 408c8ebae37SRussell King struct dma_chan *chan; 409c8ebae37SRussell King struct dma_device *device; 410c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 41105f5799cSVinod Koul enum dma_data_direction buffer_dirn; 412c8ebae37SRussell King int nr_sg; 413c8ebae37SRussell King 41458c7ccbfSPer Forlin /* Check if next job is already prepared */ 41558c7ccbfSPer Forlin if (data->host_cookie && !next && 41658c7ccbfSPer Forlin host->dma_current && host->dma_desc_current) 41758c7ccbfSPer Forlin return 0; 41858c7ccbfSPer Forlin 41958c7ccbfSPer Forlin if (!next) { 420c8ebae37SRussell King host->dma_current = NULL; 42158c7ccbfSPer Forlin host->dma_desc_current = NULL; 42258c7ccbfSPer Forlin } 423c8ebae37SRussell King 424c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 42505f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 42605f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 427c8ebae37SRussell King chan = host->dma_rx_channel; 428c8ebae37SRussell King } else { 42905f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 43005f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 431c8ebae37SRussell King chan = host->dma_tx_channel; 432c8ebae37SRussell King } 433c8ebae37SRussell King 434c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 435c8ebae37SRussell King if (!chan) 436c8ebae37SRussell King return -EINVAL; 437c8ebae37SRussell King 438c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 43958c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 440c8ebae37SRussell King return -EINVAL; 441c8ebae37SRussell King 442c8ebae37SRussell King device = chan->device; 44305f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 444c8ebae37SRussell King if (nr_sg == 0) 445c8ebae37SRussell King return -EINVAL; 446c8ebae37SRussell King 447c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 44816052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 449c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 450c8ebae37SRussell King if (!desc) 451c8ebae37SRussell King goto unmap_exit; 452c8ebae37SRussell King 45358c7ccbfSPer Forlin if (next) { 45458c7ccbfSPer Forlin next->dma_chan = chan; 45558c7ccbfSPer Forlin next->dma_desc = desc; 45658c7ccbfSPer Forlin } else { 457c8ebae37SRussell King host->dma_current = chan; 45858c7ccbfSPer Forlin host->dma_desc_current = desc; 45958c7ccbfSPer Forlin } 460c8ebae37SRussell King 46158c7ccbfSPer Forlin return 0; 46258c7ccbfSPer Forlin 46358c7ccbfSPer Forlin unmap_exit: 46458c7ccbfSPer Forlin if (!next) 46558c7ccbfSPer Forlin dmaengine_terminate_all(chan); 46605f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 46758c7ccbfSPer Forlin return -ENOMEM; 46858c7ccbfSPer Forlin } 46958c7ccbfSPer Forlin 47058c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 47158c7ccbfSPer Forlin { 47258c7ccbfSPer Forlin int ret; 47358c7ccbfSPer Forlin struct mmc_data *data = host->data; 47458c7ccbfSPer Forlin 47558c7ccbfSPer Forlin ret = mmci_dma_prep_data(host, host->data, NULL); 47658c7ccbfSPer Forlin if (ret) 47758c7ccbfSPer Forlin return ret; 47858c7ccbfSPer Forlin 47958c7ccbfSPer Forlin /* Okay, go for it. */ 480c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 481c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 482c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 48358c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 48458c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 485c8ebae37SRussell King 486c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 487c8ebae37SRussell King 488c8ebae37SRussell King /* Trigger the DMA transfer */ 489c8ebae37SRussell King writel(datactrl, host->base + MMCIDATACTRL); 490c8ebae37SRussell King 491c8ebae37SRussell King /* 492c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 493c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 494c8ebae37SRussell King * call mmci_data_end() 495c8ebae37SRussell King */ 496c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 497c8ebae37SRussell King host->base + MMCIMASK0); 498c8ebae37SRussell King return 0; 499c8ebae37SRussell King } 50058c7ccbfSPer Forlin 50158c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 50258c7ccbfSPer Forlin { 50358c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 50458c7ccbfSPer Forlin 50558c7ccbfSPer Forlin if (data->host_cookie && data->host_cookie != next->cookie) { 506a3c76eb9SGirish K S pr_warning("[%s] invalid cookie: data->host_cookie %d" 50758c7ccbfSPer Forlin " host->next_data.cookie %d\n", 50858c7ccbfSPer Forlin __func__, data->host_cookie, host->next_data.cookie); 50958c7ccbfSPer Forlin data->host_cookie = 0; 51058c7ccbfSPer Forlin } 51158c7ccbfSPer Forlin 51258c7ccbfSPer Forlin if (!data->host_cookie) 51358c7ccbfSPer Forlin return; 51458c7ccbfSPer Forlin 51558c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 51658c7ccbfSPer Forlin host->dma_current = next->dma_chan; 51758c7ccbfSPer Forlin 51858c7ccbfSPer Forlin next->dma_desc = NULL; 51958c7ccbfSPer Forlin next->dma_chan = NULL; 52058c7ccbfSPer Forlin } 52158c7ccbfSPer Forlin 52258c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 52358c7ccbfSPer Forlin bool is_first_req) 52458c7ccbfSPer Forlin { 52558c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 52658c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 52758c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 52858c7ccbfSPer Forlin 52958c7ccbfSPer Forlin if (!data) 53058c7ccbfSPer Forlin return; 53158c7ccbfSPer Forlin 53258c7ccbfSPer Forlin if (data->host_cookie) { 53358c7ccbfSPer Forlin data->host_cookie = 0; 53458c7ccbfSPer Forlin return; 53558c7ccbfSPer Forlin } 53658c7ccbfSPer Forlin 53758c7ccbfSPer Forlin /* if config for dma */ 53858c7ccbfSPer Forlin if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 53958c7ccbfSPer Forlin ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 54058c7ccbfSPer Forlin if (mmci_dma_prep_data(host, data, nd)) 54158c7ccbfSPer Forlin data->host_cookie = 0; 54258c7ccbfSPer Forlin else 54358c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 54458c7ccbfSPer Forlin } 54558c7ccbfSPer Forlin } 54658c7ccbfSPer Forlin 54758c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 54858c7ccbfSPer Forlin int err) 54958c7ccbfSPer Forlin { 55058c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 55158c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 55258c7ccbfSPer Forlin struct dma_chan *chan; 55358c7ccbfSPer Forlin enum dma_data_direction dir; 55458c7ccbfSPer Forlin 55558c7ccbfSPer Forlin if (!data) 55658c7ccbfSPer Forlin return; 55758c7ccbfSPer Forlin 55858c7ccbfSPer Forlin if (data->flags & MMC_DATA_READ) { 55958c7ccbfSPer Forlin dir = DMA_FROM_DEVICE; 56058c7ccbfSPer Forlin chan = host->dma_rx_channel; 56158c7ccbfSPer Forlin } else { 56258c7ccbfSPer Forlin dir = DMA_TO_DEVICE; 56358c7ccbfSPer Forlin chan = host->dma_tx_channel; 56458c7ccbfSPer Forlin } 56558c7ccbfSPer Forlin 56658c7ccbfSPer Forlin 56758c7ccbfSPer Forlin /* if config for dma */ 56858c7ccbfSPer Forlin if (chan) { 56958c7ccbfSPer Forlin if (err) 57058c7ccbfSPer Forlin dmaengine_terminate_all(chan); 5718e3336b1SPer Forlin if (data->host_cookie) 57258c7ccbfSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 57358c7ccbfSPer Forlin data->sg_len, dir); 57458c7ccbfSPer Forlin mrq->data->host_cookie = 0; 57558c7ccbfSPer Forlin } 57658c7ccbfSPer Forlin } 57758c7ccbfSPer Forlin 578c8ebae37SRussell King #else 579c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 58058c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 58158c7ccbfSPer Forlin { 58258c7ccbfSPer Forlin } 583c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 584c8ebae37SRussell King { 585c8ebae37SRussell King } 586c8ebae37SRussell King 587c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 588c8ebae37SRussell King { 589c8ebae37SRussell King } 590c8ebae37SRussell King 591c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 592c8ebae37SRussell King { 593c8ebae37SRussell King } 594c8ebae37SRussell King 595c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 596c8ebae37SRussell King { 597c8ebae37SRussell King } 598c8ebae37SRussell King 599c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 600c8ebae37SRussell King { 601c8ebae37SRussell King return -ENOSYS; 602c8ebae37SRussell King } 60358c7ccbfSPer Forlin 60458c7ccbfSPer Forlin #define mmci_pre_request NULL 60558c7ccbfSPer Forlin #define mmci_post_request NULL 60658c7ccbfSPer Forlin 607c8ebae37SRussell King #endif 608c8ebae37SRussell King 6091c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 6101c6a0718SPierre Ossman { 6118301bb68SRabin Vincent struct variant_data *variant = host->variant; 6121c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 6131c6a0718SPierre Ossman unsigned long long clks; 6141c6a0718SPierre Ossman void __iomem *base; 6151c6a0718SPierre Ossman int blksz_bits; 6161c6a0718SPierre Ossman 61764de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 6181c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 6191c6a0718SPierre Ossman 6201c6a0718SPierre Ossman host->data = data; 621528320dbSRabin Vincent host->size = data->blksz * data->blocks; 62251d4375dSRussell King data->bytes_xfered = 0; 6231c6a0718SPierre Ossman 6241c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 6251c6a0718SPierre Ossman do_div(clks, 1000000000UL); 6261c6a0718SPierre Ossman 6271c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 6281c6a0718SPierre Ossman 6291c6a0718SPierre Ossman base = host->base; 6301c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 6311c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 6321c6a0718SPierre Ossman 6331c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 6341c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 6351c6a0718SPierre Ossman 6361784b157SPhilippe Langlais if (variant->blksz_datactrl16) 6371784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 6381784b157SPhilippe Langlais else 6391c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 640c8ebae37SRussell King 641c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 6421c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 643c8ebae37SRussell King 6447258db7eSUlf Hansson /* The ST Micro variants has a special bit to enable SDIO */ 6457258db7eSUlf Hansson if (variant->sdio && host->mmc->card) 6467258db7eSUlf Hansson if (mmc_card_sdio(host->mmc->card)) 6477258db7eSUlf Hansson datactrl |= MCI_ST_DPSM_SDIOEN; 6487258db7eSUlf Hansson 649c8ebae37SRussell King /* 650c8ebae37SRussell King * Attempt to use DMA operation mode, if this 651c8ebae37SRussell King * should fail, fall back to PIO mode 652c8ebae37SRussell King */ 653c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 654c8ebae37SRussell King return; 655c8ebae37SRussell King 656c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 657c8ebae37SRussell King mmci_init_sg(host, data); 658c8ebae37SRussell King 659c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 6601c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 6611c6a0718SPierre Ossman 6621c6a0718SPierre Ossman /* 663c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 664c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 665c4d877c1SRussell King * is available. 6661c6a0718SPierre Ossman */ 667c4d877c1SRussell King if (host->size < variant->fifohalfsize) 6681c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 6691c6a0718SPierre Ossman } else { 6701c6a0718SPierre Ossman /* 6711c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 6721c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 6731c6a0718SPierre Ossman */ 6741c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 6751c6a0718SPierre Ossman } 6761c6a0718SPierre Ossman 6771c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 6781c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 6792686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 6801c6a0718SPierre Ossman } 6811c6a0718SPierre Ossman 6821c6a0718SPierre Ossman static void 6831c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 6841c6a0718SPierre Ossman { 6851c6a0718SPierre Ossman void __iomem *base = host->base; 6861c6a0718SPierre Ossman 68764de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 6881c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 6891c6a0718SPierre Ossman 6901c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 6911c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 6921c6a0718SPierre Ossman udelay(1); 6931c6a0718SPierre Ossman } 6941c6a0718SPierre Ossman 6951c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 6961c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 6971c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 6981c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 6991c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 7001c6a0718SPierre Ossman } 7011c6a0718SPierre Ossman if (/*interrupt*/0) 7021c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 7031c6a0718SPierre Ossman 7041c6a0718SPierre Ossman host->cmd = cmd; 7051c6a0718SPierre Ossman 7061c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 7071c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 7081c6a0718SPierre Ossman } 7091c6a0718SPierre Ossman 7101c6a0718SPierre Ossman static void 7111c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 7121c6a0718SPierre Ossman unsigned int status) 7131c6a0718SPierre Ossman { 714f20f8f21SLinus Walleij /* First check for errors */ 715b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 716b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 7178cb28155SLinus Walleij u32 remain, success; 718f20f8f21SLinus Walleij 719c8ebae37SRussell King /* Terminate the DMA transfer */ 720c8ebae37SRussell King if (dma_inprogress(host)) 721c8ebae37SRussell King mmci_dma_data_error(host); 722c8ebae37SRussell King 723c8afc9d5SRussell King /* 724c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 725c8afc9d5SRussell King * the data counter gives the number of bytes transferred 726c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 727c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 728c8afc9d5SRussell King * matters for FIFO overruns only. 729c8afc9d5SRussell King */ 730f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 7318cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 7328cb28155SLinus Walleij 733c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 734c8afc9d5SRussell King status, success); 7358cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 7368cb28155SLinus Walleij /* Last block was not successful */ 737c8afc9d5SRussell King success -= 1; 73817b0429dSPierre Ossman data->error = -EILSEQ; 7398cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 74017b0429dSPierre Ossman data->error = -ETIMEDOUT; 741757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 742757df746SLinus Walleij data->error = -ECOMM; 743c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 74417b0429dSPierre Ossman data->error = -EIO; 745c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 746c8afc9d5SRussell King if (success > host->variant->fifosize) 747c8afc9d5SRussell King success -= host->variant->fifosize; 748c8afc9d5SRussell King else 749c8afc9d5SRussell King success = 0; 7508cb28155SLinus Walleij data->error = -EIO; 7514ce1d6cbSRabin Vincent } 75251d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 7531c6a0718SPierre Ossman } 754f20f8f21SLinus Walleij 7558cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 7568cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 757f20f8f21SLinus Walleij 758ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 759c8ebae37SRussell King if (dma_inprogress(host)) 760c8ebae37SRussell King mmci_dma_unmap(host, data); 7611c6a0718SPierre Ossman mmci_stop_data(host); 7621c6a0718SPierre Ossman 7638cb28155SLinus Walleij if (!data->error) 7648cb28155SLinus Walleij /* The error clause is handled above, success! */ 76551d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 766f20f8f21SLinus Walleij 7671c6a0718SPierre Ossman if (!data->stop) { 7681c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 7691c6a0718SPierre Ossman } else { 7701c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 7711c6a0718SPierre Ossman } 7721c6a0718SPierre Ossman } 7731c6a0718SPierre Ossman } 7741c6a0718SPierre Ossman 7751c6a0718SPierre Ossman static void 7761c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 7771c6a0718SPierre Ossman unsigned int status) 7781c6a0718SPierre Ossman { 7791c6a0718SPierre Ossman void __iomem *base = host->base; 7801c6a0718SPierre Ossman 7811c6a0718SPierre Ossman host->cmd = NULL; 7821c6a0718SPierre Ossman 7831c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 78417b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 7851c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 78617b0429dSPierre Ossman cmd->error = -EILSEQ; 7879047b435SRussell King - ARM Linux } else { 7889047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 7899047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 7909047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 7919047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 7921c6a0718SPierre Ossman } 7931c6a0718SPierre Ossman 79417b0429dSPierre Ossman if (!cmd->data || cmd->error) { 7953b6e3c73SUlf Hansson if (host->data) { 7963b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 7973b6e3c73SUlf Hansson if (dma_inprogress(host)) 7983b6e3c73SUlf Hansson mmci_dma_data_error(host); 7991c6a0718SPierre Ossman mmci_stop_data(host); 8003b6e3c73SUlf Hansson } 8011c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 8021c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 8031c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 8041c6a0718SPierre Ossman } 8051c6a0718SPierre Ossman } 8061c6a0718SPierre Ossman 8071c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 8081c6a0718SPierre Ossman { 8091c6a0718SPierre Ossman void __iomem *base = host->base; 8101c6a0718SPierre Ossman char *ptr = buffer; 8111c6a0718SPierre Ossman u32 status; 81226eed9a5SLinus Walleij int host_remain = host->size; 8131c6a0718SPierre Ossman 8141c6a0718SPierre Ossman do { 81526eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 8161c6a0718SPierre Ossman 8171c6a0718SPierre Ossman if (count > remain) 8181c6a0718SPierre Ossman count = remain; 8191c6a0718SPierre Ossman 8201c6a0718SPierre Ossman if (count <= 0) 8211c6a0718SPierre Ossman break; 8221c6a0718SPierre Ossman 823393e5e24SUlf Hansson /* 824393e5e24SUlf Hansson * SDIO especially may want to send something that is 825393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 826393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 827393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 828393e5e24SUlf Hansson */ 829393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 830393e5e24SUlf Hansson if (count < 4) { 831393e5e24SUlf Hansson unsigned char buf[4]; 832393e5e24SUlf Hansson readsl(base + MMCIFIFO, buf, 1); 833393e5e24SUlf Hansson memcpy(ptr, buf, count); 834393e5e24SUlf Hansson } else { 8351c6a0718SPierre Ossman readsl(base + MMCIFIFO, ptr, count >> 2); 836393e5e24SUlf Hansson count &= ~0x3; 837393e5e24SUlf Hansson } 838393e5e24SUlf Hansson } else { 839393e5e24SUlf Hansson readsl(base + MMCIFIFO, ptr, count >> 2); 840393e5e24SUlf Hansson } 8411c6a0718SPierre Ossman 8421c6a0718SPierre Ossman ptr += count; 8431c6a0718SPierre Ossman remain -= count; 84426eed9a5SLinus Walleij host_remain -= count; 8451c6a0718SPierre Ossman 8461c6a0718SPierre Ossman if (remain == 0) 8471c6a0718SPierre Ossman break; 8481c6a0718SPierre Ossman 8491c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8501c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 8511c6a0718SPierre Ossman 8521c6a0718SPierre Ossman return ptr - buffer; 8531c6a0718SPierre Ossman } 8541c6a0718SPierre Ossman 8551c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 8561c6a0718SPierre Ossman { 8578301bb68SRabin Vincent struct variant_data *variant = host->variant; 8581c6a0718SPierre Ossman void __iomem *base = host->base; 8591c6a0718SPierre Ossman char *ptr = buffer; 8601c6a0718SPierre Ossman 8611c6a0718SPierre Ossman do { 8621c6a0718SPierre Ossman unsigned int count, maxcnt; 8631c6a0718SPierre Ossman 8648301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 8658301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 8661c6a0718SPierre Ossman count = min(remain, maxcnt); 8671c6a0718SPierre Ossman 86834177802SLinus Walleij /* 86934177802SLinus Walleij * The ST Micro variant for SDIO transfer sizes 87034177802SLinus Walleij * less then 8 bytes should have clock H/W flow 87134177802SLinus Walleij * control disabled. 87234177802SLinus Walleij */ 87334177802SLinus Walleij if (variant->sdio && 87434177802SLinus Walleij mmc_card_sdio(host->mmc->card)) { 8757437cfa5SUlf Hansson u32 clk; 87634177802SLinus Walleij if (count < 8) 8777437cfa5SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 87834177802SLinus Walleij else 8797437cfa5SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 8807437cfa5SUlf Hansson 8817437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 88234177802SLinus Walleij } 88334177802SLinus Walleij 88434177802SLinus Walleij /* 88534177802SLinus Walleij * SDIO especially may want to send something that is 88634177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 88734177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 88834177802SLinus Walleij * So compensate by adding +3 on the count, a single 88934177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 89034177802SLinus Walleij * 32bit writes etc. 89134177802SLinus Walleij */ 89234177802SLinus Walleij writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 8931c6a0718SPierre Ossman 8941c6a0718SPierre Ossman ptr += count; 8951c6a0718SPierre Ossman remain -= count; 8961c6a0718SPierre Ossman 8971c6a0718SPierre Ossman if (remain == 0) 8981c6a0718SPierre Ossman break; 8991c6a0718SPierre Ossman 9001c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9011c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 9021c6a0718SPierre Ossman 9031c6a0718SPierre Ossman return ptr - buffer; 9041c6a0718SPierre Ossman } 9051c6a0718SPierre Ossman 9061c6a0718SPierre Ossman /* 9071c6a0718SPierre Ossman * PIO data transfer IRQ handler. 9081c6a0718SPierre Ossman */ 9091c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 9101c6a0718SPierre Ossman { 9111c6a0718SPierre Ossman struct mmci_host *host = dev_id; 9124ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 9138301bb68SRabin Vincent struct variant_data *variant = host->variant; 9141c6a0718SPierre Ossman void __iomem *base = host->base; 9154ce1d6cbSRabin Vincent unsigned long flags; 9161c6a0718SPierre Ossman u32 status; 9171c6a0718SPierre Ossman 9181c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9191c6a0718SPierre Ossman 92064de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 9211c6a0718SPierre Ossman 9224ce1d6cbSRabin Vincent local_irq_save(flags); 9234ce1d6cbSRabin Vincent 9241c6a0718SPierre Ossman do { 9251c6a0718SPierre Ossman unsigned int remain, len; 9261c6a0718SPierre Ossman char *buffer; 9271c6a0718SPierre Ossman 9281c6a0718SPierre Ossman /* 9291c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 9301c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 9311c6a0718SPierre Ossman * definition it is more than half empty. 9321c6a0718SPierre Ossman * 9331c6a0718SPierre Ossman * For read, check for data available. 9341c6a0718SPierre Ossman */ 9351c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 9361c6a0718SPierre Ossman break; 9371c6a0718SPierre Ossman 9384ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 9394ce1d6cbSRabin Vincent break; 9404ce1d6cbSRabin Vincent 9414ce1d6cbSRabin Vincent buffer = sg_miter->addr; 9424ce1d6cbSRabin Vincent remain = sg_miter->length; 9431c6a0718SPierre Ossman 9441c6a0718SPierre Ossman len = 0; 9451c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 9461c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 9471c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 9481c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 9491c6a0718SPierre Ossman 9504ce1d6cbSRabin Vincent sg_miter->consumed = len; 9511c6a0718SPierre Ossman 9521c6a0718SPierre Ossman host->size -= len; 9531c6a0718SPierre Ossman remain -= len; 9541c6a0718SPierre Ossman 9551c6a0718SPierre Ossman if (remain) 9561c6a0718SPierre Ossman break; 9571c6a0718SPierre Ossman 9581c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9591c6a0718SPierre Ossman } while (1); 9601c6a0718SPierre Ossman 9614ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 9624ce1d6cbSRabin Vincent 9634ce1d6cbSRabin Vincent local_irq_restore(flags); 9644ce1d6cbSRabin Vincent 9651c6a0718SPierre Ossman /* 966c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 967c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 9681c6a0718SPierre Ossman */ 969c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 9702686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 9711c6a0718SPierre Ossman 9721c6a0718SPierre Ossman /* 9731c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 9741c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 9751c6a0718SPierre Ossman * the chip itself has disabled the data path, and 9761c6a0718SPierre Ossman * stops us racing with our data end IRQ. 9771c6a0718SPierre Ossman */ 9781c6a0718SPierre Ossman if (host->size == 0) { 9792686b4b4SLinus Walleij mmci_set_mask1(host, 0); 9801c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 9811c6a0718SPierre Ossman } 9821c6a0718SPierre Ossman 9831c6a0718SPierre Ossman return IRQ_HANDLED; 9841c6a0718SPierre Ossman } 9851c6a0718SPierre Ossman 9861c6a0718SPierre Ossman /* 9871c6a0718SPierre Ossman * Handle completion of command and data transfers. 9881c6a0718SPierre Ossman */ 9891c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 9901c6a0718SPierre Ossman { 9911c6a0718SPierre Ossman struct mmci_host *host = dev_id; 9921c6a0718SPierre Ossman u32 status; 9931c6a0718SPierre Ossman int ret = 0; 9941c6a0718SPierre Ossman 9951c6a0718SPierre Ossman spin_lock(&host->lock); 9961c6a0718SPierre Ossman 9971c6a0718SPierre Ossman do { 9981c6a0718SPierre Ossman struct mmc_command *cmd; 9991c6a0718SPierre Ossman struct mmc_data *data; 10001c6a0718SPierre Ossman 10011c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 10022686b4b4SLinus Walleij 10032686b4b4SLinus Walleij if (host->singleirq) { 10042686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 10052686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 10062686b4b4SLinus Walleij 10072686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 10082686b4b4SLinus Walleij } 10092686b4b4SLinus Walleij 10101c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 10111c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 10121c6a0718SPierre Ossman 101364de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 10141c6a0718SPierre Ossman 10151c6a0718SPierre Ossman data = host->data; 1016b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1017b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1018b63038d6SUlf Hansson MCI_DATABLOCKEND) && data) 10191c6a0718SPierre Ossman mmci_data_irq(host, data, status); 10201c6a0718SPierre Ossman 10211c6a0718SPierre Ossman cmd = host->cmd; 10221c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 10231c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 10241c6a0718SPierre Ossman 10251c6a0718SPierre Ossman ret = 1; 10261c6a0718SPierre Ossman } while (status); 10271c6a0718SPierre Ossman 10281c6a0718SPierre Ossman spin_unlock(&host->lock); 10291c6a0718SPierre Ossman 10301c6a0718SPierre Ossman return IRQ_RETVAL(ret); 10311c6a0718SPierre Ossman } 10321c6a0718SPierre Ossman 10331c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 10341c6a0718SPierre Ossman { 10351c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10369e943021SLinus Walleij unsigned long flags; 10371c6a0718SPierre Ossman 10381c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 10391c6a0718SPierre Ossman 1040019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 104164de0289SLinus Walleij dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 104264de0289SLinus Walleij mrq->data->blksz); 1043255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 1044255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1045255d01afSPierre Ossman return; 1046255d01afSPierre Ossman } 1047255d01afSPierre Ossman 10481c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 10491c3be369SRussell King 10509e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 10511c6a0718SPierre Ossman 10521c6a0718SPierre Ossman host->mrq = mrq; 10531c6a0718SPierre Ossman 105458c7ccbfSPer Forlin if (mrq->data) 105558c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 105658c7ccbfSPer Forlin 10571c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 10581c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 10591c6a0718SPierre Ossman 10601c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 10611c6a0718SPierre Ossman 10629e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 10631c6a0718SPierre Ossman } 10641c6a0718SPierre Ossman 10651c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 10661c6a0718SPierre Ossman { 10671c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10687d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1069a6a6464aSLinus Walleij u32 pwr = 0; 1070a6a6464aSLinus Walleij unsigned long flags; 107199fc5131SLinus Walleij int ret; 10721c6a0718SPierre Ossman 10732cd976c4SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 10742cd976c4SUlf Hansson 1075bc521818SUlf Hansson if (host->plat->ios_handler && 1076bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1077bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1078bc521818SUlf Hansson 10791c6a0718SPierre Ossman switch (ios->power_mode) { 10801c6a0718SPierre Ossman case MMC_POWER_OFF: 108199fc5131SLinus Walleij if (host->vcc) 108299fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 10831c6a0718SPierre Ossman break; 10841c6a0718SPierre Ossman case MMC_POWER_UP: 108599fc5131SLinus Walleij if (host->vcc) { 108699fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 108799fc5131SLinus Walleij if (ret) { 108899fc5131SLinus Walleij dev_err(mmc_dev(mmc), "unable to set OCR\n"); 108999fc5131SLinus Walleij /* 109099fc5131SLinus Walleij * The .set_ios() function in the mmc_host_ops 109199fc5131SLinus Walleij * struct return void, and failing to set the 109299fc5131SLinus Walleij * power should be rare so we print an error 109399fc5131SLinus Walleij * and return here. 109499fc5131SLinus Walleij */ 10952cd976c4SUlf Hansson goto out; 109699fc5131SLinus Walleij } 109799fc5131SLinus Walleij } 10987d72a1d4SUlf Hansson /* 10997d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 11007d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 11017d72a1d4SUlf Hansson * configured in the variant data. 11027d72a1d4SUlf Hansson */ 11037d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 11047d72a1d4SUlf Hansson 11051c6a0718SPierre Ossman break; 11061c6a0718SPierre Ossman case MMC_POWER_ON: 11071c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 11081c6a0718SPierre Ossman break; 11091c6a0718SPierre Ossman } 11101c6a0718SPierre Ossman 11114d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 11124d1a3a0dSUlf Hansson /* 11134d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 11144d1a3a0dSUlf Hansson * indicating signal direction for the signals in 11154d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 11164d1a3a0dSUlf Hansson */ 11174d1a3a0dSUlf Hansson pwr |= host->plat->sigdir; 11184d1a3a0dSUlf Hansson 11194d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 11204d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 11214d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 11224d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 11234d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 11244d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 11254d1a3a0dSUlf Hansson } 11264d1a3a0dSUlf Hansson 1127cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1128f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 11291c6a0718SPierre Ossman pwr |= MCI_ROD; 1130cc30d60eSLinus Walleij else { 1131cc30d60eSLinus Walleij /* 1132cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1133cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1134cc30d60eSLinus Walleij */ 1135cc30d60eSLinus Walleij pwr |= MCI_OD; 1136cc30d60eSLinus Walleij } 1137cc30d60eSLinus Walleij } 11381c6a0718SPierre Ossman 1139a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1140a6a6464aSLinus Walleij 1141a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 11427437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1143a6a6464aSLinus Walleij 1144a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 11452cd976c4SUlf Hansson 11462cd976c4SUlf Hansson out: 11472cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 11482cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 11491c6a0718SPierre Ossman } 11501c6a0718SPierre Ossman 115189001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 115289001446SRussell King { 115389001446SRussell King struct mmci_host *host = mmc_priv(mmc); 115489001446SRussell King 115589001446SRussell King if (host->gpio_wp == -ENOSYS) 115689001446SRussell King return -ENOSYS; 115789001446SRussell King 115818a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 115989001446SRussell King } 116089001446SRussell King 116189001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 116289001446SRussell King { 116389001446SRussell King struct mmci_host *host = mmc_priv(mmc); 116429719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 116589001446SRussell King unsigned int status; 116689001446SRussell King 11674b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 11684b8caec0SRabin Vincent if (!plat->status) 11694b8caec0SRabin Vincent return 1; /* Assume always present */ 11704b8caec0SRabin Vincent 117129719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 11724b8caec0SRabin Vincent } else 117318a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 117418a06301SLinus Walleij ^ plat->cd_invert; 117589001446SRussell King 117674bc8093SRussell King /* 117774bc8093SRussell King * Use positive logic throughout - status is zero for no card, 117874bc8093SRussell King * non-zero for card inserted. 117974bc8093SRussell King */ 118074bc8093SRussell King return status; 118189001446SRussell King } 118289001446SRussell King 1183148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1184148b8b39SRabin Vincent { 1185148b8b39SRabin Vincent struct mmci_host *host = dev_id; 1186148b8b39SRabin Vincent 1187148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1188148b8b39SRabin Vincent 1189148b8b39SRabin Vincent return IRQ_HANDLED; 1190148b8b39SRabin Vincent } 1191148b8b39SRabin Vincent 11921c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 11931c6a0718SPierre Ossman .request = mmci_request, 119458c7ccbfSPer Forlin .pre_req = mmci_pre_request, 119558c7ccbfSPer Forlin .post_req = mmci_post_request, 11961c6a0718SPierre Ossman .set_ios = mmci_set_ios, 119789001446SRussell King .get_ro = mmci_get_ro, 119889001446SRussell King .get_cd = mmci_get_cd, 11991c6a0718SPierre Ossman }; 12001c6a0718SPierre Ossman 1201000bc9d5SLee Jones #ifdef CONFIG_OF 1202000bc9d5SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1203000bc9d5SLee Jones struct mmci_platform_data *pdata) 1204000bc9d5SLee Jones { 1205000bc9d5SLee Jones int bus_width = 0; 1206000bc9d5SLee Jones 12079a597016SLee Jones pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1208000bc9d5SLee Jones if (!pdata->gpio_wp) 1209000bc9d5SLee Jones pdata->gpio_wp = -1; 1210000bc9d5SLee Jones 12119a597016SLee Jones pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1212000bc9d5SLee Jones if (!pdata->gpio_cd) 1213000bc9d5SLee Jones pdata->gpio_cd = -1; 1214000bc9d5SLee Jones 1215000bc9d5SLee Jones if (of_get_property(np, "cd-inverted", NULL)) 1216000bc9d5SLee Jones pdata->cd_invert = true; 1217000bc9d5SLee Jones else 1218000bc9d5SLee Jones pdata->cd_invert = false; 1219000bc9d5SLee Jones 1220000bc9d5SLee Jones of_property_read_u32(np, "max-frequency", &pdata->f_max); 1221000bc9d5SLee Jones if (!pdata->f_max) 1222000bc9d5SLee Jones pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1223000bc9d5SLee Jones 1224000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1225000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1226000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1227000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1228000bc9d5SLee Jones 1229000bc9d5SLee Jones of_property_read_u32(np, "bus-width", &bus_width); 1230000bc9d5SLee Jones switch (bus_width) { 1231000bc9d5SLee Jones case 0 : 1232000bc9d5SLee Jones /* No bus-width supplied. */ 1233000bc9d5SLee Jones break; 1234000bc9d5SLee Jones case 4 : 1235000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1236000bc9d5SLee Jones break; 1237000bc9d5SLee Jones case 8 : 1238000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1239000bc9d5SLee Jones break; 1240000bc9d5SLee Jones default : 1241000bc9d5SLee Jones pr_warn("%s: Unsupported bus width\n", np->full_name); 1242000bc9d5SLee Jones } 1243000bc9d5SLee Jones } 1244000bc9d5SLee Jones #endif 1245000bc9d5SLee Jones 1246aa25afadSRussell King static int __devinit mmci_probe(struct amba_device *dev, 1247aa25afadSRussell King const struct amba_id *id) 12481c6a0718SPierre Ossman { 12496ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1250000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 12514956e109SRabin Vincent struct variant_data *variant = id->data; 12521c6a0718SPierre Ossman struct mmci_host *host; 12531c6a0718SPierre Ossman struct mmc_host *mmc; 12541c6a0718SPierre Ossman int ret; 12551c6a0718SPierre Ossman 1256000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1257000bc9d5SLee Jones if (!plat && !np) { 1258000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1259000bc9d5SLee Jones return -EINVAL; 12601c6a0718SPierre Ossman } 12611c6a0718SPierre Ossman 1262000bc9d5SLee Jones if (np) 1263000bc9d5SLee Jones mmci_dt_populate_generic_pdata(np, plat); 1264000bc9d5SLee Jones 12651c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 12661c6a0718SPierre Ossman if (ret) 12671c6a0718SPierre Ossman goto out; 12681c6a0718SPierre Ossman 12691c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 12701c6a0718SPierre Ossman if (!mmc) { 12711c6a0718SPierre Ossman ret = -ENOMEM; 12721c6a0718SPierre Ossman goto rel_regions; 12731c6a0718SPierre Ossman } 12741c6a0718SPierre Ossman 12751c6a0718SPierre Ossman host = mmc_priv(mmc); 12764ea580f1SRabin Vincent host->mmc = mmc; 1277012b7d33SRussell King 127889001446SRussell King host->gpio_wp = -ENOSYS; 127989001446SRussell King host->gpio_cd = -ENOSYS; 1280148b8b39SRabin Vincent host->gpio_cd_irq = -1; 128189001446SRussell King 1282012b7d33SRussell King host->hw_designer = amba_manf(dev); 1283012b7d33SRussell King host->hw_revision = amba_rev(dev); 128464de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 128564de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1286012b7d33SRussell King 1287ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 12881c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 12891c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 12901c6a0718SPierre Ossman host->clk = NULL; 12911c6a0718SPierre Ossman goto host_free; 12921c6a0718SPierre Ossman } 12931c6a0718SPierre Ossman 129452ca0f3aSRussell King ret = clk_prepare(host->clk); 12951c6a0718SPierre Ossman if (ret) 12961c6a0718SPierre Ossman goto clk_free; 12971c6a0718SPierre Ossman 129852ca0f3aSRussell King ret = clk_enable(host->clk); 129952ca0f3aSRussell King if (ret) 130052ca0f3aSRussell King goto clk_unprep; 130152ca0f3aSRussell King 13021c6a0718SPierre Ossman host->plat = plat; 13034956e109SRabin Vincent host->variant = variant; 13041c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1305c8df9a53SLinus Walleij /* 1306c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1307c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1308c8df9a53SLinus Walleij * (if possible). 1309c8df9a53SLinus Walleij */ 1310c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1311c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1312c8df9a53SLinus Walleij if (ret < 0) 1313c8df9a53SLinus Walleij goto clk_disable; 1314c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 131564de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 131664de0289SLinus Walleij host->mclk); 1317c8df9a53SLinus Walleij } 1318c8ebae37SRussell King host->phybase = dev->res.start; 1319dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 13201c6a0718SPierre Ossman if (!host->base) { 13211c6a0718SPierre Ossman ret = -ENOMEM; 13221c6a0718SPierre Ossman goto clk_disable; 13231c6a0718SPierre Ossman } 13241c6a0718SPierre Ossman 13251c6a0718SPierre Ossman mmc->ops = &mmci_ops; 13267f294e49SLinus Walleij /* 13277f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 13287f294e49SLinus Walleij * clock divider equations which means that the minimum divider 13297f294e49SLinus Walleij * differs too. 13307f294e49SLinus Walleij */ 13317f294e49SLinus Walleij if (variant->st_clkdiv) 13327f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 13337f294e49SLinus Walleij else 13347f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1335808d97ccSLinus Walleij /* 1336808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1337808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1338808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1339808d97ccSLinus Walleij * default value in case it is not specified. Either 1340808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1341808d97ccSLinus Walleij * of course. 1342808d97ccSLinus Walleij */ 1343808d97ccSLinus Walleij if (plat->f_max) 1344808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1345808d97ccSLinus Walleij else 13461c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 134764de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 134864de0289SLinus Walleij 134934e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 135034e84f39SLinus Walleij /* If we're using the regulator framework, try to fetch a regulator */ 135134e84f39SLinus Walleij host->vcc = regulator_get(&dev->dev, "vmmc"); 135234e84f39SLinus Walleij if (IS_ERR(host->vcc)) 135334e84f39SLinus Walleij host->vcc = NULL; 135434e84f39SLinus Walleij else { 135534e84f39SLinus Walleij int mask = mmc_regulator_get_ocrmask(host->vcc); 135634e84f39SLinus Walleij 135734e84f39SLinus Walleij if (mask < 0) 135834e84f39SLinus Walleij dev_err(&dev->dev, "error getting OCR mask (%d)\n", 135934e84f39SLinus Walleij mask); 136034e84f39SLinus Walleij else { 136134e84f39SLinus Walleij host->mmc->ocr_avail = (u32) mask; 136234e84f39SLinus Walleij if (plat->ocr_mask) 136334e84f39SLinus Walleij dev_warn(&dev->dev, 136434e84f39SLinus Walleij "Provided ocr_mask/setpower will not be used " 136534e84f39SLinus Walleij "(using regulator instead)\n"); 136634e84f39SLinus Walleij } 136734e84f39SLinus Walleij } 136834e84f39SLinus Walleij #endif 136934e84f39SLinus Walleij /* Fall back to platform data if no regulator is found */ 137034e84f39SLinus Walleij if (host->vcc == NULL) 13711c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 13729e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 13735a092627SPer Forlin mmc->caps2 = plat->capabilities2; 13741c6a0718SPierre Ossman 13751c6a0718SPierre Ossman /* 13761c6a0718SPierre Ossman * We can do SGIO 13771c6a0718SPierre Ossman */ 1378a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 13791c6a0718SPierre Ossman 13801c6a0718SPierre Ossman /* 138108458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 138208458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 138308458ef6SRabin Vincent * single request. 13841c6a0718SPierre Ossman */ 138508458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 13861c6a0718SPierre Ossman 13871c6a0718SPierre Ossman /* 13881c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 13891c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 13901c6a0718SPierre Ossman */ 13911c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 13921c6a0718SPierre Ossman 13931c6a0718SPierre Ossman /* 13941c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 13951c6a0718SPierre Ossman */ 13968f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 13971c6a0718SPierre Ossman 13981c6a0718SPierre Ossman /* 13998f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 14008f7f6b7eSWill Deacon * the maximum request size. 14011c6a0718SPierre Ossman */ 14028f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 14031c6a0718SPierre Ossman 14041c6a0718SPierre Ossman spin_lock_init(&host->lock); 14051c6a0718SPierre Ossman 14061c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14071c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 14081c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 14091c6a0718SPierre Ossman 141089001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 141189001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 141289001446SRussell King if (ret == 0) 141389001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 141489001446SRussell King if (ret == 0) 141589001446SRussell King host->gpio_cd = plat->gpio_cd; 141689001446SRussell King else if (ret != -ENOSYS) 141789001446SRussell King goto err_gpio_cd; 1418148b8b39SRabin Vincent 141917ee083bSLinus Walleij /* 142017ee083bSLinus Walleij * A gpio pin that will detect cards when inserted and removed 142117ee083bSLinus Walleij * will most likely want to trigger on the edges if it is 142217ee083bSLinus Walleij * 0 when ejected and 1 when inserted (or mutatis mutandis 142317ee083bSLinus Walleij * for the inverted case) so we request triggers on both 142417ee083bSLinus Walleij * edges. 142517ee083bSLinus Walleij */ 1426148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 142717ee083bSLinus Walleij mmci_cd_irq, 142817ee083bSLinus Walleij IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1429148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1430148b8b39SRabin Vincent if (ret >= 0) 1431148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 143289001446SRussell King } 143389001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 143489001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 143589001446SRussell King if (ret == 0) 143689001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 143789001446SRussell King if (ret == 0) 143889001446SRussell King host->gpio_wp = plat->gpio_wp; 143989001446SRussell King else if (ret != -ENOSYS) 144089001446SRussell King goto err_gpio_wp; 144189001446SRussell King } 144289001446SRussell King 14434b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 14444b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1445148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1446148b8b39SRabin Vincent 14471c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 14481c6a0718SPierre Ossman if (ret) 14491c6a0718SPierre Ossman goto unmap; 14501c6a0718SPierre Ossman 1451023f117cSRussell King if (dev->irq[1] == NO_IRQ || !dev->irq[1]) 14522686b4b4SLinus Walleij host->singleirq = true; 14532686b4b4SLinus Walleij else { 14542686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 14552686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 14561c6a0718SPierre Ossman if (ret) 14571c6a0718SPierre Ossman goto irq0_free; 14582686b4b4SLinus Walleij } 14591c6a0718SPierre Ossman 14608cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 14611c6a0718SPierre Ossman 14621c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 14631c6a0718SPierre Ossman 1464c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1465c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1466c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1467c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1468c8ebae37SRussell King 1469c8ebae37SRussell King mmci_dma_setup(host); 14701c6a0718SPierre Ossman 14712cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 14722cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 14731c3be369SRussell King pm_runtime_put(&dev->dev); 14741c3be369SRussell King 14758c11a94dSRussell King mmc_add_host(mmc); 14768c11a94dSRussell King 14771c6a0718SPierre Ossman return 0; 14781c6a0718SPierre Ossman 14791c6a0718SPierre Ossman irq0_free: 14801c6a0718SPierre Ossman free_irq(dev->irq[0], host); 14811c6a0718SPierre Ossman unmap: 148289001446SRussell King if (host->gpio_wp != -ENOSYS) 148389001446SRussell King gpio_free(host->gpio_wp); 148489001446SRussell King err_gpio_wp: 1485148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1486148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 148789001446SRussell King if (host->gpio_cd != -ENOSYS) 148889001446SRussell King gpio_free(host->gpio_cd); 148989001446SRussell King err_gpio_cd: 14901c6a0718SPierre Ossman iounmap(host->base); 14911c6a0718SPierre Ossman clk_disable: 14921c6a0718SPierre Ossman clk_disable(host->clk); 149352ca0f3aSRussell King clk_unprep: 149452ca0f3aSRussell King clk_unprepare(host->clk); 14951c6a0718SPierre Ossman clk_free: 14961c6a0718SPierre Ossman clk_put(host->clk); 14971c6a0718SPierre Ossman host_free: 14981c6a0718SPierre Ossman mmc_free_host(mmc); 14991c6a0718SPierre Ossman rel_regions: 15001c6a0718SPierre Ossman amba_release_regions(dev); 15011c6a0718SPierre Ossman out: 15021c6a0718SPierre Ossman return ret; 15031c6a0718SPierre Ossman } 15041c6a0718SPierre Ossman 15056dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 15061c6a0718SPierre Ossman { 15071c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 15081c6a0718SPierre Ossman 15091c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 15101c6a0718SPierre Ossman 15111c6a0718SPierre Ossman if (mmc) { 15121c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15131c6a0718SPierre Ossman 15141c3be369SRussell King /* 15151c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 15161c3be369SRussell King * version here so that we can access the primecell. 15171c3be369SRussell King */ 15181c3be369SRussell King pm_runtime_get_sync(&dev->dev); 15191c3be369SRussell King 15201c6a0718SPierre Ossman mmc_remove_host(mmc); 15211c6a0718SPierre Ossman 15221c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 15231c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 15241c6a0718SPierre Ossman 15251c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 15261c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 15271c6a0718SPierre Ossman 1528c8ebae37SRussell King mmci_dma_release(host); 15291c6a0718SPierre Ossman free_irq(dev->irq[0], host); 15302686b4b4SLinus Walleij if (!host->singleirq) 15311c6a0718SPierre Ossman free_irq(dev->irq[1], host); 15321c6a0718SPierre Ossman 153389001446SRussell King if (host->gpio_wp != -ENOSYS) 153489001446SRussell King gpio_free(host->gpio_wp); 1535148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1536148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 153789001446SRussell King if (host->gpio_cd != -ENOSYS) 153889001446SRussell King gpio_free(host->gpio_cd); 153989001446SRussell King 15401c6a0718SPierre Ossman iounmap(host->base); 15411c6a0718SPierre Ossman clk_disable(host->clk); 154252ca0f3aSRussell King clk_unprepare(host->clk); 15431c6a0718SPierre Ossman clk_put(host->clk); 15441c6a0718SPierre Ossman 154599fc5131SLinus Walleij if (host->vcc) 154699fc5131SLinus Walleij mmc_regulator_set_ocr(mmc, host->vcc, 0); 154734e84f39SLinus Walleij regulator_put(host->vcc); 154834e84f39SLinus Walleij 15491c6a0718SPierre Ossman mmc_free_host(mmc); 15501c6a0718SPierre Ossman 15511c6a0718SPierre Ossman amba_release_regions(dev); 15521c6a0718SPierre Ossman } 15531c6a0718SPierre Ossman 15541c6a0718SPierre Ossman return 0; 15551c6a0718SPierre Ossman } 15561c6a0718SPierre Ossman 155748fa7003SUlf Hansson #ifdef CONFIG_SUSPEND 155848fa7003SUlf Hansson static int mmci_suspend(struct device *dev) 15591c6a0718SPierre Ossman { 156048fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 156148fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 15621c6a0718SPierre Ossman int ret = 0; 15631c6a0718SPierre Ossman 15641c6a0718SPierre Ossman if (mmc) { 15651c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15661c6a0718SPierre Ossman 15671a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 15682cd976c4SUlf Hansson if (ret == 0) { 15692cd976c4SUlf Hansson pm_runtime_get_sync(dev); 15701c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 15711c6a0718SPierre Ossman } 15722cd976c4SUlf Hansson } 15731c6a0718SPierre Ossman 15741c6a0718SPierre Ossman return ret; 15751c6a0718SPierre Ossman } 15761c6a0718SPierre Ossman 157748fa7003SUlf Hansson static int mmci_resume(struct device *dev) 15781c6a0718SPierre Ossman { 157948fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 158048fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 15811c6a0718SPierre Ossman int ret = 0; 15821c6a0718SPierre Ossman 15831c6a0718SPierre Ossman if (mmc) { 15841c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15851c6a0718SPierre Ossman 15861c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 15872cd976c4SUlf Hansson pm_runtime_put(dev); 15881c6a0718SPierre Ossman 15891c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 15901c6a0718SPierre Ossman } 15911c6a0718SPierre Ossman 15921c6a0718SPierre Ossman return ret; 15931c6a0718SPierre Ossman } 15941c6a0718SPierre Ossman #endif 15951c6a0718SPierre Ossman 159648fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 159748fa7003SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 159848fa7003SUlf Hansson }; 159948fa7003SUlf Hansson 16001c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 16011c6a0718SPierre Ossman { 16021c6a0718SPierre Ossman .id = 0x00041180, 1603768fbc18SPawel Moll .mask = 0xff0fffff, 16044956e109SRabin Vincent .data = &variant_arm, 16051c6a0718SPierre Ossman }, 16061c6a0718SPierre Ossman { 1607768fbc18SPawel Moll .id = 0x01041180, 1608768fbc18SPawel Moll .mask = 0xff0fffff, 1609768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1610768fbc18SPawel Moll }, 1611768fbc18SPawel Moll { 16121c6a0718SPierre Ossman .id = 0x00041181, 16131c6a0718SPierre Ossman .mask = 0x000fffff, 16144956e109SRabin Vincent .data = &variant_arm, 16151c6a0718SPierre Ossman }, 1616cc30d60eSLinus Walleij /* ST Micro variants */ 1617cc30d60eSLinus Walleij { 1618cc30d60eSLinus Walleij .id = 0x00180180, 1619cc30d60eSLinus Walleij .mask = 0x00ffffff, 16204956e109SRabin Vincent .data = &variant_u300, 1621cc30d60eSLinus Walleij }, 1622cc30d60eSLinus Walleij { 1623cc30d60eSLinus Walleij .id = 0x00280180, 1624cc30d60eSLinus Walleij .mask = 0x00ffffff, 16254956e109SRabin Vincent .data = &variant_u300, 16264956e109SRabin Vincent }, 16274956e109SRabin Vincent { 16284956e109SRabin Vincent .id = 0x00480180, 16291784b157SPhilippe Langlais .mask = 0xf0ffffff, 16304956e109SRabin Vincent .data = &variant_ux500, 1631cc30d60eSLinus Walleij }, 16321784b157SPhilippe Langlais { 16331784b157SPhilippe Langlais .id = 0x10480180, 16341784b157SPhilippe Langlais .mask = 0xf0ffffff, 16351784b157SPhilippe Langlais .data = &variant_ux500v2, 16361784b157SPhilippe Langlais }, 16371c6a0718SPierre Ossman { 0, 0 }, 16381c6a0718SPierre Ossman }; 16391c6a0718SPierre Ossman 16409f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 16419f99835fSDave Martin 16421c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 16431c6a0718SPierre Ossman .drv = { 16441c6a0718SPierre Ossman .name = DRIVER_NAME, 164548fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 16461c6a0718SPierre Ossman }, 16471c6a0718SPierre Ossman .probe = mmci_probe, 16486dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 16491c6a0718SPierre Ossman .id_table = mmci_ids, 16501c6a0718SPierre Ossman }; 16511c6a0718SPierre Ossman 16529e5ed094Sviresh kumar module_amba_driver(mmci_driver); 16531c6a0718SPierre Ossman 16541c6a0718SPierre Ossman module_param(fmax, uint, 0444); 16551c6a0718SPierre Ossman 16561c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 16571c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1658