11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 16ef289982SUlf Hansson #include <linux/io.h> 171c6a0718SPierre Ossman #include <linux/interrupt.h> 18613b152cSRussell King #include <linux/kernel.h> 19000bc9d5SLee Jones #include <linux/slab.h> 201c6a0718SPierre Ossman #include <linux/delay.h> 211c6a0718SPierre Ossman #include <linux/err.h> 221c6a0718SPierre Ossman #include <linux/highmem.h> 23019a5f56SNicolas Pitre #include <linux/log2.h> 2470be208fSUlf Hansson #include <linux/mmc/pm.h> 251c6a0718SPierre Ossman #include <linux/mmc/host.h> 2634177802SLinus Walleij #include <linux/mmc/card.h> 27d2762090SUlf Hansson #include <linux/mmc/slot-gpio.h> 281c6a0718SPierre Ossman #include <linux/amba/bus.h> 291c6a0718SPierre Ossman #include <linux/clk.h> 30bd6dee6fSJens Axboe #include <linux/scatterlist.h> 3189001446SRussell King #include <linux/gpio.h> 329a597016SLee Jones #include <linux/of_gpio.h> 3334e84f39SLinus Walleij #include <linux/regulator/consumer.h> 34c8ebae37SRussell King #include <linux/dmaengine.h> 35c8ebae37SRussell King #include <linux/dma-mapping.h> 36c8ebae37SRussell King #include <linux/amba/mmci.h> 371c3be369SRussell King #include <linux/pm_runtime.h> 38258aea76SViresh Kumar #include <linux/types.h> 39a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 401c6a0718SPierre Ossman 411c6a0718SPierre Ossman #include <asm/div64.h> 421c6a0718SPierre Ossman #include <asm/io.h> 431c6a0718SPierre Ossman 441c6a0718SPierre Ossman #include "mmci.h" 459cb15142SSrinivas Kandagatla #include "mmci_qcom_dml.h" 461c6a0718SPierre Ossman 471c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 481c6a0718SPierre Ossman 491c6a0718SPierre Ossman static unsigned int fmax = 515633; 501c6a0718SPierre Ossman 514956e109SRabin Vincent /** 524956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 534956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 544380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 55e1412d85SSrinivas Kandagatla * @clkreg_8bit_bus_enable: enable value for 8 bit bus 56e8740644SSrinivas Kandagatla * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 5708458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 588301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 598301bb68SRabin Vincent * is asserted (likewise for RX) 608301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 618301bb68SRabin Vincent * is asserted (likewise for RX) 62ae7b0061SSrinivas Kandagatla * @data_cmd_enable: enable value for data commands. 63c7354133SSrinivas Kandagatla * @st_sdio: enable ST specific SDIO logic 64b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 65e17dca2bSSrinivas Kandagatla * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 661784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 67ff783233SSrinivas Kandagatla * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 68ff783233SSrinivas Kandagatla * register 695df014dfSSrinivas Kandagatla * @datactrl_mask_sdio: SDIO enable mask in datactrl register 707d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 71dc6500bfSSrinivas Kandagatla * @f_max: maximum clk frequency supported by the controller. 724d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 73f4670daeSUlf Hansson * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 7449adc0caSLinus Walleij * @busy_detect: true if the variant supports busy detection on DAT0. 7549adc0caSLinus Walleij * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM 7649adc0caSLinus Walleij * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register 7749adc0caSLinus Walleij * indicating that the card is busy 7849adc0caSLinus Walleij * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for 7949adc0caSLinus Walleij * getting busy end detection interrupts 801ff44433SUlf Hansson * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 813f4e6f7bSSrinivas Kandagatla * @explicit_mclk_control: enable explicit mclk control in driver. 829c34b73dSSrinivas Kandagatla * @qcom_fifo: enables qcom specific fifo pio read logic. 839cb15142SSrinivas Kandagatla * @qcom_dml: enables qcom specific dma glue for dma transfers. 847878289bSUlf Hansson * @reversed_irq_handling: handle data irq before cmd irq. 854956e109SRabin Vincent */ 864956e109SRabin Vincent struct variant_data { 874956e109SRabin Vincent unsigned int clkreg; 884380c14fSRabin Vincent unsigned int clkreg_enable; 89e1412d85SSrinivas Kandagatla unsigned int clkreg_8bit_bus_enable; 90e8740644SSrinivas Kandagatla unsigned int clkreg_neg_edge_enable; 9108458ef6SRabin Vincent unsigned int datalength_bits; 928301bb68SRabin Vincent unsigned int fifosize; 938301bb68SRabin Vincent unsigned int fifohalfsize; 94ae7b0061SSrinivas Kandagatla unsigned int data_cmd_enable; 95e17dca2bSSrinivas Kandagatla unsigned int datactrl_mask_ddrmode; 965df014dfSSrinivas Kandagatla unsigned int datactrl_mask_sdio; 97c7354133SSrinivas Kandagatla bool st_sdio; 98b70a67f9SLinus Walleij bool st_clkdiv; 991784b157SPhilippe Langlais bool blksz_datactrl16; 100ff783233SSrinivas Kandagatla bool blksz_datactrl4; 1017d72a1d4SUlf Hansson u32 pwrreg_powerup; 102dc6500bfSSrinivas Kandagatla u32 f_max; 1034d1a3a0dSUlf Hansson bool signal_direction; 104f4670daeSUlf Hansson bool pwrreg_clkgate; 10501259620SUlf Hansson bool busy_detect; 10649adc0caSLinus Walleij u32 busy_dpsm_flag; 10749adc0caSLinus Walleij u32 busy_detect_flag; 10849adc0caSLinus Walleij u32 busy_detect_mask; 1091ff44433SUlf Hansson bool pwrreg_nopower; 1103f4e6f7bSSrinivas Kandagatla bool explicit_mclk_control; 1119c34b73dSSrinivas Kandagatla bool qcom_fifo; 1129cb15142SSrinivas Kandagatla bool qcom_dml; 1137878289bSUlf Hansson bool reversed_irq_handling; 1144956e109SRabin Vincent }; 1154956e109SRabin Vincent 1164956e109SRabin Vincent static struct variant_data variant_arm = { 1178301bb68SRabin Vincent .fifosize = 16 * 4, 1188301bb68SRabin Vincent .fifohalfsize = 8 * 4, 11908458ef6SRabin Vincent .datalength_bits = 16, 1207d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 121dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1227878289bSUlf Hansson .reversed_irq_handling = true, 1234956e109SRabin Vincent }; 1244956e109SRabin Vincent 125768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 126768fbc18SPawel Moll .fifosize = 128 * 4, 127768fbc18SPawel Moll .fifohalfsize = 64 * 4, 128768fbc18SPawel Moll .datalength_bits = 16, 1297d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 130dc6500bfSSrinivas Kandagatla .f_max = 100000000, 131768fbc18SPawel Moll }; 132768fbc18SPawel Moll 1333a37298aSPawel Moll static struct variant_data variant_arm_extended_fifo_hwfc = { 1343a37298aSPawel Moll .fifosize = 128 * 4, 1353a37298aSPawel Moll .fifohalfsize = 64 * 4, 1363a37298aSPawel Moll .clkreg_enable = MCI_ARM_HWFCEN, 1373a37298aSPawel Moll .datalength_bits = 16, 1383a37298aSPawel Moll .pwrreg_powerup = MCI_PWR_UP, 139dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1403a37298aSPawel Moll }; 1413a37298aSPawel Moll 1424956e109SRabin Vincent static struct variant_data variant_u300 = { 1438301bb68SRabin Vincent .fifosize = 16 * 4, 1448301bb68SRabin Vincent .fifohalfsize = 8 * 4, 14549ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 146e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 14708458ef6SRabin Vincent .datalength_bits = 16, 1485db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 149c7354133SSrinivas Kandagatla .st_sdio = true, 1507d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 151dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1524d1a3a0dSUlf Hansson .signal_direction = true, 153f4670daeSUlf Hansson .pwrreg_clkgate = true, 1541ff44433SUlf Hansson .pwrreg_nopower = true, 1554956e109SRabin Vincent }; 1564956e109SRabin Vincent 15734fd4213SLinus Walleij static struct variant_data variant_nomadik = { 15834fd4213SLinus Walleij .fifosize = 16 * 4, 15934fd4213SLinus Walleij .fifohalfsize = 8 * 4, 16034fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 161f5abc767SLinus Walleij .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 16234fd4213SLinus Walleij .datalength_bits = 24, 1635db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 164c7354133SSrinivas Kandagatla .st_sdio = true, 16534fd4213SLinus Walleij .st_clkdiv = true, 16634fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 167dc6500bfSSrinivas Kandagatla .f_max = 100000000, 16834fd4213SLinus Walleij .signal_direction = true, 169f4670daeSUlf Hansson .pwrreg_clkgate = true, 1701ff44433SUlf Hansson .pwrreg_nopower = true, 17134fd4213SLinus Walleij }; 17234fd4213SLinus Walleij 1734956e109SRabin Vincent static struct variant_data variant_ux500 = { 1748301bb68SRabin Vincent .fifosize = 30 * 4, 1758301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1764956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 17749ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 178e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 179e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 18008458ef6SRabin Vincent .datalength_bits = 24, 1815db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 182c7354133SSrinivas Kandagatla .st_sdio = true, 183b70a67f9SLinus Walleij .st_clkdiv = true, 1847d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 185dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1864d1a3a0dSUlf Hansson .signal_direction = true, 187f4670daeSUlf Hansson .pwrreg_clkgate = true, 18801259620SUlf Hansson .busy_detect = true, 18949adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 19049adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 19149adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 1921ff44433SUlf Hansson .pwrreg_nopower = true, 1934956e109SRabin Vincent }; 194b70a67f9SLinus Walleij 1951784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1961784b157SPhilippe Langlais .fifosize = 30 * 4, 1971784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1981784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1991784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 200e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 201e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 2025db3eee7SLinus Walleij .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 2031784b157SPhilippe Langlais .datalength_bits = 24, 2045db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 205c7354133SSrinivas Kandagatla .st_sdio = true, 2061784b157SPhilippe Langlais .st_clkdiv = true, 2071784b157SPhilippe Langlais .blksz_datactrl16 = true, 2087d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 209dc6500bfSSrinivas Kandagatla .f_max = 100000000, 2104d1a3a0dSUlf Hansson .signal_direction = true, 211f4670daeSUlf Hansson .pwrreg_clkgate = true, 21201259620SUlf Hansson .busy_detect = true, 21349adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 21449adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 21549adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 2161ff44433SUlf Hansson .pwrreg_nopower = true, 2171784b157SPhilippe Langlais }; 2181784b157SPhilippe Langlais 21955b604aeSSrinivas Kandagatla static struct variant_data variant_qcom = { 22055b604aeSSrinivas Kandagatla .fifosize = 16 * 4, 22155b604aeSSrinivas Kandagatla .fifohalfsize = 8 * 4, 22255b604aeSSrinivas Kandagatla .clkreg = MCI_CLK_ENABLE, 22355b604aeSSrinivas Kandagatla .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 22455b604aeSSrinivas Kandagatla MCI_QCOM_CLK_SELECT_IN_FBCLK, 22555b604aeSSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 22655b604aeSSrinivas Kandagatla .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 2275db3eee7SLinus Walleij .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 22855b604aeSSrinivas Kandagatla .blksz_datactrl4 = true, 22955b604aeSSrinivas Kandagatla .datalength_bits = 24, 23055b604aeSSrinivas Kandagatla .pwrreg_powerup = MCI_PWR_UP, 23155b604aeSSrinivas Kandagatla .f_max = 208000000, 23255b604aeSSrinivas Kandagatla .explicit_mclk_control = true, 23355b604aeSSrinivas Kandagatla .qcom_fifo = true, 2349cb15142SSrinivas Kandagatla .qcom_dml = true, 23555b604aeSSrinivas Kandagatla }; 23655b604aeSSrinivas Kandagatla 23749adc0caSLinus Walleij /* Busy detection for the ST Micro variant */ 23801259620SUlf Hansson static int mmci_card_busy(struct mmc_host *mmc) 23901259620SUlf Hansson { 24001259620SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 24101259620SUlf Hansson unsigned long flags; 24201259620SUlf Hansson int busy = 0; 24301259620SUlf Hansson 24401259620SUlf Hansson spin_lock_irqsave(&host->lock, flags); 24549adc0caSLinus Walleij if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 24601259620SUlf Hansson busy = 1; 24701259620SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 24801259620SUlf Hansson 24901259620SUlf Hansson return busy; 25001259620SUlf Hansson } 25101259620SUlf Hansson 252a6a6464aSLinus Walleij /* 253653a761eSUlf Hansson * Validate mmc prerequisites 254653a761eSUlf Hansson */ 255653a761eSUlf Hansson static int mmci_validate_data(struct mmci_host *host, 256653a761eSUlf Hansson struct mmc_data *data) 257653a761eSUlf Hansson { 258653a761eSUlf Hansson if (!data) 259653a761eSUlf Hansson return 0; 260653a761eSUlf Hansson 261653a761eSUlf Hansson if (!is_power_of_2(data->blksz)) { 262653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), 263653a761eSUlf Hansson "unsupported block size (%d bytes)\n", data->blksz); 264653a761eSUlf Hansson return -EINVAL; 265653a761eSUlf Hansson } 266653a761eSUlf Hansson 267653a761eSUlf Hansson return 0; 268653a761eSUlf Hansson } 269653a761eSUlf Hansson 270f829c042SUlf Hansson static void mmci_reg_delay(struct mmci_host *host) 271f829c042SUlf Hansson { 272f829c042SUlf Hansson /* 273f829c042SUlf Hansson * According to the spec, at least three feedback clock cycles 274f829c042SUlf Hansson * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 275f829c042SUlf Hansson * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 276f829c042SUlf Hansson * Worst delay time during card init is at 100 kHz => 30 us. 277f829c042SUlf Hansson * Worst delay time when up and running is at 25 MHz => 120 ns. 278f829c042SUlf Hansson */ 279f829c042SUlf Hansson if (host->cclk < 25000000) 280f829c042SUlf Hansson udelay(30); 281f829c042SUlf Hansson else 282f829c042SUlf Hansson ndelay(120); 283f829c042SUlf Hansson } 284f829c042SUlf Hansson 285653a761eSUlf Hansson /* 286a6a6464aSLinus Walleij * This must be called with host->lock held 287a6a6464aSLinus Walleij */ 2887437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 2897437cfa5SUlf Hansson { 2907437cfa5SUlf Hansson if (host->clk_reg != clk) { 2917437cfa5SUlf Hansson host->clk_reg = clk; 2927437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 2937437cfa5SUlf Hansson } 2947437cfa5SUlf Hansson } 2957437cfa5SUlf Hansson 2967437cfa5SUlf Hansson /* 2977437cfa5SUlf Hansson * This must be called with host->lock held 2987437cfa5SUlf Hansson */ 2997437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 3007437cfa5SUlf Hansson { 3017437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 3027437cfa5SUlf Hansson host->pwr_reg = pwr; 3037437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 3047437cfa5SUlf Hansson } 3057437cfa5SUlf Hansson } 3067437cfa5SUlf Hansson 3077437cfa5SUlf Hansson /* 3087437cfa5SUlf Hansson * This must be called with host->lock held 3097437cfa5SUlf Hansson */ 3109cc639a2SUlf Hansson static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 3119cc639a2SUlf Hansson { 31249adc0caSLinus Walleij /* Keep busy mode in DPSM if enabled */ 31349adc0caSLinus Walleij datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 31401259620SUlf Hansson 3159cc639a2SUlf Hansson if (host->datactrl_reg != datactrl) { 3169cc639a2SUlf Hansson host->datactrl_reg = datactrl; 3179cc639a2SUlf Hansson writel(datactrl, host->base + MMCIDATACTRL); 3189cc639a2SUlf Hansson } 3199cc639a2SUlf Hansson } 3209cc639a2SUlf Hansson 3219cc639a2SUlf Hansson /* 3229cc639a2SUlf Hansson * This must be called with host->lock held 3239cc639a2SUlf Hansson */ 324a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 325a6a6464aSLinus Walleij { 3264956e109SRabin Vincent struct variant_data *variant = host->variant; 3274956e109SRabin Vincent u32 clk = variant->clkreg; 328a6a6464aSLinus Walleij 329c58a8509SUlf Hansson /* Make sure cclk reflects the current calculated clock */ 330c58a8509SUlf Hansson host->cclk = 0; 331c58a8509SUlf Hansson 332a6a6464aSLinus Walleij if (desired) { 3333f4e6f7bSSrinivas Kandagatla if (variant->explicit_mclk_control) { 3343f4e6f7bSSrinivas Kandagatla host->cclk = host->mclk; 3353f4e6f7bSSrinivas Kandagatla } else if (desired >= host->mclk) { 336a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 337399bc486SLinus Walleij if (variant->st_clkdiv) 338399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 339a6a6464aSLinus Walleij host->cclk = host->mclk; 340b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 341b70a67f9SLinus Walleij /* 342b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 343b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 344b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 345b70a67f9SLinus Walleij * frequency 346b70a67f9SLinus Walleij */ 347b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 348b70a67f9SLinus Walleij if (clk >= 256) 349b70a67f9SLinus Walleij clk = 255; 350b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 351a6a6464aSLinus Walleij } else { 352b70a67f9SLinus Walleij /* 353b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 354b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 355b70a67f9SLinus Walleij */ 356a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 357a6a6464aSLinus Walleij if (clk >= 256) 358a6a6464aSLinus Walleij clk = 255; 359a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 360a6a6464aSLinus Walleij } 3614380c14fSRabin Vincent 3624380c14fSRabin Vincent clk |= variant->clkreg_enable; 363a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 364a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 365a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 366a6a6464aSLinus Walleij } 367a6a6464aSLinus Walleij 368c58a8509SUlf Hansson /* Set actual clock for debug */ 369c58a8509SUlf Hansson host->mmc->actual_clock = host->cclk; 370c58a8509SUlf Hansson 3719e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 372771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 373771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 374e1412d85SSrinivas Kandagatla clk |= variant->clkreg_8bit_bus_enable; 3759e6c82cdSLinus Walleij 3766dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 3776dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 378e8740644SSrinivas Kandagatla clk |= variant->clkreg_neg_edge_enable; 3796dbb6ee0SUlf Hansson 3807437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 381a6a6464aSLinus Walleij } 382a6a6464aSLinus Walleij 3831c6a0718SPierre Ossman static void 3841c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 3851c6a0718SPierre Ossman { 3861c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 3871c6a0718SPierre Ossman 3881c6a0718SPierre Ossman BUG_ON(host->data); 3891c6a0718SPierre Ossman 3901c6a0718SPierre Ossman host->mrq = NULL; 3911c6a0718SPierre Ossman host->cmd = NULL; 3921c6a0718SPierre Ossman 3931c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 3941c6a0718SPierre Ossman } 3951c6a0718SPierre Ossman 3962686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 3972686b4b4SLinus Walleij { 3982686b4b4SLinus Walleij void __iomem *base = host->base; 3992686b4b4SLinus Walleij 4002686b4b4SLinus Walleij if (host->singleirq) { 4012686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 4022686b4b4SLinus Walleij 4032686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 4042686b4b4SLinus Walleij mask0 |= mask; 4052686b4b4SLinus Walleij 4062686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 4072686b4b4SLinus Walleij } 4082686b4b4SLinus Walleij 4092686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 4102686b4b4SLinus Walleij } 4112686b4b4SLinus Walleij 4121c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 4131c6a0718SPierre Ossman { 4149cc639a2SUlf Hansson mmci_write_datactrlreg(host, 0); 4152686b4b4SLinus Walleij mmci_set_mask1(host, 0); 4161c6a0718SPierre Ossman host->data = NULL; 4171c6a0718SPierre Ossman } 4181c6a0718SPierre Ossman 4194ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 4204ce1d6cbSRabin Vincent { 4214ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 4224ce1d6cbSRabin Vincent 4234ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 4244ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 4254ce1d6cbSRabin Vincent else 4264ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 4274ce1d6cbSRabin Vincent 4284ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 4294ce1d6cbSRabin Vincent } 4304ce1d6cbSRabin Vincent 431c8ebae37SRussell King /* 432c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 433c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 434c8ebae37SRussell King * no custom DMA interfaces are supported. 435c8ebae37SRussell King */ 436c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 437c3be1efdSBill Pemberton static void mmci_dma_setup(struct mmci_host *host) 438c8ebae37SRussell King { 439c8ebae37SRussell King const char *rxname, *txname; 4409cb15142SSrinivas Kandagatla struct variant_data *variant = host->variant; 441c8ebae37SRussell King 4421fd83f0eSLee Jones host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 4431fd83f0eSLee Jones host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 444c8ebae37SRussell King 44558c7ccbfSPer Forlin /* initialize pre request cookie */ 44658c7ccbfSPer Forlin host->next_data.cookie = 1; 44758c7ccbfSPer Forlin 4481fd83f0eSLee Jones /* 4491fd83f0eSLee Jones * If only an RX channel is specified, the driver will 4501fd83f0eSLee Jones * attempt to use it bidirectionally, however if it is 4511fd83f0eSLee Jones * is specified but cannot be located, DMA will be disabled. 4521fd83f0eSLee Jones */ 4531fd83f0eSLee Jones if (host->dma_rx_channel && !host->dma_tx_channel) 4541fd83f0eSLee Jones host->dma_tx_channel = host->dma_rx_channel; 455c8ebae37SRussell King 456c8ebae37SRussell King if (host->dma_rx_channel) 457c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 458c8ebae37SRussell King else 459c8ebae37SRussell King rxname = "none"; 460c8ebae37SRussell King 461c8ebae37SRussell King if (host->dma_tx_channel) 462c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 463c8ebae37SRussell King else 464c8ebae37SRussell King txname = "none"; 465c8ebae37SRussell King 466c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 467c8ebae37SRussell King rxname, txname); 468c8ebae37SRussell King 469c8ebae37SRussell King /* 470c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 471c8ebae37SRussell King * the parameters of the DMA engine device. 472c8ebae37SRussell King */ 473c8ebae37SRussell King if (host->dma_tx_channel) { 474c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 475c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 476c8ebae37SRussell King 477c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 478c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 479c8ebae37SRussell King } 480c8ebae37SRussell King if (host->dma_rx_channel) { 481c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 482c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 483c8ebae37SRussell King 484c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 485c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 486c8ebae37SRussell King } 4879cb15142SSrinivas Kandagatla 4889cb15142SSrinivas Kandagatla if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) 4899cb15142SSrinivas Kandagatla if (dml_hw_init(host, host->mmc->parent->of_node)) 4909cb15142SSrinivas Kandagatla variant->qcom_dml = false; 491c8ebae37SRussell King } 492c8ebae37SRussell King 493c8ebae37SRussell King /* 4946e0ee714SBill Pemberton * This is used in or so inline it 495c8ebae37SRussell King * so it can be discarded. 496c8ebae37SRussell King */ 497c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 498c8ebae37SRussell King { 499c8ebae37SRussell King if (host->dma_rx_channel) 500c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 5018c3a05b4SUlf Hansson if (host->dma_tx_channel) 502c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 503c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 504c8ebae37SRussell King } 505c8ebae37SRussell King 506653a761eSUlf Hansson static void mmci_dma_data_error(struct mmci_host *host) 507653a761eSUlf Hansson { 508653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 509653a761eSUlf Hansson dmaengine_terminate_all(host->dma_current); 510e13934bdSLinus Walleij host->dma_in_progress = false; 511653a761eSUlf Hansson host->dma_current = NULL; 512653a761eSUlf Hansson host->dma_desc_current = NULL; 513653a761eSUlf Hansson host->data->host_cookie = 0; 514653a761eSUlf Hansson } 515653a761eSUlf Hansson 516c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 517c8ebae37SRussell King { 518653a761eSUlf Hansson struct dma_chan *chan; 519653a761eSUlf Hansson 520feeef096SHeiner Kallweit if (data->flags & MMC_DATA_READ) 521653a761eSUlf Hansson chan = host->dma_rx_channel; 522feeef096SHeiner Kallweit else 523653a761eSUlf Hansson chan = host->dma_tx_channel; 524653a761eSUlf Hansson 525feeef096SHeiner Kallweit dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 526feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 527653a761eSUlf Hansson } 528653a761eSUlf Hansson 529653a761eSUlf Hansson static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 530653a761eSUlf Hansson { 531c8ebae37SRussell King u32 status; 532c8ebae37SRussell King int i; 533c8ebae37SRussell King 534c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 535c8ebae37SRussell King for (i = 0; ; i++) { 536c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 537c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 538c8ebae37SRussell King break; 539c8ebae37SRussell King udelay(10); 540c8ebae37SRussell King } 541c8ebae37SRussell King 542c8ebae37SRussell King /* 543c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 544c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 545c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 546c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 547c8ebae37SRussell King */ 548c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 549653a761eSUlf Hansson mmci_dma_data_error(host); 550c8ebae37SRussell King if (!data->error) 551c8ebae37SRussell King data->error = -EIO; 552c8ebae37SRussell King } 553c8ebae37SRussell King 55458c7ccbfSPer Forlin if (!data->host_cookie) 555653a761eSUlf Hansson mmci_dma_unmap(host, data); 556c8ebae37SRussell King 557c8ebae37SRussell King /* 558c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 559c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 560c8ebae37SRussell King */ 561c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 562c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 563c8ebae37SRussell King mmci_dma_release(host); 564c8ebae37SRussell King } 565653a761eSUlf Hansson 566e13934bdSLinus Walleij host->dma_in_progress = false; 567653a761eSUlf Hansson host->dma_current = NULL; 568653a761eSUlf Hansson host->dma_desc_current = NULL; 569c8ebae37SRussell King } 570c8ebae37SRussell King 571653a761eSUlf Hansson /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 572653a761eSUlf Hansson static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 573653a761eSUlf Hansson struct dma_chan **dma_chan, 574653a761eSUlf Hansson struct dma_async_tx_descriptor **dma_desc) 575c8ebae37SRussell King { 576c8ebae37SRussell King struct variant_data *variant = host->variant; 577c8ebae37SRussell King struct dma_slave_config conf = { 578c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 579c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 580c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 581c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 582c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 583c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 584258aea76SViresh Kumar .device_fc = false, 585c8ebae37SRussell King }; 586c8ebae37SRussell King struct dma_chan *chan; 587c8ebae37SRussell King struct dma_device *device; 588c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 589c8ebae37SRussell King int nr_sg; 5909cb15142SSrinivas Kandagatla unsigned long flags = DMA_CTRL_ACK; 591c8ebae37SRussell King 592c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 59305f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 594c8ebae37SRussell King chan = host->dma_rx_channel; 595c8ebae37SRussell King } else { 59605f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 597c8ebae37SRussell King chan = host->dma_tx_channel; 598c8ebae37SRussell King } 599c8ebae37SRussell King 600c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 601c8ebae37SRussell King if (!chan) 602c8ebae37SRussell King return -EINVAL; 603c8ebae37SRussell King 604c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 60558c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 606c8ebae37SRussell King return -EINVAL; 607c8ebae37SRussell King 608c8ebae37SRussell King device = chan->device; 609feeef096SHeiner Kallweit nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 610feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 611c8ebae37SRussell King if (nr_sg == 0) 612c8ebae37SRussell King return -EINVAL; 613c8ebae37SRussell King 6149cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 6159cb15142SSrinivas Kandagatla flags |= DMA_PREP_INTERRUPT; 6169cb15142SSrinivas Kandagatla 617c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 61816052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 6199cb15142SSrinivas Kandagatla conf.direction, flags); 620c8ebae37SRussell King if (!desc) 621c8ebae37SRussell King goto unmap_exit; 622c8ebae37SRussell King 623653a761eSUlf Hansson *dma_chan = chan; 624653a761eSUlf Hansson *dma_desc = desc; 625c8ebae37SRussell King 62658c7ccbfSPer Forlin return 0; 62758c7ccbfSPer Forlin 62858c7ccbfSPer Forlin unmap_exit: 629feeef096SHeiner Kallweit dma_unmap_sg(device->dev, data->sg, data->sg_len, 630feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 63158c7ccbfSPer Forlin return -ENOMEM; 63258c7ccbfSPer Forlin } 63358c7ccbfSPer Forlin 634653a761eSUlf Hansson static inline int mmci_dma_prep_data(struct mmci_host *host, 635653a761eSUlf Hansson struct mmc_data *data) 636653a761eSUlf Hansson { 637653a761eSUlf Hansson /* Check if next job is already prepared. */ 638653a761eSUlf Hansson if (host->dma_current && host->dma_desc_current) 639653a761eSUlf Hansson return 0; 640653a761eSUlf Hansson 641653a761eSUlf Hansson /* No job were prepared thus do it now. */ 642653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &host->dma_current, 643653a761eSUlf Hansson &host->dma_desc_current); 644653a761eSUlf Hansson } 645653a761eSUlf Hansson 646653a761eSUlf Hansson static inline int mmci_dma_prep_next(struct mmci_host *host, 647653a761eSUlf Hansson struct mmc_data *data) 648653a761eSUlf Hansson { 649653a761eSUlf Hansson struct mmci_host_next *nd = &host->next_data; 650653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 651653a761eSUlf Hansson } 652653a761eSUlf Hansson 65358c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 65458c7ccbfSPer Forlin { 65558c7ccbfSPer Forlin int ret; 65658c7ccbfSPer Forlin struct mmc_data *data = host->data; 65758c7ccbfSPer Forlin 658653a761eSUlf Hansson ret = mmci_dma_prep_data(host, host->data); 65958c7ccbfSPer Forlin if (ret) 66058c7ccbfSPer Forlin return ret; 66158c7ccbfSPer Forlin 66258c7ccbfSPer Forlin /* Okay, go for it. */ 663c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 664c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 665c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 666e13934bdSLinus Walleij host->dma_in_progress = true; 66758c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 66858c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 669c8ebae37SRussell King 6709cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 6719cb15142SSrinivas Kandagatla dml_start_xfer(host, data); 6729cb15142SSrinivas Kandagatla 673c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 674c8ebae37SRussell King 675c8ebae37SRussell King /* Trigger the DMA transfer */ 6769cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 677c8ebae37SRussell King 678c8ebae37SRussell King /* 679c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 680c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 681c8ebae37SRussell King * call mmci_data_end() 682c8ebae37SRussell King */ 683c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 684c8ebae37SRussell King host->base + MMCIMASK0); 685c8ebae37SRussell King return 0; 686c8ebae37SRussell King } 68758c7ccbfSPer Forlin 68858c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 68958c7ccbfSPer Forlin { 69058c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 69158c7ccbfSPer Forlin 692653a761eSUlf Hansson WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 693653a761eSUlf Hansson WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 69458c7ccbfSPer Forlin 69558c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 69658c7ccbfSPer Forlin host->dma_current = next->dma_chan; 69758c7ccbfSPer Forlin next->dma_desc = NULL; 69858c7ccbfSPer Forlin next->dma_chan = NULL; 69958c7ccbfSPer Forlin } 70058c7ccbfSPer Forlin 701d3c6aac3SLinus Walleij static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 70258c7ccbfSPer Forlin { 70358c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 70458c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 70558c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 70658c7ccbfSPer Forlin 70758c7ccbfSPer Forlin if (!data) 70858c7ccbfSPer Forlin return; 70958c7ccbfSPer Forlin 710653a761eSUlf Hansson BUG_ON(data->host_cookie); 71158c7ccbfSPer Forlin 712653a761eSUlf Hansson if (mmci_validate_data(host, data)) 713653a761eSUlf Hansson return; 714653a761eSUlf Hansson 715653a761eSUlf Hansson if (!mmci_dma_prep_next(host, data)) 71658c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 71758c7ccbfSPer Forlin } 71858c7ccbfSPer Forlin 71958c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 72058c7ccbfSPer Forlin int err) 72158c7ccbfSPer Forlin { 72258c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 72358c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 72458c7ccbfSPer Forlin 725653a761eSUlf Hansson if (!data || !data->host_cookie) 72658c7ccbfSPer Forlin return; 72758c7ccbfSPer Forlin 728653a761eSUlf Hansson mmci_dma_unmap(host, data); 729653a761eSUlf Hansson 730653a761eSUlf Hansson if (err) { 731653a761eSUlf Hansson struct mmci_host_next *next = &host->next_data; 732653a761eSUlf Hansson struct dma_chan *chan; 733653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) 73458c7ccbfSPer Forlin chan = host->dma_rx_channel; 735653a761eSUlf Hansson else 73658c7ccbfSPer Forlin chan = host->dma_tx_channel; 73758c7ccbfSPer Forlin dmaengine_terminate_all(chan); 738653a761eSUlf Hansson 739b5c16a60SSrinivas Kandagatla if (host->dma_desc_current == next->dma_desc) 740b5c16a60SSrinivas Kandagatla host->dma_desc_current = NULL; 741b5c16a60SSrinivas Kandagatla 742e13934bdSLinus Walleij if (host->dma_current == next->dma_chan) { 743e13934bdSLinus Walleij host->dma_in_progress = false; 744b5c16a60SSrinivas Kandagatla host->dma_current = NULL; 745e13934bdSLinus Walleij } 746b5c16a60SSrinivas Kandagatla 747653a761eSUlf Hansson next->dma_desc = NULL; 748653a761eSUlf Hansson next->dma_chan = NULL; 749b5c16a60SSrinivas Kandagatla data->host_cookie = 0; 75058c7ccbfSPer Forlin } 75158c7ccbfSPer Forlin } 75258c7ccbfSPer Forlin 753c8ebae37SRussell King #else 754c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 75558c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 75658c7ccbfSPer Forlin { 75758c7ccbfSPer Forlin } 758c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 759c8ebae37SRussell King { 760c8ebae37SRussell King } 761c8ebae37SRussell King 762c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 763c8ebae37SRussell King { 764c8ebae37SRussell King } 765c8ebae37SRussell King 766c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 767c8ebae37SRussell King { 768c8ebae37SRussell King } 769c8ebae37SRussell King 770653a761eSUlf Hansson static inline void mmci_dma_finalize(struct mmci_host *host, 771653a761eSUlf Hansson struct mmc_data *data) 772653a761eSUlf Hansson { 773653a761eSUlf Hansson } 774653a761eSUlf Hansson 775c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 776c8ebae37SRussell King { 777c8ebae37SRussell King } 778c8ebae37SRussell King 779c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 780c8ebae37SRussell King { 781c8ebae37SRussell King return -ENOSYS; 782c8ebae37SRussell King } 78358c7ccbfSPer Forlin 78458c7ccbfSPer Forlin #define mmci_pre_request NULL 78558c7ccbfSPer Forlin #define mmci_post_request NULL 78658c7ccbfSPer Forlin 787c8ebae37SRussell King #endif 788c8ebae37SRussell King 7891c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 7901c6a0718SPierre Ossman { 7918301bb68SRabin Vincent struct variant_data *variant = host->variant; 7921c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 7931c6a0718SPierre Ossman unsigned long long clks; 7941c6a0718SPierre Ossman void __iomem *base; 7951c6a0718SPierre Ossman int blksz_bits; 7961c6a0718SPierre Ossman 79764de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 7981c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 7991c6a0718SPierre Ossman 8001c6a0718SPierre Ossman host->data = data; 801528320dbSRabin Vincent host->size = data->blksz * data->blocks; 80251d4375dSRussell King data->bytes_xfered = 0; 8031c6a0718SPierre Ossman 8041c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 805c4a35769SSrinivas Kandagatla do_div(clks, NSEC_PER_SEC); 8061c6a0718SPierre Ossman 8071c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 8081c6a0718SPierre Ossman 8091c6a0718SPierre Ossman base = host->base; 8101c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 8111c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 8121c6a0718SPierre Ossman 8131c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 8141c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 8151c6a0718SPierre Ossman 8161784b157SPhilippe Langlais if (variant->blksz_datactrl16) 8171784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 818ff783233SSrinivas Kandagatla else if (variant->blksz_datactrl4) 819ff783233SSrinivas Kandagatla datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 8201784b157SPhilippe Langlais else 8211c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 822c8ebae37SRussell King 823c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 8241c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 825c8ebae37SRussell King 826c7354133SSrinivas Kandagatla if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 82706c1a121SUlf Hansson u32 clk; 828c7354133SSrinivas Kandagatla 8295df014dfSSrinivas Kandagatla datactrl |= variant->datactrl_mask_sdio; 8307258db7eSUlf Hansson 831c8ebae37SRussell King /* 83270ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 83370ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 83470ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 83570ac0935SUlf Hansson * depends on the rate of MCLK. 83606c1a121SUlf Hansson */ 837c7354133SSrinivas Kandagatla if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 83870ac0935SUlf Hansson (host->size < 8 || 83970ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 84006c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 84106c1a121SUlf Hansson else 84206c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 84306c1a121SUlf Hansson 84406c1a121SUlf Hansson mmci_write_clkreg(host, clk); 84506c1a121SUlf Hansson } 84606c1a121SUlf Hansson 8476dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 8486dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 849e17dca2bSSrinivas Kandagatla datactrl |= variant->datactrl_mask_ddrmode; 8506dbb6ee0SUlf Hansson 85106c1a121SUlf Hansson /* 852c8ebae37SRussell King * Attempt to use DMA operation mode, if this 853c8ebae37SRussell King * should fail, fall back to PIO mode 854c8ebae37SRussell King */ 855c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 856c8ebae37SRussell King return; 857c8ebae37SRussell King 858c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 859c8ebae37SRussell King mmci_init_sg(host, data); 860c8ebae37SRussell King 861c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 8621c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 8631c6a0718SPierre Ossman 8641c6a0718SPierre Ossman /* 865c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 866c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 867c4d877c1SRussell King * is available. 8681c6a0718SPierre Ossman */ 869c4d877c1SRussell King if (host->size < variant->fifohalfsize) 8701c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 8711c6a0718SPierre Ossman } else { 8721c6a0718SPierre Ossman /* 8731c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 8741c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 8751c6a0718SPierre Ossman */ 8761c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 8771c6a0718SPierre Ossman } 8781c6a0718SPierre Ossman 8799cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 8801c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 8812686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 8821c6a0718SPierre Ossman } 8831c6a0718SPierre Ossman 8841c6a0718SPierre Ossman static void 8851c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 8861c6a0718SPierre Ossman { 8871c6a0718SPierre Ossman void __iomem *base = host->base; 8881c6a0718SPierre Ossman 88964de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 8901c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 8911c6a0718SPierre Ossman 8921c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 8931c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 8946adb2a80SSrinivas Kandagatla mmci_reg_delay(host); 8951c6a0718SPierre Ossman } 8961c6a0718SPierre Ossman 8971c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 8981c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 8991c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 9001c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 9011c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 9021c6a0718SPierre Ossman } 9031c6a0718SPierre Ossman if (/*interrupt*/0) 9041c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 9051c6a0718SPierre Ossman 906ae7b0061SSrinivas Kandagatla if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 907ae7b0061SSrinivas Kandagatla c |= host->variant->data_cmd_enable; 908ae7b0061SSrinivas Kandagatla 9091c6a0718SPierre Ossman host->cmd = cmd; 9101c6a0718SPierre Ossman 9111c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 9121c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 9131c6a0718SPierre Ossman } 9141c6a0718SPierre Ossman 9151c6a0718SPierre Ossman static void 9161c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 9171c6a0718SPierre Ossman unsigned int status) 9181c6a0718SPierre Ossman { 9191cb9da50SUlf Hansson /* Make sure we have data to handle */ 9201cb9da50SUlf Hansson if (!data) 9211cb9da50SUlf Hansson return; 9221cb9da50SUlf Hansson 923f20f8f21SLinus Walleij /* First check for errors */ 924b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 925b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 9268cb28155SLinus Walleij u32 remain, success; 927f20f8f21SLinus Walleij 928c8ebae37SRussell King /* Terminate the DMA transfer */ 929653a761eSUlf Hansson if (dma_inprogress(host)) { 930c8ebae37SRussell King mmci_dma_data_error(host); 931653a761eSUlf Hansson mmci_dma_unmap(host, data); 932653a761eSUlf Hansson } 933c8ebae37SRussell King 934c8afc9d5SRussell King /* 935c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 936c8afc9d5SRussell King * the data counter gives the number of bytes transferred 937c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 938c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 939c8afc9d5SRussell King * matters for FIFO overruns only. 940c8afc9d5SRussell King */ 941f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 9428cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 9438cb28155SLinus Walleij 944c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 945c8afc9d5SRussell King status, success); 9468cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 9478cb28155SLinus Walleij /* Last block was not successful */ 948c8afc9d5SRussell King success -= 1; 94917b0429dSPierre Ossman data->error = -EILSEQ; 9508cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 95117b0429dSPierre Ossman data->error = -ETIMEDOUT; 952757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 953757df746SLinus Walleij data->error = -ECOMM; 954c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 95517b0429dSPierre Ossman data->error = -EIO; 956c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 957c8afc9d5SRussell King if (success > host->variant->fifosize) 958c8afc9d5SRussell King success -= host->variant->fifosize; 959c8afc9d5SRussell King else 960c8afc9d5SRussell King success = 0; 9618cb28155SLinus Walleij data->error = -EIO; 9624ce1d6cbSRabin Vincent } 96351d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 9641c6a0718SPierre Ossman } 965f20f8f21SLinus Walleij 9668cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 9678cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 968f20f8f21SLinus Walleij 969ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 970c8ebae37SRussell King if (dma_inprogress(host)) 971653a761eSUlf Hansson mmci_dma_finalize(host, data); 9721c6a0718SPierre Ossman mmci_stop_data(host); 9731c6a0718SPierre Ossman 9748cb28155SLinus Walleij if (!data->error) 9758cb28155SLinus Walleij /* The error clause is handled above, success! */ 97651d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 977f20f8f21SLinus Walleij 978024629c6SUlf Hansson if (!data->stop || host->mrq->sbc) { 9791c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 9801c6a0718SPierre Ossman } else { 9811c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 9821c6a0718SPierre Ossman } 9831c6a0718SPierre Ossman } 9841c6a0718SPierre Ossman } 9851c6a0718SPierre Ossman 9861c6a0718SPierre Ossman static void 9871c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 9881c6a0718SPierre Ossman unsigned int status) 9891c6a0718SPierre Ossman { 9901c6a0718SPierre Ossman void __iomem *base = host->base; 99149adc0caSLinus Walleij bool sbc; 992ad82bfeaSUlf Hansson 993ad82bfeaSUlf Hansson if (!cmd) 994ad82bfeaSUlf Hansson return; 995ad82bfeaSUlf Hansson 996ad82bfeaSUlf Hansson sbc = (cmd == host->mrq->sbc); 997ad82bfeaSUlf Hansson 99849adc0caSLinus Walleij /* 99949adc0caSLinus Walleij * We need to be one of these interrupts to be considered worth 100049adc0caSLinus Walleij * handling. Note that we tag on any latent IRQs postponed 100149adc0caSLinus Walleij * due to waiting for busy status. 100249adc0caSLinus Walleij */ 100349adc0caSLinus Walleij if (!((status|host->busy_status) & 100449adc0caSLinus Walleij (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1005ad82bfeaSUlf Hansson return; 10068d94b54dSUlf Hansson 100749adc0caSLinus Walleij /* 100849adc0caSLinus Walleij * ST Micro variant: handle busy detection. 100949adc0caSLinus Walleij */ 101049adc0caSLinus Walleij if (host->variant->busy_detect) { 101149adc0caSLinus Walleij bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 101249adc0caSLinus Walleij 101349adc0caSLinus Walleij /* We are busy with a command, return */ 101449adc0caSLinus Walleij if (host->busy_status && 101549adc0caSLinus Walleij (status & host->variant->busy_detect_flag)) 10168d94b54dSUlf Hansson return; 10178d94b54dSUlf Hansson 101849adc0caSLinus Walleij /* 101949adc0caSLinus Walleij * We were not busy, but we now got a busy response on 102049adc0caSLinus Walleij * something that was not an error, and we double-check 102149adc0caSLinus Walleij * that the special busy status bit is still set before 102249adc0caSLinus Walleij * proceeding. 102349adc0caSLinus Walleij */ 10248d94b54dSUlf Hansson if (!host->busy_status && busy_resp && 10258d94b54dSUlf Hansson !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 102649adc0caSLinus Walleij (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 10275cad24d8SJean-Nicolas Graux 10285cad24d8SJean-Nicolas Graux /* Clear the busy start IRQ */ 10295cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 10305cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 10315cad24d8SJean-Nicolas Graux 10325cad24d8SJean-Nicolas Graux /* Unmask the busy end IRQ */ 103349adc0caSLinus Walleij writel(readl(base + MMCIMASK0) | 103449adc0caSLinus Walleij host->variant->busy_detect_mask, 10358d94b54dSUlf Hansson base + MMCIMASK0); 103649adc0caSLinus Walleij /* 103749adc0caSLinus Walleij * Now cache the last response status code (until 103849adc0caSLinus Walleij * the busy bit goes low), and return. 103949adc0caSLinus Walleij */ 104049adc0caSLinus Walleij host->busy_status = 104149adc0caSLinus Walleij status & (MCI_CMDSENT|MCI_CMDRESPEND); 10428d94b54dSUlf Hansson return; 10438d94b54dSUlf Hansson } 10448d94b54dSUlf Hansson 104549adc0caSLinus Walleij /* 104649adc0caSLinus Walleij * At this point we are not busy with a command, we have 10475cad24d8SJean-Nicolas Graux * not received a new busy request, clear and mask the busy 10485cad24d8SJean-Nicolas Graux * end IRQ and fall through to process the IRQ. 104949adc0caSLinus Walleij */ 10508d94b54dSUlf Hansson if (host->busy_status) { 10515cad24d8SJean-Nicolas Graux 10525cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 10535cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 10545cad24d8SJean-Nicolas Graux 105549adc0caSLinus Walleij writel(readl(base + MMCIMASK0) & 105649adc0caSLinus Walleij ~host->variant->busy_detect_mask, 10578d94b54dSUlf Hansson base + MMCIMASK0); 10588d94b54dSUlf Hansson host->busy_status = 0; 10598d94b54dSUlf Hansson } 106049adc0caSLinus Walleij } 10611c6a0718SPierre Ossman 10621c6a0718SPierre Ossman host->cmd = NULL; 10631c6a0718SPierre Ossman 10641c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 106517b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 10661c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 106717b0429dSPierre Ossman cmd->error = -EILSEQ; 10689047b435SRussell King - ARM Linux } else { 10699047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 10709047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 10719047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 10729047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 10731c6a0718SPierre Ossman } 10741c6a0718SPierre Ossman 1075024629c6SUlf Hansson if ((!sbc && !cmd->data) || cmd->error) { 10763b6e3c73SUlf Hansson if (host->data) { 10773b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 1078653a761eSUlf Hansson if (dma_inprogress(host)) { 10793b6e3c73SUlf Hansson mmci_dma_data_error(host); 1080653a761eSUlf Hansson mmci_dma_unmap(host, host->data); 1081653a761eSUlf Hansson } 10821c6a0718SPierre Ossman mmci_stop_data(host); 10833b6e3c73SUlf Hansson } 1084024629c6SUlf Hansson mmci_request_end(host, host->mrq); 1085024629c6SUlf Hansson } else if (sbc) { 1086024629c6SUlf Hansson mmci_start_command(host, host->mrq->cmd, 0); 10871c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 10881c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 10891c6a0718SPierre Ossman } 10901c6a0718SPierre Ossman } 10911c6a0718SPierre Ossman 10929c34b73dSSrinivas Kandagatla static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 10939c34b73dSSrinivas Kandagatla { 10949c34b73dSSrinivas Kandagatla return remain - (readl(host->base + MMCIFIFOCNT) << 2); 10959c34b73dSSrinivas Kandagatla } 10969c34b73dSSrinivas Kandagatla 10979c34b73dSSrinivas Kandagatla static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 10989c34b73dSSrinivas Kandagatla { 10999c34b73dSSrinivas Kandagatla /* 11009c34b73dSSrinivas Kandagatla * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 11019c34b73dSSrinivas Kandagatla * from the fifo range should be used 11029c34b73dSSrinivas Kandagatla */ 11039c34b73dSSrinivas Kandagatla if (status & MCI_RXFIFOHALFFULL) 11049c34b73dSSrinivas Kandagatla return host->variant->fifohalfsize; 11059c34b73dSSrinivas Kandagatla else if (status & MCI_RXDATAAVLBL) 11069c34b73dSSrinivas Kandagatla return 4; 11079c34b73dSSrinivas Kandagatla 11089c34b73dSSrinivas Kandagatla return 0; 11099c34b73dSSrinivas Kandagatla } 11109c34b73dSSrinivas Kandagatla 11111c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 11121c6a0718SPierre Ossman { 11131c6a0718SPierre Ossman void __iomem *base = host->base; 11141c6a0718SPierre Ossman char *ptr = buffer; 11159c34b73dSSrinivas Kandagatla u32 status = readl(host->base + MMCISTATUS); 111626eed9a5SLinus Walleij int host_remain = host->size; 11171c6a0718SPierre Ossman 11181c6a0718SPierre Ossman do { 11199c34b73dSSrinivas Kandagatla int count = host->get_rx_fifocnt(host, status, host_remain); 11201c6a0718SPierre Ossman 11211c6a0718SPierre Ossman if (count > remain) 11221c6a0718SPierre Ossman count = remain; 11231c6a0718SPierre Ossman 11241c6a0718SPierre Ossman if (count <= 0) 11251c6a0718SPierre Ossman break; 11261c6a0718SPierre Ossman 1127393e5e24SUlf Hansson /* 1128393e5e24SUlf Hansson * SDIO especially may want to send something that is 1129393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 1130393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 1131393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 1132393e5e24SUlf Hansson */ 1133393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 1134393e5e24SUlf Hansson if (count < 4) { 1135393e5e24SUlf Hansson unsigned char buf[4]; 11364b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 1137393e5e24SUlf Hansson memcpy(ptr, buf, count); 1138393e5e24SUlf Hansson } else { 11394b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1140393e5e24SUlf Hansson count &= ~0x3; 1141393e5e24SUlf Hansson } 1142393e5e24SUlf Hansson } else { 11434b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1144393e5e24SUlf Hansson } 11451c6a0718SPierre Ossman 11461c6a0718SPierre Ossman ptr += count; 11471c6a0718SPierre Ossman remain -= count; 114826eed9a5SLinus Walleij host_remain -= count; 11491c6a0718SPierre Ossman 11501c6a0718SPierre Ossman if (remain == 0) 11511c6a0718SPierre Ossman break; 11521c6a0718SPierre Ossman 11531c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11541c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 11551c6a0718SPierre Ossman 11561c6a0718SPierre Ossman return ptr - buffer; 11571c6a0718SPierre Ossman } 11581c6a0718SPierre Ossman 11591c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 11601c6a0718SPierre Ossman { 11618301bb68SRabin Vincent struct variant_data *variant = host->variant; 11621c6a0718SPierre Ossman void __iomem *base = host->base; 11631c6a0718SPierre Ossman char *ptr = buffer; 11641c6a0718SPierre Ossman 11651c6a0718SPierre Ossman do { 11661c6a0718SPierre Ossman unsigned int count, maxcnt; 11671c6a0718SPierre Ossman 11688301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 11698301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 11701c6a0718SPierre Ossman count = min(remain, maxcnt); 11711c6a0718SPierre Ossman 117234177802SLinus Walleij /* 117334177802SLinus Walleij * SDIO especially may want to send something that is 117434177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 117534177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 117634177802SLinus Walleij * So compensate by adding +3 on the count, a single 117734177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 117834177802SLinus Walleij * 32bit writes etc. 117934177802SLinus Walleij */ 11804b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 11811c6a0718SPierre Ossman 11821c6a0718SPierre Ossman ptr += count; 11831c6a0718SPierre Ossman remain -= count; 11841c6a0718SPierre Ossman 11851c6a0718SPierre Ossman if (remain == 0) 11861c6a0718SPierre Ossman break; 11871c6a0718SPierre Ossman 11881c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11891c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 11901c6a0718SPierre Ossman 11911c6a0718SPierre Ossman return ptr - buffer; 11921c6a0718SPierre Ossman } 11931c6a0718SPierre Ossman 11941c6a0718SPierre Ossman /* 11951c6a0718SPierre Ossman * PIO data transfer IRQ handler. 11961c6a0718SPierre Ossman */ 11971c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 11981c6a0718SPierre Ossman { 11991c6a0718SPierre Ossman struct mmci_host *host = dev_id; 12004ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 12018301bb68SRabin Vincent struct variant_data *variant = host->variant; 12021c6a0718SPierre Ossman void __iomem *base = host->base; 12034ce1d6cbSRabin Vincent unsigned long flags; 12041c6a0718SPierre Ossman u32 status; 12051c6a0718SPierre Ossman 12061c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 12071c6a0718SPierre Ossman 120864de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 12091c6a0718SPierre Ossman 12104ce1d6cbSRabin Vincent local_irq_save(flags); 12114ce1d6cbSRabin Vincent 12121c6a0718SPierre Ossman do { 12131c6a0718SPierre Ossman unsigned int remain, len; 12141c6a0718SPierre Ossman char *buffer; 12151c6a0718SPierre Ossman 12161c6a0718SPierre Ossman /* 12171c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 12181c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 12191c6a0718SPierre Ossman * definition it is more than half empty. 12201c6a0718SPierre Ossman * 12211c6a0718SPierre Ossman * For read, check for data available. 12221c6a0718SPierre Ossman */ 12231c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 12241c6a0718SPierre Ossman break; 12251c6a0718SPierre Ossman 12264ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 12274ce1d6cbSRabin Vincent break; 12284ce1d6cbSRabin Vincent 12294ce1d6cbSRabin Vincent buffer = sg_miter->addr; 12304ce1d6cbSRabin Vincent remain = sg_miter->length; 12311c6a0718SPierre Ossman 12321c6a0718SPierre Ossman len = 0; 12331c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 12341c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 12351c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 12361c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 12371c6a0718SPierre Ossman 12384ce1d6cbSRabin Vincent sg_miter->consumed = len; 12391c6a0718SPierre Ossman 12401c6a0718SPierre Ossman host->size -= len; 12411c6a0718SPierre Ossman remain -= len; 12421c6a0718SPierre Ossman 12431c6a0718SPierre Ossman if (remain) 12441c6a0718SPierre Ossman break; 12451c6a0718SPierre Ossman 12461c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 12471c6a0718SPierre Ossman } while (1); 12481c6a0718SPierre Ossman 12494ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 12504ce1d6cbSRabin Vincent 12514ce1d6cbSRabin Vincent local_irq_restore(flags); 12524ce1d6cbSRabin Vincent 12531c6a0718SPierre Ossman /* 1254c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 1255c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 12561c6a0718SPierre Ossman */ 1257c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 12582686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 12591c6a0718SPierre Ossman 12601c6a0718SPierre Ossman /* 12611c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 12621c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 12631c6a0718SPierre Ossman * the chip itself has disabled the data path, and 12641c6a0718SPierre Ossman * stops us racing with our data end IRQ. 12651c6a0718SPierre Ossman */ 12661c6a0718SPierre Ossman if (host->size == 0) { 12672686b4b4SLinus Walleij mmci_set_mask1(host, 0); 12681c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 12691c6a0718SPierre Ossman } 12701c6a0718SPierre Ossman 12711c6a0718SPierre Ossman return IRQ_HANDLED; 12721c6a0718SPierre Ossman } 12731c6a0718SPierre Ossman 12741c6a0718SPierre Ossman /* 12751c6a0718SPierre Ossman * Handle completion of command and data transfers. 12761c6a0718SPierre Ossman */ 12771c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 12781c6a0718SPierre Ossman { 12791c6a0718SPierre Ossman struct mmci_host *host = dev_id; 12801c6a0718SPierre Ossman u32 status; 12811c6a0718SPierre Ossman int ret = 0; 12821c6a0718SPierre Ossman 12831c6a0718SPierre Ossman spin_lock(&host->lock); 12841c6a0718SPierre Ossman 12851c6a0718SPierre Ossman do { 12861c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 12872686b4b4SLinus Walleij 12882686b4b4SLinus Walleij if (host->singleirq) { 12892686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 12902686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 12912686b4b4SLinus Walleij 12922686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 12932686b4b4SLinus Walleij } 12942686b4b4SLinus Walleij 12958d94b54dSUlf Hansson /* 12965cad24d8SJean-Nicolas Graux * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 12975cad24d8SJean-Nicolas Graux * enabled) in mmci_cmd_irq() function where ST Micro busy 12985cad24d8SJean-Nicolas Graux * detection variant is handled. Considering the HW seems to be 12995cad24d8SJean-Nicolas Graux * triggering the IRQ on both edges while monitoring DAT0 for 13005cad24d8SJean-Nicolas Graux * busy completion and that same status bit is used to monitor 13015cad24d8SJean-Nicolas Graux * start and end of busy detection, special care must be taken 13025cad24d8SJean-Nicolas Graux * to make sure that both start and end interrupts are always 13035cad24d8SJean-Nicolas Graux * cleared one after the other. 13048d94b54dSUlf Hansson */ 13051c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 13065cad24d8SJean-Nicolas Graux if (host->variant->busy_detect) 13075cad24d8SJean-Nicolas Graux writel(status & ~host->variant->busy_detect_mask, 13085cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 13095cad24d8SJean-Nicolas Graux else 13101c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 13111c6a0718SPierre Ossman 131264de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 13131c6a0718SPierre Ossman 13147878289bSUlf Hansson if (host->variant->reversed_irq_handling) { 13157878289bSUlf Hansson mmci_data_irq(host, host->data, status); 13167878289bSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 13177878289bSUlf Hansson } else { 1318ad82bfeaSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 13191cb9da50SUlf Hansson mmci_data_irq(host, host->data, status); 13207878289bSUlf Hansson } 13211c6a0718SPierre Ossman 132249adc0caSLinus Walleij /* 132349adc0caSLinus Walleij * Don't poll for busy completion in irq context. 132449adc0caSLinus Walleij */ 132549adc0caSLinus Walleij if (host->variant->busy_detect && host->busy_status) 132649adc0caSLinus Walleij status &= ~host->variant->busy_detect_flag; 13278d94b54dSUlf Hansson 13281c6a0718SPierre Ossman ret = 1; 13291c6a0718SPierre Ossman } while (status); 13301c6a0718SPierre Ossman 13311c6a0718SPierre Ossman spin_unlock(&host->lock); 13321c6a0718SPierre Ossman 13331c6a0718SPierre Ossman return IRQ_RETVAL(ret); 13341c6a0718SPierre Ossman } 13351c6a0718SPierre Ossman 13361c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 13371c6a0718SPierre Ossman { 13381c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 13399e943021SLinus Walleij unsigned long flags; 13401c6a0718SPierre Ossman 13411c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 13421c6a0718SPierre Ossman 1343653a761eSUlf Hansson mrq->cmd->error = mmci_validate_data(host, mrq->data); 1344653a761eSUlf Hansson if (mrq->cmd->error) { 1345255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1346255d01afSPierre Ossman return; 1347255d01afSPierre Ossman } 1348255d01afSPierre Ossman 13499e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 13501c6a0718SPierre Ossman 13511c6a0718SPierre Ossman host->mrq = mrq; 13521c6a0718SPierre Ossman 135358c7ccbfSPer Forlin if (mrq->data) 135458c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 135558c7ccbfSPer Forlin 13561c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 13571c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 13581c6a0718SPierre Ossman 1359024629c6SUlf Hansson if (mrq->sbc) 1360024629c6SUlf Hansson mmci_start_command(host, mrq->sbc, 0); 1361024629c6SUlf Hansson else 13621c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 13631c6a0718SPierre Ossman 13649e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 13651c6a0718SPierre Ossman } 13661c6a0718SPierre Ossman 13671c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 13681c6a0718SPierre Ossman { 13691c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 13707d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1371a6a6464aSLinus Walleij u32 pwr = 0; 1372a6a6464aSLinus Walleij unsigned long flags; 1373db90f91fSLee Jones int ret; 13741c6a0718SPierre Ossman 1375bc521818SUlf Hansson if (host->plat->ios_handler && 1376bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1377bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1378bc521818SUlf Hansson 13791c6a0718SPierre Ossman switch (ios->power_mode) { 13801c6a0718SPierre Ossman case MMC_POWER_OFF: 1381599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1382599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1383237fb5e6SLee Jones 13847c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1385237fb5e6SLee Jones regulator_disable(mmc->supply.vqmmc); 13867c0136efSUlf Hansson host->vqmmc_enabled = false; 13877c0136efSUlf Hansson } 1388237fb5e6SLee Jones 13891c6a0718SPierre Ossman break; 13901c6a0718SPierre Ossman case MMC_POWER_UP: 1391599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1392599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1393599c1d5cSUlf Hansson 13947d72a1d4SUlf Hansson /* 13957d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 13967d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 13977d72a1d4SUlf Hansson * configured in the variant data. 13987d72a1d4SUlf Hansson */ 13997d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 14007d72a1d4SUlf Hansson 14011c6a0718SPierre Ossman break; 14021c6a0718SPierre Ossman case MMC_POWER_ON: 14037c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1404db90f91fSLee Jones ret = regulator_enable(mmc->supply.vqmmc); 1405db90f91fSLee Jones if (ret < 0) 1406db90f91fSLee Jones dev_err(mmc_dev(mmc), 1407db90f91fSLee Jones "failed to enable vqmmc regulator\n"); 14087c0136efSUlf Hansson else 14097c0136efSUlf Hansson host->vqmmc_enabled = true; 1410db90f91fSLee Jones } 1411237fb5e6SLee Jones 14121c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 14131c6a0718SPierre Ossman break; 14141c6a0718SPierre Ossman } 14151c6a0718SPierre Ossman 14164d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 14174d1a3a0dSUlf Hansson /* 14184d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 14194d1a3a0dSUlf Hansson * indicating signal direction for the signals in 14204d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 14214d1a3a0dSUlf Hansson */ 14224593df29SUlf Hansson pwr |= host->pwr_reg_add; 14234d1a3a0dSUlf Hansson 14244d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 14254d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 14264d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 14274d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 14284d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 14294d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 14304d1a3a0dSUlf Hansson } 14314d1a3a0dSUlf Hansson 1432cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1433f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 14341c6a0718SPierre Ossman pwr |= MCI_ROD; 1435cc30d60eSLinus Walleij else { 1436cc30d60eSLinus Walleij /* 1437cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1438cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1439cc30d60eSLinus Walleij */ 1440cc30d60eSLinus Walleij pwr |= MCI_OD; 1441cc30d60eSLinus Walleij } 1442cc30d60eSLinus Walleij } 14431c6a0718SPierre Ossman 1444f4670daeSUlf Hansson /* 1445f4670daeSUlf Hansson * If clock = 0 and the variant requires the MMCIPOWER to be used for 1446f4670daeSUlf Hansson * gating the clock, the MCI_PWR_ON bit is cleared. 1447f4670daeSUlf Hansson */ 1448f4670daeSUlf Hansson if (!ios->clock && variant->pwrreg_clkgate) 1449f4670daeSUlf Hansson pwr &= ~MCI_PWR_ON; 1450f4670daeSUlf Hansson 14513f4e6f7bSSrinivas Kandagatla if (host->variant->explicit_mclk_control && 14523f4e6f7bSSrinivas Kandagatla ios->clock != host->clock_cache) { 14533f4e6f7bSSrinivas Kandagatla ret = clk_set_rate(host->clk, ios->clock); 14543f4e6f7bSSrinivas Kandagatla if (ret < 0) 14553f4e6f7bSSrinivas Kandagatla dev_err(mmc_dev(host->mmc), 14563f4e6f7bSSrinivas Kandagatla "Error setting clock rate (%d)\n", ret); 14573f4e6f7bSSrinivas Kandagatla else 14583f4e6f7bSSrinivas Kandagatla host->mclk = clk_get_rate(host->clk); 14593f4e6f7bSSrinivas Kandagatla } 14603f4e6f7bSSrinivas Kandagatla host->clock_cache = ios->clock; 14613f4e6f7bSSrinivas Kandagatla 1462a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1463a6a6464aSLinus Walleij 1464a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 14657437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1466f829c042SUlf Hansson mmci_reg_delay(host); 1467a6a6464aSLinus Walleij 1468a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 14691c6a0718SPierre Ossman } 14701c6a0718SPierre Ossman 147189001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 147289001446SRussell King { 147389001446SRussell King struct mmci_host *host = mmc_priv(mmc); 147429719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 1475d2762090SUlf Hansson unsigned int status = mmc_gpio_get_cd(mmc); 147689001446SRussell King 1477d2762090SUlf Hansson if (status == -ENOSYS) { 14784b8caec0SRabin Vincent if (!plat->status) 14794b8caec0SRabin Vincent return 1; /* Assume always present */ 14804b8caec0SRabin Vincent 148129719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 1482d2762090SUlf Hansson } 148374bc8093SRussell King return status; 148489001446SRussell King } 148589001446SRussell King 14860f3ed7f7SUlf Hansson static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 14870f3ed7f7SUlf Hansson { 14880f3ed7f7SUlf Hansson int ret = 0; 14890f3ed7f7SUlf Hansson 14900f3ed7f7SUlf Hansson if (!IS_ERR(mmc->supply.vqmmc)) { 14910f3ed7f7SUlf Hansson 14920f3ed7f7SUlf Hansson switch (ios->signal_voltage) { 14930f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_330: 14940f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14950f3ed7f7SUlf Hansson 2700000, 3600000); 14960f3ed7f7SUlf Hansson break; 14970f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_180: 14980f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14990f3ed7f7SUlf Hansson 1700000, 1950000); 15000f3ed7f7SUlf Hansson break; 15010f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_120: 15020f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 15030f3ed7f7SUlf Hansson 1100000, 1300000); 15040f3ed7f7SUlf Hansson break; 15050f3ed7f7SUlf Hansson } 15060f3ed7f7SUlf Hansson 15070f3ed7f7SUlf Hansson if (ret) 15080f3ed7f7SUlf Hansson dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 15090f3ed7f7SUlf Hansson } 15100f3ed7f7SUlf Hansson 15110f3ed7f7SUlf Hansson return ret; 15120f3ed7f7SUlf Hansson } 15130f3ed7f7SUlf Hansson 151401259620SUlf Hansson static struct mmc_host_ops mmci_ops = { 15151c6a0718SPierre Ossman .request = mmci_request, 151658c7ccbfSPer Forlin .pre_req = mmci_pre_request, 151758c7ccbfSPer Forlin .post_req = mmci_post_request, 15181c6a0718SPierre Ossman .set_ios = mmci_set_ios, 1519d2762090SUlf Hansson .get_ro = mmc_gpio_get_ro, 152089001446SRussell King .get_cd = mmci_get_cd, 15210f3ed7f7SUlf Hansson .start_signal_voltage_switch = mmci_sig_volt_switch, 15221c6a0718SPierre Ossman }; 15231c6a0718SPierre Ossman 152478f87df2SUlf Hansson static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 152578f87df2SUlf Hansson { 15264593df29SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 152778f87df2SUlf Hansson int ret = mmc_of_parse(mmc); 1528000bc9d5SLee Jones 152978f87df2SUlf Hansson if (ret) 153078f87df2SUlf Hansson return ret; 1531000bc9d5SLee Jones 15324593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat0", NULL)) 15334593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA0DIREN; 15344593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat2", NULL)) 15354593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA2DIREN; 15364593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat31", NULL)) 15374593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA31DIREN; 15384593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat74", NULL)) 15394593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA74DIREN; 15404593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-cmd", NULL)) 15414593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_CMDDIREN; 15424593df29SUlf Hansson if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 15434593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_FBCLKEN; 15444593df29SUlf Hansson 1545000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 154678f87df2SUlf Hansson mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1547000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 154878f87df2SUlf Hansson mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1549000bc9d5SLee Jones 155078f87df2SUlf Hansson return 0; 1551000bc9d5SLee Jones } 1552000bc9d5SLee Jones 1553c3be1efdSBill Pemberton static int mmci_probe(struct amba_device *dev, 1554aa25afadSRussell King const struct amba_id *id) 15551c6a0718SPierre Ossman { 15566ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1557000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 15584956e109SRabin Vincent struct variant_data *variant = id->data; 15591c6a0718SPierre Ossman struct mmci_host *host; 15601c6a0718SPierre Ossman struct mmc_host *mmc; 15611c6a0718SPierre Ossman int ret; 15621c6a0718SPierre Ossman 1563000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1564000bc9d5SLee Jones if (!plat && !np) { 1565000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1566000bc9d5SLee Jones return -EINVAL; 15671c6a0718SPierre Ossman } 15681c6a0718SPierre Ossman 1569b9b52918SLee Jones if (!plat) { 1570b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1571b9b52918SLee Jones if (!plat) 1572b9b52918SLee Jones return -ENOMEM; 1573b9b52918SLee Jones } 1574b9b52918SLee Jones 15751c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1576ef289982SUlf Hansson if (!mmc) 1577ef289982SUlf Hansson return -ENOMEM; 15781c6a0718SPierre Ossman 157978f87df2SUlf Hansson ret = mmci_of_parse(np, mmc); 158078f87df2SUlf Hansson if (ret) 158178f87df2SUlf Hansson goto host_free; 158278f87df2SUlf Hansson 15831c6a0718SPierre Ossman host = mmc_priv(mmc); 15844ea580f1SRabin Vincent host->mmc = mmc; 1585012b7d33SRussell King 1586012b7d33SRussell King host->hw_designer = amba_manf(dev); 1587012b7d33SRussell King host->hw_revision = amba_rev(dev); 158864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 158964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1590012b7d33SRussell King 1591665ba56fSUlf Hansson host->clk = devm_clk_get(&dev->dev, NULL); 15921c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 15931c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 15941c6a0718SPierre Ossman goto host_free; 15951c6a0718SPierre Ossman } 15961c6a0718SPierre Ossman 1597ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 15981c6a0718SPierre Ossman if (ret) 1599665ba56fSUlf Hansson goto host_free; 16001c6a0718SPierre Ossman 16019c34b73dSSrinivas Kandagatla if (variant->qcom_fifo) 16029c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 16039c34b73dSSrinivas Kandagatla else 16049c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_get_rx_fifocnt; 16059c34b73dSSrinivas Kandagatla 16061c6a0718SPierre Ossman host->plat = plat; 16074956e109SRabin Vincent host->variant = variant; 16081c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1609c8df9a53SLinus Walleij /* 1610c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1611c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1612c8df9a53SLinus Walleij * (if possible). 1613c8df9a53SLinus Walleij */ 1614dc6500bfSSrinivas Kandagatla if (host->mclk > variant->f_max) { 1615dc6500bfSSrinivas Kandagatla ret = clk_set_rate(host->clk, variant->f_max); 1616c8df9a53SLinus Walleij if (ret < 0) 1617c8df9a53SLinus Walleij goto clk_disable; 1618c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 161964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 162064de0289SLinus Walleij host->mclk); 1621c8df9a53SLinus Walleij } 1622ef289982SUlf Hansson 1623c8ebae37SRussell King host->phybase = dev->res.start; 1624ef289982SUlf Hansson host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1625ef289982SUlf Hansson if (IS_ERR(host->base)) { 1626ef289982SUlf Hansson ret = PTR_ERR(host->base); 16271c6a0718SPierre Ossman goto clk_disable; 16281c6a0718SPierre Ossman } 16291c6a0718SPierre Ossman 16307f294e49SLinus Walleij /* 16317f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 16327f294e49SLinus Walleij * clock divider equations which means that the minimum divider 16337f294e49SLinus Walleij * differs too. 16343f4e6f7bSSrinivas Kandagatla * on Qualcomm like controllers get the nearest minimum clock to 100Khz 16357f294e49SLinus Walleij */ 16367f294e49SLinus Walleij if (variant->st_clkdiv) 16377f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 16383f4e6f7bSSrinivas Kandagatla else if (variant->explicit_mclk_control) 16393f4e6f7bSSrinivas Kandagatla mmc->f_min = clk_round_rate(host->clk, 100000); 16407f294e49SLinus Walleij else 16417f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1642808d97ccSLinus Walleij /* 164378f87df2SUlf Hansson * If no maximum operating frequency is supplied, fall back to use 164478f87df2SUlf Hansson * the module parameter, which has a (low) default value in case it 164578f87df2SUlf Hansson * is not specified. Either value must not exceed the clock rate into 16465080a08dSUlf Hansson * the block, of course. 1647808d97ccSLinus Walleij */ 164878f87df2SUlf Hansson if (mmc->f_max) 16493f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16503f4e6f7bSSrinivas Kandagatla min(variant->f_max, mmc->f_max) : 16513f4e6f7bSSrinivas Kandagatla min(host->mclk, mmc->f_max); 1652808d97ccSLinus Walleij else 16533f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16543f4e6f7bSSrinivas Kandagatla fmax : min(host->mclk, fmax); 16553f4e6f7bSSrinivas Kandagatla 16563f4e6f7bSSrinivas Kandagatla 165764de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 165864de0289SLinus Walleij 1659599c1d5cSUlf Hansson /* Get regulators and the supported OCR mask */ 16609369c97cSBjorn Andersson ret = mmc_regulator_get_supply(mmc); 16619369c97cSBjorn Andersson if (ret == -EPROBE_DEFER) 16629369c97cSBjorn Andersson goto clk_disable; 16639369c97cSBjorn Andersson 1664599c1d5cSUlf Hansson if (!mmc->ocr_avail) 16651c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 1666599c1d5cSUlf Hansson else if (plat->ocr_mask) 1667599c1d5cSUlf Hansson dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1668599c1d5cSUlf Hansson 166978f87df2SUlf Hansson /* DT takes precedence over platform data. */ 167078f87df2SUlf Hansson if (!np) { 1671d2762090SUlf Hansson if (!plat->cd_invert) 1672d2762090SUlf Hansson mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1673d2762090SUlf Hansson mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 167478f87df2SUlf Hansson } 16751c6a0718SPierre Ossman 16769dd8a8b8SUlf Hansson /* We support these capabilities. */ 16779dd8a8b8SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 16789dd8a8b8SUlf Hansson 167949adc0caSLinus Walleij /* 168049adc0caSLinus Walleij * Enable busy detection. 168149adc0caSLinus Walleij */ 16828d94b54dSUlf Hansson if (variant->busy_detect) { 16838d94b54dSUlf Hansson mmci_ops.card_busy = mmci_card_busy; 168449adc0caSLinus Walleij /* 168549adc0caSLinus Walleij * Not all variants have a flag to enable busy detection 168649adc0caSLinus Walleij * in the DPSM, but if they do, set it here. 168749adc0caSLinus Walleij */ 168849adc0caSLinus Walleij if (variant->busy_dpsm_flag) 168949adc0caSLinus Walleij mmci_write_datactrlreg(host, 169049adc0caSLinus Walleij host->variant->busy_dpsm_flag); 16918d94b54dSUlf Hansson mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 16928d94b54dSUlf Hansson mmc->max_busy_timeout = 0; 16938d94b54dSUlf Hansson } 16948d94b54dSUlf Hansson 16958d94b54dSUlf Hansson mmc->ops = &mmci_ops; 16968d94b54dSUlf Hansson 169770be208fSUlf Hansson /* We support these PM capabilities. */ 169878f87df2SUlf Hansson mmc->pm_caps |= MMC_PM_KEEP_POWER; 169970be208fSUlf Hansson 17001c6a0718SPierre Ossman /* 17011c6a0718SPierre Ossman * We can do SGIO 17021c6a0718SPierre Ossman */ 1703a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 17041c6a0718SPierre Ossman 17051c6a0718SPierre Ossman /* 170608458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 170708458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 170808458ef6SRabin Vincent * single request. 17091c6a0718SPierre Ossman */ 171008458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 17111c6a0718SPierre Ossman 17121c6a0718SPierre Ossman /* 17131c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 17141c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 17151c6a0718SPierre Ossman */ 17161c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 17171c6a0718SPierre Ossman 17181c6a0718SPierre Ossman /* 17191c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 17201c6a0718SPierre Ossman */ 17218f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 17221c6a0718SPierre Ossman 17231c6a0718SPierre Ossman /* 17248f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 17258f7f6b7eSWill Deacon * the maximum request size. 17261c6a0718SPierre Ossman */ 17278f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 17281c6a0718SPierre Ossman 17291c6a0718SPierre Ossman spin_lock_init(&host->lock); 17301c6a0718SPierre Ossman 17311c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 17321c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 17331c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 17341c6a0718SPierre Ossman 1735ce437aa4SLinus Walleij /* 1736ce437aa4SLinus Walleij * If: 1737ce437aa4SLinus Walleij * - not using DT but using a descriptor table, or 1738ce437aa4SLinus Walleij * - using a table of descriptors ALONGSIDE DT, or 1739ce437aa4SLinus Walleij * look up these descriptors named "cd" and "wp" right here, fail 1740ce437aa4SLinus Walleij * silently of these do not exist and proceed to try platform data 1741ce437aa4SLinus Walleij */ 1742ce437aa4SLinus Walleij if (!np) { 174389168b48SLinus Walleij ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1744ce437aa4SLinus Walleij if (ret < 0) { 1745ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1746ce437aa4SLinus Walleij goto clk_disable; 1747ce437aa4SLinus Walleij else if (gpio_is_valid(plat->gpio_cd)) { 1748d2762090SUlf Hansson ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1749d2762090SUlf Hansson if (ret) 1750ef289982SUlf Hansson goto clk_disable; 175189001446SRussell King } 1752ce437aa4SLinus Walleij } 1753ce437aa4SLinus Walleij 175489168b48SLinus Walleij ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1755ce437aa4SLinus Walleij if (ret < 0) { 1756ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1757ce437aa4SLinus Walleij goto clk_disable; 1758ce437aa4SLinus Walleij else if (gpio_is_valid(plat->gpio_wp)) { 1759d2762090SUlf Hansson ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1760d2762090SUlf Hansson if (ret) 1761ef289982SUlf Hansson goto clk_disable; 176289001446SRussell King } 1763ce437aa4SLinus Walleij } 1764ce437aa4SLinus Walleij } 176589001446SRussell King 1766ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1767ef289982SUlf Hansson DRIVER_NAME " (cmd)", host); 17681c6a0718SPierre Ossman if (ret) 1769ef289982SUlf Hansson goto clk_disable; 17701c6a0718SPierre Ossman 1771dfb85185SRussell King if (!dev->irq[1]) 17722686b4b4SLinus Walleij host->singleirq = true; 17732686b4b4SLinus Walleij else { 1774ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1775ef289982SUlf Hansson IRQF_SHARED, DRIVER_NAME " (pio)", host); 17761c6a0718SPierre Ossman if (ret) 1777ef289982SUlf Hansson goto clk_disable; 17782686b4b4SLinus Walleij } 17791c6a0718SPierre Ossman 17808cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 17811c6a0718SPierre Ossman 17821c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 17831c6a0718SPierre Ossman 1784c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1785c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1786c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1787c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1788c8ebae37SRussell King 1789c8ebae37SRussell King mmci_dma_setup(host); 17901c6a0718SPierre Ossman 17912cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 17922cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 17931c3be369SRussell King 17948c11a94dSRussell King mmc_add_host(mmc); 17958c11a94dSRussell King 17966f2d3c89SUlf Hansson pm_runtime_put(&dev->dev); 17971c6a0718SPierre Ossman return 0; 17981c6a0718SPierre Ossman 17991c6a0718SPierre Ossman clk_disable: 1800ac940938SJulia Lawall clk_disable_unprepare(host->clk); 18011c6a0718SPierre Ossman host_free: 18021c6a0718SPierre Ossman mmc_free_host(mmc); 18031c6a0718SPierre Ossman return ret; 18041c6a0718SPierre Ossman } 18051c6a0718SPierre Ossman 18066e0ee714SBill Pemberton static int mmci_remove(struct amba_device *dev) 18071c6a0718SPierre Ossman { 18081c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 18091c6a0718SPierre Ossman 18101c6a0718SPierre Ossman if (mmc) { 18111c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 18121c6a0718SPierre Ossman 18131c3be369SRussell King /* 18141c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 18151c3be369SRussell King * version here so that we can access the primecell. 18161c3be369SRussell King */ 18171c3be369SRussell King pm_runtime_get_sync(&dev->dev); 18181c3be369SRussell King 18191c6a0718SPierre Ossman mmc_remove_host(mmc); 18201c6a0718SPierre Ossman 18211c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 18221c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 18231c6a0718SPierre Ossman 18241c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 18251c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 18261c6a0718SPierre Ossman 1827c8ebae37SRussell King mmci_dma_release(host); 1828ac940938SJulia Lawall clk_disable_unprepare(host->clk); 18291c6a0718SPierre Ossman mmc_free_host(mmc); 18301c6a0718SPierre Ossman } 18311c6a0718SPierre Ossman 18321c6a0718SPierre Ossman return 0; 18331c6a0718SPierre Ossman } 18341c6a0718SPierre Ossman 1835571dce4fSUlf Hansson #ifdef CONFIG_PM 18361ff44433SUlf Hansson static void mmci_save(struct mmci_host *host) 18371ff44433SUlf Hansson { 18381ff44433SUlf Hansson unsigned long flags; 18391ff44433SUlf Hansson 18401ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18411ff44433SUlf Hansson 18421ff44433SUlf Hansson writel(0, host->base + MMCIMASK0); 184342dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18441ff44433SUlf Hansson writel(0, host->base + MMCIDATACTRL); 18451ff44433SUlf Hansson writel(0, host->base + MMCIPOWER); 18461ff44433SUlf Hansson writel(0, host->base + MMCICLOCK); 184742dcc89aSUlf Hansson } 18481ff44433SUlf Hansson mmci_reg_delay(host); 18491ff44433SUlf Hansson 18501ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18511ff44433SUlf Hansson } 18521ff44433SUlf Hansson 18531ff44433SUlf Hansson static void mmci_restore(struct mmci_host *host) 18541ff44433SUlf Hansson { 18551ff44433SUlf Hansson unsigned long flags; 18561ff44433SUlf Hansson 18571ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18581ff44433SUlf Hansson 185942dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18601ff44433SUlf Hansson writel(host->clk_reg, host->base + MMCICLOCK); 18611ff44433SUlf Hansson writel(host->datactrl_reg, host->base + MMCIDATACTRL); 18621ff44433SUlf Hansson writel(host->pwr_reg, host->base + MMCIPOWER); 186342dcc89aSUlf Hansson } 18641ff44433SUlf Hansson writel(MCI_IRQENABLE, host->base + MMCIMASK0); 18651ff44433SUlf Hansson mmci_reg_delay(host); 18661ff44433SUlf Hansson 18671ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18681ff44433SUlf Hansson } 18691ff44433SUlf Hansson 18708259293aSUlf Hansson static int mmci_runtime_suspend(struct device *dev) 18718259293aSUlf Hansson { 18728259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18738259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18748259293aSUlf Hansson 18758259293aSUlf Hansson if (mmc) { 18768259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 1877e36bd9c6SUlf Hansson pinctrl_pm_select_sleep_state(dev); 18781ff44433SUlf Hansson mmci_save(host); 18798259293aSUlf Hansson clk_disable_unprepare(host->clk); 18808259293aSUlf Hansson } 18818259293aSUlf Hansson 18828259293aSUlf Hansson return 0; 18838259293aSUlf Hansson } 18848259293aSUlf Hansson 18858259293aSUlf Hansson static int mmci_runtime_resume(struct device *dev) 18868259293aSUlf Hansson { 18878259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18888259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18898259293aSUlf Hansson 18908259293aSUlf Hansson if (mmc) { 18918259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 18928259293aSUlf Hansson clk_prepare_enable(host->clk); 18931ff44433SUlf Hansson mmci_restore(host); 1894e36bd9c6SUlf Hansson pinctrl_pm_select_default_state(dev); 18958259293aSUlf Hansson } 18968259293aSUlf Hansson 18978259293aSUlf Hansson return 0; 18988259293aSUlf Hansson } 18998259293aSUlf Hansson #endif 19008259293aSUlf Hansson 190148fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 1902f3737fa3SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1903f3737fa3SUlf Hansson pm_runtime_force_resume) 19046ed23b80SRafael J. Wysocki SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 190548fa7003SUlf Hansson }; 190648fa7003SUlf Hansson 190788411deaSArvind Yadav static const struct amba_id mmci_ids[] = { 19081c6a0718SPierre Ossman { 19091c6a0718SPierre Ossman .id = 0x00041180, 1910768fbc18SPawel Moll .mask = 0xff0fffff, 19114956e109SRabin Vincent .data = &variant_arm, 19121c6a0718SPierre Ossman }, 19131c6a0718SPierre Ossman { 1914768fbc18SPawel Moll .id = 0x01041180, 1915768fbc18SPawel Moll .mask = 0xff0fffff, 1916768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1917768fbc18SPawel Moll }, 1918768fbc18SPawel Moll { 19193a37298aSPawel Moll .id = 0x02041180, 19203a37298aSPawel Moll .mask = 0xff0fffff, 19213a37298aSPawel Moll .data = &variant_arm_extended_fifo_hwfc, 19223a37298aSPawel Moll }, 19233a37298aSPawel Moll { 19241c6a0718SPierre Ossman .id = 0x00041181, 19251c6a0718SPierre Ossman .mask = 0x000fffff, 19264956e109SRabin Vincent .data = &variant_arm, 19271c6a0718SPierre Ossman }, 1928cc30d60eSLinus Walleij /* ST Micro variants */ 1929cc30d60eSLinus Walleij { 1930cc30d60eSLinus Walleij .id = 0x00180180, 1931cc30d60eSLinus Walleij .mask = 0x00ffffff, 19324956e109SRabin Vincent .data = &variant_u300, 1933cc30d60eSLinus Walleij }, 1934cc30d60eSLinus Walleij { 193534fd4213SLinus Walleij .id = 0x10180180, 193634fd4213SLinus Walleij .mask = 0xf0ffffff, 193734fd4213SLinus Walleij .data = &variant_nomadik, 193834fd4213SLinus Walleij }, 193934fd4213SLinus Walleij { 1940cc30d60eSLinus Walleij .id = 0x00280180, 1941cc30d60eSLinus Walleij .mask = 0x00ffffff, 19420bcb7efdSLinus Walleij .data = &variant_nomadik, 19434956e109SRabin Vincent }, 19444956e109SRabin Vincent { 19454956e109SRabin Vincent .id = 0x00480180, 19461784b157SPhilippe Langlais .mask = 0xf0ffffff, 19474956e109SRabin Vincent .data = &variant_ux500, 1948cc30d60eSLinus Walleij }, 19491784b157SPhilippe Langlais { 19501784b157SPhilippe Langlais .id = 0x10480180, 19511784b157SPhilippe Langlais .mask = 0xf0ffffff, 19521784b157SPhilippe Langlais .data = &variant_ux500v2, 19531784b157SPhilippe Langlais }, 195455b604aeSSrinivas Kandagatla /* Qualcomm variants */ 195555b604aeSSrinivas Kandagatla { 195655b604aeSSrinivas Kandagatla .id = 0x00051180, 195755b604aeSSrinivas Kandagatla .mask = 0x000fffff, 195855b604aeSSrinivas Kandagatla .data = &variant_qcom, 195955b604aeSSrinivas Kandagatla }, 19601c6a0718SPierre Ossman { 0, 0 }, 19611c6a0718SPierre Ossman }; 19621c6a0718SPierre Ossman 19639f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 19649f99835fSDave Martin 19651c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 19661c6a0718SPierre Ossman .drv = { 19671c6a0718SPierre Ossman .name = DRIVER_NAME, 196848fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 19691c6a0718SPierre Ossman }, 19701c6a0718SPierre Ossman .probe = mmci_probe, 19710433c143SBill Pemberton .remove = mmci_remove, 19721c6a0718SPierre Ossman .id_table = mmci_ids, 19731c6a0718SPierre Ossman }; 19741c6a0718SPierre Ossman 19759e5ed094Sviresh kumar module_amba_driver(mmci_driver); 19761c6a0718SPierre Ossman 19771c6a0718SPierre Ossman module_param(fmax, uint, 0444); 19781c6a0718SPierre Ossman 19791c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 19801c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1981