11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 16ef289982SUlf Hansson #include <linux/io.h> 171c6a0718SPierre Ossman #include <linux/interrupt.h> 18613b152cSRussell King #include <linux/kernel.h> 19000bc9d5SLee Jones #include <linux/slab.h> 201c6a0718SPierre Ossman #include <linux/delay.h> 211c6a0718SPierre Ossman #include <linux/err.h> 221c6a0718SPierre Ossman #include <linux/highmem.h> 23019a5f56SNicolas Pitre #include <linux/log2.h> 2470be208fSUlf Hansson #include <linux/mmc/pm.h> 251c6a0718SPierre Ossman #include <linux/mmc/host.h> 2634177802SLinus Walleij #include <linux/mmc/card.h> 27d2762090SUlf Hansson #include <linux/mmc/slot-gpio.h> 281c6a0718SPierre Ossman #include <linux/amba/bus.h> 291c6a0718SPierre Ossman #include <linux/clk.h> 30bd6dee6fSJens Axboe #include <linux/scatterlist.h> 319ef986a6SLinus Walleij #include <linux/of.h> 3234e84f39SLinus Walleij #include <linux/regulator/consumer.h> 33c8ebae37SRussell King #include <linux/dmaengine.h> 34c8ebae37SRussell King #include <linux/dma-mapping.h> 35c8ebae37SRussell King #include <linux/amba/mmci.h> 361c3be369SRussell King #include <linux/pm_runtime.h> 37258aea76SViresh Kumar #include <linux/types.h> 38a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 391c6a0718SPierre Ossman 401c6a0718SPierre Ossman #include <asm/div64.h> 411c6a0718SPierre Ossman #include <asm/io.h> 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #include "mmci.h" 449cb15142SSrinivas Kandagatla #include "mmci_qcom_dml.h" 451c6a0718SPierre Ossman 461c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 471c6a0718SPierre Ossman 481c6a0718SPierre Ossman static unsigned int fmax = 515633; 491c6a0718SPierre Ossman 504956e109SRabin Vincent static struct variant_data variant_arm = { 518301bb68SRabin Vincent .fifosize = 16 * 4, 528301bb68SRabin Vincent .fifohalfsize = 8 * 4, 5308458ef6SRabin Vincent .datalength_bits = 16, 547d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 55dc6500bfSSrinivas Kandagatla .f_max = 100000000, 567878289bSUlf Hansson .reversed_irq_handling = true, 576ea9cdf3SPatrice Chotard .mmcimask1 = true, 587f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 5911dfb970SPatrice Chotard .opendrain = MCI_ROD, 604956e109SRabin Vincent }; 614956e109SRabin Vincent 62768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 63768fbc18SPawel Moll .fifosize = 128 * 4, 64768fbc18SPawel Moll .fifohalfsize = 64 * 4, 65768fbc18SPawel Moll .datalength_bits = 16, 667d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 67dc6500bfSSrinivas Kandagatla .f_max = 100000000, 686ea9cdf3SPatrice Chotard .mmcimask1 = true, 697f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 7011dfb970SPatrice Chotard .opendrain = MCI_ROD, 71768fbc18SPawel Moll }; 72768fbc18SPawel Moll 733a37298aSPawel Moll static struct variant_data variant_arm_extended_fifo_hwfc = { 743a37298aSPawel Moll .fifosize = 128 * 4, 753a37298aSPawel Moll .fifohalfsize = 64 * 4, 763a37298aSPawel Moll .clkreg_enable = MCI_ARM_HWFCEN, 773a37298aSPawel Moll .datalength_bits = 16, 783a37298aSPawel Moll .pwrreg_powerup = MCI_PWR_UP, 79dc6500bfSSrinivas Kandagatla .f_max = 100000000, 806ea9cdf3SPatrice Chotard .mmcimask1 = true, 817f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 8211dfb970SPatrice Chotard .opendrain = MCI_ROD, 833a37298aSPawel Moll }; 843a37298aSPawel Moll 854956e109SRabin Vincent static struct variant_data variant_u300 = { 868301bb68SRabin Vincent .fifosize = 16 * 4, 878301bb68SRabin Vincent .fifohalfsize = 8 * 4, 8849ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 89e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 9008458ef6SRabin Vincent .datalength_bits = 16, 915db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 92c7354133SSrinivas Kandagatla .st_sdio = true, 937d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 94dc6500bfSSrinivas Kandagatla .f_max = 100000000, 954d1a3a0dSUlf Hansson .signal_direction = true, 96f4670daeSUlf Hansson .pwrreg_clkgate = true, 971ff44433SUlf Hansson .pwrreg_nopower = true, 986ea9cdf3SPatrice Chotard .mmcimask1 = true, 997f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 10011dfb970SPatrice Chotard .opendrain = MCI_OD, 1014956e109SRabin Vincent }; 1024956e109SRabin Vincent 10334fd4213SLinus Walleij static struct variant_data variant_nomadik = { 10434fd4213SLinus Walleij .fifosize = 16 * 4, 10534fd4213SLinus Walleij .fifohalfsize = 8 * 4, 10634fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 107f5abc767SLinus Walleij .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 10834fd4213SLinus Walleij .datalength_bits = 24, 1095db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 110c7354133SSrinivas Kandagatla .st_sdio = true, 11134fd4213SLinus Walleij .st_clkdiv = true, 11234fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 113dc6500bfSSrinivas Kandagatla .f_max = 100000000, 11434fd4213SLinus Walleij .signal_direction = true, 115f4670daeSUlf Hansson .pwrreg_clkgate = true, 1161ff44433SUlf Hansson .pwrreg_nopower = true, 1176ea9cdf3SPatrice Chotard .mmcimask1 = true, 1187f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 11911dfb970SPatrice Chotard .opendrain = MCI_OD, 12034fd4213SLinus Walleij }; 12134fd4213SLinus Walleij 1224956e109SRabin Vincent static struct variant_data variant_ux500 = { 1238301bb68SRabin Vincent .fifosize = 30 * 4, 1248301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1254956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 12649ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 127e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 128e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 12908458ef6SRabin Vincent .datalength_bits = 24, 1305db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 131c7354133SSrinivas Kandagatla .st_sdio = true, 132b70a67f9SLinus Walleij .st_clkdiv = true, 1337d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 134dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1354d1a3a0dSUlf Hansson .signal_direction = true, 136f4670daeSUlf Hansson .pwrreg_clkgate = true, 13701259620SUlf Hansson .busy_detect = true, 13849adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 13949adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 14049adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 1411ff44433SUlf Hansson .pwrreg_nopower = true, 1426ea9cdf3SPatrice Chotard .mmcimask1 = true, 1437f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 14411dfb970SPatrice Chotard .opendrain = MCI_OD, 1454956e109SRabin Vincent }; 146b70a67f9SLinus Walleij 1471784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1481784b157SPhilippe Langlais .fifosize = 30 * 4, 1491784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1501784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1511784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 152e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 153e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 1545db3eee7SLinus Walleij .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 1551784b157SPhilippe Langlais .datalength_bits = 24, 1565db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 157c7354133SSrinivas Kandagatla .st_sdio = true, 1581784b157SPhilippe Langlais .st_clkdiv = true, 1591784b157SPhilippe Langlais .blksz_datactrl16 = true, 1607d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 161dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1624d1a3a0dSUlf Hansson .signal_direction = true, 163f4670daeSUlf Hansson .pwrreg_clkgate = true, 16401259620SUlf Hansson .busy_detect = true, 16549adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 16649adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 16749adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 1681ff44433SUlf Hansson .pwrreg_nopower = true, 1696ea9cdf3SPatrice Chotard .mmcimask1 = true, 1707f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 17111dfb970SPatrice Chotard .opendrain = MCI_OD, 1721784b157SPhilippe Langlais }; 1731784b157SPhilippe Langlais 1742a9d6c80SPatrice Chotard static struct variant_data variant_stm32 = { 1752a9d6c80SPatrice Chotard .fifosize = 32 * 4, 1762a9d6c80SPatrice Chotard .fifohalfsize = 8 * 4, 1772a9d6c80SPatrice Chotard .clkreg = MCI_CLK_ENABLE, 1782a9d6c80SPatrice Chotard .clkreg_enable = MCI_ST_UX500_HWFCEN, 1792a9d6c80SPatrice Chotard .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 1802a9d6c80SPatrice Chotard .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 1812a9d6c80SPatrice Chotard .datalength_bits = 24, 1822a9d6c80SPatrice Chotard .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 1832a9d6c80SPatrice Chotard .st_sdio = true, 1842a9d6c80SPatrice Chotard .st_clkdiv = true, 1852a9d6c80SPatrice Chotard .pwrreg_powerup = MCI_PWR_ON, 1862a9d6c80SPatrice Chotard .f_max = 48000000, 1872a9d6c80SPatrice Chotard .pwrreg_clkgate = true, 1882a9d6c80SPatrice Chotard .pwrreg_nopower = true, 1892a9d6c80SPatrice Chotard }; 1902a9d6c80SPatrice Chotard 19155b604aeSSrinivas Kandagatla static struct variant_data variant_qcom = { 19255b604aeSSrinivas Kandagatla .fifosize = 16 * 4, 19355b604aeSSrinivas Kandagatla .fifohalfsize = 8 * 4, 19455b604aeSSrinivas Kandagatla .clkreg = MCI_CLK_ENABLE, 19555b604aeSSrinivas Kandagatla .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 19655b604aeSSrinivas Kandagatla MCI_QCOM_CLK_SELECT_IN_FBCLK, 19755b604aeSSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 19855b604aeSSrinivas Kandagatla .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 1995db3eee7SLinus Walleij .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 20055b604aeSSrinivas Kandagatla .blksz_datactrl4 = true, 20155b604aeSSrinivas Kandagatla .datalength_bits = 24, 20255b604aeSSrinivas Kandagatla .pwrreg_powerup = MCI_PWR_UP, 20355b604aeSSrinivas Kandagatla .f_max = 208000000, 20455b604aeSSrinivas Kandagatla .explicit_mclk_control = true, 20555b604aeSSrinivas Kandagatla .qcom_fifo = true, 2069cb15142SSrinivas Kandagatla .qcom_dml = true, 2076ea9cdf3SPatrice Chotard .mmcimask1 = true, 2087f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 20911dfb970SPatrice Chotard .opendrain = MCI_ROD, 21029aba07aSUlf Hansson .init = qcom_variant_init, 21155b604aeSSrinivas Kandagatla }; 21255b604aeSSrinivas Kandagatla 21349adc0caSLinus Walleij /* Busy detection for the ST Micro variant */ 21401259620SUlf Hansson static int mmci_card_busy(struct mmc_host *mmc) 21501259620SUlf Hansson { 21601259620SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 21701259620SUlf Hansson unsigned long flags; 21801259620SUlf Hansson int busy = 0; 21901259620SUlf Hansson 22001259620SUlf Hansson spin_lock_irqsave(&host->lock, flags); 22149adc0caSLinus Walleij if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 22201259620SUlf Hansson busy = 1; 22301259620SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 22401259620SUlf Hansson 22501259620SUlf Hansson return busy; 22601259620SUlf Hansson } 22701259620SUlf Hansson 228a6a6464aSLinus Walleij /* 229653a761eSUlf Hansson * Validate mmc prerequisites 230653a761eSUlf Hansson */ 231653a761eSUlf Hansson static int mmci_validate_data(struct mmci_host *host, 232653a761eSUlf Hansson struct mmc_data *data) 233653a761eSUlf Hansson { 234653a761eSUlf Hansson if (!data) 235653a761eSUlf Hansson return 0; 236653a761eSUlf Hansson 237653a761eSUlf Hansson if (!is_power_of_2(data->blksz)) { 238653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), 239653a761eSUlf Hansson "unsupported block size (%d bytes)\n", data->blksz); 240653a761eSUlf Hansson return -EINVAL; 241653a761eSUlf Hansson } 242653a761eSUlf Hansson 243653a761eSUlf Hansson return 0; 244653a761eSUlf Hansson } 245653a761eSUlf Hansson 246f829c042SUlf Hansson static void mmci_reg_delay(struct mmci_host *host) 247f829c042SUlf Hansson { 248f829c042SUlf Hansson /* 249f829c042SUlf Hansson * According to the spec, at least three feedback clock cycles 250f829c042SUlf Hansson * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 251f829c042SUlf Hansson * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 252f829c042SUlf Hansson * Worst delay time during card init is at 100 kHz => 30 us. 253f829c042SUlf Hansson * Worst delay time when up and running is at 25 MHz => 120 ns. 254f829c042SUlf Hansson */ 255f829c042SUlf Hansson if (host->cclk < 25000000) 256f829c042SUlf Hansson udelay(30); 257f829c042SUlf Hansson else 258f829c042SUlf Hansson ndelay(120); 259f829c042SUlf Hansson } 260f829c042SUlf Hansson 261653a761eSUlf Hansson /* 262a6a6464aSLinus Walleij * This must be called with host->lock held 263a6a6464aSLinus Walleij */ 2647437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 2657437cfa5SUlf Hansson { 2667437cfa5SUlf Hansson if (host->clk_reg != clk) { 2677437cfa5SUlf Hansson host->clk_reg = clk; 2687437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 2697437cfa5SUlf Hansson } 2707437cfa5SUlf Hansson } 2717437cfa5SUlf Hansson 2727437cfa5SUlf Hansson /* 2737437cfa5SUlf Hansson * This must be called with host->lock held 2747437cfa5SUlf Hansson */ 2757437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 2767437cfa5SUlf Hansson { 2777437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 2787437cfa5SUlf Hansson host->pwr_reg = pwr; 2797437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 2807437cfa5SUlf Hansson } 2817437cfa5SUlf Hansson } 2827437cfa5SUlf Hansson 2837437cfa5SUlf Hansson /* 2847437cfa5SUlf Hansson * This must be called with host->lock held 2857437cfa5SUlf Hansson */ 2869cc639a2SUlf Hansson static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 2879cc639a2SUlf Hansson { 28849adc0caSLinus Walleij /* Keep busy mode in DPSM if enabled */ 28949adc0caSLinus Walleij datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 29001259620SUlf Hansson 2919cc639a2SUlf Hansson if (host->datactrl_reg != datactrl) { 2929cc639a2SUlf Hansson host->datactrl_reg = datactrl; 2939cc639a2SUlf Hansson writel(datactrl, host->base + MMCIDATACTRL); 2949cc639a2SUlf Hansson } 2959cc639a2SUlf Hansson } 2969cc639a2SUlf Hansson 2979cc639a2SUlf Hansson /* 2989cc639a2SUlf Hansson * This must be called with host->lock held 2999cc639a2SUlf Hansson */ 300a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 301a6a6464aSLinus Walleij { 3024956e109SRabin Vincent struct variant_data *variant = host->variant; 3034956e109SRabin Vincent u32 clk = variant->clkreg; 304a6a6464aSLinus Walleij 305c58a8509SUlf Hansson /* Make sure cclk reflects the current calculated clock */ 306c58a8509SUlf Hansson host->cclk = 0; 307c58a8509SUlf Hansson 308a6a6464aSLinus Walleij if (desired) { 3093f4e6f7bSSrinivas Kandagatla if (variant->explicit_mclk_control) { 3103f4e6f7bSSrinivas Kandagatla host->cclk = host->mclk; 3113f4e6f7bSSrinivas Kandagatla } else if (desired >= host->mclk) { 312a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 313399bc486SLinus Walleij if (variant->st_clkdiv) 314399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 315a6a6464aSLinus Walleij host->cclk = host->mclk; 316b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 317b70a67f9SLinus Walleij /* 318b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 319b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 320b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 321b70a67f9SLinus Walleij * frequency 322b70a67f9SLinus Walleij */ 323b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 324b70a67f9SLinus Walleij if (clk >= 256) 325b70a67f9SLinus Walleij clk = 255; 326b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 327a6a6464aSLinus Walleij } else { 328b70a67f9SLinus Walleij /* 329b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 330b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 331b70a67f9SLinus Walleij */ 332a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 333a6a6464aSLinus Walleij if (clk >= 256) 334a6a6464aSLinus Walleij clk = 255; 335a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 336a6a6464aSLinus Walleij } 3374380c14fSRabin Vincent 3384380c14fSRabin Vincent clk |= variant->clkreg_enable; 339a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 340a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 341a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 342a6a6464aSLinus Walleij } 343a6a6464aSLinus Walleij 344c58a8509SUlf Hansson /* Set actual clock for debug */ 345c58a8509SUlf Hansson host->mmc->actual_clock = host->cclk; 346c58a8509SUlf Hansson 3479e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 348771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 349771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 350e1412d85SSrinivas Kandagatla clk |= variant->clkreg_8bit_bus_enable; 3519e6c82cdSLinus Walleij 3526dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 3536dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 354e8740644SSrinivas Kandagatla clk |= variant->clkreg_neg_edge_enable; 3556dbb6ee0SUlf Hansson 3567437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 357a6a6464aSLinus Walleij } 358a6a6464aSLinus Walleij 3591c6a0718SPierre Ossman static void 3601c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 3611c6a0718SPierre Ossman { 3621c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 3631c6a0718SPierre Ossman 3641c6a0718SPierre Ossman BUG_ON(host->data); 3651c6a0718SPierre Ossman 3661c6a0718SPierre Ossman host->mrq = NULL; 3671c6a0718SPierre Ossman host->cmd = NULL; 3681c6a0718SPierre Ossman 3691c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 3701c6a0718SPierre Ossman } 3711c6a0718SPierre Ossman 3722686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 3732686b4b4SLinus Walleij { 3742686b4b4SLinus Walleij void __iomem *base = host->base; 3756ea9cdf3SPatrice Chotard struct variant_data *variant = host->variant; 3762686b4b4SLinus Walleij 3772686b4b4SLinus Walleij if (host->singleirq) { 3782686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 3792686b4b4SLinus Walleij 3802686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 3812686b4b4SLinus Walleij mask0 |= mask; 3822686b4b4SLinus Walleij 3832686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 3842686b4b4SLinus Walleij } 3852686b4b4SLinus Walleij 3866ea9cdf3SPatrice Chotard if (variant->mmcimask1) 3872686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 3886ea9cdf3SPatrice Chotard 3896ea9cdf3SPatrice Chotard host->mask1_reg = mask; 3902686b4b4SLinus Walleij } 3912686b4b4SLinus Walleij 3921c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 3931c6a0718SPierre Ossman { 3949cc639a2SUlf Hansson mmci_write_datactrlreg(host, 0); 3952686b4b4SLinus Walleij mmci_set_mask1(host, 0); 3961c6a0718SPierre Ossman host->data = NULL; 3971c6a0718SPierre Ossman } 3981c6a0718SPierre Ossman 3994ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 4004ce1d6cbSRabin Vincent { 4014ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 4024ce1d6cbSRabin Vincent 4034ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 4044ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 4054ce1d6cbSRabin Vincent else 4064ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 4074ce1d6cbSRabin Vincent 4084ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 4094ce1d6cbSRabin Vincent } 4104ce1d6cbSRabin Vincent 411c8ebae37SRussell King /* 412c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 413c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 414c8ebae37SRussell King * no custom DMA interfaces are supported. 415c8ebae37SRussell King */ 416c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 417c3be1efdSBill Pemberton static void mmci_dma_setup(struct mmci_host *host) 418c8ebae37SRussell King { 419c8ebae37SRussell King const char *rxname, *txname; 420c8ebae37SRussell King 4211fd83f0eSLee Jones host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 4221fd83f0eSLee Jones host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 423c8ebae37SRussell King 42458c7ccbfSPer Forlin /* initialize pre request cookie */ 42558c7ccbfSPer Forlin host->next_data.cookie = 1; 42658c7ccbfSPer Forlin 4271fd83f0eSLee Jones /* 4281fd83f0eSLee Jones * If only an RX channel is specified, the driver will 4291fd83f0eSLee Jones * attempt to use it bidirectionally, however if it is 4301fd83f0eSLee Jones * is specified but cannot be located, DMA will be disabled. 4311fd83f0eSLee Jones */ 4321fd83f0eSLee Jones if (host->dma_rx_channel && !host->dma_tx_channel) 4331fd83f0eSLee Jones host->dma_tx_channel = host->dma_rx_channel; 434c8ebae37SRussell King 435c8ebae37SRussell King if (host->dma_rx_channel) 436c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 437c8ebae37SRussell King else 438c8ebae37SRussell King rxname = "none"; 439c8ebae37SRussell King 440c8ebae37SRussell King if (host->dma_tx_channel) 441c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 442c8ebae37SRussell King else 443c8ebae37SRussell King txname = "none"; 444c8ebae37SRussell King 445c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 446c8ebae37SRussell King rxname, txname); 447c8ebae37SRussell King 448c8ebae37SRussell King /* 449c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 450c8ebae37SRussell King * the parameters of the DMA engine device. 451c8ebae37SRussell King */ 452c8ebae37SRussell King if (host->dma_tx_channel) { 453c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 454c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 455c8ebae37SRussell King 456c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 457c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 458c8ebae37SRussell King } 459c8ebae37SRussell King if (host->dma_rx_channel) { 460c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 461c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 462c8ebae37SRussell King 463c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 464c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 465c8ebae37SRussell King } 4669cb15142SSrinivas Kandagatla 46729aba07aSUlf Hansson if (host->ops && host->ops->dma_setup) 46829aba07aSUlf Hansson host->ops->dma_setup(host); 469c8ebae37SRussell King } 470c8ebae37SRussell King 471c8ebae37SRussell King /* 4726e0ee714SBill Pemberton * This is used in or so inline it 473c8ebae37SRussell King * so it can be discarded. 474c8ebae37SRussell King */ 475c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 476c8ebae37SRussell King { 477c8ebae37SRussell King if (host->dma_rx_channel) 478c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 4798c3a05b4SUlf Hansson if (host->dma_tx_channel) 480c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 481c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 482c8ebae37SRussell King } 483c8ebae37SRussell King 484c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 485c8ebae37SRussell King { 486653a761eSUlf Hansson struct dma_chan *chan; 487653a761eSUlf Hansson 488feeef096SHeiner Kallweit if (data->flags & MMC_DATA_READ) 489653a761eSUlf Hansson chan = host->dma_rx_channel; 490feeef096SHeiner Kallweit else 491653a761eSUlf Hansson chan = host->dma_tx_channel; 492653a761eSUlf Hansson 493feeef096SHeiner Kallweit dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 494feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 495653a761eSUlf Hansson } 496653a761eSUlf Hansson 4977b2a6d51SLudovic Barre static void mmci_dma_data_error(struct mmci_host *host) 4987b2a6d51SLudovic Barre { 4997b2a6d51SLudovic Barre dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 5007b2a6d51SLudovic Barre dmaengine_terminate_all(host->dma_current); 5017b2a6d51SLudovic Barre host->dma_in_progress = false; 5027b2a6d51SLudovic Barre host->dma_current = NULL; 5037b2a6d51SLudovic Barre host->dma_desc_current = NULL; 5047b2a6d51SLudovic Barre host->data->host_cookie = 0; 5057b2a6d51SLudovic Barre 5067b2a6d51SLudovic Barre mmci_dma_unmap(host, host->data); 5077b2a6d51SLudovic Barre } 5087b2a6d51SLudovic Barre 509653a761eSUlf Hansson static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 510653a761eSUlf Hansson { 511c8ebae37SRussell King u32 status; 512c8ebae37SRussell King int i; 513c8ebae37SRussell King 514c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 515c8ebae37SRussell King for (i = 0; ; i++) { 516c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 517c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 518c8ebae37SRussell King break; 519c8ebae37SRussell King udelay(10); 520c8ebae37SRussell King } 521c8ebae37SRussell King 522c8ebae37SRussell King /* 523c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 524c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 525c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 526c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 527c8ebae37SRussell King */ 528c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 529653a761eSUlf Hansson mmci_dma_data_error(host); 530c8ebae37SRussell King if (!data->error) 531c8ebae37SRussell King data->error = -EIO; 5327b2a6d51SLudovic Barre } else if (!data->host_cookie) { 533653a761eSUlf Hansson mmci_dma_unmap(host, data); 5347b2a6d51SLudovic Barre } 535c8ebae37SRussell King 536c8ebae37SRussell King /* 537c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 538c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 539c8ebae37SRussell King */ 540c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 541c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 542c8ebae37SRussell King mmci_dma_release(host); 543c8ebae37SRussell King } 544653a761eSUlf Hansson 545e13934bdSLinus Walleij host->dma_in_progress = false; 546653a761eSUlf Hansson host->dma_current = NULL; 547653a761eSUlf Hansson host->dma_desc_current = NULL; 548c8ebae37SRussell King } 549c8ebae37SRussell King 550653a761eSUlf Hansson /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 551653a761eSUlf Hansson static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 552653a761eSUlf Hansson struct dma_chan **dma_chan, 553653a761eSUlf Hansson struct dma_async_tx_descriptor **dma_desc) 554c8ebae37SRussell King { 555c8ebae37SRussell King struct variant_data *variant = host->variant; 556c8ebae37SRussell King struct dma_slave_config conf = { 557c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 558c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 559c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 560c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 561c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 562c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 563258aea76SViresh Kumar .device_fc = false, 564c8ebae37SRussell King }; 565c8ebae37SRussell King struct dma_chan *chan; 566c8ebae37SRussell King struct dma_device *device; 567c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 568c8ebae37SRussell King int nr_sg; 5699cb15142SSrinivas Kandagatla unsigned long flags = DMA_CTRL_ACK; 570c8ebae37SRussell King 571c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 57205f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 573c8ebae37SRussell King chan = host->dma_rx_channel; 574c8ebae37SRussell King } else { 57505f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 576c8ebae37SRussell King chan = host->dma_tx_channel; 577c8ebae37SRussell King } 578c8ebae37SRussell King 579c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 580c8ebae37SRussell King if (!chan) 581c8ebae37SRussell King return -EINVAL; 582c8ebae37SRussell King 583c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 58458c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 585c8ebae37SRussell King return -EINVAL; 586c8ebae37SRussell King 587c8ebae37SRussell King device = chan->device; 588feeef096SHeiner Kallweit nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 589feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 590c8ebae37SRussell King if (nr_sg == 0) 591c8ebae37SRussell King return -EINVAL; 592c8ebae37SRussell King 5939cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 5949cb15142SSrinivas Kandagatla flags |= DMA_PREP_INTERRUPT; 5959cb15142SSrinivas Kandagatla 596c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 59716052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 5989cb15142SSrinivas Kandagatla conf.direction, flags); 599c8ebae37SRussell King if (!desc) 600c8ebae37SRussell King goto unmap_exit; 601c8ebae37SRussell King 602653a761eSUlf Hansson *dma_chan = chan; 603653a761eSUlf Hansson *dma_desc = desc; 604c8ebae37SRussell King 60558c7ccbfSPer Forlin return 0; 60658c7ccbfSPer Forlin 60758c7ccbfSPer Forlin unmap_exit: 608feeef096SHeiner Kallweit dma_unmap_sg(device->dev, data->sg, data->sg_len, 609feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 61058c7ccbfSPer Forlin return -ENOMEM; 61158c7ccbfSPer Forlin } 61258c7ccbfSPer Forlin 613653a761eSUlf Hansson static inline int mmci_dma_prep_data(struct mmci_host *host, 614653a761eSUlf Hansson struct mmc_data *data) 615653a761eSUlf Hansson { 616653a761eSUlf Hansson /* Check if next job is already prepared. */ 617653a761eSUlf Hansson if (host->dma_current && host->dma_desc_current) 618653a761eSUlf Hansson return 0; 619653a761eSUlf Hansson 620653a761eSUlf Hansson /* No job were prepared thus do it now. */ 621653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &host->dma_current, 622653a761eSUlf Hansson &host->dma_desc_current); 623653a761eSUlf Hansson } 624653a761eSUlf Hansson 625653a761eSUlf Hansson static inline int mmci_dma_prep_next(struct mmci_host *host, 626653a761eSUlf Hansson struct mmc_data *data) 627653a761eSUlf Hansson { 628653a761eSUlf Hansson struct mmci_host_next *nd = &host->next_data; 629653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 630653a761eSUlf Hansson } 631653a761eSUlf Hansson 63258c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 63358c7ccbfSPer Forlin { 63458c7ccbfSPer Forlin int ret; 63558c7ccbfSPer Forlin struct mmc_data *data = host->data; 63658c7ccbfSPer Forlin 637653a761eSUlf Hansson ret = mmci_dma_prep_data(host, host->data); 63858c7ccbfSPer Forlin if (ret) 63958c7ccbfSPer Forlin return ret; 64058c7ccbfSPer Forlin 64158c7ccbfSPer Forlin /* Okay, go for it. */ 642c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 643c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 644c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 645e13934bdSLinus Walleij host->dma_in_progress = true; 64658c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 64758c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 648c8ebae37SRussell King 6499cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 6509cb15142SSrinivas Kandagatla dml_start_xfer(host, data); 6519cb15142SSrinivas Kandagatla 652c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 653c8ebae37SRussell King 654c8ebae37SRussell King /* Trigger the DMA transfer */ 6559cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 656c8ebae37SRussell King 657c8ebae37SRussell King /* 658c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 659c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 660c8ebae37SRussell King * call mmci_data_end() 661c8ebae37SRussell King */ 662c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 663c8ebae37SRussell King host->base + MMCIMASK0); 664c8ebae37SRussell King return 0; 665c8ebae37SRussell King } 66658c7ccbfSPer Forlin 66758c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 66858c7ccbfSPer Forlin { 66958c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 67058c7ccbfSPer Forlin 671653a761eSUlf Hansson WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 672653a761eSUlf Hansson WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 67358c7ccbfSPer Forlin 67458c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 67558c7ccbfSPer Forlin host->dma_current = next->dma_chan; 67658c7ccbfSPer Forlin next->dma_desc = NULL; 67758c7ccbfSPer Forlin next->dma_chan = NULL; 67858c7ccbfSPer Forlin } 67958c7ccbfSPer Forlin 680d3c6aac3SLinus Walleij static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 68158c7ccbfSPer Forlin { 68258c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 68358c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 68458c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 68558c7ccbfSPer Forlin 68658c7ccbfSPer Forlin if (!data) 68758c7ccbfSPer Forlin return; 68858c7ccbfSPer Forlin 689653a761eSUlf Hansson BUG_ON(data->host_cookie); 69058c7ccbfSPer Forlin 691653a761eSUlf Hansson if (mmci_validate_data(host, data)) 692653a761eSUlf Hansson return; 693653a761eSUlf Hansson 694653a761eSUlf Hansson if (!mmci_dma_prep_next(host, data)) 69558c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 69658c7ccbfSPer Forlin } 69758c7ccbfSPer Forlin 69858c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 69958c7ccbfSPer Forlin int err) 70058c7ccbfSPer Forlin { 70158c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 70258c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 70358c7ccbfSPer Forlin 704653a761eSUlf Hansson if (!data || !data->host_cookie) 70558c7ccbfSPer Forlin return; 70658c7ccbfSPer Forlin 707653a761eSUlf Hansson mmci_dma_unmap(host, data); 708653a761eSUlf Hansson 709653a761eSUlf Hansson if (err) { 710653a761eSUlf Hansson struct mmci_host_next *next = &host->next_data; 711653a761eSUlf Hansson struct dma_chan *chan; 712653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) 71358c7ccbfSPer Forlin chan = host->dma_rx_channel; 714653a761eSUlf Hansson else 71558c7ccbfSPer Forlin chan = host->dma_tx_channel; 71658c7ccbfSPer Forlin dmaengine_terminate_all(chan); 717653a761eSUlf Hansson 718b5c16a60SSrinivas Kandagatla if (host->dma_desc_current == next->dma_desc) 719b5c16a60SSrinivas Kandagatla host->dma_desc_current = NULL; 720b5c16a60SSrinivas Kandagatla 721e13934bdSLinus Walleij if (host->dma_current == next->dma_chan) { 722e13934bdSLinus Walleij host->dma_in_progress = false; 723b5c16a60SSrinivas Kandagatla host->dma_current = NULL; 724e13934bdSLinus Walleij } 725b5c16a60SSrinivas Kandagatla 726653a761eSUlf Hansson next->dma_desc = NULL; 727653a761eSUlf Hansson next->dma_chan = NULL; 728b5c16a60SSrinivas Kandagatla data->host_cookie = 0; 72958c7ccbfSPer Forlin } 73058c7ccbfSPer Forlin } 73158c7ccbfSPer Forlin 732c8ebae37SRussell King #else 733c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 73458c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 73558c7ccbfSPer Forlin { 73658c7ccbfSPer Forlin } 737c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 738c8ebae37SRussell King { 739c8ebae37SRussell King } 740c8ebae37SRussell King 741c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 742c8ebae37SRussell King { 743c8ebae37SRussell King } 744c8ebae37SRussell King 745653a761eSUlf Hansson static inline void mmci_dma_finalize(struct mmci_host *host, 746653a761eSUlf Hansson struct mmc_data *data) 747653a761eSUlf Hansson { 748653a761eSUlf Hansson } 749653a761eSUlf Hansson 750c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 751c8ebae37SRussell King { 752c8ebae37SRussell King } 753c8ebae37SRussell King 754c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 755c8ebae37SRussell King { 756c8ebae37SRussell King return -ENOSYS; 757c8ebae37SRussell King } 75858c7ccbfSPer Forlin 75958c7ccbfSPer Forlin #define mmci_pre_request NULL 76058c7ccbfSPer Forlin #define mmci_post_request NULL 76158c7ccbfSPer Forlin 762c8ebae37SRussell King #endif 763c8ebae37SRussell King 7641c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 7651c6a0718SPierre Ossman { 7668301bb68SRabin Vincent struct variant_data *variant = host->variant; 7671c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 7681c6a0718SPierre Ossman unsigned long long clks; 7691c6a0718SPierre Ossman void __iomem *base; 7701c6a0718SPierre Ossman int blksz_bits; 7711c6a0718SPierre Ossman 77264de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 7731c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 7741c6a0718SPierre Ossman 7751c6a0718SPierre Ossman host->data = data; 776528320dbSRabin Vincent host->size = data->blksz * data->blocks; 77751d4375dSRussell King data->bytes_xfered = 0; 7781c6a0718SPierre Ossman 7791c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 780c4a35769SSrinivas Kandagatla do_div(clks, NSEC_PER_SEC); 7811c6a0718SPierre Ossman 7821c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 7831c6a0718SPierre Ossman 7841c6a0718SPierre Ossman base = host->base; 7851c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 7861c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 7871c6a0718SPierre Ossman 7881c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 7891c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 7901c6a0718SPierre Ossman 7911784b157SPhilippe Langlais if (variant->blksz_datactrl16) 7921784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 793ff783233SSrinivas Kandagatla else if (variant->blksz_datactrl4) 794ff783233SSrinivas Kandagatla datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 7951784b157SPhilippe Langlais else 7961c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 797c8ebae37SRussell King 798c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 7991c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 800c8ebae37SRussell King 801c7354133SSrinivas Kandagatla if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 80206c1a121SUlf Hansson u32 clk; 803c7354133SSrinivas Kandagatla 8045df014dfSSrinivas Kandagatla datactrl |= variant->datactrl_mask_sdio; 8057258db7eSUlf Hansson 806c8ebae37SRussell King /* 80770ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 80870ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 80970ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 81070ac0935SUlf Hansson * depends on the rate of MCLK. 81106c1a121SUlf Hansson */ 812c7354133SSrinivas Kandagatla if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 81370ac0935SUlf Hansson (host->size < 8 || 81470ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 81506c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 81606c1a121SUlf Hansson else 81706c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 81806c1a121SUlf Hansson 81906c1a121SUlf Hansson mmci_write_clkreg(host, clk); 82006c1a121SUlf Hansson } 82106c1a121SUlf Hansson 8226dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 8236dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 824e17dca2bSSrinivas Kandagatla datactrl |= variant->datactrl_mask_ddrmode; 8256dbb6ee0SUlf Hansson 82606c1a121SUlf Hansson /* 827c8ebae37SRussell King * Attempt to use DMA operation mode, if this 828c8ebae37SRussell King * should fail, fall back to PIO mode 829c8ebae37SRussell King */ 830c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 831c8ebae37SRussell King return; 832c8ebae37SRussell King 833c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 834c8ebae37SRussell King mmci_init_sg(host, data); 835c8ebae37SRussell King 836c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 8371c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 8381c6a0718SPierre Ossman 8391c6a0718SPierre Ossman /* 840c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 841c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 842c4d877c1SRussell King * is available. 8431c6a0718SPierre Ossman */ 844c4d877c1SRussell King if (host->size < variant->fifohalfsize) 8451c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 8461c6a0718SPierre Ossman } else { 8471c6a0718SPierre Ossman /* 8481c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 8491c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 8501c6a0718SPierre Ossman */ 8511c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 8521c6a0718SPierre Ossman } 8531c6a0718SPierre Ossman 8549cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 8551c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 8562686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 8571c6a0718SPierre Ossman } 8581c6a0718SPierre Ossman 8591c6a0718SPierre Ossman static void 8601c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 8611c6a0718SPierre Ossman { 8621c6a0718SPierre Ossman void __iomem *base = host->base; 8631c6a0718SPierre Ossman 86464de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 8651c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 8661c6a0718SPierre Ossman 8671c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 8681c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 8696adb2a80SSrinivas Kandagatla mmci_reg_delay(host); 8701c6a0718SPierre Ossman } 8711c6a0718SPierre Ossman 8721c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 8731c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 8741c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 8751c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 8761c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 8771c6a0718SPierre Ossman } 8781c6a0718SPierre Ossman if (/*interrupt*/0) 8791c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 8801c6a0718SPierre Ossman 881ae7b0061SSrinivas Kandagatla if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 882ae7b0061SSrinivas Kandagatla c |= host->variant->data_cmd_enable; 883ae7b0061SSrinivas Kandagatla 8841c6a0718SPierre Ossman host->cmd = cmd; 8851c6a0718SPierre Ossman 8861c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 8871c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 8881c6a0718SPierre Ossman } 8891c6a0718SPierre Ossman 8901c6a0718SPierre Ossman static void 8911c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 8921c6a0718SPierre Ossman unsigned int status) 8931c6a0718SPierre Ossman { 8941cb9da50SUlf Hansson /* Make sure we have data to handle */ 8951cb9da50SUlf Hansson if (!data) 8961cb9da50SUlf Hansson return; 8971cb9da50SUlf Hansson 898f20f8f21SLinus Walleij /* First check for errors */ 8997f7b5503SPatrice Chotard if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT | 9007f7b5503SPatrice Chotard host->variant->start_err | 901b63038d6SUlf Hansson MCI_TXUNDERRUN | MCI_RXOVERRUN)) { 9028cb28155SLinus Walleij u32 remain, success; 903f20f8f21SLinus Walleij 904c8ebae37SRussell King /* Terminate the DMA transfer */ 9057b2a6d51SLudovic Barre if (dma_inprogress(host)) 906c8ebae37SRussell King mmci_dma_data_error(host); 907c8ebae37SRussell King 908c8afc9d5SRussell King /* 909c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 910c8afc9d5SRussell King * the data counter gives the number of bytes transferred 911c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 912c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 913c8afc9d5SRussell King * matters for FIFO overruns only. 914c8afc9d5SRussell King */ 915f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 9168cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 9178cb28155SLinus Walleij 918c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 919c8afc9d5SRussell King status, success); 9208cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 9218cb28155SLinus Walleij /* Last block was not successful */ 922c8afc9d5SRussell King success -= 1; 92317b0429dSPierre Ossman data->error = -EILSEQ; 9248cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 92517b0429dSPierre Ossman data->error = -ETIMEDOUT; 926757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 927757df746SLinus Walleij data->error = -ECOMM; 928c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 92917b0429dSPierre Ossman data->error = -EIO; 930c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 931c8afc9d5SRussell King if (success > host->variant->fifosize) 932c8afc9d5SRussell King success -= host->variant->fifosize; 933c8afc9d5SRussell King else 934c8afc9d5SRussell King success = 0; 9358cb28155SLinus Walleij data->error = -EIO; 9364ce1d6cbSRabin Vincent } 93751d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 9381c6a0718SPierre Ossman } 939f20f8f21SLinus Walleij 9408cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 9418cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 942f20f8f21SLinus Walleij 943ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 944c8ebae37SRussell King if (dma_inprogress(host)) 945653a761eSUlf Hansson mmci_dma_finalize(host, data); 9461c6a0718SPierre Ossman mmci_stop_data(host); 9471c6a0718SPierre Ossman 9488cb28155SLinus Walleij if (!data->error) 9498cb28155SLinus Walleij /* The error clause is handled above, success! */ 95051d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 951f20f8f21SLinus Walleij 952024629c6SUlf Hansson if (!data->stop || host->mrq->sbc) { 9531c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 9541c6a0718SPierre Ossman } else { 9551c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 9561c6a0718SPierre Ossman } 9571c6a0718SPierre Ossman } 9581c6a0718SPierre Ossman } 9591c6a0718SPierre Ossman 9601c6a0718SPierre Ossman static void 9611c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 9621c6a0718SPierre Ossman unsigned int status) 9631c6a0718SPierre Ossman { 9641c6a0718SPierre Ossman void __iomem *base = host->base; 96549adc0caSLinus Walleij bool sbc; 966ad82bfeaSUlf Hansson 967ad82bfeaSUlf Hansson if (!cmd) 968ad82bfeaSUlf Hansson return; 969ad82bfeaSUlf Hansson 970ad82bfeaSUlf Hansson sbc = (cmd == host->mrq->sbc); 971ad82bfeaSUlf Hansson 97249adc0caSLinus Walleij /* 97349adc0caSLinus Walleij * We need to be one of these interrupts to be considered worth 97449adc0caSLinus Walleij * handling. Note that we tag on any latent IRQs postponed 97549adc0caSLinus Walleij * due to waiting for busy status. 97649adc0caSLinus Walleij */ 97749adc0caSLinus Walleij if (!((status|host->busy_status) & 97849adc0caSLinus Walleij (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 979ad82bfeaSUlf Hansson return; 9808d94b54dSUlf Hansson 98149adc0caSLinus Walleij /* 98249adc0caSLinus Walleij * ST Micro variant: handle busy detection. 98349adc0caSLinus Walleij */ 98449adc0caSLinus Walleij if (host->variant->busy_detect) { 98549adc0caSLinus Walleij bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 98649adc0caSLinus Walleij 98749adc0caSLinus Walleij /* We are busy with a command, return */ 98849adc0caSLinus Walleij if (host->busy_status && 98949adc0caSLinus Walleij (status & host->variant->busy_detect_flag)) 9908d94b54dSUlf Hansson return; 9918d94b54dSUlf Hansson 99249adc0caSLinus Walleij /* 99349adc0caSLinus Walleij * We were not busy, but we now got a busy response on 99449adc0caSLinus Walleij * something that was not an error, and we double-check 99549adc0caSLinus Walleij * that the special busy status bit is still set before 99649adc0caSLinus Walleij * proceeding. 99749adc0caSLinus Walleij */ 9988d94b54dSUlf Hansson if (!host->busy_status && busy_resp && 9998d94b54dSUlf Hansson !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 100049adc0caSLinus Walleij (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 10015cad24d8SJean-Nicolas Graux 10025cad24d8SJean-Nicolas Graux /* Clear the busy start IRQ */ 10035cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 10045cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 10055cad24d8SJean-Nicolas Graux 10065cad24d8SJean-Nicolas Graux /* Unmask the busy end IRQ */ 100749adc0caSLinus Walleij writel(readl(base + MMCIMASK0) | 100849adc0caSLinus Walleij host->variant->busy_detect_mask, 10098d94b54dSUlf Hansson base + MMCIMASK0); 101049adc0caSLinus Walleij /* 101149adc0caSLinus Walleij * Now cache the last response status code (until 101249adc0caSLinus Walleij * the busy bit goes low), and return. 101349adc0caSLinus Walleij */ 101449adc0caSLinus Walleij host->busy_status = 101549adc0caSLinus Walleij status & (MCI_CMDSENT|MCI_CMDRESPEND); 10168d94b54dSUlf Hansson return; 10178d94b54dSUlf Hansson } 10188d94b54dSUlf Hansson 101949adc0caSLinus Walleij /* 102049adc0caSLinus Walleij * At this point we are not busy with a command, we have 10215cad24d8SJean-Nicolas Graux * not received a new busy request, clear and mask the busy 10225cad24d8SJean-Nicolas Graux * end IRQ and fall through to process the IRQ. 102349adc0caSLinus Walleij */ 10248d94b54dSUlf Hansson if (host->busy_status) { 10255cad24d8SJean-Nicolas Graux 10265cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 10275cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 10285cad24d8SJean-Nicolas Graux 102949adc0caSLinus Walleij writel(readl(base + MMCIMASK0) & 103049adc0caSLinus Walleij ~host->variant->busy_detect_mask, 10318d94b54dSUlf Hansson base + MMCIMASK0); 10328d94b54dSUlf Hansson host->busy_status = 0; 10338d94b54dSUlf Hansson } 103449adc0caSLinus Walleij } 10351c6a0718SPierre Ossman 10361c6a0718SPierre Ossman host->cmd = NULL; 10371c6a0718SPierre Ossman 10381c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 103917b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 10401c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 104117b0429dSPierre Ossman cmd->error = -EILSEQ; 10429047b435SRussell King - ARM Linux } else { 10439047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 10449047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 10459047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 10469047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 10471c6a0718SPierre Ossman } 10481c6a0718SPierre Ossman 1049024629c6SUlf Hansson if ((!sbc && !cmd->data) || cmd->error) { 10503b6e3c73SUlf Hansson if (host->data) { 10513b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 10527b2a6d51SLudovic Barre if (dma_inprogress(host)) 10533b6e3c73SUlf Hansson mmci_dma_data_error(host); 10547b2a6d51SLudovic Barre 10551c6a0718SPierre Ossman mmci_stop_data(host); 10563b6e3c73SUlf Hansson } 1057024629c6SUlf Hansson mmci_request_end(host, host->mrq); 1058024629c6SUlf Hansson } else if (sbc) { 1059024629c6SUlf Hansson mmci_start_command(host, host->mrq->cmd, 0); 10601c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 10611c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 10621c6a0718SPierre Ossman } 10631c6a0718SPierre Ossman } 10641c6a0718SPierre Ossman 10659c34b73dSSrinivas Kandagatla static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 10669c34b73dSSrinivas Kandagatla { 10679c34b73dSSrinivas Kandagatla return remain - (readl(host->base + MMCIFIFOCNT) << 2); 10689c34b73dSSrinivas Kandagatla } 10699c34b73dSSrinivas Kandagatla 10709c34b73dSSrinivas Kandagatla static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 10719c34b73dSSrinivas Kandagatla { 10729c34b73dSSrinivas Kandagatla /* 10739c34b73dSSrinivas Kandagatla * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 10749c34b73dSSrinivas Kandagatla * from the fifo range should be used 10759c34b73dSSrinivas Kandagatla */ 10769c34b73dSSrinivas Kandagatla if (status & MCI_RXFIFOHALFFULL) 10779c34b73dSSrinivas Kandagatla return host->variant->fifohalfsize; 10789c34b73dSSrinivas Kandagatla else if (status & MCI_RXDATAAVLBL) 10799c34b73dSSrinivas Kandagatla return 4; 10809c34b73dSSrinivas Kandagatla 10819c34b73dSSrinivas Kandagatla return 0; 10829c34b73dSSrinivas Kandagatla } 10839c34b73dSSrinivas Kandagatla 10841c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 10851c6a0718SPierre Ossman { 10861c6a0718SPierre Ossman void __iomem *base = host->base; 10871c6a0718SPierre Ossman char *ptr = buffer; 10889c34b73dSSrinivas Kandagatla u32 status = readl(host->base + MMCISTATUS); 108926eed9a5SLinus Walleij int host_remain = host->size; 10901c6a0718SPierre Ossman 10911c6a0718SPierre Ossman do { 10929c34b73dSSrinivas Kandagatla int count = host->get_rx_fifocnt(host, status, host_remain); 10931c6a0718SPierre Ossman 10941c6a0718SPierre Ossman if (count > remain) 10951c6a0718SPierre Ossman count = remain; 10961c6a0718SPierre Ossman 10971c6a0718SPierre Ossman if (count <= 0) 10981c6a0718SPierre Ossman break; 10991c6a0718SPierre Ossman 1100393e5e24SUlf Hansson /* 1101393e5e24SUlf Hansson * SDIO especially may want to send something that is 1102393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 1103393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 1104393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 1105393e5e24SUlf Hansson */ 1106393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 1107393e5e24SUlf Hansson if (count < 4) { 1108393e5e24SUlf Hansson unsigned char buf[4]; 11094b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 1110393e5e24SUlf Hansson memcpy(ptr, buf, count); 1111393e5e24SUlf Hansson } else { 11124b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1113393e5e24SUlf Hansson count &= ~0x3; 1114393e5e24SUlf Hansson } 1115393e5e24SUlf Hansson } else { 11164b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1117393e5e24SUlf Hansson } 11181c6a0718SPierre Ossman 11191c6a0718SPierre Ossman ptr += count; 11201c6a0718SPierre Ossman remain -= count; 112126eed9a5SLinus Walleij host_remain -= count; 11221c6a0718SPierre Ossman 11231c6a0718SPierre Ossman if (remain == 0) 11241c6a0718SPierre Ossman break; 11251c6a0718SPierre Ossman 11261c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11271c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 11281c6a0718SPierre Ossman 11291c6a0718SPierre Ossman return ptr - buffer; 11301c6a0718SPierre Ossman } 11311c6a0718SPierre Ossman 11321c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 11331c6a0718SPierre Ossman { 11348301bb68SRabin Vincent struct variant_data *variant = host->variant; 11351c6a0718SPierre Ossman void __iomem *base = host->base; 11361c6a0718SPierre Ossman char *ptr = buffer; 11371c6a0718SPierre Ossman 11381c6a0718SPierre Ossman do { 11391c6a0718SPierre Ossman unsigned int count, maxcnt; 11401c6a0718SPierre Ossman 11418301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 11428301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 11431c6a0718SPierre Ossman count = min(remain, maxcnt); 11441c6a0718SPierre Ossman 114534177802SLinus Walleij /* 114634177802SLinus Walleij * SDIO especially may want to send something that is 114734177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 114834177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 114934177802SLinus Walleij * So compensate by adding +3 on the count, a single 115034177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 115134177802SLinus Walleij * 32bit writes etc. 115234177802SLinus Walleij */ 11534b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 11541c6a0718SPierre Ossman 11551c6a0718SPierre Ossman ptr += count; 11561c6a0718SPierre Ossman remain -= count; 11571c6a0718SPierre Ossman 11581c6a0718SPierre Ossman if (remain == 0) 11591c6a0718SPierre Ossman break; 11601c6a0718SPierre Ossman 11611c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11621c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 11631c6a0718SPierre Ossman 11641c6a0718SPierre Ossman return ptr - buffer; 11651c6a0718SPierre Ossman } 11661c6a0718SPierre Ossman 11671c6a0718SPierre Ossman /* 11681c6a0718SPierre Ossman * PIO data transfer IRQ handler. 11691c6a0718SPierre Ossman */ 11701c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 11711c6a0718SPierre Ossman { 11721c6a0718SPierre Ossman struct mmci_host *host = dev_id; 11734ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 11748301bb68SRabin Vincent struct variant_data *variant = host->variant; 11751c6a0718SPierre Ossman void __iomem *base = host->base; 11761c6a0718SPierre Ossman u32 status; 11771c6a0718SPierre Ossman 11781c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11791c6a0718SPierre Ossman 118064de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 11811c6a0718SPierre Ossman 11821c6a0718SPierre Ossman do { 11831c6a0718SPierre Ossman unsigned int remain, len; 11841c6a0718SPierre Ossman char *buffer; 11851c6a0718SPierre Ossman 11861c6a0718SPierre Ossman /* 11871c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 11881c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 11891c6a0718SPierre Ossman * definition it is more than half empty. 11901c6a0718SPierre Ossman * 11911c6a0718SPierre Ossman * For read, check for data available. 11921c6a0718SPierre Ossman */ 11931c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 11941c6a0718SPierre Ossman break; 11951c6a0718SPierre Ossman 11964ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 11974ce1d6cbSRabin Vincent break; 11984ce1d6cbSRabin Vincent 11994ce1d6cbSRabin Vincent buffer = sg_miter->addr; 12004ce1d6cbSRabin Vincent remain = sg_miter->length; 12011c6a0718SPierre Ossman 12021c6a0718SPierre Ossman len = 0; 12031c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 12041c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 12051c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 12061c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 12071c6a0718SPierre Ossman 12084ce1d6cbSRabin Vincent sg_miter->consumed = len; 12091c6a0718SPierre Ossman 12101c6a0718SPierre Ossman host->size -= len; 12111c6a0718SPierre Ossman remain -= len; 12121c6a0718SPierre Ossman 12131c6a0718SPierre Ossman if (remain) 12141c6a0718SPierre Ossman break; 12151c6a0718SPierre Ossman 12161c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 12171c6a0718SPierre Ossman } while (1); 12181c6a0718SPierre Ossman 12194ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 12204ce1d6cbSRabin Vincent 12211c6a0718SPierre Ossman /* 1222c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 1223c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 12241c6a0718SPierre Ossman */ 1225c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 12262686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 12271c6a0718SPierre Ossman 12281c6a0718SPierre Ossman /* 12291c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 12301c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 12311c6a0718SPierre Ossman * the chip itself has disabled the data path, and 12321c6a0718SPierre Ossman * stops us racing with our data end IRQ. 12331c6a0718SPierre Ossman */ 12341c6a0718SPierre Ossman if (host->size == 0) { 12352686b4b4SLinus Walleij mmci_set_mask1(host, 0); 12361c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 12371c6a0718SPierre Ossman } 12381c6a0718SPierre Ossman 12391c6a0718SPierre Ossman return IRQ_HANDLED; 12401c6a0718SPierre Ossman } 12411c6a0718SPierre Ossman 12421c6a0718SPierre Ossman /* 12431c6a0718SPierre Ossman * Handle completion of command and data transfers. 12441c6a0718SPierre Ossman */ 12451c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 12461c6a0718SPierre Ossman { 12471c6a0718SPierre Ossman struct mmci_host *host = dev_id; 12481c6a0718SPierre Ossman u32 status; 12491c6a0718SPierre Ossman int ret = 0; 12501c6a0718SPierre Ossman 12511c6a0718SPierre Ossman spin_lock(&host->lock); 12521c6a0718SPierre Ossman 12531c6a0718SPierre Ossman do { 12541c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 12552686b4b4SLinus Walleij 12562686b4b4SLinus Walleij if (host->singleirq) { 12576ea9cdf3SPatrice Chotard if (status & host->mask1_reg) 12582686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 12592686b4b4SLinus Walleij 12602686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 12612686b4b4SLinus Walleij } 12622686b4b4SLinus Walleij 12638d94b54dSUlf Hansson /* 12645cad24d8SJean-Nicolas Graux * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 12655cad24d8SJean-Nicolas Graux * enabled) in mmci_cmd_irq() function where ST Micro busy 12665cad24d8SJean-Nicolas Graux * detection variant is handled. Considering the HW seems to be 12675cad24d8SJean-Nicolas Graux * triggering the IRQ on both edges while monitoring DAT0 for 12685cad24d8SJean-Nicolas Graux * busy completion and that same status bit is used to monitor 12695cad24d8SJean-Nicolas Graux * start and end of busy detection, special care must be taken 12705cad24d8SJean-Nicolas Graux * to make sure that both start and end interrupts are always 12715cad24d8SJean-Nicolas Graux * cleared one after the other. 12728d94b54dSUlf Hansson */ 12731c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 12745cad24d8SJean-Nicolas Graux if (host->variant->busy_detect) 12755cad24d8SJean-Nicolas Graux writel(status & ~host->variant->busy_detect_mask, 12765cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 12775cad24d8SJean-Nicolas Graux else 12781c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 12791c6a0718SPierre Ossman 128064de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 12811c6a0718SPierre Ossman 12827878289bSUlf Hansson if (host->variant->reversed_irq_handling) { 12837878289bSUlf Hansson mmci_data_irq(host, host->data, status); 12847878289bSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 12857878289bSUlf Hansson } else { 1286ad82bfeaSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 12871cb9da50SUlf Hansson mmci_data_irq(host, host->data, status); 12887878289bSUlf Hansson } 12891c6a0718SPierre Ossman 129049adc0caSLinus Walleij /* 129149adc0caSLinus Walleij * Don't poll for busy completion in irq context. 129249adc0caSLinus Walleij */ 129349adc0caSLinus Walleij if (host->variant->busy_detect && host->busy_status) 129449adc0caSLinus Walleij status &= ~host->variant->busy_detect_flag; 12958d94b54dSUlf Hansson 12961c6a0718SPierre Ossman ret = 1; 12971c6a0718SPierre Ossman } while (status); 12981c6a0718SPierre Ossman 12991c6a0718SPierre Ossman spin_unlock(&host->lock); 13001c6a0718SPierre Ossman 13011c6a0718SPierre Ossman return IRQ_RETVAL(ret); 13021c6a0718SPierre Ossman } 13031c6a0718SPierre Ossman 13041c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 13051c6a0718SPierre Ossman { 13061c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 13079e943021SLinus Walleij unsigned long flags; 13081c6a0718SPierre Ossman 13091c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 13101c6a0718SPierre Ossman 1311653a761eSUlf Hansson mrq->cmd->error = mmci_validate_data(host, mrq->data); 1312653a761eSUlf Hansson if (mrq->cmd->error) { 1313255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1314255d01afSPierre Ossman return; 1315255d01afSPierre Ossman } 1316255d01afSPierre Ossman 13179e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 13181c6a0718SPierre Ossman 13191c6a0718SPierre Ossman host->mrq = mrq; 13201c6a0718SPierre Ossman 132158c7ccbfSPer Forlin if (mrq->data) 132258c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 132358c7ccbfSPer Forlin 13241c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 13251c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 13261c6a0718SPierre Ossman 1327024629c6SUlf Hansson if (mrq->sbc) 1328024629c6SUlf Hansson mmci_start_command(host, mrq->sbc, 0); 1329024629c6SUlf Hansson else 13301c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 13311c6a0718SPierre Ossman 13329e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 13331c6a0718SPierre Ossman } 13341c6a0718SPierre Ossman 13351c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 13361c6a0718SPierre Ossman { 13371c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 13387d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1339a6a6464aSLinus Walleij u32 pwr = 0; 1340a6a6464aSLinus Walleij unsigned long flags; 1341db90f91fSLee Jones int ret; 13421c6a0718SPierre Ossman 1343bc521818SUlf Hansson if (host->plat->ios_handler && 1344bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1345bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1346bc521818SUlf Hansson 13471c6a0718SPierre Ossman switch (ios->power_mode) { 13481c6a0718SPierre Ossman case MMC_POWER_OFF: 1349599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1350599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1351237fb5e6SLee Jones 13527c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1353237fb5e6SLee Jones regulator_disable(mmc->supply.vqmmc); 13547c0136efSUlf Hansson host->vqmmc_enabled = false; 13557c0136efSUlf Hansson } 1356237fb5e6SLee Jones 13571c6a0718SPierre Ossman break; 13581c6a0718SPierre Ossman case MMC_POWER_UP: 1359599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1360599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1361599c1d5cSUlf Hansson 13627d72a1d4SUlf Hansson /* 13637d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 13647d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 13657d72a1d4SUlf Hansson * configured in the variant data. 13667d72a1d4SUlf Hansson */ 13677d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 13687d72a1d4SUlf Hansson 13691c6a0718SPierre Ossman break; 13701c6a0718SPierre Ossman case MMC_POWER_ON: 13717c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1372db90f91fSLee Jones ret = regulator_enable(mmc->supply.vqmmc); 1373db90f91fSLee Jones if (ret < 0) 1374db90f91fSLee Jones dev_err(mmc_dev(mmc), 1375db90f91fSLee Jones "failed to enable vqmmc regulator\n"); 13767c0136efSUlf Hansson else 13777c0136efSUlf Hansson host->vqmmc_enabled = true; 1378db90f91fSLee Jones } 1379237fb5e6SLee Jones 13801c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 13811c6a0718SPierre Ossman break; 13821c6a0718SPierre Ossman } 13831c6a0718SPierre Ossman 13844d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 13854d1a3a0dSUlf Hansson /* 13864d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 13874d1a3a0dSUlf Hansson * indicating signal direction for the signals in 13884d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 13894d1a3a0dSUlf Hansson */ 13904593df29SUlf Hansson pwr |= host->pwr_reg_add; 13914d1a3a0dSUlf Hansson 13924d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 13934d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 13944d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 13954d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 13964d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 13974d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 13984d1a3a0dSUlf Hansson } 13994d1a3a0dSUlf Hansson 1400f9bb304cSPatrice Chotard if (variant->opendrain) { 1401f9bb304cSPatrice Chotard if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 140211dfb970SPatrice Chotard pwr |= variant->opendrain; 1403f9bb304cSPatrice Chotard } else { 1404f9bb304cSPatrice Chotard /* 1405f9bb304cSPatrice Chotard * If the variant cannot configure the pads by its own, then we 1406f9bb304cSPatrice Chotard * expect the pinctrl to be able to do that for us 1407f9bb304cSPatrice Chotard */ 1408f9bb304cSPatrice Chotard if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1409f9bb304cSPatrice Chotard pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1410f9bb304cSPatrice Chotard else 1411f9bb304cSPatrice Chotard pinctrl_select_state(host->pinctrl, host->pins_default); 1412f9bb304cSPatrice Chotard } 14131c6a0718SPierre Ossman 1414f4670daeSUlf Hansson /* 1415f4670daeSUlf Hansson * If clock = 0 and the variant requires the MMCIPOWER to be used for 1416f4670daeSUlf Hansson * gating the clock, the MCI_PWR_ON bit is cleared. 1417f4670daeSUlf Hansson */ 1418f4670daeSUlf Hansson if (!ios->clock && variant->pwrreg_clkgate) 1419f4670daeSUlf Hansson pwr &= ~MCI_PWR_ON; 1420f4670daeSUlf Hansson 14213f4e6f7bSSrinivas Kandagatla if (host->variant->explicit_mclk_control && 14223f4e6f7bSSrinivas Kandagatla ios->clock != host->clock_cache) { 14233f4e6f7bSSrinivas Kandagatla ret = clk_set_rate(host->clk, ios->clock); 14243f4e6f7bSSrinivas Kandagatla if (ret < 0) 14253f4e6f7bSSrinivas Kandagatla dev_err(mmc_dev(host->mmc), 14263f4e6f7bSSrinivas Kandagatla "Error setting clock rate (%d)\n", ret); 14273f4e6f7bSSrinivas Kandagatla else 14283f4e6f7bSSrinivas Kandagatla host->mclk = clk_get_rate(host->clk); 14293f4e6f7bSSrinivas Kandagatla } 14303f4e6f7bSSrinivas Kandagatla host->clock_cache = ios->clock; 14313f4e6f7bSSrinivas Kandagatla 1432a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1433a6a6464aSLinus Walleij 1434a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 14357437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1436f829c042SUlf Hansson mmci_reg_delay(host); 1437a6a6464aSLinus Walleij 1438a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 14391c6a0718SPierre Ossman } 14401c6a0718SPierre Ossman 144189001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 144289001446SRussell King { 144389001446SRussell King struct mmci_host *host = mmc_priv(mmc); 144429719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 1445d2762090SUlf Hansson unsigned int status = mmc_gpio_get_cd(mmc); 144689001446SRussell King 1447d2762090SUlf Hansson if (status == -ENOSYS) { 14484b8caec0SRabin Vincent if (!plat->status) 14494b8caec0SRabin Vincent return 1; /* Assume always present */ 14504b8caec0SRabin Vincent 145129719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 1452d2762090SUlf Hansson } 145374bc8093SRussell King return status; 145489001446SRussell King } 145589001446SRussell King 14560f3ed7f7SUlf Hansson static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 14570f3ed7f7SUlf Hansson { 14580f3ed7f7SUlf Hansson int ret = 0; 14590f3ed7f7SUlf Hansson 14600f3ed7f7SUlf Hansson if (!IS_ERR(mmc->supply.vqmmc)) { 14610f3ed7f7SUlf Hansson 14620f3ed7f7SUlf Hansson switch (ios->signal_voltage) { 14630f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_330: 14640f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14650f3ed7f7SUlf Hansson 2700000, 3600000); 14660f3ed7f7SUlf Hansson break; 14670f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_180: 14680f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14690f3ed7f7SUlf Hansson 1700000, 1950000); 14700f3ed7f7SUlf Hansson break; 14710f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_120: 14720f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14730f3ed7f7SUlf Hansson 1100000, 1300000); 14740f3ed7f7SUlf Hansson break; 14750f3ed7f7SUlf Hansson } 14760f3ed7f7SUlf Hansson 14770f3ed7f7SUlf Hansson if (ret) 14780f3ed7f7SUlf Hansson dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 14790f3ed7f7SUlf Hansson } 14800f3ed7f7SUlf Hansson 14810f3ed7f7SUlf Hansson return ret; 14820f3ed7f7SUlf Hansson } 14830f3ed7f7SUlf Hansson 148401259620SUlf Hansson static struct mmc_host_ops mmci_ops = { 14851c6a0718SPierre Ossman .request = mmci_request, 148658c7ccbfSPer Forlin .pre_req = mmci_pre_request, 148758c7ccbfSPer Forlin .post_req = mmci_post_request, 14881c6a0718SPierre Ossman .set_ios = mmci_set_ios, 1489d2762090SUlf Hansson .get_ro = mmc_gpio_get_ro, 149089001446SRussell King .get_cd = mmci_get_cd, 14910f3ed7f7SUlf Hansson .start_signal_voltage_switch = mmci_sig_volt_switch, 14921c6a0718SPierre Ossman }; 14931c6a0718SPierre Ossman 149478f87df2SUlf Hansson static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 149578f87df2SUlf Hansson { 14964593df29SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 149778f87df2SUlf Hansson int ret = mmc_of_parse(mmc); 1498000bc9d5SLee Jones 149978f87df2SUlf Hansson if (ret) 150078f87df2SUlf Hansson return ret; 1501000bc9d5SLee Jones 15024593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat0", NULL)) 15034593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA0DIREN; 15044593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat2", NULL)) 15054593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA2DIREN; 15064593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat31", NULL)) 15074593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA31DIREN; 15084593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat74", NULL)) 15094593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA74DIREN; 15104593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-cmd", NULL)) 15114593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_CMDDIREN; 15124593df29SUlf Hansson if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 15134593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_FBCLKEN; 15144593df29SUlf Hansson 1515000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 151678f87df2SUlf Hansson mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1517000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 151878f87df2SUlf Hansson mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1519000bc9d5SLee Jones 152078f87df2SUlf Hansson return 0; 1521000bc9d5SLee Jones } 1522000bc9d5SLee Jones 1523c3be1efdSBill Pemberton static int mmci_probe(struct amba_device *dev, 1524aa25afadSRussell King const struct amba_id *id) 15251c6a0718SPierre Ossman { 15266ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1527000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 15284956e109SRabin Vincent struct variant_data *variant = id->data; 15291c6a0718SPierre Ossman struct mmci_host *host; 15301c6a0718SPierre Ossman struct mmc_host *mmc; 15311c6a0718SPierre Ossman int ret; 15321c6a0718SPierre Ossman 1533000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1534000bc9d5SLee Jones if (!plat && !np) { 1535000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1536000bc9d5SLee Jones return -EINVAL; 15371c6a0718SPierre Ossman } 15381c6a0718SPierre Ossman 1539b9b52918SLee Jones if (!plat) { 1540b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1541b9b52918SLee Jones if (!plat) 1542b9b52918SLee Jones return -ENOMEM; 1543b9b52918SLee Jones } 1544b9b52918SLee Jones 15451c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1546ef289982SUlf Hansson if (!mmc) 1547ef289982SUlf Hansson return -ENOMEM; 15481c6a0718SPierre Ossman 154978f87df2SUlf Hansson ret = mmci_of_parse(np, mmc); 155078f87df2SUlf Hansson if (ret) 155178f87df2SUlf Hansson goto host_free; 155278f87df2SUlf Hansson 15531c6a0718SPierre Ossman host = mmc_priv(mmc); 15544ea580f1SRabin Vincent host->mmc = mmc; 1555012b7d33SRussell King 1556f9bb304cSPatrice Chotard /* 1557f9bb304cSPatrice Chotard * Some variant (STM32) doesn't have opendrain bit, nevertheless 1558f9bb304cSPatrice Chotard * pins can be set accordingly using pinctrl 1559f9bb304cSPatrice Chotard */ 1560f9bb304cSPatrice Chotard if (!variant->opendrain) { 1561f9bb304cSPatrice Chotard host->pinctrl = devm_pinctrl_get(&dev->dev); 1562f9bb304cSPatrice Chotard if (IS_ERR(host->pinctrl)) { 1563f9bb304cSPatrice Chotard dev_err(&dev->dev, "failed to get pinctrl"); 1564310eb252SWei Yongjun ret = PTR_ERR(host->pinctrl); 1565f9bb304cSPatrice Chotard goto host_free; 1566f9bb304cSPatrice Chotard } 1567f9bb304cSPatrice Chotard 1568f9bb304cSPatrice Chotard host->pins_default = pinctrl_lookup_state(host->pinctrl, 1569f9bb304cSPatrice Chotard PINCTRL_STATE_DEFAULT); 1570f9bb304cSPatrice Chotard if (IS_ERR(host->pins_default)) { 1571f9bb304cSPatrice Chotard dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1572310eb252SWei Yongjun ret = PTR_ERR(host->pins_default); 1573f9bb304cSPatrice Chotard goto host_free; 1574f9bb304cSPatrice Chotard } 1575f9bb304cSPatrice Chotard 1576f9bb304cSPatrice Chotard host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1577f9bb304cSPatrice Chotard MMCI_PINCTRL_STATE_OPENDRAIN); 1578f9bb304cSPatrice Chotard if (IS_ERR(host->pins_opendrain)) { 1579f9bb304cSPatrice Chotard dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1580310eb252SWei Yongjun ret = PTR_ERR(host->pins_opendrain); 1581f9bb304cSPatrice Chotard goto host_free; 1582f9bb304cSPatrice Chotard } 1583f9bb304cSPatrice Chotard } 1584f9bb304cSPatrice Chotard 1585012b7d33SRussell King host->hw_designer = amba_manf(dev); 1586012b7d33SRussell King host->hw_revision = amba_rev(dev); 158764de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 158864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1589012b7d33SRussell King 1590665ba56fSUlf Hansson host->clk = devm_clk_get(&dev->dev, NULL); 15911c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 15921c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 15931c6a0718SPierre Ossman goto host_free; 15941c6a0718SPierre Ossman } 15951c6a0718SPierre Ossman 1596ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 15971c6a0718SPierre Ossman if (ret) 1598665ba56fSUlf Hansson goto host_free; 15991c6a0718SPierre Ossman 16009c34b73dSSrinivas Kandagatla if (variant->qcom_fifo) 16019c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 16029c34b73dSSrinivas Kandagatla else 16039c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_get_rx_fifocnt; 16049c34b73dSSrinivas Kandagatla 16051c6a0718SPierre Ossman host->plat = plat; 16064956e109SRabin Vincent host->variant = variant; 16071c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1608c8df9a53SLinus Walleij /* 1609c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1610c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1611c8df9a53SLinus Walleij * (if possible). 1612c8df9a53SLinus Walleij */ 1613dc6500bfSSrinivas Kandagatla if (host->mclk > variant->f_max) { 1614dc6500bfSSrinivas Kandagatla ret = clk_set_rate(host->clk, variant->f_max); 1615c8df9a53SLinus Walleij if (ret < 0) 1616c8df9a53SLinus Walleij goto clk_disable; 1617c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 161864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 161964de0289SLinus Walleij host->mclk); 1620c8df9a53SLinus Walleij } 1621ef289982SUlf Hansson 1622c8ebae37SRussell King host->phybase = dev->res.start; 1623ef289982SUlf Hansson host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1624ef289982SUlf Hansson if (IS_ERR(host->base)) { 1625ef289982SUlf Hansson ret = PTR_ERR(host->base); 16261c6a0718SPierre Ossman goto clk_disable; 16271c6a0718SPierre Ossman } 16281c6a0718SPierre Ossman 1629ed9067fdSUlf Hansson if (variant->init) 1630ed9067fdSUlf Hansson variant->init(host); 1631ed9067fdSUlf Hansson 16327f294e49SLinus Walleij /* 16337f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 16347f294e49SLinus Walleij * clock divider equations which means that the minimum divider 16357f294e49SLinus Walleij * differs too. 16363f4e6f7bSSrinivas Kandagatla * on Qualcomm like controllers get the nearest minimum clock to 100Khz 16377f294e49SLinus Walleij */ 16387f294e49SLinus Walleij if (variant->st_clkdiv) 16397f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 16403f4e6f7bSSrinivas Kandagatla else if (variant->explicit_mclk_control) 16413f4e6f7bSSrinivas Kandagatla mmc->f_min = clk_round_rate(host->clk, 100000); 16427f294e49SLinus Walleij else 16437f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1644808d97ccSLinus Walleij /* 164578f87df2SUlf Hansson * If no maximum operating frequency is supplied, fall back to use 164678f87df2SUlf Hansson * the module parameter, which has a (low) default value in case it 164778f87df2SUlf Hansson * is not specified. Either value must not exceed the clock rate into 16485080a08dSUlf Hansson * the block, of course. 1649808d97ccSLinus Walleij */ 165078f87df2SUlf Hansson if (mmc->f_max) 16513f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16523f4e6f7bSSrinivas Kandagatla min(variant->f_max, mmc->f_max) : 16533f4e6f7bSSrinivas Kandagatla min(host->mclk, mmc->f_max); 1654808d97ccSLinus Walleij else 16553f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16563f4e6f7bSSrinivas Kandagatla fmax : min(host->mclk, fmax); 16573f4e6f7bSSrinivas Kandagatla 16583f4e6f7bSSrinivas Kandagatla 165964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 166064de0289SLinus Walleij 1661599c1d5cSUlf Hansson /* Get regulators and the supported OCR mask */ 16629369c97cSBjorn Andersson ret = mmc_regulator_get_supply(mmc); 166351006952SWolfram Sang if (ret) 16649369c97cSBjorn Andersson goto clk_disable; 16659369c97cSBjorn Andersson 1666599c1d5cSUlf Hansson if (!mmc->ocr_avail) 16671c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 1668599c1d5cSUlf Hansson else if (plat->ocr_mask) 1669599c1d5cSUlf Hansson dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1670599c1d5cSUlf Hansson 16719dd8a8b8SUlf Hansson /* We support these capabilities. */ 16729dd8a8b8SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 16739dd8a8b8SUlf Hansson 167449adc0caSLinus Walleij /* 167549adc0caSLinus Walleij * Enable busy detection. 167649adc0caSLinus Walleij */ 16778d94b54dSUlf Hansson if (variant->busy_detect) { 16788d94b54dSUlf Hansson mmci_ops.card_busy = mmci_card_busy; 167949adc0caSLinus Walleij /* 168049adc0caSLinus Walleij * Not all variants have a flag to enable busy detection 168149adc0caSLinus Walleij * in the DPSM, but if they do, set it here. 168249adc0caSLinus Walleij */ 168349adc0caSLinus Walleij if (variant->busy_dpsm_flag) 168449adc0caSLinus Walleij mmci_write_datactrlreg(host, 168549adc0caSLinus Walleij host->variant->busy_dpsm_flag); 16868d94b54dSUlf Hansson mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 16878d94b54dSUlf Hansson mmc->max_busy_timeout = 0; 16888d94b54dSUlf Hansson } 16898d94b54dSUlf Hansson 16908d94b54dSUlf Hansson mmc->ops = &mmci_ops; 16918d94b54dSUlf Hansson 169270be208fSUlf Hansson /* We support these PM capabilities. */ 169378f87df2SUlf Hansson mmc->pm_caps |= MMC_PM_KEEP_POWER; 169470be208fSUlf Hansson 16951c6a0718SPierre Ossman /* 16961c6a0718SPierre Ossman * We can do SGIO 16971c6a0718SPierre Ossman */ 1698a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 16991c6a0718SPierre Ossman 17001c6a0718SPierre Ossman /* 170108458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 170208458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 170308458ef6SRabin Vincent * single request. 17041c6a0718SPierre Ossman */ 170508458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 17061c6a0718SPierre Ossman 17071c6a0718SPierre Ossman /* 17081c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 17091c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 17101c6a0718SPierre Ossman */ 17111c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 17121c6a0718SPierre Ossman 17131c6a0718SPierre Ossman /* 17141c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 17151c6a0718SPierre Ossman */ 17168f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 17171c6a0718SPierre Ossman 17181c6a0718SPierre Ossman /* 17198f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 17208f7f6b7eSWill Deacon * the maximum request size. 17211c6a0718SPierre Ossman */ 17228f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 17231c6a0718SPierre Ossman 17241c6a0718SPierre Ossman spin_lock_init(&host->lock); 17251c6a0718SPierre Ossman 17261c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 17276ea9cdf3SPatrice Chotard 17286ea9cdf3SPatrice Chotard if (variant->mmcimask1) 17291c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 17306ea9cdf3SPatrice Chotard 17311c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 17321c6a0718SPierre Ossman 1733ce437aa4SLinus Walleij /* 1734ce437aa4SLinus Walleij * If: 1735ce437aa4SLinus Walleij * - not using DT but using a descriptor table, or 1736ce437aa4SLinus Walleij * - using a table of descriptors ALONGSIDE DT, or 1737ce437aa4SLinus Walleij * look up these descriptors named "cd" and "wp" right here, fail 17389ef986a6SLinus Walleij * silently of these do not exist 1739ce437aa4SLinus Walleij */ 1740ce437aa4SLinus Walleij if (!np) { 174189168b48SLinus Walleij ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1742ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1743ce437aa4SLinus Walleij goto clk_disable; 1744ce437aa4SLinus Walleij 174589168b48SLinus Walleij ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1746ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1747ce437aa4SLinus Walleij goto clk_disable; 1748ce437aa4SLinus Walleij } 174989001446SRussell King 1750ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1751ef289982SUlf Hansson DRIVER_NAME " (cmd)", host); 17521c6a0718SPierre Ossman if (ret) 1753ef289982SUlf Hansson goto clk_disable; 17541c6a0718SPierre Ossman 1755dfb85185SRussell King if (!dev->irq[1]) 17562686b4b4SLinus Walleij host->singleirq = true; 17572686b4b4SLinus Walleij else { 1758ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1759ef289982SUlf Hansson IRQF_SHARED, DRIVER_NAME " (pio)", host); 17601c6a0718SPierre Ossman if (ret) 1761ef289982SUlf Hansson goto clk_disable; 17622686b4b4SLinus Walleij } 17631c6a0718SPierre Ossman 17648cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 17651c6a0718SPierre Ossman 17661c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 17671c6a0718SPierre Ossman 1768c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1769c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1770c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1771c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1772c8ebae37SRussell King 1773c8ebae37SRussell King mmci_dma_setup(host); 17741c6a0718SPierre Ossman 17752cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 17762cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 17771c3be369SRussell King 17788c11a94dSRussell King mmc_add_host(mmc); 17798c11a94dSRussell King 17806f2d3c89SUlf Hansson pm_runtime_put(&dev->dev); 17811c6a0718SPierre Ossman return 0; 17821c6a0718SPierre Ossman 17831c6a0718SPierre Ossman clk_disable: 1784ac940938SJulia Lawall clk_disable_unprepare(host->clk); 17851c6a0718SPierre Ossman host_free: 17861c6a0718SPierre Ossman mmc_free_host(mmc); 17871c6a0718SPierre Ossman return ret; 17881c6a0718SPierre Ossman } 17891c6a0718SPierre Ossman 17906e0ee714SBill Pemberton static int mmci_remove(struct amba_device *dev) 17911c6a0718SPierre Ossman { 17921c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 17931c6a0718SPierre Ossman 17941c6a0718SPierre Ossman if (mmc) { 17951c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 17966ea9cdf3SPatrice Chotard struct variant_data *variant = host->variant; 17971c6a0718SPierre Ossman 17981c3be369SRussell King /* 17991c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 18001c3be369SRussell King * version here so that we can access the primecell. 18011c3be369SRussell King */ 18021c3be369SRussell King pm_runtime_get_sync(&dev->dev); 18031c3be369SRussell King 18041c6a0718SPierre Ossman mmc_remove_host(mmc); 18051c6a0718SPierre Ossman 18061c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 18076ea9cdf3SPatrice Chotard 18086ea9cdf3SPatrice Chotard if (variant->mmcimask1) 18091c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 18101c6a0718SPierre Ossman 18111c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 18121c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 18131c6a0718SPierre Ossman 1814c8ebae37SRussell King mmci_dma_release(host); 1815ac940938SJulia Lawall clk_disable_unprepare(host->clk); 18161c6a0718SPierre Ossman mmc_free_host(mmc); 18171c6a0718SPierre Ossman } 18181c6a0718SPierre Ossman 18191c6a0718SPierre Ossman return 0; 18201c6a0718SPierre Ossman } 18211c6a0718SPierre Ossman 1822571dce4fSUlf Hansson #ifdef CONFIG_PM 18231ff44433SUlf Hansson static void mmci_save(struct mmci_host *host) 18241ff44433SUlf Hansson { 18251ff44433SUlf Hansson unsigned long flags; 18261ff44433SUlf Hansson 18271ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18281ff44433SUlf Hansson 18291ff44433SUlf Hansson writel(0, host->base + MMCIMASK0); 183042dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18311ff44433SUlf Hansson writel(0, host->base + MMCIDATACTRL); 18321ff44433SUlf Hansson writel(0, host->base + MMCIPOWER); 18331ff44433SUlf Hansson writel(0, host->base + MMCICLOCK); 183442dcc89aSUlf Hansson } 18351ff44433SUlf Hansson mmci_reg_delay(host); 18361ff44433SUlf Hansson 18371ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18381ff44433SUlf Hansson } 18391ff44433SUlf Hansson 18401ff44433SUlf Hansson static void mmci_restore(struct mmci_host *host) 18411ff44433SUlf Hansson { 18421ff44433SUlf Hansson unsigned long flags; 18431ff44433SUlf Hansson 18441ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18451ff44433SUlf Hansson 184642dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18471ff44433SUlf Hansson writel(host->clk_reg, host->base + MMCICLOCK); 18481ff44433SUlf Hansson writel(host->datactrl_reg, host->base + MMCIDATACTRL); 18491ff44433SUlf Hansson writel(host->pwr_reg, host->base + MMCIPOWER); 185042dcc89aSUlf Hansson } 18511ff44433SUlf Hansson writel(MCI_IRQENABLE, host->base + MMCIMASK0); 18521ff44433SUlf Hansson mmci_reg_delay(host); 18531ff44433SUlf Hansson 18541ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18551ff44433SUlf Hansson } 18561ff44433SUlf Hansson 18578259293aSUlf Hansson static int mmci_runtime_suspend(struct device *dev) 18588259293aSUlf Hansson { 18598259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18608259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18618259293aSUlf Hansson 18628259293aSUlf Hansson if (mmc) { 18638259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 1864e36bd9c6SUlf Hansson pinctrl_pm_select_sleep_state(dev); 18651ff44433SUlf Hansson mmci_save(host); 18668259293aSUlf Hansson clk_disable_unprepare(host->clk); 18678259293aSUlf Hansson } 18688259293aSUlf Hansson 18698259293aSUlf Hansson return 0; 18708259293aSUlf Hansson } 18718259293aSUlf Hansson 18728259293aSUlf Hansson static int mmci_runtime_resume(struct device *dev) 18738259293aSUlf Hansson { 18748259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18758259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18768259293aSUlf Hansson 18778259293aSUlf Hansson if (mmc) { 18788259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 18798259293aSUlf Hansson clk_prepare_enable(host->clk); 18801ff44433SUlf Hansson mmci_restore(host); 1881e36bd9c6SUlf Hansson pinctrl_pm_select_default_state(dev); 18828259293aSUlf Hansson } 18838259293aSUlf Hansson 18848259293aSUlf Hansson return 0; 18858259293aSUlf Hansson } 18868259293aSUlf Hansson #endif 18878259293aSUlf Hansson 188848fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 1889f3737fa3SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1890f3737fa3SUlf Hansson pm_runtime_force_resume) 18916ed23b80SRafael J. Wysocki SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 189248fa7003SUlf Hansson }; 189348fa7003SUlf Hansson 189488411deaSArvind Yadav static const struct amba_id mmci_ids[] = { 18951c6a0718SPierre Ossman { 18961c6a0718SPierre Ossman .id = 0x00041180, 1897768fbc18SPawel Moll .mask = 0xff0fffff, 18984956e109SRabin Vincent .data = &variant_arm, 18991c6a0718SPierre Ossman }, 19001c6a0718SPierre Ossman { 1901768fbc18SPawel Moll .id = 0x01041180, 1902768fbc18SPawel Moll .mask = 0xff0fffff, 1903768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1904768fbc18SPawel Moll }, 1905768fbc18SPawel Moll { 19063a37298aSPawel Moll .id = 0x02041180, 19073a37298aSPawel Moll .mask = 0xff0fffff, 19083a37298aSPawel Moll .data = &variant_arm_extended_fifo_hwfc, 19093a37298aSPawel Moll }, 19103a37298aSPawel Moll { 19111c6a0718SPierre Ossman .id = 0x00041181, 19121c6a0718SPierre Ossman .mask = 0x000fffff, 19134956e109SRabin Vincent .data = &variant_arm, 19141c6a0718SPierre Ossman }, 1915cc30d60eSLinus Walleij /* ST Micro variants */ 1916cc30d60eSLinus Walleij { 1917cc30d60eSLinus Walleij .id = 0x00180180, 1918cc30d60eSLinus Walleij .mask = 0x00ffffff, 19194956e109SRabin Vincent .data = &variant_u300, 1920cc30d60eSLinus Walleij }, 1921cc30d60eSLinus Walleij { 192234fd4213SLinus Walleij .id = 0x10180180, 192334fd4213SLinus Walleij .mask = 0xf0ffffff, 192434fd4213SLinus Walleij .data = &variant_nomadik, 192534fd4213SLinus Walleij }, 192634fd4213SLinus Walleij { 1927cc30d60eSLinus Walleij .id = 0x00280180, 1928cc30d60eSLinus Walleij .mask = 0x00ffffff, 19290bcb7efdSLinus Walleij .data = &variant_nomadik, 19304956e109SRabin Vincent }, 19314956e109SRabin Vincent { 19324956e109SRabin Vincent .id = 0x00480180, 19331784b157SPhilippe Langlais .mask = 0xf0ffffff, 19344956e109SRabin Vincent .data = &variant_ux500, 1935cc30d60eSLinus Walleij }, 19361784b157SPhilippe Langlais { 19371784b157SPhilippe Langlais .id = 0x10480180, 19381784b157SPhilippe Langlais .mask = 0xf0ffffff, 19391784b157SPhilippe Langlais .data = &variant_ux500v2, 19401784b157SPhilippe Langlais }, 19412a9d6c80SPatrice Chotard { 19422a9d6c80SPatrice Chotard .id = 0x00880180, 19432a9d6c80SPatrice Chotard .mask = 0x00ffffff, 19442a9d6c80SPatrice Chotard .data = &variant_stm32, 19452a9d6c80SPatrice Chotard }, 194655b604aeSSrinivas Kandagatla /* Qualcomm variants */ 194755b604aeSSrinivas Kandagatla { 194855b604aeSSrinivas Kandagatla .id = 0x00051180, 194955b604aeSSrinivas Kandagatla .mask = 0x000fffff, 195055b604aeSSrinivas Kandagatla .data = &variant_qcom, 195155b604aeSSrinivas Kandagatla }, 19521c6a0718SPierre Ossman { 0, 0 }, 19531c6a0718SPierre Ossman }; 19541c6a0718SPierre Ossman 19559f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 19569f99835fSDave Martin 19571c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 19581c6a0718SPierre Ossman .drv = { 19591c6a0718SPierre Ossman .name = DRIVER_NAME, 196048fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 19611c6a0718SPierre Ossman }, 19621c6a0718SPierre Ossman .probe = mmci_probe, 19630433c143SBill Pemberton .remove = mmci_remove, 19641c6a0718SPierre Ossman .id_table = mmci_ids, 19651c6a0718SPierre Ossman }; 19661c6a0718SPierre Ossman 19679e5ed094Sviresh kumar module_amba_driver(mmci_driver); 19681c6a0718SPierre Ossman 19691c6a0718SPierre Ossman module_param(fmax, uint, 0444); 19701c6a0718SPierre Ossman 19711c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 19721c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1973