11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 18000bc9d5SLee Jones #include <linux/slab.h> 191c6a0718SPierre Ossman #include <linux/delay.h> 201c6a0718SPierre Ossman #include <linux/err.h> 211c6a0718SPierre Ossman #include <linux/highmem.h> 22019a5f56SNicolas Pitre #include <linux/log2.h> 231c6a0718SPierre Ossman #include <linux/mmc/host.h> 2434177802SLinus Walleij #include <linux/mmc/card.h> 251c6a0718SPierre Ossman #include <linux/amba/bus.h> 261c6a0718SPierre Ossman #include <linux/clk.h> 27bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2889001446SRussell King #include <linux/gpio.h> 299a597016SLee Jones #include <linux/of_gpio.h> 3034e84f39SLinus Walleij #include <linux/regulator/consumer.h> 31c8ebae37SRussell King #include <linux/dmaengine.h> 32c8ebae37SRussell King #include <linux/dma-mapping.h> 33c8ebae37SRussell King #include <linux/amba/mmci.h> 341c3be369SRussell King #include <linux/pm_runtime.h> 35258aea76SViresh Kumar #include <linux/types.h> 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #include <asm/div64.h> 381c6a0718SPierre Ossman #include <asm/io.h> 391c6a0718SPierre Ossman #include <asm/sizes.h> 401c6a0718SPierre Ossman 411c6a0718SPierre Ossman #include "mmci.h" 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman static unsigned int fmax = 515633; 461c6a0718SPierre Ossman 474956e109SRabin Vincent /** 484956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 494956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 504380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 5108458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 528301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 538301bb68SRabin Vincent * is asserted (likewise for RX) 548301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 558301bb68SRabin Vincent * is asserted (likewise for RX) 5634177802SLinus Walleij * @sdio: variant supports SDIO 57b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 581784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 597d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 604d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 614956e109SRabin Vincent */ 624956e109SRabin Vincent struct variant_data { 634956e109SRabin Vincent unsigned int clkreg; 644380c14fSRabin Vincent unsigned int clkreg_enable; 6508458ef6SRabin Vincent unsigned int datalength_bits; 668301bb68SRabin Vincent unsigned int fifosize; 678301bb68SRabin Vincent unsigned int fifohalfsize; 6834177802SLinus Walleij bool sdio; 69b70a67f9SLinus Walleij bool st_clkdiv; 701784b157SPhilippe Langlais bool blksz_datactrl16; 717d72a1d4SUlf Hansson u32 pwrreg_powerup; 724d1a3a0dSUlf Hansson bool signal_direction; 734956e109SRabin Vincent }; 744956e109SRabin Vincent 754956e109SRabin Vincent static struct variant_data variant_arm = { 768301bb68SRabin Vincent .fifosize = 16 * 4, 778301bb68SRabin Vincent .fifohalfsize = 8 * 4, 7808458ef6SRabin Vincent .datalength_bits = 16, 797d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 804956e109SRabin Vincent }; 814956e109SRabin Vincent 82768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 83768fbc18SPawel Moll .fifosize = 128 * 4, 84768fbc18SPawel Moll .fifohalfsize = 64 * 4, 85768fbc18SPawel Moll .datalength_bits = 16, 867d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 87768fbc18SPawel Moll }; 88768fbc18SPawel Moll 894956e109SRabin Vincent static struct variant_data variant_u300 = { 908301bb68SRabin Vincent .fifosize = 16 * 4, 918301bb68SRabin Vincent .fifohalfsize = 8 * 4, 9249ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 9308458ef6SRabin Vincent .datalength_bits = 16, 9434177802SLinus Walleij .sdio = true, 957d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 964d1a3a0dSUlf Hansson .signal_direction = true, 974956e109SRabin Vincent }; 984956e109SRabin Vincent 9934fd4213SLinus Walleij static struct variant_data variant_nomadik = { 10034fd4213SLinus Walleij .fifosize = 16 * 4, 10134fd4213SLinus Walleij .fifohalfsize = 8 * 4, 10234fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 10334fd4213SLinus Walleij .datalength_bits = 24, 10434fd4213SLinus Walleij .sdio = true, 10534fd4213SLinus Walleij .st_clkdiv = true, 10634fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 10734fd4213SLinus Walleij .signal_direction = true, 10834fd4213SLinus Walleij }; 10934fd4213SLinus Walleij 1104956e109SRabin Vincent static struct variant_data variant_ux500 = { 1118301bb68SRabin Vincent .fifosize = 30 * 4, 1128301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1134956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 11449ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 11508458ef6SRabin Vincent .datalength_bits = 24, 11634177802SLinus Walleij .sdio = true, 117b70a67f9SLinus Walleij .st_clkdiv = true, 1187d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1194d1a3a0dSUlf Hansson .signal_direction = true, 1204956e109SRabin Vincent }; 121b70a67f9SLinus Walleij 1221784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1231784b157SPhilippe Langlais .fifosize = 30 * 4, 1241784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1251784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1261784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1271784b157SPhilippe Langlais .datalength_bits = 24, 1281784b157SPhilippe Langlais .sdio = true, 1291784b157SPhilippe Langlais .st_clkdiv = true, 1301784b157SPhilippe Langlais .blksz_datactrl16 = true, 1317d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1324d1a3a0dSUlf Hansson .signal_direction = true, 1331784b157SPhilippe Langlais }; 1341784b157SPhilippe Langlais 135a6a6464aSLinus Walleij /* 136a6a6464aSLinus Walleij * This must be called with host->lock held 137a6a6464aSLinus Walleij */ 1387437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 1397437cfa5SUlf Hansson { 1407437cfa5SUlf Hansson if (host->clk_reg != clk) { 1417437cfa5SUlf Hansson host->clk_reg = clk; 1427437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 1437437cfa5SUlf Hansson } 1447437cfa5SUlf Hansson } 1457437cfa5SUlf Hansson 1467437cfa5SUlf Hansson /* 1477437cfa5SUlf Hansson * This must be called with host->lock held 1487437cfa5SUlf Hansson */ 1497437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 1507437cfa5SUlf Hansson { 1517437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 1527437cfa5SUlf Hansson host->pwr_reg = pwr; 1537437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 1547437cfa5SUlf Hansson } 1557437cfa5SUlf Hansson } 1567437cfa5SUlf Hansson 1577437cfa5SUlf Hansson /* 1587437cfa5SUlf Hansson * This must be called with host->lock held 1597437cfa5SUlf Hansson */ 160a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 161a6a6464aSLinus Walleij { 1624956e109SRabin Vincent struct variant_data *variant = host->variant; 1634956e109SRabin Vincent u32 clk = variant->clkreg; 164a6a6464aSLinus Walleij 165a6a6464aSLinus Walleij if (desired) { 166a6a6464aSLinus Walleij if (desired >= host->mclk) { 167a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 168399bc486SLinus Walleij if (variant->st_clkdiv) 169399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 170a6a6464aSLinus Walleij host->cclk = host->mclk; 171b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 172b70a67f9SLinus Walleij /* 173b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 174b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 175b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 176b70a67f9SLinus Walleij * frequency 177b70a67f9SLinus Walleij */ 178b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 179b70a67f9SLinus Walleij if (clk >= 256) 180b70a67f9SLinus Walleij clk = 255; 181b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 182a6a6464aSLinus Walleij } else { 183b70a67f9SLinus Walleij /* 184b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 185b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 186b70a67f9SLinus Walleij */ 187a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 188a6a6464aSLinus Walleij if (clk >= 256) 189a6a6464aSLinus Walleij clk = 255; 190a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 191a6a6464aSLinus Walleij } 1924380c14fSRabin Vincent 1934380c14fSRabin Vincent clk |= variant->clkreg_enable; 194a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 195a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 196a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 197a6a6464aSLinus Walleij } 198a6a6464aSLinus Walleij 1999e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 200771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 201771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 202771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 2039e6c82cdSLinus Walleij 2047437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 205a6a6464aSLinus Walleij } 206a6a6464aSLinus Walleij 2071c6a0718SPierre Ossman static void 2081c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 2091c6a0718SPierre Ossman { 2101c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 2111c6a0718SPierre Ossman 2121c6a0718SPierre Ossman BUG_ON(host->data); 2131c6a0718SPierre Ossman 2141c6a0718SPierre Ossman host->mrq = NULL; 2151c6a0718SPierre Ossman host->cmd = NULL; 2161c6a0718SPierre Ossman 2171c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2182cd976c4SUlf Hansson 2192cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 2202cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 2211c6a0718SPierre Ossman } 2221c6a0718SPierre Ossman 2232686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 2242686b4b4SLinus Walleij { 2252686b4b4SLinus Walleij void __iomem *base = host->base; 2262686b4b4SLinus Walleij 2272686b4b4SLinus Walleij if (host->singleirq) { 2282686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 2292686b4b4SLinus Walleij 2302686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 2312686b4b4SLinus Walleij mask0 |= mask; 2322686b4b4SLinus Walleij 2332686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 2342686b4b4SLinus Walleij } 2352686b4b4SLinus Walleij 2362686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 2372686b4b4SLinus Walleij } 2382686b4b4SLinus Walleij 2391c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 2401c6a0718SPierre Ossman { 2411c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 2422686b4b4SLinus Walleij mmci_set_mask1(host, 0); 2431c6a0718SPierre Ossman host->data = NULL; 2441c6a0718SPierre Ossman } 2451c6a0718SPierre Ossman 2464ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 2474ce1d6cbSRabin Vincent { 2484ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 2494ce1d6cbSRabin Vincent 2504ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 2514ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 2524ce1d6cbSRabin Vincent else 2534ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 2544ce1d6cbSRabin Vincent 2554ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 2564ce1d6cbSRabin Vincent } 2574ce1d6cbSRabin Vincent 258c8ebae37SRussell King /* 259c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 260c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 261c8ebae37SRussell King * no custom DMA interfaces are supported. 262c8ebae37SRussell King */ 263c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 264c8ebae37SRussell King static void __devinit mmci_dma_setup(struct mmci_host *host) 265c8ebae37SRussell King { 266c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 267c8ebae37SRussell King const char *rxname, *txname; 268c8ebae37SRussell King dma_cap_mask_t mask; 269c8ebae37SRussell King 270c8ebae37SRussell King if (!plat || !plat->dma_filter) { 271c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 272c8ebae37SRussell King return; 273c8ebae37SRussell King } 274c8ebae37SRussell King 27558c7ccbfSPer Forlin /* initialize pre request cookie */ 27658c7ccbfSPer Forlin host->next_data.cookie = 1; 27758c7ccbfSPer Forlin 278c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 279c8ebae37SRussell King dma_cap_zero(mask); 280c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 281c8ebae37SRussell King 282c8ebae37SRussell King /* 283c8ebae37SRussell King * If only an RX channel is specified, the driver will 284c8ebae37SRussell King * attempt to use it bidirectionally, however if it is 285c8ebae37SRussell King * is specified but cannot be located, DMA will be disabled. 286c8ebae37SRussell King */ 287c8ebae37SRussell King if (plat->dma_rx_param) { 288c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 289c8ebae37SRussell King plat->dma_filter, 290c8ebae37SRussell King plat->dma_rx_param); 291c8ebae37SRussell King /* E.g if no DMA hardware is present */ 292c8ebae37SRussell King if (!host->dma_rx_channel) 293c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 294c8ebae37SRussell King } 295c8ebae37SRussell King 296c8ebae37SRussell King if (plat->dma_tx_param) { 297c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 298c8ebae37SRussell King plat->dma_filter, 299c8ebae37SRussell King plat->dma_tx_param); 300c8ebae37SRussell King if (!host->dma_tx_channel) 301c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 302c8ebae37SRussell King } else { 303c8ebae37SRussell King host->dma_tx_channel = host->dma_rx_channel; 304c8ebae37SRussell King } 305c8ebae37SRussell King 306c8ebae37SRussell King if (host->dma_rx_channel) 307c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 308c8ebae37SRussell King else 309c8ebae37SRussell King rxname = "none"; 310c8ebae37SRussell King 311c8ebae37SRussell King if (host->dma_tx_channel) 312c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 313c8ebae37SRussell King else 314c8ebae37SRussell King txname = "none"; 315c8ebae37SRussell King 316c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 317c8ebae37SRussell King rxname, txname); 318c8ebae37SRussell King 319c8ebae37SRussell King /* 320c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 321c8ebae37SRussell King * the parameters of the DMA engine device. 322c8ebae37SRussell King */ 323c8ebae37SRussell King if (host->dma_tx_channel) { 324c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 325c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 326c8ebae37SRussell King 327c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 328c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 329c8ebae37SRussell King } 330c8ebae37SRussell King if (host->dma_rx_channel) { 331c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 332c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 333c8ebae37SRussell King 334c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 335c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 336c8ebae37SRussell King } 337c8ebae37SRussell King } 338c8ebae37SRussell King 339c8ebae37SRussell King /* 340c8ebae37SRussell King * This is used in __devinit or __devexit so inline it 341c8ebae37SRussell King * so it can be discarded. 342c8ebae37SRussell King */ 343c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 344c8ebae37SRussell King { 345c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 346c8ebae37SRussell King 347c8ebae37SRussell King if (host->dma_rx_channel) 348c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 349c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 350c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 351c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 352c8ebae37SRussell King } 353c8ebae37SRussell King 354c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 355c8ebae37SRussell King { 356c8ebae37SRussell King struct dma_chan *chan = host->dma_current; 357c8ebae37SRussell King enum dma_data_direction dir; 358c8ebae37SRussell King u32 status; 359c8ebae37SRussell King int i; 360c8ebae37SRussell King 361c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 362c8ebae37SRussell King for (i = 0; ; i++) { 363c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 364c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 365c8ebae37SRussell King break; 366c8ebae37SRussell King udelay(10); 367c8ebae37SRussell King } 368c8ebae37SRussell King 369c8ebae37SRussell King /* 370c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 371c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 372c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 373c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 374c8ebae37SRussell King */ 375c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 376c8ebae37SRussell King dmaengine_terminate_all(chan); 377c8ebae37SRussell King if (!data->error) 378c8ebae37SRussell King data->error = -EIO; 379c8ebae37SRussell King } 380c8ebae37SRussell King 381c8ebae37SRussell King if (data->flags & MMC_DATA_WRITE) { 382c8ebae37SRussell King dir = DMA_TO_DEVICE; 383c8ebae37SRussell King } else { 384c8ebae37SRussell King dir = DMA_FROM_DEVICE; 385c8ebae37SRussell King } 386c8ebae37SRussell King 38758c7ccbfSPer Forlin if (!data->host_cookie) 388c8ebae37SRussell King dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 389c8ebae37SRussell King 390c8ebae37SRussell King /* 391c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 392c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 393c8ebae37SRussell King */ 394c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 395c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 396c8ebae37SRussell King mmci_dma_release(host); 397c8ebae37SRussell King } 398c8ebae37SRussell King } 399c8ebae37SRussell King 400c8ebae37SRussell King static void mmci_dma_data_error(struct mmci_host *host) 401c8ebae37SRussell King { 402c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 403c8ebae37SRussell King dmaengine_terminate_all(host->dma_current); 404c8ebae37SRussell King } 405c8ebae37SRussell King 40658c7ccbfSPer Forlin static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 40758c7ccbfSPer Forlin struct mmci_host_next *next) 408c8ebae37SRussell King { 409c8ebae37SRussell King struct variant_data *variant = host->variant; 410c8ebae37SRussell King struct dma_slave_config conf = { 411c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 412c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 413c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 414c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 415c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 416c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 417258aea76SViresh Kumar .device_fc = false, 418c8ebae37SRussell King }; 419c8ebae37SRussell King struct dma_chan *chan; 420c8ebae37SRussell King struct dma_device *device; 421c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 42205f5799cSVinod Koul enum dma_data_direction buffer_dirn; 423c8ebae37SRussell King int nr_sg; 424c8ebae37SRussell King 42558c7ccbfSPer Forlin /* Check if next job is already prepared */ 42658c7ccbfSPer Forlin if (data->host_cookie && !next && 42758c7ccbfSPer Forlin host->dma_current && host->dma_desc_current) 42858c7ccbfSPer Forlin return 0; 42958c7ccbfSPer Forlin 43058c7ccbfSPer Forlin if (!next) { 431c8ebae37SRussell King host->dma_current = NULL; 43258c7ccbfSPer Forlin host->dma_desc_current = NULL; 43358c7ccbfSPer Forlin } 434c8ebae37SRussell King 435c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 43605f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 43705f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 438c8ebae37SRussell King chan = host->dma_rx_channel; 439c8ebae37SRussell King } else { 44005f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 44105f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 442c8ebae37SRussell King chan = host->dma_tx_channel; 443c8ebae37SRussell King } 444c8ebae37SRussell King 445c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 446c8ebae37SRussell King if (!chan) 447c8ebae37SRussell King return -EINVAL; 448c8ebae37SRussell King 449c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 45058c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 451c8ebae37SRussell King return -EINVAL; 452c8ebae37SRussell King 453c8ebae37SRussell King device = chan->device; 45405f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 455c8ebae37SRussell King if (nr_sg == 0) 456c8ebae37SRussell King return -EINVAL; 457c8ebae37SRussell King 458c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 45916052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 460c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 461c8ebae37SRussell King if (!desc) 462c8ebae37SRussell King goto unmap_exit; 463c8ebae37SRussell King 46458c7ccbfSPer Forlin if (next) { 46558c7ccbfSPer Forlin next->dma_chan = chan; 46658c7ccbfSPer Forlin next->dma_desc = desc; 46758c7ccbfSPer Forlin } else { 468c8ebae37SRussell King host->dma_current = chan; 46958c7ccbfSPer Forlin host->dma_desc_current = desc; 47058c7ccbfSPer Forlin } 471c8ebae37SRussell King 47258c7ccbfSPer Forlin return 0; 47358c7ccbfSPer Forlin 47458c7ccbfSPer Forlin unmap_exit: 47558c7ccbfSPer Forlin if (!next) 47658c7ccbfSPer Forlin dmaengine_terminate_all(chan); 47705f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 47858c7ccbfSPer Forlin return -ENOMEM; 47958c7ccbfSPer Forlin } 48058c7ccbfSPer Forlin 48158c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 48258c7ccbfSPer Forlin { 48358c7ccbfSPer Forlin int ret; 48458c7ccbfSPer Forlin struct mmc_data *data = host->data; 48558c7ccbfSPer Forlin 48658c7ccbfSPer Forlin ret = mmci_dma_prep_data(host, host->data, NULL); 48758c7ccbfSPer Forlin if (ret) 48858c7ccbfSPer Forlin return ret; 48958c7ccbfSPer Forlin 49058c7ccbfSPer Forlin /* Okay, go for it. */ 491c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 492c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 493c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 49458c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 49558c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 496c8ebae37SRussell King 497c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 498c8ebae37SRussell King 499c8ebae37SRussell King /* Trigger the DMA transfer */ 500c8ebae37SRussell King writel(datactrl, host->base + MMCIDATACTRL); 501c8ebae37SRussell King 502c8ebae37SRussell King /* 503c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 504c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 505c8ebae37SRussell King * call mmci_data_end() 506c8ebae37SRussell King */ 507c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 508c8ebae37SRussell King host->base + MMCIMASK0); 509c8ebae37SRussell King return 0; 510c8ebae37SRussell King } 51158c7ccbfSPer Forlin 51258c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 51358c7ccbfSPer Forlin { 51458c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 51558c7ccbfSPer Forlin 51658c7ccbfSPer Forlin if (data->host_cookie && data->host_cookie != next->cookie) { 517a3c76eb9SGirish K S pr_warning("[%s] invalid cookie: data->host_cookie %d" 51858c7ccbfSPer Forlin " host->next_data.cookie %d\n", 51958c7ccbfSPer Forlin __func__, data->host_cookie, host->next_data.cookie); 52058c7ccbfSPer Forlin data->host_cookie = 0; 52158c7ccbfSPer Forlin } 52258c7ccbfSPer Forlin 52358c7ccbfSPer Forlin if (!data->host_cookie) 52458c7ccbfSPer Forlin return; 52558c7ccbfSPer Forlin 52658c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 52758c7ccbfSPer Forlin host->dma_current = next->dma_chan; 52858c7ccbfSPer Forlin 52958c7ccbfSPer Forlin next->dma_desc = NULL; 53058c7ccbfSPer Forlin next->dma_chan = NULL; 53158c7ccbfSPer Forlin } 53258c7ccbfSPer Forlin 53358c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 53458c7ccbfSPer Forlin bool is_first_req) 53558c7ccbfSPer Forlin { 53658c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 53758c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 53858c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 53958c7ccbfSPer Forlin 54058c7ccbfSPer Forlin if (!data) 54158c7ccbfSPer Forlin return; 54258c7ccbfSPer Forlin 54358c7ccbfSPer Forlin if (data->host_cookie) { 54458c7ccbfSPer Forlin data->host_cookie = 0; 54558c7ccbfSPer Forlin return; 54658c7ccbfSPer Forlin } 54758c7ccbfSPer Forlin 54858c7ccbfSPer Forlin /* if config for dma */ 54958c7ccbfSPer Forlin if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 55058c7ccbfSPer Forlin ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 55158c7ccbfSPer Forlin if (mmci_dma_prep_data(host, data, nd)) 55258c7ccbfSPer Forlin data->host_cookie = 0; 55358c7ccbfSPer Forlin else 55458c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 55558c7ccbfSPer Forlin } 55658c7ccbfSPer Forlin } 55758c7ccbfSPer Forlin 55858c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 55958c7ccbfSPer Forlin int err) 56058c7ccbfSPer Forlin { 56158c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 56258c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 56358c7ccbfSPer Forlin struct dma_chan *chan; 56458c7ccbfSPer Forlin enum dma_data_direction dir; 56558c7ccbfSPer Forlin 56658c7ccbfSPer Forlin if (!data) 56758c7ccbfSPer Forlin return; 56858c7ccbfSPer Forlin 56958c7ccbfSPer Forlin if (data->flags & MMC_DATA_READ) { 57058c7ccbfSPer Forlin dir = DMA_FROM_DEVICE; 57158c7ccbfSPer Forlin chan = host->dma_rx_channel; 57258c7ccbfSPer Forlin } else { 57358c7ccbfSPer Forlin dir = DMA_TO_DEVICE; 57458c7ccbfSPer Forlin chan = host->dma_tx_channel; 57558c7ccbfSPer Forlin } 57658c7ccbfSPer Forlin 57758c7ccbfSPer Forlin 57858c7ccbfSPer Forlin /* if config for dma */ 57958c7ccbfSPer Forlin if (chan) { 58058c7ccbfSPer Forlin if (err) 58158c7ccbfSPer Forlin dmaengine_terminate_all(chan); 5828e3336b1SPer Forlin if (data->host_cookie) 58358c7ccbfSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 58458c7ccbfSPer Forlin data->sg_len, dir); 58558c7ccbfSPer Forlin mrq->data->host_cookie = 0; 58658c7ccbfSPer Forlin } 58758c7ccbfSPer Forlin } 58858c7ccbfSPer Forlin 589c8ebae37SRussell King #else 590c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 59158c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 59258c7ccbfSPer Forlin { 59358c7ccbfSPer Forlin } 594c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 595c8ebae37SRussell King { 596c8ebae37SRussell King } 597c8ebae37SRussell King 598c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 599c8ebae37SRussell King { 600c8ebae37SRussell King } 601c8ebae37SRussell King 602c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 603c8ebae37SRussell King { 604c8ebae37SRussell King } 605c8ebae37SRussell King 606c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 607c8ebae37SRussell King { 608c8ebae37SRussell King } 609c8ebae37SRussell King 610c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 611c8ebae37SRussell King { 612c8ebae37SRussell King return -ENOSYS; 613c8ebae37SRussell King } 61458c7ccbfSPer Forlin 61558c7ccbfSPer Forlin #define mmci_pre_request NULL 61658c7ccbfSPer Forlin #define mmci_post_request NULL 61758c7ccbfSPer Forlin 618c8ebae37SRussell King #endif 619c8ebae37SRussell King 6201c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 6211c6a0718SPierre Ossman { 6228301bb68SRabin Vincent struct variant_data *variant = host->variant; 6231c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 6241c6a0718SPierre Ossman unsigned long long clks; 6251c6a0718SPierre Ossman void __iomem *base; 6261c6a0718SPierre Ossman int blksz_bits; 6271c6a0718SPierre Ossman 62864de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 6291c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 6301c6a0718SPierre Ossman 6311c6a0718SPierre Ossman host->data = data; 632528320dbSRabin Vincent host->size = data->blksz * data->blocks; 63351d4375dSRussell King data->bytes_xfered = 0; 6341c6a0718SPierre Ossman 6351c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 6361c6a0718SPierre Ossman do_div(clks, 1000000000UL); 6371c6a0718SPierre Ossman 6381c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 6391c6a0718SPierre Ossman 6401c6a0718SPierre Ossman base = host->base; 6411c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 6421c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 6431c6a0718SPierre Ossman 6441c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 6451c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 6461c6a0718SPierre Ossman 6471784b157SPhilippe Langlais if (variant->blksz_datactrl16) 6481784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 6491784b157SPhilippe Langlais else 6501c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 651c8ebae37SRussell King 652c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 6531c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 654c8ebae37SRussell King 6557258db7eSUlf Hansson /* The ST Micro variants has a special bit to enable SDIO */ 6567258db7eSUlf Hansson if (variant->sdio && host->mmc->card) 65706c1a121SUlf Hansson if (mmc_card_sdio(host->mmc->card)) { 65806c1a121SUlf Hansson /* 65906c1a121SUlf Hansson * The ST Micro variants has a special bit 66006c1a121SUlf Hansson * to enable SDIO. 66106c1a121SUlf Hansson */ 66206c1a121SUlf Hansson u32 clk; 66306c1a121SUlf Hansson 6647258db7eSUlf Hansson datactrl |= MCI_ST_DPSM_SDIOEN; 6657258db7eSUlf Hansson 666c8ebae37SRussell King /* 66770ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 66870ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 66970ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 67070ac0935SUlf Hansson * depends on the rate of MCLK. 67106c1a121SUlf Hansson */ 67270ac0935SUlf Hansson if (data->flags & MMC_DATA_WRITE && 67370ac0935SUlf Hansson (host->size < 8 || 67470ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 67506c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 67606c1a121SUlf Hansson else 67706c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 67806c1a121SUlf Hansson 67906c1a121SUlf Hansson mmci_write_clkreg(host, clk); 68006c1a121SUlf Hansson } 68106c1a121SUlf Hansson 68206c1a121SUlf Hansson /* 683c8ebae37SRussell King * Attempt to use DMA operation mode, if this 684c8ebae37SRussell King * should fail, fall back to PIO mode 685c8ebae37SRussell King */ 686c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 687c8ebae37SRussell King return; 688c8ebae37SRussell King 689c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 690c8ebae37SRussell King mmci_init_sg(host, data); 691c8ebae37SRussell King 692c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 6931c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 6941c6a0718SPierre Ossman 6951c6a0718SPierre Ossman /* 696c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 697c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 698c4d877c1SRussell King * is available. 6991c6a0718SPierre Ossman */ 700c4d877c1SRussell King if (host->size < variant->fifohalfsize) 7011c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 7021c6a0718SPierre Ossman } else { 7031c6a0718SPierre Ossman /* 7041c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 7051c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 7061c6a0718SPierre Ossman */ 7071c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 7081c6a0718SPierre Ossman } 7091c6a0718SPierre Ossman 7101c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 7111c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 7122686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 7131c6a0718SPierre Ossman } 7141c6a0718SPierre Ossman 7151c6a0718SPierre Ossman static void 7161c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 7171c6a0718SPierre Ossman { 7181c6a0718SPierre Ossman void __iomem *base = host->base; 7191c6a0718SPierre Ossman 72064de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 7211c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 7221c6a0718SPierre Ossman 7231c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 7241c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 7251c6a0718SPierre Ossman udelay(1); 7261c6a0718SPierre Ossman } 7271c6a0718SPierre Ossman 7281c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 7291c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 7301c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 7311c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 7321c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 7331c6a0718SPierre Ossman } 7341c6a0718SPierre Ossman if (/*interrupt*/0) 7351c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 7361c6a0718SPierre Ossman 7371c6a0718SPierre Ossman host->cmd = cmd; 7381c6a0718SPierre Ossman 7391c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 7401c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 7411c6a0718SPierre Ossman } 7421c6a0718SPierre Ossman 7431c6a0718SPierre Ossman static void 7441c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 7451c6a0718SPierre Ossman unsigned int status) 7461c6a0718SPierre Ossman { 747f20f8f21SLinus Walleij /* First check for errors */ 748b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 749b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 7508cb28155SLinus Walleij u32 remain, success; 751f20f8f21SLinus Walleij 752c8ebae37SRussell King /* Terminate the DMA transfer */ 753c8ebae37SRussell King if (dma_inprogress(host)) 754c8ebae37SRussell King mmci_dma_data_error(host); 755c8ebae37SRussell King 756c8afc9d5SRussell King /* 757c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 758c8afc9d5SRussell King * the data counter gives the number of bytes transferred 759c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 760c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 761c8afc9d5SRussell King * matters for FIFO overruns only. 762c8afc9d5SRussell King */ 763f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 7648cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 7658cb28155SLinus Walleij 766c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 767c8afc9d5SRussell King status, success); 7688cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 7698cb28155SLinus Walleij /* Last block was not successful */ 770c8afc9d5SRussell King success -= 1; 77117b0429dSPierre Ossman data->error = -EILSEQ; 7728cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 77317b0429dSPierre Ossman data->error = -ETIMEDOUT; 774757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 775757df746SLinus Walleij data->error = -ECOMM; 776c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 77717b0429dSPierre Ossman data->error = -EIO; 778c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 779c8afc9d5SRussell King if (success > host->variant->fifosize) 780c8afc9d5SRussell King success -= host->variant->fifosize; 781c8afc9d5SRussell King else 782c8afc9d5SRussell King success = 0; 7838cb28155SLinus Walleij data->error = -EIO; 7844ce1d6cbSRabin Vincent } 78551d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 7861c6a0718SPierre Ossman } 787f20f8f21SLinus Walleij 7888cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 7898cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 790f20f8f21SLinus Walleij 791ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 792c8ebae37SRussell King if (dma_inprogress(host)) 793c8ebae37SRussell King mmci_dma_unmap(host, data); 7941c6a0718SPierre Ossman mmci_stop_data(host); 7951c6a0718SPierre Ossman 7968cb28155SLinus Walleij if (!data->error) 7978cb28155SLinus Walleij /* The error clause is handled above, success! */ 79851d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 799f20f8f21SLinus Walleij 8001c6a0718SPierre Ossman if (!data->stop) { 8011c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 8021c6a0718SPierre Ossman } else { 8031c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 8041c6a0718SPierre Ossman } 8051c6a0718SPierre Ossman } 8061c6a0718SPierre Ossman } 8071c6a0718SPierre Ossman 8081c6a0718SPierre Ossman static void 8091c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 8101c6a0718SPierre Ossman unsigned int status) 8111c6a0718SPierre Ossman { 8121c6a0718SPierre Ossman void __iomem *base = host->base; 8131c6a0718SPierre Ossman 8141c6a0718SPierre Ossman host->cmd = NULL; 8151c6a0718SPierre Ossman 8161c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 81717b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 8181c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 81917b0429dSPierre Ossman cmd->error = -EILSEQ; 8209047b435SRussell King - ARM Linux } else { 8219047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 8229047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 8239047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 8249047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 8251c6a0718SPierre Ossman } 8261c6a0718SPierre Ossman 82717b0429dSPierre Ossman if (!cmd->data || cmd->error) { 8283b6e3c73SUlf Hansson if (host->data) { 8293b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 8303b6e3c73SUlf Hansson if (dma_inprogress(host)) 8313b6e3c73SUlf Hansson mmci_dma_data_error(host); 8321c6a0718SPierre Ossman mmci_stop_data(host); 8333b6e3c73SUlf Hansson } 8341c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 8351c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 8361c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 8371c6a0718SPierre Ossman } 8381c6a0718SPierre Ossman } 8391c6a0718SPierre Ossman 8401c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 8411c6a0718SPierre Ossman { 8421c6a0718SPierre Ossman void __iomem *base = host->base; 8431c6a0718SPierre Ossman char *ptr = buffer; 8441c6a0718SPierre Ossman u32 status; 84526eed9a5SLinus Walleij int host_remain = host->size; 8461c6a0718SPierre Ossman 8471c6a0718SPierre Ossman do { 84826eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 8491c6a0718SPierre Ossman 8501c6a0718SPierre Ossman if (count > remain) 8511c6a0718SPierre Ossman count = remain; 8521c6a0718SPierre Ossman 8531c6a0718SPierre Ossman if (count <= 0) 8541c6a0718SPierre Ossman break; 8551c6a0718SPierre Ossman 856393e5e24SUlf Hansson /* 857393e5e24SUlf Hansson * SDIO especially may want to send something that is 858393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 859393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 860393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 861393e5e24SUlf Hansson */ 862393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 863393e5e24SUlf Hansson if (count < 4) { 864393e5e24SUlf Hansson unsigned char buf[4]; 865393e5e24SUlf Hansson readsl(base + MMCIFIFO, buf, 1); 866393e5e24SUlf Hansson memcpy(ptr, buf, count); 867393e5e24SUlf Hansson } else { 8681c6a0718SPierre Ossman readsl(base + MMCIFIFO, ptr, count >> 2); 869393e5e24SUlf Hansson count &= ~0x3; 870393e5e24SUlf Hansson } 871393e5e24SUlf Hansson } else { 872393e5e24SUlf Hansson readsl(base + MMCIFIFO, ptr, count >> 2); 873393e5e24SUlf Hansson } 8741c6a0718SPierre Ossman 8751c6a0718SPierre Ossman ptr += count; 8761c6a0718SPierre Ossman remain -= count; 87726eed9a5SLinus Walleij host_remain -= count; 8781c6a0718SPierre Ossman 8791c6a0718SPierre Ossman if (remain == 0) 8801c6a0718SPierre Ossman break; 8811c6a0718SPierre Ossman 8821c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8831c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 8841c6a0718SPierre Ossman 8851c6a0718SPierre Ossman return ptr - buffer; 8861c6a0718SPierre Ossman } 8871c6a0718SPierre Ossman 8881c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 8891c6a0718SPierre Ossman { 8908301bb68SRabin Vincent struct variant_data *variant = host->variant; 8911c6a0718SPierre Ossman void __iomem *base = host->base; 8921c6a0718SPierre Ossman char *ptr = buffer; 8931c6a0718SPierre Ossman 8941c6a0718SPierre Ossman do { 8951c6a0718SPierre Ossman unsigned int count, maxcnt; 8961c6a0718SPierre Ossman 8978301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 8988301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 8991c6a0718SPierre Ossman count = min(remain, maxcnt); 9001c6a0718SPierre Ossman 90134177802SLinus Walleij /* 90234177802SLinus Walleij * SDIO especially may want to send something that is 90334177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 90434177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 90534177802SLinus Walleij * So compensate by adding +3 on the count, a single 90634177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 90734177802SLinus Walleij * 32bit writes etc. 90834177802SLinus Walleij */ 90934177802SLinus Walleij writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 9101c6a0718SPierre Ossman 9111c6a0718SPierre Ossman ptr += count; 9121c6a0718SPierre Ossman remain -= count; 9131c6a0718SPierre Ossman 9141c6a0718SPierre Ossman if (remain == 0) 9151c6a0718SPierre Ossman break; 9161c6a0718SPierre Ossman 9171c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9181c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 9191c6a0718SPierre Ossman 9201c6a0718SPierre Ossman return ptr - buffer; 9211c6a0718SPierre Ossman } 9221c6a0718SPierre Ossman 9231c6a0718SPierre Ossman /* 9241c6a0718SPierre Ossman * PIO data transfer IRQ handler. 9251c6a0718SPierre Ossman */ 9261c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 9271c6a0718SPierre Ossman { 9281c6a0718SPierre Ossman struct mmci_host *host = dev_id; 9294ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 9308301bb68SRabin Vincent struct variant_data *variant = host->variant; 9311c6a0718SPierre Ossman void __iomem *base = host->base; 9324ce1d6cbSRabin Vincent unsigned long flags; 9331c6a0718SPierre Ossman u32 status; 9341c6a0718SPierre Ossman 9351c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9361c6a0718SPierre Ossman 93764de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 9381c6a0718SPierre Ossman 9394ce1d6cbSRabin Vincent local_irq_save(flags); 9404ce1d6cbSRabin Vincent 9411c6a0718SPierre Ossman do { 9421c6a0718SPierre Ossman unsigned int remain, len; 9431c6a0718SPierre Ossman char *buffer; 9441c6a0718SPierre Ossman 9451c6a0718SPierre Ossman /* 9461c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 9471c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 9481c6a0718SPierre Ossman * definition it is more than half empty. 9491c6a0718SPierre Ossman * 9501c6a0718SPierre Ossman * For read, check for data available. 9511c6a0718SPierre Ossman */ 9521c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 9531c6a0718SPierre Ossman break; 9541c6a0718SPierre Ossman 9554ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 9564ce1d6cbSRabin Vincent break; 9574ce1d6cbSRabin Vincent 9584ce1d6cbSRabin Vincent buffer = sg_miter->addr; 9594ce1d6cbSRabin Vincent remain = sg_miter->length; 9601c6a0718SPierre Ossman 9611c6a0718SPierre Ossman len = 0; 9621c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 9631c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 9641c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 9651c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 9661c6a0718SPierre Ossman 9674ce1d6cbSRabin Vincent sg_miter->consumed = len; 9681c6a0718SPierre Ossman 9691c6a0718SPierre Ossman host->size -= len; 9701c6a0718SPierre Ossman remain -= len; 9711c6a0718SPierre Ossman 9721c6a0718SPierre Ossman if (remain) 9731c6a0718SPierre Ossman break; 9741c6a0718SPierre Ossman 9751c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9761c6a0718SPierre Ossman } while (1); 9771c6a0718SPierre Ossman 9784ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 9794ce1d6cbSRabin Vincent 9804ce1d6cbSRabin Vincent local_irq_restore(flags); 9814ce1d6cbSRabin Vincent 9821c6a0718SPierre Ossman /* 983c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 984c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 9851c6a0718SPierre Ossman */ 986c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 9872686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 9881c6a0718SPierre Ossman 9891c6a0718SPierre Ossman /* 9901c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 9911c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 9921c6a0718SPierre Ossman * the chip itself has disabled the data path, and 9931c6a0718SPierre Ossman * stops us racing with our data end IRQ. 9941c6a0718SPierre Ossman */ 9951c6a0718SPierre Ossman if (host->size == 0) { 9962686b4b4SLinus Walleij mmci_set_mask1(host, 0); 9971c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 9981c6a0718SPierre Ossman } 9991c6a0718SPierre Ossman 10001c6a0718SPierre Ossman return IRQ_HANDLED; 10011c6a0718SPierre Ossman } 10021c6a0718SPierre Ossman 10031c6a0718SPierre Ossman /* 10041c6a0718SPierre Ossman * Handle completion of command and data transfers. 10051c6a0718SPierre Ossman */ 10061c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 10071c6a0718SPierre Ossman { 10081c6a0718SPierre Ossman struct mmci_host *host = dev_id; 10091c6a0718SPierre Ossman u32 status; 10101c6a0718SPierre Ossman int ret = 0; 10111c6a0718SPierre Ossman 10121c6a0718SPierre Ossman spin_lock(&host->lock); 10131c6a0718SPierre Ossman 10141c6a0718SPierre Ossman do { 10151c6a0718SPierre Ossman struct mmc_command *cmd; 10161c6a0718SPierre Ossman struct mmc_data *data; 10171c6a0718SPierre Ossman 10181c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 10192686b4b4SLinus Walleij 10202686b4b4SLinus Walleij if (host->singleirq) { 10212686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 10222686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 10232686b4b4SLinus Walleij 10242686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 10252686b4b4SLinus Walleij } 10262686b4b4SLinus Walleij 10271c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 10281c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 10291c6a0718SPierre Ossman 103064de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 10311c6a0718SPierre Ossman 10321c6a0718SPierre Ossman data = host->data; 1033b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1034b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1035b63038d6SUlf Hansson MCI_DATABLOCKEND) && data) 10361c6a0718SPierre Ossman mmci_data_irq(host, data, status); 10371c6a0718SPierre Ossman 10381c6a0718SPierre Ossman cmd = host->cmd; 10391c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 10401c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 10411c6a0718SPierre Ossman 10421c6a0718SPierre Ossman ret = 1; 10431c6a0718SPierre Ossman } while (status); 10441c6a0718SPierre Ossman 10451c6a0718SPierre Ossman spin_unlock(&host->lock); 10461c6a0718SPierre Ossman 10471c6a0718SPierre Ossman return IRQ_RETVAL(ret); 10481c6a0718SPierre Ossman } 10491c6a0718SPierre Ossman 10501c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 10511c6a0718SPierre Ossman { 10521c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10539e943021SLinus Walleij unsigned long flags; 10541c6a0718SPierre Ossman 10551c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 10561c6a0718SPierre Ossman 1057019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 105864de0289SLinus Walleij dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 105964de0289SLinus Walleij mrq->data->blksz); 1060255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 1061255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1062255d01afSPierre Ossman return; 1063255d01afSPierre Ossman } 1064255d01afSPierre Ossman 10651c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 10661c3be369SRussell King 10679e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 10681c6a0718SPierre Ossman 10691c6a0718SPierre Ossman host->mrq = mrq; 10701c6a0718SPierre Ossman 107158c7ccbfSPer Forlin if (mrq->data) 107258c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 107358c7ccbfSPer Forlin 10741c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 10751c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 10761c6a0718SPierre Ossman 10771c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 10781c6a0718SPierre Ossman 10799e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 10801c6a0718SPierre Ossman } 10811c6a0718SPierre Ossman 10821c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 10831c6a0718SPierre Ossman { 10841c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10857d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1086a6a6464aSLinus Walleij u32 pwr = 0; 1087a6a6464aSLinus Walleij unsigned long flags; 108899fc5131SLinus Walleij int ret; 10891c6a0718SPierre Ossman 10902cd976c4SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 10912cd976c4SUlf Hansson 1092bc521818SUlf Hansson if (host->plat->ios_handler && 1093bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1094bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1095bc521818SUlf Hansson 10961c6a0718SPierre Ossman switch (ios->power_mode) { 10971c6a0718SPierre Ossman case MMC_POWER_OFF: 109899fc5131SLinus Walleij if (host->vcc) 109999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 11001c6a0718SPierre Ossman break; 11011c6a0718SPierre Ossman case MMC_POWER_UP: 110299fc5131SLinus Walleij if (host->vcc) { 110399fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 110499fc5131SLinus Walleij if (ret) { 110599fc5131SLinus Walleij dev_err(mmc_dev(mmc), "unable to set OCR\n"); 110699fc5131SLinus Walleij /* 110799fc5131SLinus Walleij * The .set_ios() function in the mmc_host_ops 110899fc5131SLinus Walleij * struct return void, and failing to set the 110999fc5131SLinus Walleij * power should be rare so we print an error 111099fc5131SLinus Walleij * and return here. 111199fc5131SLinus Walleij */ 11122cd976c4SUlf Hansson goto out; 111399fc5131SLinus Walleij } 111499fc5131SLinus Walleij } 11157d72a1d4SUlf Hansson /* 11167d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 11177d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 11187d72a1d4SUlf Hansson * configured in the variant data. 11197d72a1d4SUlf Hansson */ 11207d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 11217d72a1d4SUlf Hansson 11221c6a0718SPierre Ossman break; 11231c6a0718SPierre Ossman case MMC_POWER_ON: 11241c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 11251c6a0718SPierre Ossman break; 11261c6a0718SPierre Ossman } 11271c6a0718SPierre Ossman 11284d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 11294d1a3a0dSUlf Hansson /* 11304d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 11314d1a3a0dSUlf Hansson * indicating signal direction for the signals in 11324d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 11334d1a3a0dSUlf Hansson */ 11344d1a3a0dSUlf Hansson pwr |= host->plat->sigdir; 11354d1a3a0dSUlf Hansson 11364d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 11374d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 11384d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 11394d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 11404d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 11414d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 11424d1a3a0dSUlf Hansson } 11434d1a3a0dSUlf Hansson 1144cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1145f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 11461c6a0718SPierre Ossman pwr |= MCI_ROD; 1147cc30d60eSLinus Walleij else { 1148cc30d60eSLinus Walleij /* 1149cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1150cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1151cc30d60eSLinus Walleij */ 1152cc30d60eSLinus Walleij pwr |= MCI_OD; 1153cc30d60eSLinus Walleij } 1154cc30d60eSLinus Walleij } 11551c6a0718SPierre Ossman 1156a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1157a6a6464aSLinus Walleij 1158a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 11597437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1160a6a6464aSLinus Walleij 1161a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 11622cd976c4SUlf Hansson 11632cd976c4SUlf Hansson out: 11642cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 11652cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 11661c6a0718SPierre Ossman } 11671c6a0718SPierre Ossman 116889001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 116989001446SRussell King { 117089001446SRussell King struct mmci_host *host = mmc_priv(mmc); 117189001446SRussell King 117289001446SRussell King if (host->gpio_wp == -ENOSYS) 117389001446SRussell King return -ENOSYS; 117489001446SRussell King 117518a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 117689001446SRussell King } 117789001446SRussell King 117889001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 117989001446SRussell King { 118089001446SRussell King struct mmci_host *host = mmc_priv(mmc); 118129719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 118289001446SRussell King unsigned int status; 118389001446SRussell King 11844b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 11854b8caec0SRabin Vincent if (!plat->status) 11864b8caec0SRabin Vincent return 1; /* Assume always present */ 11874b8caec0SRabin Vincent 118829719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 11894b8caec0SRabin Vincent } else 119018a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 119118a06301SLinus Walleij ^ plat->cd_invert; 119289001446SRussell King 119374bc8093SRussell King /* 119474bc8093SRussell King * Use positive logic throughout - status is zero for no card, 119574bc8093SRussell King * non-zero for card inserted. 119674bc8093SRussell King */ 119774bc8093SRussell King return status; 119889001446SRussell King } 119989001446SRussell King 1200148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1201148b8b39SRabin Vincent { 1202148b8b39SRabin Vincent struct mmci_host *host = dev_id; 1203148b8b39SRabin Vincent 1204148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1205148b8b39SRabin Vincent 1206148b8b39SRabin Vincent return IRQ_HANDLED; 1207148b8b39SRabin Vincent } 1208148b8b39SRabin Vincent 12091c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 12101c6a0718SPierre Ossman .request = mmci_request, 121158c7ccbfSPer Forlin .pre_req = mmci_pre_request, 121258c7ccbfSPer Forlin .post_req = mmci_post_request, 12131c6a0718SPierre Ossman .set_ios = mmci_set_ios, 121489001446SRussell King .get_ro = mmci_get_ro, 121589001446SRussell King .get_cd = mmci_get_cd, 12161c6a0718SPierre Ossman }; 12171c6a0718SPierre Ossman 1218000bc9d5SLee Jones #ifdef CONFIG_OF 1219000bc9d5SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1220000bc9d5SLee Jones struct mmci_platform_data *pdata) 1221000bc9d5SLee Jones { 1222000bc9d5SLee Jones int bus_width = 0; 1223000bc9d5SLee Jones 12249a597016SLee Jones pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 12259a597016SLee Jones pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1226000bc9d5SLee Jones 1227000bc9d5SLee Jones if (of_get_property(np, "cd-inverted", NULL)) 1228000bc9d5SLee Jones pdata->cd_invert = true; 1229000bc9d5SLee Jones else 1230000bc9d5SLee Jones pdata->cd_invert = false; 1231000bc9d5SLee Jones 1232000bc9d5SLee Jones of_property_read_u32(np, "max-frequency", &pdata->f_max); 1233000bc9d5SLee Jones if (!pdata->f_max) 1234000bc9d5SLee Jones pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1235000bc9d5SLee Jones 1236000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1237000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1238000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1239000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1240000bc9d5SLee Jones 1241000bc9d5SLee Jones of_property_read_u32(np, "bus-width", &bus_width); 1242000bc9d5SLee Jones switch (bus_width) { 1243000bc9d5SLee Jones case 0 : 1244000bc9d5SLee Jones /* No bus-width supplied. */ 1245000bc9d5SLee Jones break; 1246000bc9d5SLee Jones case 4 : 1247000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1248000bc9d5SLee Jones break; 1249000bc9d5SLee Jones case 8 : 1250000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1251000bc9d5SLee Jones break; 1252000bc9d5SLee Jones default : 1253000bc9d5SLee Jones pr_warn("%s: Unsupported bus width\n", np->full_name); 1254000bc9d5SLee Jones } 1255000bc9d5SLee Jones } 1256c0a120a4SLee Jones #else 1257c0a120a4SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1258c0a120a4SLee Jones struct mmci_platform_data *pdata) 1259c0a120a4SLee Jones { 1260c0a120a4SLee Jones return; 1261c0a120a4SLee Jones } 1262000bc9d5SLee Jones #endif 1263000bc9d5SLee Jones 1264aa25afadSRussell King static int __devinit mmci_probe(struct amba_device *dev, 1265aa25afadSRussell King const struct amba_id *id) 12661c6a0718SPierre Ossman { 12676ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1268000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 12694956e109SRabin Vincent struct variant_data *variant = id->data; 12701c6a0718SPierre Ossman struct mmci_host *host; 12711c6a0718SPierre Ossman struct mmc_host *mmc; 12721c6a0718SPierre Ossman int ret; 12731c6a0718SPierre Ossman 1274000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1275000bc9d5SLee Jones if (!plat && !np) { 1276000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1277000bc9d5SLee Jones return -EINVAL; 12781c6a0718SPierre Ossman } 12791c6a0718SPierre Ossman 1280b9b52918SLee Jones if (!plat) { 1281b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1282b9b52918SLee Jones if (!plat) 1283b9b52918SLee Jones return -ENOMEM; 1284b9b52918SLee Jones } 1285b9b52918SLee Jones 1286000bc9d5SLee Jones if (np) 1287000bc9d5SLee Jones mmci_dt_populate_generic_pdata(np, plat); 1288000bc9d5SLee Jones 12891c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 12901c6a0718SPierre Ossman if (ret) 12911c6a0718SPierre Ossman goto out; 12921c6a0718SPierre Ossman 12931c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 12941c6a0718SPierre Ossman if (!mmc) { 12951c6a0718SPierre Ossman ret = -ENOMEM; 12961c6a0718SPierre Ossman goto rel_regions; 12971c6a0718SPierre Ossman } 12981c6a0718SPierre Ossman 12991c6a0718SPierre Ossman host = mmc_priv(mmc); 13004ea580f1SRabin Vincent host->mmc = mmc; 1301012b7d33SRussell King 130289001446SRussell King host->gpio_wp = -ENOSYS; 130389001446SRussell King host->gpio_cd = -ENOSYS; 1304148b8b39SRabin Vincent host->gpio_cd_irq = -1; 130589001446SRussell King 1306012b7d33SRussell King host->hw_designer = amba_manf(dev); 1307012b7d33SRussell King host->hw_revision = amba_rev(dev); 130864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 130964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1310012b7d33SRussell King 1311ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 13121c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 13131c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 13141c6a0718SPierre Ossman host->clk = NULL; 13151c6a0718SPierre Ossman goto host_free; 13161c6a0718SPierre Ossman } 13171c6a0718SPierre Ossman 1318ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 13191c6a0718SPierre Ossman if (ret) 13201c6a0718SPierre Ossman goto clk_free; 13211c6a0718SPierre Ossman 13221c6a0718SPierre Ossman host->plat = plat; 13234956e109SRabin Vincent host->variant = variant; 13241c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1325c8df9a53SLinus Walleij /* 1326c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1327c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1328c8df9a53SLinus Walleij * (if possible). 1329c8df9a53SLinus Walleij */ 1330c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1331c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1332c8df9a53SLinus Walleij if (ret < 0) 1333c8df9a53SLinus Walleij goto clk_disable; 1334c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 133564de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 133664de0289SLinus Walleij host->mclk); 1337c8df9a53SLinus Walleij } 1338c8ebae37SRussell King host->phybase = dev->res.start; 1339dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 13401c6a0718SPierre Ossman if (!host->base) { 13411c6a0718SPierre Ossman ret = -ENOMEM; 13421c6a0718SPierre Ossman goto clk_disable; 13431c6a0718SPierre Ossman } 13441c6a0718SPierre Ossman 13451c6a0718SPierre Ossman mmc->ops = &mmci_ops; 13467f294e49SLinus Walleij /* 13477f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 13487f294e49SLinus Walleij * clock divider equations which means that the minimum divider 13497f294e49SLinus Walleij * differs too. 13507f294e49SLinus Walleij */ 13517f294e49SLinus Walleij if (variant->st_clkdiv) 13527f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 13537f294e49SLinus Walleij else 13547f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1355808d97ccSLinus Walleij /* 1356808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1357808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1358808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1359808d97ccSLinus Walleij * default value in case it is not specified. Either 1360808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1361808d97ccSLinus Walleij * of course. 1362808d97ccSLinus Walleij */ 1363808d97ccSLinus Walleij if (plat->f_max) 1364808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1365808d97ccSLinus Walleij else 13661c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 136764de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 136864de0289SLinus Walleij 136934e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 137034e84f39SLinus Walleij /* If we're using the regulator framework, try to fetch a regulator */ 137134e84f39SLinus Walleij host->vcc = regulator_get(&dev->dev, "vmmc"); 137234e84f39SLinus Walleij if (IS_ERR(host->vcc)) 137334e84f39SLinus Walleij host->vcc = NULL; 137434e84f39SLinus Walleij else { 137534e84f39SLinus Walleij int mask = mmc_regulator_get_ocrmask(host->vcc); 137634e84f39SLinus Walleij 137734e84f39SLinus Walleij if (mask < 0) 137834e84f39SLinus Walleij dev_err(&dev->dev, "error getting OCR mask (%d)\n", 137934e84f39SLinus Walleij mask); 138034e84f39SLinus Walleij else { 138134e84f39SLinus Walleij host->mmc->ocr_avail = (u32) mask; 138234e84f39SLinus Walleij if (plat->ocr_mask) 138334e84f39SLinus Walleij dev_warn(&dev->dev, 138434e84f39SLinus Walleij "Provided ocr_mask/setpower will not be used " 138534e84f39SLinus Walleij "(using regulator instead)\n"); 138634e84f39SLinus Walleij } 138734e84f39SLinus Walleij } 138834e84f39SLinus Walleij #endif 138934e84f39SLinus Walleij /* Fall back to platform data if no regulator is found */ 139034e84f39SLinus Walleij if (host->vcc == NULL) 13911c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 13929e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 13935a092627SPer Forlin mmc->caps2 = plat->capabilities2; 13941c6a0718SPierre Ossman 13951c6a0718SPierre Ossman /* 13961c6a0718SPierre Ossman * We can do SGIO 13971c6a0718SPierre Ossman */ 1398a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 13991c6a0718SPierre Ossman 14001c6a0718SPierre Ossman /* 140108458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 140208458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 140308458ef6SRabin Vincent * single request. 14041c6a0718SPierre Ossman */ 140508458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 14061c6a0718SPierre Ossman 14071c6a0718SPierre Ossman /* 14081c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 14091c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 14101c6a0718SPierre Ossman */ 14111c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 14121c6a0718SPierre Ossman 14131c6a0718SPierre Ossman /* 14141c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 14151c6a0718SPierre Ossman */ 14168f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 14171c6a0718SPierre Ossman 14181c6a0718SPierre Ossman /* 14198f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 14208f7f6b7eSWill Deacon * the maximum request size. 14211c6a0718SPierre Ossman */ 14228f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 14231c6a0718SPierre Ossman 14241c6a0718SPierre Ossman spin_lock_init(&host->lock); 14251c6a0718SPierre Ossman 14261c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14271c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 14281c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 14291c6a0718SPierre Ossman 14302805b9abSRoland Stigge if (plat->gpio_cd == -EPROBE_DEFER) { 14312805b9abSRoland Stigge ret = -EPROBE_DEFER; 14322805b9abSRoland Stigge goto err_gpio_cd; 14332805b9abSRoland Stigge } 143489001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 143589001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 143689001446SRussell King if (ret == 0) 143789001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 143889001446SRussell King if (ret == 0) 143989001446SRussell King host->gpio_cd = plat->gpio_cd; 144089001446SRussell King else if (ret != -ENOSYS) 144189001446SRussell King goto err_gpio_cd; 1442148b8b39SRabin Vincent 144317ee083bSLinus Walleij /* 144417ee083bSLinus Walleij * A gpio pin that will detect cards when inserted and removed 144517ee083bSLinus Walleij * will most likely want to trigger on the edges if it is 144617ee083bSLinus Walleij * 0 when ejected and 1 when inserted (or mutatis mutandis 144717ee083bSLinus Walleij * for the inverted case) so we request triggers on both 144817ee083bSLinus Walleij * edges. 144917ee083bSLinus Walleij */ 1450148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 145117ee083bSLinus Walleij mmci_cd_irq, 145217ee083bSLinus Walleij IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1453148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1454148b8b39SRabin Vincent if (ret >= 0) 1455148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 145689001446SRussell King } 14572805b9abSRoland Stigge if (plat->gpio_wp == -EPROBE_DEFER) { 14582805b9abSRoland Stigge ret = -EPROBE_DEFER; 14592805b9abSRoland Stigge goto err_gpio_wp; 14602805b9abSRoland Stigge } 146189001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 146289001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 146389001446SRussell King if (ret == 0) 146489001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 146589001446SRussell King if (ret == 0) 146689001446SRussell King host->gpio_wp = plat->gpio_wp; 146789001446SRussell King else if (ret != -ENOSYS) 146889001446SRussell King goto err_gpio_wp; 146989001446SRussell King } 147089001446SRussell King 14714b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 14724b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1473148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1474148b8b39SRabin Vincent 14751c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 14761c6a0718SPierre Ossman if (ret) 14771c6a0718SPierre Ossman goto unmap; 14781c6a0718SPierre Ossman 1479dfb85185SRussell King if (!dev->irq[1]) 14802686b4b4SLinus Walleij host->singleirq = true; 14812686b4b4SLinus Walleij else { 14822686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 14832686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 14841c6a0718SPierre Ossman if (ret) 14851c6a0718SPierre Ossman goto irq0_free; 14862686b4b4SLinus Walleij } 14871c6a0718SPierre Ossman 14888cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 14891c6a0718SPierre Ossman 14901c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 14911c6a0718SPierre Ossman 1492c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1493c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1494c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1495c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1496c8ebae37SRussell King 1497c8ebae37SRussell King mmci_dma_setup(host); 14981c6a0718SPierre Ossman 14992cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 15002cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 15011c3be369SRussell King pm_runtime_put(&dev->dev); 15021c3be369SRussell King 15038c11a94dSRussell King mmc_add_host(mmc); 15048c11a94dSRussell King 15051c6a0718SPierre Ossman return 0; 15061c6a0718SPierre Ossman 15071c6a0718SPierre Ossman irq0_free: 15081c6a0718SPierre Ossman free_irq(dev->irq[0], host); 15091c6a0718SPierre Ossman unmap: 151089001446SRussell King if (host->gpio_wp != -ENOSYS) 151189001446SRussell King gpio_free(host->gpio_wp); 151289001446SRussell King err_gpio_wp: 1513148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1514148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 151589001446SRussell King if (host->gpio_cd != -ENOSYS) 151689001446SRussell King gpio_free(host->gpio_cd); 151789001446SRussell King err_gpio_cd: 15181c6a0718SPierre Ossman iounmap(host->base); 15191c6a0718SPierre Ossman clk_disable: 1520ac940938SJulia Lawall clk_disable_unprepare(host->clk); 15211c6a0718SPierre Ossman clk_free: 15221c6a0718SPierre Ossman clk_put(host->clk); 15231c6a0718SPierre Ossman host_free: 15241c6a0718SPierre Ossman mmc_free_host(mmc); 15251c6a0718SPierre Ossman rel_regions: 15261c6a0718SPierre Ossman amba_release_regions(dev); 15271c6a0718SPierre Ossman out: 15281c6a0718SPierre Ossman return ret; 15291c6a0718SPierre Ossman } 15301c6a0718SPierre Ossman 15316dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 15321c6a0718SPierre Ossman { 15331c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 15341c6a0718SPierre Ossman 15351c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 15361c6a0718SPierre Ossman 15371c6a0718SPierre Ossman if (mmc) { 15381c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15391c6a0718SPierre Ossman 15401c3be369SRussell King /* 15411c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 15421c3be369SRussell King * version here so that we can access the primecell. 15431c3be369SRussell King */ 15441c3be369SRussell King pm_runtime_get_sync(&dev->dev); 15451c3be369SRussell King 15461c6a0718SPierre Ossman mmc_remove_host(mmc); 15471c6a0718SPierre Ossman 15481c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 15491c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 15501c6a0718SPierre Ossman 15511c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 15521c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 15531c6a0718SPierre Ossman 1554c8ebae37SRussell King mmci_dma_release(host); 15551c6a0718SPierre Ossman free_irq(dev->irq[0], host); 15562686b4b4SLinus Walleij if (!host->singleirq) 15571c6a0718SPierre Ossman free_irq(dev->irq[1], host); 15581c6a0718SPierre Ossman 155989001446SRussell King if (host->gpio_wp != -ENOSYS) 156089001446SRussell King gpio_free(host->gpio_wp); 1561148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1562148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 156389001446SRussell King if (host->gpio_cd != -ENOSYS) 156489001446SRussell King gpio_free(host->gpio_cd); 156589001446SRussell King 15661c6a0718SPierre Ossman iounmap(host->base); 1567ac940938SJulia Lawall clk_disable_unprepare(host->clk); 15681c6a0718SPierre Ossman clk_put(host->clk); 15691c6a0718SPierre Ossman 157099fc5131SLinus Walleij if (host->vcc) 157199fc5131SLinus Walleij mmc_regulator_set_ocr(mmc, host->vcc, 0); 157234e84f39SLinus Walleij regulator_put(host->vcc); 157334e84f39SLinus Walleij 15741c6a0718SPierre Ossman mmc_free_host(mmc); 15751c6a0718SPierre Ossman 15761c6a0718SPierre Ossman amba_release_regions(dev); 15771c6a0718SPierre Ossman } 15781c6a0718SPierre Ossman 15791c6a0718SPierre Ossman return 0; 15801c6a0718SPierre Ossman } 15811c6a0718SPierre Ossman 158248fa7003SUlf Hansson #ifdef CONFIG_SUSPEND 158348fa7003SUlf Hansson static int mmci_suspend(struct device *dev) 15841c6a0718SPierre Ossman { 158548fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 158648fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 15871c6a0718SPierre Ossman int ret = 0; 15881c6a0718SPierre Ossman 15891c6a0718SPierre Ossman if (mmc) { 15901c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15911c6a0718SPierre Ossman 15921a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 15932cd976c4SUlf Hansson if (ret == 0) { 15942cd976c4SUlf Hansson pm_runtime_get_sync(dev); 15951c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 15961c6a0718SPierre Ossman } 15972cd976c4SUlf Hansson } 15981c6a0718SPierre Ossman 15991c6a0718SPierre Ossman return ret; 16001c6a0718SPierre Ossman } 16011c6a0718SPierre Ossman 160248fa7003SUlf Hansson static int mmci_resume(struct device *dev) 16031c6a0718SPierre Ossman { 160448fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 160548fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 16061c6a0718SPierre Ossman int ret = 0; 16071c6a0718SPierre Ossman 16081c6a0718SPierre Ossman if (mmc) { 16091c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 16101c6a0718SPierre Ossman 16111c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 16122cd976c4SUlf Hansson pm_runtime_put(dev); 16131c6a0718SPierre Ossman 16141c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 16151c6a0718SPierre Ossman } 16161c6a0718SPierre Ossman 16171c6a0718SPierre Ossman return ret; 16181c6a0718SPierre Ossman } 16191c6a0718SPierre Ossman #endif 16201c6a0718SPierre Ossman 162148fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 162248fa7003SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 162348fa7003SUlf Hansson }; 162448fa7003SUlf Hansson 16251c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 16261c6a0718SPierre Ossman { 16271c6a0718SPierre Ossman .id = 0x00041180, 1628768fbc18SPawel Moll .mask = 0xff0fffff, 16294956e109SRabin Vincent .data = &variant_arm, 16301c6a0718SPierre Ossman }, 16311c6a0718SPierre Ossman { 1632768fbc18SPawel Moll .id = 0x01041180, 1633768fbc18SPawel Moll .mask = 0xff0fffff, 1634768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1635768fbc18SPawel Moll }, 1636768fbc18SPawel Moll { 16371c6a0718SPierre Ossman .id = 0x00041181, 16381c6a0718SPierre Ossman .mask = 0x000fffff, 16394956e109SRabin Vincent .data = &variant_arm, 16401c6a0718SPierre Ossman }, 1641cc30d60eSLinus Walleij /* ST Micro variants */ 1642cc30d60eSLinus Walleij { 1643cc30d60eSLinus Walleij .id = 0x00180180, 1644cc30d60eSLinus Walleij .mask = 0x00ffffff, 16454956e109SRabin Vincent .data = &variant_u300, 1646cc30d60eSLinus Walleij }, 1647cc30d60eSLinus Walleij { 164834fd4213SLinus Walleij .id = 0x10180180, 164934fd4213SLinus Walleij .mask = 0xf0ffffff, 165034fd4213SLinus Walleij .data = &variant_nomadik, 165134fd4213SLinus Walleij }, 165234fd4213SLinus Walleij { 1653cc30d60eSLinus Walleij .id = 0x00280180, 1654cc30d60eSLinus Walleij .mask = 0x00ffffff, 16554956e109SRabin Vincent .data = &variant_u300, 16564956e109SRabin Vincent }, 16574956e109SRabin Vincent { 16584956e109SRabin Vincent .id = 0x00480180, 16591784b157SPhilippe Langlais .mask = 0xf0ffffff, 16604956e109SRabin Vincent .data = &variant_ux500, 1661cc30d60eSLinus Walleij }, 16621784b157SPhilippe Langlais { 16631784b157SPhilippe Langlais .id = 0x10480180, 16641784b157SPhilippe Langlais .mask = 0xf0ffffff, 16651784b157SPhilippe Langlais .data = &variant_ux500v2, 16661784b157SPhilippe Langlais }, 16671c6a0718SPierre Ossman { 0, 0 }, 16681c6a0718SPierre Ossman }; 16691c6a0718SPierre Ossman 16709f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 16719f99835fSDave Martin 16721c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 16731c6a0718SPierre Ossman .drv = { 16741c6a0718SPierre Ossman .name = DRIVER_NAME, 167548fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 16761c6a0718SPierre Ossman }, 16771c6a0718SPierre Ossman .probe = mmci_probe, 16786dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 16791c6a0718SPierre Ossman .id_table = mmci_ids, 16801c6a0718SPierre Ossman }; 16811c6a0718SPierre Ossman 16829e5ed094Sviresh kumar module_amba_driver(mmci_driver); 16831c6a0718SPierre Ossman 16841c6a0718SPierre Ossman module_param(fmax, uint, 0444); 16851c6a0718SPierre Ossman 16861c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 16871c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1688