11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 16ef289982SUlf Hansson #include <linux/io.h> 171c6a0718SPierre Ossman #include <linux/interrupt.h> 18613b152cSRussell King #include <linux/kernel.h> 19000bc9d5SLee Jones #include <linux/slab.h> 201c6a0718SPierre Ossman #include <linux/delay.h> 211c6a0718SPierre Ossman #include <linux/err.h> 221c6a0718SPierre Ossman #include <linux/highmem.h> 23019a5f56SNicolas Pitre #include <linux/log2.h> 2470be208fSUlf Hansson #include <linux/mmc/pm.h> 251c6a0718SPierre Ossman #include <linux/mmc/host.h> 2634177802SLinus Walleij #include <linux/mmc/card.h> 27d2762090SUlf Hansson #include <linux/mmc/slot-gpio.h> 281c6a0718SPierre Ossman #include <linux/amba/bus.h> 291c6a0718SPierre Ossman #include <linux/clk.h> 30bd6dee6fSJens Axboe #include <linux/scatterlist.h> 3189001446SRussell King #include <linux/gpio.h> 329a597016SLee Jones #include <linux/of_gpio.h> 3334e84f39SLinus Walleij #include <linux/regulator/consumer.h> 34c8ebae37SRussell King #include <linux/dmaengine.h> 35c8ebae37SRussell King #include <linux/dma-mapping.h> 36c8ebae37SRussell King #include <linux/amba/mmci.h> 371c3be369SRussell King #include <linux/pm_runtime.h> 38258aea76SViresh Kumar #include <linux/types.h> 39a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 401c6a0718SPierre Ossman 411c6a0718SPierre Ossman #include <asm/div64.h> 421c6a0718SPierre Ossman #include <asm/io.h> 431c6a0718SPierre Ossman #include <asm/sizes.h> 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman #include "mmci.h" 469cb15142SSrinivas Kandagatla #include "mmci_qcom_dml.h" 471c6a0718SPierre Ossman 481c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman static unsigned int fmax = 515633; 511c6a0718SPierre Ossman 524956e109SRabin Vincent /** 534956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 544956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 554380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 56e1412d85SSrinivas Kandagatla * @clkreg_8bit_bus_enable: enable value for 8 bit bus 57e8740644SSrinivas Kandagatla * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 5808458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 598301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 608301bb68SRabin Vincent * is asserted (likewise for RX) 618301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 628301bb68SRabin Vincent * is asserted (likewise for RX) 63ae7b0061SSrinivas Kandagatla * @data_cmd_enable: enable value for data commands. 64c7354133SSrinivas Kandagatla * @st_sdio: enable ST specific SDIO logic 65b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 66e17dca2bSSrinivas Kandagatla * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 671784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 68ff783233SSrinivas Kandagatla * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 69ff783233SSrinivas Kandagatla * register 705df014dfSSrinivas Kandagatla * @datactrl_mask_sdio: SDIO enable mask in datactrl register 717d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 72dc6500bfSSrinivas Kandagatla * @f_max: maximum clk frequency supported by the controller. 734d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 74f4670daeSUlf Hansson * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 7501259620SUlf Hansson * @busy_detect: true if busy detection on dat0 is supported 761ff44433SUlf Hansson * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 773f4e6f7bSSrinivas Kandagatla * @explicit_mclk_control: enable explicit mclk control in driver. 789c34b73dSSrinivas Kandagatla * @qcom_fifo: enables qcom specific fifo pio read logic. 799cb15142SSrinivas Kandagatla * @qcom_dml: enables qcom specific dma glue for dma transfers. 807878289bSUlf Hansson * @reversed_irq_handling: handle data irq before cmd irq. 814956e109SRabin Vincent */ 824956e109SRabin Vincent struct variant_data { 834956e109SRabin Vincent unsigned int clkreg; 844380c14fSRabin Vincent unsigned int clkreg_enable; 85e1412d85SSrinivas Kandagatla unsigned int clkreg_8bit_bus_enable; 86e8740644SSrinivas Kandagatla unsigned int clkreg_neg_edge_enable; 8708458ef6SRabin Vincent unsigned int datalength_bits; 888301bb68SRabin Vincent unsigned int fifosize; 898301bb68SRabin Vincent unsigned int fifohalfsize; 90ae7b0061SSrinivas Kandagatla unsigned int data_cmd_enable; 91e17dca2bSSrinivas Kandagatla unsigned int datactrl_mask_ddrmode; 925df014dfSSrinivas Kandagatla unsigned int datactrl_mask_sdio; 93c7354133SSrinivas Kandagatla bool st_sdio; 94b70a67f9SLinus Walleij bool st_clkdiv; 951784b157SPhilippe Langlais bool blksz_datactrl16; 96ff783233SSrinivas Kandagatla bool blksz_datactrl4; 977d72a1d4SUlf Hansson u32 pwrreg_powerup; 98dc6500bfSSrinivas Kandagatla u32 f_max; 994d1a3a0dSUlf Hansson bool signal_direction; 100f4670daeSUlf Hansson bool pwrreg_clkgate; 10101259620SUlf Hansson bool busy_detect; 1021ff44433SUlf Hansson bool pwrreg_nopower; 1033f4e6f7bSSrinivas Kandagatla bool explicit_mclk_control; 1049c34b73dSSrinivas Kandagatla bool qcom_fifo; 1059cb15142SSrinivas Kandagatla bool qcom_dml; 1067878289bSUlf Hansson bool reversed_irq_handling; 1074956e109SRabin Vincent }; 1084956e109SRabin Vincent 1094956e109SRabin Vincent static struct variant_data variant_arm = { 1108301bb68SRabin Vincent .fifosize = 16 * 4, 1118301bb68SRabin Vincent .fifohalfsize = 8 * 4, 11208458ef6SRabin Vincent .datalength_bits = 16, 1137d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 114dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1157878289bSUlf Hansson .reversed_irq_handling = true, 1164956e109SRabin Vincent }; 1174956e109SRabin Vincent 118768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 119768fbc18SPawel Moll .fifosize = 128 * 4, 120768fbc18SPawel Moll .fifohalfsize = 64 * 4, 121768fbc18SPawel Moll .datalength_bits = 16, 1227d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 123dc6500bfSSrinivas Kandagatla .f_max = 100000000, 124768fbc18SPawel Moll }; 125768fbc18SPawel Moll 1263a37298aSPawel Moll static struct variant_data variant_arm_extended_fifo_hwfc = { 1273a37298aSPawel Moll .fifosize = 128 * 4, 1283a37298aSPawel Moll .fifohalfsize = 64 * 4, 1293a37298aSPawel Moll .clkreg_enable = MCI_ARM_HWFCEN, 1303a37298aSPawel Moll .datalength_bits = 16, 1313a37298aSPawel Moll .pwrreg_powerup = MCI_PWR_UP, 132dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1333a37298aSPawel Moll }; 1343a37298aSPawel Moll 1354956e109SRabin Vincent static struct variant_data variant_u300 = { 1368301bb68SRabin Vincent .fifosize = 16 * 4, 1378301bb68SRabin Vincent .fifohalfsize = 8 * 4, 13849ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 139e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 14008458ef6SRabin Vincent .datalength_bits = 16, 1415df014dfSSrinivas Kandagatla .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 142c7354133SSrinivas Kandagatla .st_sdio = true, 1437d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 144dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1454d1a3a0dSUlf Hansson .signal_direction = true, 146f4670daeSUlf Hansson .pwrreg_clkgate = true, 1471ff44433SUlf Hansson .pwrreg_nopower = true, 1484956e109SRabin Vincent }; 1494956e109SRabin Vincent 15034fd4213SLinus Walleij static struct variant_data variant_nomadik = { 15134fd4213SLinus Walleij .fifosize = 16 * 4, 15234fd4213SLinus Walleij .fifohalfsize = 8 * 4, 15334fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 15434fd4213SLinus Walleij .datalength_bits = 24, 1555df014dfSSrinivas Kandagatla .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 156c7354133SSrinivas Kandagatla .st_sdio = true, 15734fd4213SLinus Walleij .st_clkdiv = true, 15834fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 159dc6500bfSSrinivas Kandagatla .f_max = 100000000, 16034fd4213SLinus Walleij .signal_direction = true, 161f4670daeSUlf Hansson .pwrreg_clkgate = true, 1621ff44433SUlf Hansson .pwrreg_nopower = true, 16334fd4213SLinus Walleij }; 16434fd4213SLinus Walleij 1654956e109SRabin Vincent static struct variant_data variant_ux500 = { 1668301bb68SRabin Vincent .fifosize = 30 * 4, 1678301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1684956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 16949ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 170e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 171e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 17208458ef6SRabin Vincent .datalength_bits = 24, 1735df014dfSSrinivas Kandagatla .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 174c7354133SSrinivas Kandagatla .st_sdio = true, 175b70a67f9SLinus Walleij .st_clkdiv = true, 1767d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 177dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1784d1a3a0dSUlf Hansson .signal_direction = true, 179f4670daeSUlf Hansson .pwrreg_clkgate = true, 18001259620SUlf Hansson .busy_detect = true, 1811ff44433SUlf Hansson .pwrreg_nopower = true, 1824956e109SRabin Vincent }; 183b70a67f9SLinus Walleij 1841784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1851784b157SPhilippe Langlais .fifosize = 30 * 4, 1861784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1871784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1881784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 189e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 190e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 191e17dca2bSSrinivas Kandagatla .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, 1921784b157SPhilippe Langlais .datalength_bits = 24, 1935df014dfSSrinivas Kandagatla .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 194c7354133SSrinivas Kandagatla .st_sdio = true, 1951784b157SPhilippe Langlais .st_clkdiv = true, 1961784b157SPhilippe Langlais .blksz_datactrl16 = true, 1977d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 198dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1994d1a3a0dSUlf Hansson .signal_direction = true, 200f4670daeSUlf Hansson .pwrreg_clkgate = true, 20101259620SUlf Hansson .busy_detect = true, 2021ff44433SUlf Hansson .pwrreg_nopower = true, 2031784b157SPhilippe Langlais }; 2041784b157SPhilippe Langlais 20555b604aeSSrinivas Kandagatla static struct variant_data variant_qcom = { 20655b604aeSSrinivas Kandagatla .fifosize = 16 * 4, 20755b604aeSSrinivas Kandagatla .fifohalfsize = 8 * 4, 20855b604aeSSrinivas Kandagatla .clkreg = MCI_CLK_ENABLE, 20955b604aeSSrinivas Kandagatla .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 21055b604aeSSrinivas Kandagatla MCI_QCOM_CLK_SELECT_IN_FBCLK, 21155b604aeSSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 21255b604aeSSrinivas Kandagatla .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 21355b604aeSSrinivas Kandagatla .data_cmd_enable = MCI_QCOM_CSPM_DATCMD, 21455b604aeSSrinivas Kandagatla .blksz_datactrl4 = true, 21555b604aeSSrinivas Kandagatla .datalength_bits = 24, 21655b604aeSSrinivas Kandagatla .pwrreg_powerup = MCI_PWR_UP, 21755b604aeSSrinivas Kandagatla .f_max = 208000000, 21855b604aeSSrinivas Kandagatla .explicit_mclk_control = true, 21955b604aeSSrinivas Kandagatla .qcom_fifo = true, 2209cb15142SSrinivas Kandagatla .qcom_dml = true, 22155b604aeSSrinivas Kandagatla }; 22255b604aeSSrinivas Kandagatla 22301259620SUlf Hansson static int mmci_card_busy(struct mmc_host *mmc) 22401259620SUlf Hansson { 22501259620SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 22601259620SUlf Hansson unsigned long flags; 22701259620SUlf Hansson int busy = 0; 22801259620SUlf Hansson 22901259620SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 23001259620SUlf Hansson 23101259620SUlf Hansson spin_lock_irqsave(&host->lock, flags); 23201259620SUlf Hansson if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 23301259620SUlf Hansson busy = 1; 23401259620SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 23501259620SUlf Hansson 23601259620SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 23701259620SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 23801259620SUlf Hansson 23901259620SUlf Hansson return busy; 24001259620SUlf Hansson } 24101259620SUlf Hansson 242a6a6464aSLinus Walleij /* 243653a761eSUlf Hansson * Validate mmc prerequisites 244653a761eSUlf Hansson */ 245653a761eSUlf Hansson static int mmci_validate_data(struct mmci_host *host, 246653a761eSUlf Hansson struct mmc_data *data) 247653a761eSUlf Hansson { 248653a761eSUlf Hansson if (!data) 249653a761eSUlf Hansson return 0; 250653a761eSUlf Hansson 251653a761eSUlf Hansson if (!is_power_of_2(data->blksz)) { 252653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), 253653a761eSUlf Hansson "unsupported block size (%d bytes)\n", data->blksz); 254653a761eSUlf Hansson return -EINVAL; 255653a761eSUlf Hansson } 256653a761eSUlf Hansson 257653a761eSUlf Hansson return 0; 258653a761eSUlf Hansson } 259653a761eSUlf Hansson 260f829c042SUlf Hansson static void mmci_reg_delay(struct mmci_host *host) 261f829c042SUlf Hansson { 262f829c042SUlf Hansson /* 263f829c042SUlf Hansson * According to the spec, at least three feedback clock cycles 264f829c042SUlf Hansson * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 265f829c042SUlf Hansson * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 266f829c042SUlf Hansson * Worst delay time during card init is at 100 kHz => 30 us. 267f829c042SUlf Hansson * Worst delay time when up and running is at 25 MHz => 120 ns. 268f829c042SUlf Hansson */ 269f829c042SUlf Hansson if (host->cclk < 25000000) 270f829c042SUlf Hansson udelay(30); 271f829c042SUlf Hansson else 272f829c042SUlf Hansson ndelay(120); 273f829c042SUlf Hansson } 274f829c042SUlf Hansson 275653a761eSUlf Hansson /* 276a6a6464aSLinus Walleij * This must be called with host->lock held 277a6a6464aSLinus Walleij */ 2787437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 2797437cfa5SUlf Hansson { 2807437cfa5SUlf Hansson if (host->clk_reg != clk) { 2817437cfa5SUlf Hansson host->clk_reg = clk; 2827437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 2837437cfa5SUlf Hansson } 2847437cfa5SUlf Hansson } 2857437cfa5SUlf Hansson 2867437cfa5SUlf Hansson /* 2877437cfa5SUlf Hansson * This must be called with host->lock held 2887437cfa5SUlf Hansson */ 2897437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 2907437cfa5SUlf Hansson { 2917437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 2927437cfa5SUlf Hansson host->pwr_reg = pwr; 2937437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 2947437cfa5SUlf Hansson } 2957437cfa5SUlf Hansson } 2967437cfa5SUlf Hansson 2977437cfa5SUlf Hansson /* 2987437cfa5SUlf Hansson * This must be called with host->lock held 2997437cfa5SUlf Hansson */ 3009cc639a2SUlf Hansson static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 3019cc639a2SUlf Hansson { 30201259620SUlf Hansson /* Keep ST Micro busy mode if enabled */ 30301259620SUlf Hansson datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 30401259620SUlf Hansson 3059cc639a2SUlf Hansson if (host->datactrl_reg != datactrl) { 3069cc639a2SUlf Hansson host->datactrl_reg = datactrl; 3079cc639a2SUlf Hansson writel(datactrl, host->base + MMCIDATACTRL); 3089cc639a2SUlf Hansson } 3099cc639a2SUlf Hansson } 3109cc639a2SUlf Hansson 3119cc639a2SUlf Hansson /* 3129cc639a2SUlf Hansson * This must be called with host->lock held 3139cc639a2SUlf Hansson */ 314a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 315a6a6464aSLinus Walleij { 3164956e109SRabin Vincent struct variant_data *variant = host->variant; 3174956e109SRabin Vincent u32 clk = variant->clkreg; 318a6a6464aSLinus Walleij 319c58a8509SUlf Hansson /* Make sure cclk reflects the current calculated clock */ 320c58a8509SUlf Hansson host->cclk = 0; 321c58a8509SUlf Hansson 322a6a6464aSLinus Walleij if (desired) { 3233f4e6f7bSSrinivas Kandagatla if (variant->explicit_mclk_control) { 3243f4e6f7bSSrinivas Kandagatla host->cclk = host->mclk; 3253f4e6f7bSSrinivas Kandagatla } else if (desired >= host->mclk) { 326a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 327399bc486SLinus Walleij if (variant->st_clkdiv) 328399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 329a6a6464aSLinus Walleij host->cclk = host->mclk; 330b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 331b70a67f9SLinus Walleij /* 332b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 333b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 334b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 335b70a67f9SLinus Walleij * frequency 336b70a67f9SLinus Walleij */ 337b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 338b70a67f9SLinus Walleij if (clk >= 256) 339b70a67f9SLinus Walleij clk = 255; 340b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 341a6a6464aSLinus Walleij } else { 342b70a67f9SLinus Walleij /* 343b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 344b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 345b70a67f9SLinus Walleij */ 346a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 347a6a6464aSLinus Walleij if (clk >= 256) 348a6a6464aSLinus Walleij clk = 255; 349a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 350a6a6464aSLinus Walleij } 3514380c14fSRabin Vincent 3524380c14fSRabin Vincent clk |= variant->clkreg_enable; 353a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 354a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 355a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 356a6a6464aSLinus Walleij } 357a6a6464aSLinus Walleij 358c58a8509SUlf Hansson /* Set actual clock for debug */ 359c58a8509SUlf Hansson host->mmc->actual_clock = host->cclk; 360c58a8509SUlf Hansson 3619e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 362771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 363771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 364e1412d85SSrinivas Kandagatla clk |= variant->clkreg_8bit_bus_enable; 3659e6c82cdSLinus Walleij 3666dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 3676dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 368e8740644SSrinivas Kandagatla clk |= variant->clkreg_neg_edge_enable; 3696dbb6ee0SUlf Hansson 3707437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 371a6a6464aSLinus Walleij } 372a6a6464aSLinus Walleij 3731c6a0718SPierre Ossman static void 3741c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 3751c6a0718SPierre Ossman { 3761c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 3771c6a0718SPierre Ossman 3781c6a0718SPierre Ossman BUG_ON(host->data); 3791c6a0718SPierre Ossman 3801c6a0718SPierre Ossman host->mrq = NULL; 3811c6a0718SPierre Ossman host->cmd = NULL; 3821c6a0718SPierre Ossman 3831c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 3842cd976c4SUlf Hansson 3852cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 3862cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 3871c6a0718SPierre Ossman } 3881c6a0718SPierre Ossman 3892686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 3902686b4b4SLinus Walleij { 3912686b4b4SLinus Walleij void __iomem *base = host->base; 3922686b4b4SLinus Walleij 3932686b4b4SLinus Walleij if (host->singleirq) { 3942686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 3952686b4b4SLinus Walleij 3962686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 3972686b4b4SLinus Walleij mask0 |= mask; 3982686b4b4SLinus Walleij 3992686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 4002686b4b4SLinus Walleij } 4012686b4b4SLinus Walleij 4022686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 4032686b4b4SLinus Walleij } 4042686b4b4SLinus Walleij 4051c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 4061c6a0718SPierre Ossman { 4079cc639a2SUlf Hansson mmci_write_datactrlreg(host, 0); 4082686b4b4SLinus Walleij mmci_set_mask1(host, 0); 4091c6a0718SPierre Ossman host->data = NULL; 4101c6a0718SPierre Ossman } 4111c6a0718SPierre Ossman 4124ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 4134ce1d6cbSRabin Vincent { 4144ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 4154ce1d6cbSRabin Vincent 4164ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 4174ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 4184ce1d6cbSRabin Vincent else 4194ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 4204ce1d6cbSRabin Vincent 4214ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 4224ce1d6cbSRabin Vincent } 4234ce1d6cbSRabin Vincent 424c8ebae37SRussell King /* 425c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 426c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 427c8ebae37SRussell King * no custom DMA interfaces are supported. 428c8ebae37SRussell King */ 429c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 430c3be1efdSBill Pemberton static void mmci_dma_setup(struct mmci_host *host) 431c8ebae37SRussell King { 432c8ebae37SRussell King const char *rxname, *txname; 433c8ebae37SRussell King dma_cap_mask_t mask; 4349cb15142SSrinivas Kandagatla struct variant_data *variant = host->variant; 435c8ebae37SRussell King 4361fd83f0eSLee Jones host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 4371fd83f0eSLee Jones host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 438c8ebae37SRussell King 43958c7ccbfSPer Forlin /* initialize pre request cookie */ 44058c7ccbfSPer Forlin host->next_data.cookie = 1; 44158c7ccbfSPer Forlin 442c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 443c8ebae37SRussell King dma_cap_zero(mask); 444c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 445c8ebae37SRussell King 4461fd83f0eSLee Jones /* 4471fd83f0eSLee Jones * If only an RX channel is specified, the driver will 4481fd83f0eSLee Jones * attempt to use it bidirectionally, however if it is 4491fd83f0eSLee Jones * is specified but cannot be located, DMA will be disabled. 4501fd83f0eSLee Jones */ 4511fd83f0eSLee Jones if (host->dma_rx_channel && !host->dma_tx_channel) 4521fd83f0eSLee Jones host->dma_tx_channel = host->dma_rx_channel; 453c8ebae37SRussell King 454c8ebae37SRussell King if (host->dma_rx_channel) 455c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 456c8ebae37SRussell King else 457c8ebae37SRussell King rxname = "none"; 458c8ebae37SRussell King 459c8ebae37SRussell King if (host->dma_tx_channel) 460c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 461c8ebae37SRussell King else 462c8ebae37SRussell King txname = "none"; 463c8ebae37SRussell King 464c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 465c8ebae37SRussell King rxname, txname); 466c8ebae37SRussell King 467c8ebae37SRussell King /* 468c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 469c8ebae37SRussell King * the parameters of the DMA engine device. 470c8ebae37SRussell King */ 471c8ebae37SRussell King if (host->dma_tx_channel) { 472c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 473c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 474c8ebae37SRussell King 475c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 476c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 477c8ebae37SRussell King } 478c8ebae37SRussell King if (host->dma_rx_channel) { 479c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 480c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 481c8ebae37SRussell King 482c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 483c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 484c8ebae37SRussell King } 4859cb15142SSrinivas Kandagatla 4869cb15142SSrinivas Kandagatla if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) 4879cb15142SSrinivas Kandagatla if (dml_hw_init(host, host->mmc->parent->of_node)) 4889cb15142SSrinivas Kandagatla variant->qcom_dml = false; 489c8ebae37SRussell King } 490c8ebae37SRussell King 491c8ebae37SRussell King /* 4926e0ee714SBill Pemberton * This is used in or so inline it 493c8ebae37SRussell King * so it can be discarded. 494c8ebae37SRussell King */ 495c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 496c8ebae37SRussell King { 497c8ebae37SRussell King if (host->dma_rx_channel) 498c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 4998c3a05b4SUlf Hansson if (host->dma_tx_channel) 500c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 501c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 502c8ebae37SRussell King } 503c8ebae37SRussell King 504653a761eSUlf Hansson static void mmci_dma_data_error(struct mmci_host *host) 505653a761eSUlf Hansson { 506653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 507653a761eSUlf Hansson dmaengine_terminate_all(host->dma_current); 508653a761eSUlf Hansson host->dma_current = NULL; 509653a761eSUlf Hansson host->dma_desc_current = NULL; 510653a761eSUlf Hansson host->data->host_cookie = 0; 511653a761eSUlf Hansson } 512653a761eSUlf Hansson 513c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 514c8ebae37SRussell King { 515653a761eSUlf Hansson struct dma_chan *chan; 516c8ebae37SRussell King enum dma_data_direction dir; 517653a761eSUlf Hansson 518653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) { 519653a761eSUlf Hansson dir = DMA_FROM_DEVICE; 520653a761eSUlf Hansson chan = host->dma_rx_channel; 521653a761eSUlf Hansson } else { 522653a761eSUlf Hansson dir = DMA_TO_DEVICE; 523653a761eSUlf Hansson chan = host->dma_tx_channel; 524653a761eSUlf Hansson } 525653a761eSUlf Hansson 526653a761eSUlf Hansson dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 527653a761eSUlf Hansson } 528653a761eSUlf Hansson 529653a761eSUlf Hansson static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 530653a761eSUlf Hansson { 531c8ebae37SRussell King u32 status; 532c8ebae37SRussell King int i; 533c8ebae37SRussell King 534c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 535c8ebae37SRussell King for (i = 0; ; i++) { 536c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 537c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 538c8ebae37SRussell King break; 539c8ebae37SRussell King udelay(10); 540c8ebae37SRussell King } 541c8ebae37SRussell King 542c8ebae37SRussell King /* 543c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 544c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 545c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 546c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 547c8ebae37SRussell King */ 548c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 549653a761eSUlf Hansson mmci_dma_data_error(host); 550c8ebae37SRussell King if (!data->error) 551c8ebae37SRussell King data->error = -EIO; 552c8ebae37SRussell King } 553c8ebae37SRussell King 55458c7ccbfSPer Forlin if (!data->host_cookie) 555653a761eSUlf Hansson mmci_dma_unmap(host, data); 556c8ebae37SRussell King 557c8ebae37SRussell King /* 558c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 559c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 560c8ebae37SRussell King */ 561c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 562c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 563c8ebae37SRussell King mmci_dma_release(host); 564c8ebae37SRussell King } 565653a761eSUlf Hansson 566653a761eSUlf Hansson host->dma_current = NULL; 567653a761eSUlf Hansson host->dma_desc_current = NULL; 568c8ebae37SRussell King } 569c8ebae37SRussell King 570653a761eSUlf Hansson /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 571653a761eSUlf Hansson static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 572653a761eSUlf Hansson struct dma_chan **dma_chan, 573653a761eSUlf Hansson struct dma_async_tx_descriptor **dma_desc) 574c8ebae37SRussell King { 575c8ebae37SRussell King struct variant_data *variant = host->variant; 576c8ebae37SRussell King struct dma_slave_config conf = { 577c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 578c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 579c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 580c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 581c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 582c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 583258aea76SViresh Kumar .device_fc = false, 584c8ebae37SRussell King }; 585c8ebae37SRussell King struct dma_chan *chan; 586c8ebae37SRussell King struct dma_device *device; 587c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 58805f5799cSVinod Koul enum dma_data_direction buffer_dirn; 589c8ebae37SRussell King int nr_sg; 5909cb15142SSrinivas Kandagatla unsigned long flags = DMA_CTRL_ACK; 591c8ebae37SRussell King 592c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 59305f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 59405f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 595c8ebae37SRussell King chan = host->dma_rx_channel; 596c8ebae37SRussell King } else { 59705f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 59805f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 599c8ebae37SRussell King chan = host->dma_tx_channel; 600c8ebae37SRussell King } 601c8ebae37SRussell King 602c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 603c8ebae37SRussell King if (!chan) 604c8ebae37SRussell King return -EINVAL; 605c8ebae37SRussell King 606c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 60758c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 608c8ebae37SRussell King return -EINVAL; 609c8ebae37SRussell King 610c8ebae37SRussell King device = chan->device; 61105f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 612c8ebae37SRussell King if (nr_sg == 0) 613c8ebae37SRussell King return -EINVAL; 614c8ebae37SRussell King 6159cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 6169cb15142SSrinivas Kandagatla flags |= DMA_PREP_INTERRUPT; 6179cb15142SSrinivas Kandagatla 618c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 61916052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 6209cb15142SSrinivas Kandagatla conf.direction, flags); 621c8ebae37SRussell King if (!desc) 622c8ebae37SRussell King goto unmap_exit; 623c8ebae37SRussell King 624653a761eSUlf Hansson *dma_chan = chan; 625653a761eSUlf Hansson *dma_desc = desc; 626c8ebae37SRussell King 62758c7ccbfSPer Forlin return 0; 62858c7ccbfSPer Forlin 62958c7ccbfSPer Forlin unmap_exit: 63005f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 63158c7ccbfSPer Forlin return -ENOMEM; 63258c7ccbfSPer Forlin } 63358c7ccbfSPer Forlin 634653a761eSUlf Hansson static inline int mmci_dma_prep_data(struct mmci_host *host, 635653a761eSUlf Hansson struct mmc_data *data) 636653a761eSUlf Hansson { 637653a761eSUlf Hansson /* Check if next job is already prepared. */ 638653a761eSUlf Hansson if (host->dma_current && host->dma_desc_current) 639653a761eSUlf Hansson return 0; 640653a761eSUlf Hansson 641653a761eSUlf Hansson /* No job were prepared thus do it now. */ 642653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &host->dma_current, 643653a761eSUlf Hansson &host->dma_desc_current); 644653a761eSUlf Hansson } 645653a761eSUlf Hansson 646653a761eSUlf Hansson static inline int mmci_dma_prep_next(struct mmci_host *host, 647653a761eSUlf Hansson struct mmc_data *data) 648653a761eSUlf Hansson { 649653a761eSUlf Hansson struct mmci_host_next *nd = &host->next_data; 650653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 651653a761eSUlf Hansson } 652653a761eSUlf Hansson 65358c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 65458c7ccbfSPer Forlin { 65558c7ccbfSPer Forlin int ret; 65658c7ccbfSPer Forlin struct mmc_data *data = host->data; 65758c7ccbfSPer Forlin 658653a761eSUlf Hansson ret = mmci_dma_prep_data(host, host->data); 65958c7ccbfSPer Forlin if (ret) 66058c7ccbfSPer Forlin return ret; 66158c7ccbfSPer Forlin 66258c7ccbfSPer Forlin /* Okay, go for it. */ 663c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 664c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 665c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 66658c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 66758c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 668c8ebae37SRussell King 6699cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 6709cb15142SSrinivas Kandagatla dml_start_xfer(host, data); 6719cb15142SSrinivas Kandagatla 672c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 673c8ebae37SRussell King 674c8ebae37SRussell King /* Trigger the DMA transfer */ 6759cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 676c8ebae37SRussell King 677c8ebae37SRussell King /* 678c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 679c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 680c8ebae37SRussell King * call mmci_data_end() 681c8ebae37SRussell King */ 682c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 683c8ebae37SRussell King host->base + MMCIMASK0); 684c8ebae37SRussell King return 0; 685c8ebae37SRussell King } 68658c7ccbfSPer Forlin 68758c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 68858c7ccbfSPer Forlin { 68958c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 69058c7ccbfSPer Forlin 691653a761eSUlf Hansson WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 692653a761eSUlf Hansson WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 69358c7ccbfSPer Forlin 69458c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 69558c7ccbfSPer Forlin host->dma_current = next->dma_chan; 69658c7ccbfSPer Forlin next->dma_desc = NULL; 69758c7ccbfSPer Forlin next->dma_chan = NULL; 69858c7ccbfSPer Forlin } 69958c7ccbfSPer Forlin 70058c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 70158c7ccbfSPer Forlin bool is_first_req) 70258c7ccbfSPer Forlin { 70358c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 70458c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 70558c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 70658c7ccbfSPer Forlin 70758c7ccbfSPer Forlin if (!data) 70858c7ccbfSPer Forlin return; 70958c7ccbfSPer Forlin 710653a761eSUlf Hansson BUG_ON(data->host_cookie); 71158c7ccbfSPer Forlin 712653a761eSUlf Hansson if (mmci_validate_data(host, data)) 713653a761eSUlf Hansson return; 714653a761eSUlf Hansson 715653a761eSUlf Hansson if (!mmci_dma_prep_next(host, data)) 71658c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 71758c7ccbfSPer Forlin } 71858c7ccbfSPer Forlin 71958c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 72058c7ccbfSPer Forlin int err) 72158c7ccbfSPer Forlin { 72258c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 72358c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 72458c7ccbfSPer Forlin 725653a761eSUlf Hansson if (!data || !data->host_cookie) 72658c7ccbfSPer Forlin return; 72758c7ccbfSPer Forlin 728653a761eSUlf Hansson mmci_dma_unmap(host, data); 729653a761eSUlf Hansson 730653a761eSUlf Hansson if (err) { 731653a761eSUlf Hansson struct mmci_host_next *next = &host->next_data; 732653a761eSUlf Hansson struct dma_chan *chan; 733653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) 73458c7ccbfSPer Forlin chan = host->dma_rx_channel; 735653a761eSUlf Hansson else 73658c7ccbfSPer Forlin chan = host->dma_tx_channel; 73758c7ccbfSPer Forlin dmaengine_terminate_all(chan); 738653a761eSUlf Hansson 739b5c16a60SSrinivas Kandagatla if (host->dma_desc_current == next->dma_desc) 740b5c16a60SSrinivas Kandagatla host->dma_desc_current = NULL; 741b5c16a60SSrinivas Kandagatla 742b5c16a60SSrinivas Kandagatla if (host->dma_current == next->dma_chan) 743b5c16a60SSrinivas Kandagatla host->dma_current = NULL; 744b5c16a60SSrinivas Kandagatla 745653a761eSUlf Hansson next->dma_desc = NULL; 746653a761eSUlf Hansson next->dma_chan = NULL; 747b5c16a60SSrinivas Kandagatla data->host_cookie = 0; 74858c7ccbfSPer Forlin } 74958c7ccbfSPer Forlin } 75058c7ccbfSPer Forlin 751c8ebae37SRussell King #else 752c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 75358c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 75458c7ccbfSPer Forlin { 75558c7ccbfSPer Forlin } 756c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 757c8ebae37SRussell King { 758c8ebae37SRussell King } 759c8ebae37SRussell King 760c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 761c8ebae37SRussell King { 762c8ebae37SRussell King } 763c8ebae37SRussell King 764c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 765c8ebae37SRussell King { 766c8ebae37SRussell King } 767c8ebae37SRussell King 768653a761eSUlf Hansson static inline void mmci_dma_finalize(struct mmci_host *host, 769653a761eSUlf Hansson struct mmc_data *data) 770653a761eSUlf Hansson { 771653a761eSUlf Hansson } 772653a761eSUlf Hansson 773c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 774c8ebae37SRussell King { 775c8ebae37SRussell King } 776c8ebae37SRussell King 777c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 778c8ebae37SRussell King { 779c8ebae37SRussell King return -ENOSYS; 780c8ebae37SRussell King } 78158c7ccbfSPer Forlin 78258c7ccbfSPer Forlin #define mmci_pre_request NULL 78358c7ccbfSPer Forlin #define mmci_post_request NULL 78458c7ccbfSPer Forlin 785c8ebae37SRussell King #endif 786c8ebae37SRussell King 7871c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 7881c6a0718SPierre Ossman { 7898301bb68SRabin Vincent struct variant_data *variant = host->variant; 7901c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 7911c6a0718SPierre Ossman unsigned long long clks; 7921c6a0718SPierre Ossman void __iomem *base; 7931c6a0718SPierre Ossman int blksz_bits; 7941c6a0718SPierre Ossman 79564de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 7961c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 7971c6a0718SPierre Ossman 7981c6a0718SPierre Ossman host->data = data; 799528320dbSRabin Vincent host->size = data->blksz * data->blocks; 80051d4375dSRussell King data->bytes_xfered = 0; 8011c6a0718SPierre Ossman 8021c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 803c4a35769SSrinivas Kandagatla do_div(clks, NSEC_PER_SEC); 8041c6a0718SPierre Ossman 8051c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 8061c6a0718SPierre Ossman 8071c6a0718SPierre Ossman base = host->base; 8081c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 8091c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 8101c6a0718SPierre Ossman 8111c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 8121c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 8131c6a0718SPierre Ossman 8141784b157SPhilippe Langlais if (variant->blksz_datactrl16) 8151784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 816ff783233SSrinivas Kandagatla else if (variant->blksz_datactrl4) 817ff783233SSrinivas Kandagatla datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 8181784b157SPhilippe Langlais else 8191c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 820c8ebae37SRussell King 821c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 8221c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 823c8ebae37SRussell King 824c7354133SSrinivas Kandagatla if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 82506c1a121SUlf Hansson u32 clk; 826c7354133SSrinivas Kandagatla 8275df014dfSSrinivas Kandagatla datactrl |= variant->datactrl_mask_sdio; 8287258db7eSUlf Hansson 829c8ebae37SRussell King /* 83070ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 83170ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 83270ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 83370ac0935SUlf Hansson * depends on the rate of MCLK. 83406c1a121SUlf Hansson */ 835c7354133SSrinivas Kandagatla if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 83670ac0935SUlf Hansson (host->size < 8 || 83770ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 83806c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 83906c1a121SUlf Hansson else 84006c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 84106c1a121SUlf Hansson 84206c1a121SUlf Hansson mmci_write_clkreg(host, clk); 84306c1a121SUlf Hansson } 84406c1a121SUlf Hansson 8456dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 8466dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 847e17dca2bSSrinivas Kandagatla datactrl |= variant->datactrl_mask_ddrmode; 8486dbb6ee0SUlf Hansson 84906c1a121SUlf Hansson /* 850c8ebae37SRussell King * Attempt to use DMA operation mode, if this 851c8ebae37SRussell King * should fail, fall back to PIO mode 852c8ebae37SRussell King */ 853c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 854c8ebae37SRussell King return; 855c8ebae37SRussell King 856c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 857c8ebae37SRussell King mmci_init_sg(host, data); 858c8ebae37SRussell King 859c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 8601c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 8611c6a0718SPierre Ossman 8621c6a0718SPierre Ossman /* 863c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 864c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 865c4d877c1SRussell King * is available. 8661c6a0718SPierre Ossman */ 867c4d877c1SRussell King if (host->size < variant->fifohalfsize) 8681c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 8691c6a0718SPierre Ossman } else { 8701c6a0718SPierre Ossman /* 8711c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 8721c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 8731c6a0718SPierre Ossman */ 8741c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 8751c6a0718SPierre Ossman } 8761c6a0718SPierre Ossman 8779cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 8781c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 8792686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 8801c6a0718SPierre Ossman } 8811c6a0718SPierre Ossman 8821c6a0718SPierre Ossman static void 8831c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 8841c6a0718SPierre Ossman { 8851c6a0718SPierre Ossman void __iomem *base = host->base; 8861c6a0718SPierre Ossman 88764de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 8881c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 8891c6a0718SPierre Ossman 8901c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 8911c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 8926adb2a80SSrinivas Kandagatla mmci_reg_delay(host); 8931c6a0718SPierre Ossman } 8941c6a0718SPierre Ossman 8951c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 8961c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 8971c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 8981c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 8991c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 9001c6a0718SPierre Ossman } 9011c6a0718SPierre Ossman if (/*interrupt*/0) 9021c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 9031c6a0718SPierre Ossman 904ae7b0061SSrinivas Kandagatla if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 905ae7b0061SSrinivas Kandagatla c |= host->variant->data_cmd_enable; 906ae7b0061SSrinivas Kandagatla 9071c6a0718SPierre Ossman host->cmd = cmd; 9081c6a0718SPierre Ossman 9091c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 9101c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 9111c6a0718SPierre Ossman } 9121c6a0718SPierre Ossman 9131c6a0718SPierre Ossman static void 9141c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 9151c6a0718SPierre Ossman unsigned int status) 9161c6a0718SPierre Ossman { 9171cb9da50SUlf Hansson /* Make sure we have data to handle */ 9181cb9da50SUlf Hansson if (!data) 9191cb9da50SUlf Hansson return; 9201cb9da50SUlf Hansson 921f20f8f21SLinus Walleij /* First check for errors */ 922b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 923b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 9248cb28155SLinus Walleij u32 remain, success; 925f20f8f21SLinus Walleij 926c8ebae37SRussell King /* Terminate the DMA transfer */ 927653a761eSUlf Hansson if (dma_inprogress(host)) { 928c8ebae37SRussell King mmci_dma_data_error(host); 929653a761eSUlf Hansson mmci_dma_unmap(host, data); 930653a761eSUlf Hansson } 931c8ebae37SRussell King 932c8afc9d5SRussell King /* 933c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 934c8afc9d5SRussell King * the data counter gives the number of bytes transferred 935c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 936c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 937c8afc9d5SRussell King * matters for FIFO overruns only. 938c8afc9d5SRussell King */ 939f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 9408cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 9418cb28155SLinus Walleij 942c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 943c8afc9d5SRussell King status, success); 9448cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 9458cb28155SLinus Walleij /* Last block was not successful */ 946c8afc9d5SRussell King success -= 1; 94717b0429dSPierre Ossman data->error = -EILSEQ; 9488cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 94917b0429dSPierre Ossman data->error = -ETIMEDOUT; 950757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 951757df746SLinus Walleij data->error = -ECOMM; 952c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 95317b0429dSPierre Ossman data->error = -EIO; 954c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 955c8afc9d5SRussell King if (success > host->variant->fifosize) 956c8afc9d5SRussell King success -= host->variant->fifosize; 957c8afc9d5SRussell King else 958c8afc9d5SRussell King success = 0; 9598cb28155SLinus Walleij data->error = -EIO; 9604ce1d6cbSRabin Vincent } 96151d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 9621c6a0718SPierre Ossman } 963f20f8f21SLinus Walleij 9648cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 9658cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 966f20f8f21SLinus Walleij 967ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 968c8ebae37SRussell King if (dma_inprogress(host)) 969653a761eSUlf Hansson mmci_dma_finalize(host, data); 9701c6a0718SPierre Ossman mmci_stop_data(host); 9711c6a0718SPierre Ossman 9728cb28155SLinus Walleij if (!data->error) 9738cb28155SLinus Walleij /* The error clause is handled above, success! */ 97451d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 975f20f8f21SLinus Walleij 976024629c6SUlf Hansson if (!data->stop || host->mrq->sbc) { 9771c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 9781c6a0718SPierre Ossman } else { 9791c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 9801c6a0718SPierre Ossman } 9811c6a0718SPierre Ossman } 9821c6a0718SPierre Ossman } 9831c6a0718SPierre Ossman 9841c6a0718SPierre Ossman static void 9851c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 9861c6a0718SPierre Ossman unsigned int status) 9871c6a0718SPierre Ossman { 9881c6a0718SPierre Ossman void __iomem *base = host->base; 989ad82bfeaSUlf Hansson bool sbc, busy_resp; 990ad82bfeaSUlf Hansson 991ad82bfeaSUlf Hansson if (!cmd) 992ad82bfeaSUlf Hansson return; 993ad82bfeaSUlf Hansson 994ad82bfeaSUlf Hansson sbc = (cmd == host->mrq->sbc); 995ad82bfeaSUlf Hansson busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY); 996ad82bfeaSUlf Hansson 997ad82bfeaSUlf Hansson if (!((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 998ad82bfeaSUlf Hansson MCI_CMDSENT|MCI_CMDRESPEND))) 999ad82bfeaSUlf Hansson return; 10008d94b54dSUlf Hansson 10018d94b54dSUlf Hansson /* Check if we need to wait for busy completion. */ 10028d94b54dSUlf Hansson if (host->busy_status && (status & MCI_ST_CARDBUSY)) 10038d94b54dSUlf Hansson return; 10048d94b54dSUlf Hansson 10058d94b54dSUlf Hansson /* Enable busy completion if needed and supported. */ 10068d94b54dSUlf Hansson if (!host->busy_status && busy_resp && 10078d94b54dSUlf Hansson !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 10088d94b54dSUlf Hansson (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 10098d94b54dSUlf Hansson writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 10108d94b54dSUlf Hansson base + MMCIMASK0); 10118d94b54dSUlf Hansson host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 10128d94b54dSUlf Hansson return; 10138d94b54dSUlf Hansson } 10148d94b54dSUlf Hansson 10158d94b54dSUlf Hansson /* At busy completion, mask the IRQ and complete the request. */ 10168d94b54dSUlf Hansson if (host->busy_status) { 10178d94b54dSUlf Hansson writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 10188d94b54dSUlf Hansson base + MMCIMASK0); 10198d94b54dSUlf Hansson host->busy_status = 0; 10208d94b54dSUlf Hansson } 10211c6a0718SPierre Ossman 10221c6a0718SPierre Ossman host->cmd = NULL; 10231c6a0718SPierre Ossman 10241c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 102517b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 10261c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 102717b0429dSPierre Ossman cmd->error = -EILSEQ; 10289047b435SRussell King - ARM Linux } else { 10299047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 10309047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 10319047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 10329047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 10331c6a0718SPierre Ossman } 10341c6a0718SPierre Ossman 1035024629c6SUlf Hansson if ((!sbc && !cmd->data) || cmd->error) { 10363b6e3c73SUlf Hansson if (host->data) { 10373b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 1038653a761eSUlf Hansson if (dma_inprogress(host)) { 10393b6e3c73SUlf Hansson mmci_dma_data_error(host); 1040653a761eSUlf Hansson mmci_dma_unmap(host, host->data); 1041653a761eSUlf Hansson } 10421c6a0718SPierre Ossman mmci_stop_data(host); 10433b6e3c73SUlf Hansson } 1044024629c6SUlf Hansson mmci_request_end(host, host->mrq); 1045024629c6SUlf Hansson } else if (sbc) { 1046024629c6SUlf Hansson mmci_start_command(host, host->mrq->cmd, 0); 10471c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 10481c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 10491c6a0718SPierre Ossman } 10501c6a0718SPierre Ossman } 10511c6a0718SPierre Ossman 10529c34b73dSSrinivas Kandagatla static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 10539c34b73dSSrinivas Kandagatla { 10549c34b73dSSrinivas Kandagatla return remain - (readl(host->base + MMCIFIFOCNT) << 2); 10559c34b73dSSrinivas Kandagatla } 10569c34b73dSSrinivas Kandagatla 10579c34b73dSSrinivas Kandagatla static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 10589c34b73dSSrinivas Kandagatla { 10599c34b73dSSrinivas Kandagatla /* 10609c34b73dSSrinivas Kandagatla * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 10619c34b73dSSrinivas Kandagatla * from the fifo range should be used 10629c34b73dSSrinivas Kandagatla */ 10639c34b73dSSrinivas Kandagatla if (status & MCI_RXFIFOHALFFULL) 10649c34b73dSSrinivas Kandagatla return host->variant->fifohalfsize; 10659c34b73dSSrinivas Kandagatla else if (status & MCI_RXDATAAVLBL) 10669c34b73dSSrinivas Kandagatla return 4; 10679c34b73dSSrinivas Kandagatla 10689c34b73dSSrinivas Kandagatla return 0; 10699c34b73dSSrinivas Kandagatla } 10709c34b73dSSrinivas Kandagatla 10711c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 10721c6a0718SPierre Ossman { 10731c6a0718SPierre Ossman void __iomem *base = host->base; 10741c6a0718SPierre Ossman char *ptr = buffer; 10759c34b73dSSrinivas Kandagatla u32 status = readl(host->base + MMCISTATUS); 107626eed9a5SLinus Walleij int host_remain = host->size; 10771c6a0718SPierre Ossman 10781c6a0718SPierre Ossman do { 10799c34b73dSSrinivas Kandagatla int count = host->get_rx_fifocnt(host, status, host_remain); 10801c6a0718SPierre Ossman 10811c6a0718SPierre Ossman if (count > remain) 10821c6a0718SPierre Ossman count = remain; 10831c6a0718SPierre Ossman 10841c6a0718SPierre Ossman if (count <= 0) 10851c6a0718SPierre Ossman break; 10861c6a0718SPierre Ossman 1087393e5e24SUlf Hansson /* 1088393e5e24SUlf Hansson * SDIO especially may want to send something that is 1089393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 1090393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 1091393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 1092393e5e24SUlf Hansson */ 1093393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 1094393e5e24SUlf Hansson if (count < 4) { 1095393e5e24SUlf Hansson unsigned char buf[4]; 10964b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 1097393e5e24SUlf Hansson memcpy(ptr, buf, count); 1098393e5e24SUlf Hansson } else { 10994b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1100393e5e24SUlf Hansson count &= ~0x3; 1101393e5e24SUlf Hansson } 1102393e5e24SUlf Hansson } else { 11034b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1104393e5e24SUlf Hansson } 11051c6a0718SPierre Ossman 11061c6a0718SPierre Ossman ptr += count; 11071c6a0718SPierre Ossman remain -= count; 110826eed9a5SLinus Walleij host_remain -= count; 11091c6a0718SPierre Ossman 11101c6a0718SPierre Ossman if (remain == 0) 11111c6a0718SPierre Ossman break; 11121c6a0718SPierre Ossman 11131c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11141c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 11151c6a0718SPierre Ossman 11161c6a0718SPierre Ossman return ptr - buffer; 11171c6a0718SPierre Ossman } 11181c6a0718SPierre Ossman 11191c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 11201c6a0718SPierre Ossman { 11218301bb68SRabin Vincent struct variant_data *variant = host->variant; 11221c6a0718SPierre Ossman void __iomem *base = host->base; 11231c6a0718SPierre Ossman char *ptr = buffer; 11241c6a0718SPierre Ossman 11251c6a0718SPierre Ossman do { 11261c6a0718SPierre Ossman unsigned int count, maxcnt; 11271c6a0718SPierre Ossman 11288301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 11298301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 11301c6a0718SPierre Ossman count = min(remain, maxcnt); 11311c6a0718SPierre Ossman 113234177802SLinus Walleij /* 113334177802SLinus Walleij * SDIO especially may want to send something that is 113434177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 113534177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 113634177802SLinus Walleij * So compensate by adding +3 on the count, a single 113734177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 113834177802SLinus Walleij * 32bit writes etc. 113934177802SLinus Walleij */ 11404b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 11411c6a0718SPierre Ossman 11421c6a0718SPierre Ossman ptr += count; 11431c6a0718SPierre Ossman remain -= count; 11441c6a0718SPierre Ossman 11451c6a0718SPierre Ossman if (remain == 0) 11461c6a0718SPierre Ossman break; 11471c6a0718SPierre Ossman 11481c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11491c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 11501c6a0718SPierre Ossman 11511c6a0718SPierre Ossman return ptr - buffer; 11521c6a0718SPierre Ossman } 11531c6a0718SPierre Ossman 11541c6a0718SPierre Ossman /* 11551c6a0718SPierre Ossman * PIO data transfer IRQ handler. 11561c6a0718SPierre Ossman */ 11571c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 11581c6a0718SPierre Ossman { 11591c6a0718SPierre Ossman struct mmci_host *host = dev_id; 11604ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 11618301bb68SRabin Vincent struct variant_data *variant = host->variant; 11621c6a0718SPierre Ossman void __iomem *base = host->base; 11634ce1d6cbSRabin Vincent unsigned long flags; 11641c6a0718SPierre Ossman u32 status; 11651c6a0718SPierre Ossman 11661c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11671c6a0718SPierre Ossman 116864de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 11691c6a0718SPierre Ossman 11704ce1d6cbSRabin Vincent local_irq_save(flags); 11714ce1d6cbSRabin Vincent 11721c6a0718SPierre Ossman do { 11731c6a0718SPierre Ossman unsigned int remain, len; 11741c6a0718SPierre Ossman char *buffer; 11751c6a0718SPierre Ossman 11761c6a0718SPierre Ossman /* 11771c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 11781c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 11791c6a0718SPierre Ossman * definition it is more than half empty. 11801c6a0718SPierre Ossman * 11811c6a0718SPierre Ossman * For read, check for data available. 11821c6a0718SPierre Ossman */ 11831c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 11841c6a0718SPierre Ossman break; 11851c6a0718SPierre Ossman 11864ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 11874ce1d6cbSRabin Vincent break; 11884ce1d6cbSRabin Vincent 11894ce1d6cbSRabin Vincent buffer = sg_miter->addr; 11904ce1d6cbSRabin Vincent remain = sg_miter->length; 11911c6a0718SPierre Ossman 11921c6a0718SPierre Ossman len = 0; 11931c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 11941c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 11951c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 11961c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 11971c6a0718SPierre Ossman 11984ce1d6cbSRabin Vincent sg_miter->consumed = len; 11991c6a0718SPierre Ossman 12001c6a0718SPierre Ossman host->size -= len; 12011c6a0718SPierre Ossman remain -= len; 12021c6a0718SPierre Ossman 12031c6a0718SPierre Ossman if (remain) 12041c6a0718SPierre Ossman break; 12051c6a0718SPierre Ossman 12061c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 12071c6a0718SPierre Ossman } while (1); 12081c6a0718SPierre Ossman 12094ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 12104ce1d6cbSRabin Vincent 12114ce1d6cbSRabin Vincent local_irq_restore(flags); 12124ce1d6cbSRabin Vincent 12131c6a0718SPierre Ossman /* 1214c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 1215c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 12161c6a0718SPierre Ossman */ 1217c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 12182686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 12191c6a0718SPierre Ossman 12201c6a0718SPierre Ossman /* 12211c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 12221c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 12231c6a0718SPierre Ossman * the chip itself has disabled the data path, and 12241c6a0718SPierre Ossman * stops us racing with our data end IRQ. 12251c6a0718SPierre Ossman */ 12261c6a0718SPierre Ossman if (host->size == 0) { 12272686b4b4SLinus Walleij mmci_set_mask1(host, 0); 12281c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 12291c6a0718SPierre Ossman } 12301c6a0718SPierre Ossman 12311c6a0718SPierre Ossman return IRQ_HANDLED; 12321c6a0718SPierre Ossman } 12331c6a0718SPierre Ossman 12341c6a0718SPierre Ossman /* 12351c6a0718SPierre Ossman * Handle completion of command and data transfers. 12361c6a0718SPierre Ossman */ 12371c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 12381c6a0718SPierre Ossman { 12391c6a0718SPierre Ossman struct mmci_host *host = dev_id; 12401c6a0718SPierre Ossman u32 status; 12411c6a0718SPierre Ossman int ret = 0; 12421c6a0718SPierre Ossman 12431c6a0718SPierre Ossman spin_lock(&host->lock); 12441c6a0718SPierre Ossman 12451c6a0718SPierre Ossman do { 12461c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 12472686b4b4SLinus Walleij 12482686b4b4SLinus Walleij if (host->singleirq) { 12492686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 12502686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 12512686b4b4SLinus Walleij 12522686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 12532686b4b4SLinus Walleij } 12542686b4b4SLinus Walleij 12558d94b54dSUlf Hansson /* 12568d94b54dSUlf Hansson * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 12578d94b54dSUlf Hansson * enabled) since the HW seems to be triggering the IRQ on both 12588d94b54dSUlf Hansson * edges while monitoring DAT0 for busy completion. 12598d94b54dSUlf Hansson */ 12601c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 12611c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 12621c6a0718SPierre Ossman 126364de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 12641c6a0718SPierre Ossman 12657878289bSUlf Hansson if (host->variant->reversed_irq_handling) { 12667878289bSUlf Hansson mmci_data_irq(host, host->data, status); 12677878289bSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 12687878289bSUlf Hansson } else { 1269ad82bfeaSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 12701cb9da50SUlf Hansson mmci_data_irq(host, host->data, status); 12717878289bSUlf Hansson } 12721c6a0718SPierre Ossman 12738d94b54dSUlf Hansson /* Don't poll for busy completion in irq context. */ 12748d94b54dSUlf Hansson if (host->busy_status) 12758d94b54dSUlf Hansson status &= ~MCI_ST_CARDBUSY; 12768d94b54dSUlf Hansson 12771c6a0718SPierre Ossman ret = 1; 12781c6a0718SPierre Ossman } while (status); 12791c6a0718SPierre Ossman 12801c6a0718SPierre Ossman spin_unlock(&host->lock); 12811c6a0718SPierre Ossman 12821c6a0718SPierre Ossman return IRQ_RETVAL(ret); 12831c6a0718SPierre Ossman } 12841c6a0718SPierre Ossman 12851c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 12861c6a0718SPierre Ossman { 12871c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 12889e943021SLinus Walleij unsigned long flags; 12891c6a0718SPierre Ossman 12901c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 12911c6a0718SPierre Ossman 1292653a761eSUlf Hansson mrq->cmd->error = mmci_validate_data(host, mrq->data); 1293653a761eSUlf Hansson if (mrq->cmd->error) { 1294255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1295255d01afSPierre Ossman return; 1296255d01afSPierre Ossman } 1297255d01afSPierre Ossman 12981c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 12991c3be369SRussell King 13009e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 13011c6a0718SPierre Ossman 13021c6a0718SPierre Ossman host->mrq = mrq; 13031c6a0718SPierre Ossman 130458c7ccbfSPer Forlin if (mrq->data) 130558c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 130658c7ccbfSPer Forlin 13071c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 13081c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 13091c6a0718SPierre Ossman 1310024629c6SUlf Hansson if (mrq->sbc) 1311024629c6SUlf Hansson mmci_start_command(host, mrq->sbc, 0); 1312024629c6SUlf Hansson else 13131c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 13141c6a0718SPierre Ossman 13159e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 13161c6a0718SPierre Ossman } 13171c6a0718SPierre Ossman 13181c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 13191c6a0718SPierre Ossman { 13201c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 13217d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1322a6a6464aSLinus Walleij u32 pwr = 0; 1323a6a6464aSLinus Walleij unsigned long flags; 1324db90f91fSLee Jones int ret; 13251c6a0718SPierre Ossman 13262cd976c4SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 13272cd976c4SUlf Hansson 1328bc521818SUlf Hansson if (host->plat->ios_handler && 1329bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1330bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1331bc521818SUlf Hansson 13321c6a0718SPierre Ossman switch (ios->power_mode) { 13331c6a0718SPierre Ossman case MMC_POWER_OFF: 1334599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1335599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1336237fb5e6SLee Jones 13377c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1338237fb5e6SLee Jones regulator_disable(mmc->supply.vqmmc); 13397c0136efSUlf Hansson host->vqmmc_enabled = false; 13407c0136efSUlf Hansson } 1341237fb5e6SLee Jones 13421c6a0718SPierre Ossman break; 13431c6a0718SPierre Ossman case MMC_POWER_UP: 1344599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1345599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1346599c1d5cSUlf Hansson 13477d72a1d4SUlf Hansson /* 13487d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 13497d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 13507d72a1d4SUlf Hansson * configured in the variant data. 13517d72a1d4SUlf Hansson */ 13527d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 13537d72a1d4SUlf Hansson 13541c6a0718SPierre Ossman break; 13551c6a0718SPierre Ossman case MMC_POWER_ON: 13567c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1357db90f91fSLee Jones ret = regulator_enable(mmc->supply.vqmmc); 1358db90f91fSLee Jones if (ret < 0) 1359db90f91fSLee Jones dev_err(mmc_dev(mmc), 1360db90f91fSLee Jones "failed to enable vqmmc regulator\n"); 13617c0136efSUlf Hansson else 13627c0136efSUlf Hansson host->vqmmc_enabled = true; 1363db90f91fSLee Jones } 1364237fb5e6SLee Jones 13651c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 13661c6a0718SPierre Ossman break; 13671c6a0718SPierre Ossman } 13681c6a0718SPierre Ossman 13694d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 13704d1a3a0dSUlf Hansson /* 13714d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 13724d1a3a0dSUlf Hansson * indicating signal direction for the signals in 13734d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 13744d1a3a0dSUlf Hansson */ 13754593df29SUlf Hansson pwr |= host->pwr_reg_add; 13764d1a3a0dSUlf Hansson 13774d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 13784d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 13794d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 13804d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 13814d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 13824d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 13834d1a3a0dSUlf Hansson } 13844d1a3a0dSUlf Hansson 1385cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1386f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 13871c6a0718SPierre Ossman pwr |= MCI_ROD; 1388cc30d60eSLinus Walleij else { 1389cc30d60eSLinus Walleij /* 1390cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1391cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1392cc30d60eSLinus Walleij */ 1393cc30d60eSLinus Walleij pwr |= MCI_OD; 1394cc30d60eSLinus Walleij } 1395cc30d60eSLinus Walleij } 13961c6a0718SPierre Ossman 1397f4670daeSUlf Hansson /* 1398f4670daeSUlf Hansson * If clock = 0 and the variant requires the MMCIPOWER to be used for 1399f4670daeSUlf Hansson * gating the clock, the MCI_PWR_ON bit is cleared. 1400f4670daeSUlf Hansson */ 1401f4670daeSUlf Hansson if (!ios->clock && variant->pwrreg_clkgate) 1402f4670daeSUlf Hansson pwr &= ~MCI_PWR_ON; 1403f4670daeSUlf Hansson 14043f4e6f7bSSrinivas Kandagatla if (host->variant->explicit_mclk_control && 14053f4e6f7bSSrinivas Kandagatla ios->clock != host->clock_cache) { 14063f4e6f7bSSrinivas Kandagatla ret = clk_set_rate(host->clk, ios->clock); 14073f4e6f7bSSrinivas Kandagatla if (ret < 0) 14083f4e6f7bSSrinivas Kandagatla dev_err(mmc_dev(host->mmc), 14093f4e6f7bSSrinivas Kandagatla "Error setting clock rate (%d)\n", ret); 14103f4e6f7bSSrinivas Kandagatla else 14113f4e6f7bSSrinivas Kandagatla host->mclk = clk_get_rate(host->clk); 14123f4e6f7bSSrinivas Kandagatla } 14133f4e6f7bSSrinivas Kandagatla host->clock_cache = ios->clock; 14143f4e6f7bSSrinivas Kandagatla 1415a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1416a6a6464aSLinus Walleij 1417a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 14187437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1419f829c042SUlf Hansson mmci_reg_delay(host); 1420a6a6464aSLinus Walleij 1421a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 14222cd976c4SUlf Hansson 14232cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 14242cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 14251c6a0718SPierre Ossman } 14261c6a0718SPierre Ossman 142789001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 142889001446SRussell King { 142989001446SRussell King struct mmci_host *host = mmc_priv(mmc); 143029719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 1431d2762090SUlf Hansson unsigned int status = mmc_gpio_get_cd(mmc); 143289001446SRussell King 1433d2762090SUlf Hansson if (status == -ENOSYS) { 14344b8caec0SRabin Vincent if (!plat->status) 14354b8caec0SRabin Vincent return 1; /* Assume always present */ 14364b8caec0SRabin Vincent 143729719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 1438d2762090SUlf Hansson } 143974bc8093SRussell King return status; 144089001446SRussell King } 144189001446SRussell King 14420f3ed7f7SUlf Hansson static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 14430f3ed7f7SUlf Hansson { 14440f3ed7f7SUlf Hansson int ret = 0; 14450f3ed7f7SUlf Hansson 14460f3ed7f7SUlf Hansson if (!IS_ERR(mmc->supply.vqmmc)) { 14470f3ed7f7SUlf Hansson 14480f3ed7f7SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 14490f3ed7f7SUlf Hansson 14500f3ed7f7SUlf Hansson switch (ios->signal_voltage) { 14510f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_330: 14520f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14530f3ed7f7SUlf Hansson 2700000, 3600000); 14540f3ed7f7SUlf Hansson break; 14550f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_180: 14560f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14570f3ed7f7SUlf Hansson 1700000, 1950000); 14580f3ed7f7SUlf Hansson break; 14590f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_120: 14600f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 14610f3ed7f7SUlf Hansson 1100000, 1300000); 14620f3ed7f7SUlf Hansson break; 14630f3ed7f7SUlf Hansson } 14640f3ed7f7SUlf Hansson 14650f3ed7f7SUlf Hansson if (ret) 14660f3ed7f7SUlf Hansson dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 14670f3ed7f7SUlf Hansson 14680f3ed7f7SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 14690f3ed7f7SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 14700f3ed7f7SUlf Hansson } 14710f3ed7f7SUlf Hansson 14720f3ed7f7SUlf Hansson return ret; 14730f3ed7f7SUlf Hansson } 14740f3ed7f7SUlf Hansson 147501259620SUlf Hansson static struct mmc_host_ops mmci_ops = { 14761c6a0718SPierre Ossman .request = mmci_request, 147758c7ccbfSPer Forlin .pre_req = mmci_pre_request, 147858c7ccbfSPer Forlin .post_req = mmci_post_request, 14791c6a0718SPierre Ossman .set_ios = mmci_set_ios, 1480d2762090SUlf Hansson .get_ro = mmc_gpio_get_ro, 148189001446SRussell King .get_cd = mmci_get_cd, 14820f3ed7f7SUlf Hansson .start_signal_voltage_switch = mmci_sig_volt_switch, 14831c6a0718SPierre Ossman }; 14841c6a0718SPierre Ossman 148578f87df2SUlf Hansson static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 148678f87df2SUlf Hansson { 14874593df29SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 148878f87df2SUlf Hansson int ret = mmc_of_parse(mmc); 1489000bc9d5SLee Jones 149078f87df2SUlf Hansson if (ret) 149178f87df2SUlf Hansson return ret; 1492000bc9d5SLee Jones 14934593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat0", NULL)) 14944593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA0DIREN; 14954593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat2", NULL)) 14964593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA2DIREN; 14974593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat31", NULL)) 14984593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA31DIREN; 14994593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat74", NULL)) 15004593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA74DIREN; 15014593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-cmd", NULL)) 15024593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_CMDDIREN; 15034593df29SUlf Hansson if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 15044593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_FBCLKEN; 15054593df29SUlf Hansson 1506000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 150778f87df2SUlf Hansson mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1508000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 150978f87df2SUlf Hansson mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1510000bc9d5SLee Jones 151178f87df2SUlf Hansson return 0; 1512000bc9d5SLee Jones } 1513000bc9d5SLee Jones 1514c3be1efdSBill Pemberton static int mmci_probe(struct amba_device *dev, 1515aa25afadSRussell King const struct amba_id *id) 15161c6a0718SPierre Ossman { 15176ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1518000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 15194956e109SRabin Vincent struct variant_data *variant = id->data; 15201c6a0718SPierre Ossman struct mmci_host *host; 15211c6a0718SPierre Ossman struct mmc_host *mmc; 15221c6a0718SPierre Ossman int ret; 15231c6a0718SPierre Ossman 1524000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1525000bc9d5SLee Jones if (!plat && !np) { 1526000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1527000bc9d5SLee Jones return -EINVAL; 15281c6a0718SPierre Ossman } 15291c6a0718SPierre Ossman 1530b9b52918SLee Jones if (!plat) { 1531b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1532b9b52918SLee Jones if (!plat) 1533b9b52918SLee Jones return -ENOMEM; 1534b9b52918SLee Jones } 1535b9b52918SLee Jones 15361c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1537ef289982SUlf Hansson if (!mmc) 1538ef289982SUlf Hansson return -ENOMEM; 15391c6a0718SPierre Ossman 154078f87df2SUlf Hansson ret = mmci_of_parse(np, mmc); 154178f87df2SUlf Hansson if (ret) 154278f87df2SUlf Hansson goto host_free; 154378f87df2SUlf Hansson 15441c6a0718SPierre Ossman host = mmc_priv(mmc); 15454ea580f1SRabin Vincent host->mmc = mmc; 1546012b7d33SRussell King 1547012b7d33SRussell King host->hw_designer = amba_manf(dev); 1548012b7d33SRussell King host->hw_revision = amba_rev(dev); 154964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 155064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1551012b7d33SRussell King 1552665ba56fSUlf Hansson host->clk = devm_clk_get(&dev->dev, NULL); 15531c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 15541c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 15551c6a0718SPierre Ossman goto host_free; 15561c6a0718SPierre Ossman } 15571c6a0718SPierre Ossman 1558ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 15591c6a0718SPierre Ossman if (ret) 1560665ba56fSUlf Hansson goto host_free; 15611c6a0718SPierre Ossman 15629c34b73dSSrinivas Kandagatla if (variant->qcom_fifo) 15639c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 15649c34b73dSSrinivas Kandagatla else 15659c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_get_rx_fifocnt; 15669c34b73dSSrinivas Kandagatla 15671c6a0718SPierre Ossman host->plat = plat; 15684956e109SRabin Vincent host->variant = variant; 15691c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1570c8df9a53SLinus Walleij /* 1571c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1572c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1573c8df9a53SLinus Walleij * (if possible). 1574c8df9a53SLinus Walleij */ 1575dc6500bfSSrinivas Kandagatla if (host->mclk > variant->f_max) { 1576dc6500bfSSrinivas Kandagatla ret = clk_set_rate(host->clk, variant->f_max); 1577c8df9a53SLinus Walleij if (ret < 0) 1578c8df9a53SLinus Walleij goto clk_disable; 1579c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 158064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 158164de0289SLinus Walleij host->mclk); 1582c8df9a53SLinus Walleij } 1583ef289982SUlf Hansson 1584c8ebae37SRussell King host->phybase = dev->res.start; 1585ef289982SUlf Hansson host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1586ef289982SUlf Hansson if (IS_ERR(host->base)) { 1587ef289982SUlf Hansson ret = PTR_ERR(host->base); 15881c6a0718SPierre Ossman goto clk_disable; 15891c6a0718SPierre Ossman } 15901c6a0718SPierre Ossman 15917f294e49SLinus Walleij /* 15927f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 15937f294e49SLinus Walleij * clock divider equations which means that the minimum divider 15947f294e49SLinus Walleij * differs too. 15953f4e6f7bSSrinivas Kandagatla * on Qualcomm like controllers get the nearest minimum clock to 100Khz 15967f294e49SLinus Walleij */ 15977f294e49SLinus Walleij if (variant->st_clkdiv) 15987f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 15993f4e6f7bSSrinivas Kandagatla else if (variant->explicit_mclk_control) 16003f4e6f7bSSrinivas Kandagatla mmc->f_min = clk_round_rate(host->clk, 100000); 16017f294e49SLinus Walleij else 16027f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1603808d97ccSLinus Walleij /* 160478f87df2SUlf Hansson * If no maximum operating frequency is supplied, fall back to use 160578f87df2SUlf Hansson * the module parameter, which has a (low) default value in case it 160678f87df2SUlf Hansson * is not specified. Either value must not exceed the clock rate into 16075080a08dSUlf Hansson * the block, of course. 1608808d97ccSLinus Walleij */ 160978f87df2SUlf Hansson if (mmc->f_max) 16103f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16113f4e6f7bSSrinivas Kandagatla min(variant->f_max, mmc->f_max) : 16123f4e6f7bSSrinivas Kandagatla min(host->mclk, mmc->f_max); 1613808d97ccSLinus Walleij else 16143f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 16153f4e6f7bSSrinivas Kandagatla fmax : min(host->mclk, fmax); 16163f4e6f7bSSrinivas Kandagatla 16173f4e6f7bSSrinivas Kandagatla 161864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 161964de0289SLinus Walleij 1620599c1d5cSUlf Hansson /* Get regulators and the supported OCR mask */ 1621599c1d5cSUlf Hansson mmc_regulator_get_supply(mmc); 1622599c1d5cSUlf Hansson if (!mmc->ocr_avail) 16231c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 1624599c1d5cSUlf Hansson else if (plat->ocr_mask) 1625599c1d5cSUlf Hansson dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1626599c1d5cSUlf Hansson 162778f87df2SUlf Hansson /* DT takes precedence over platform data. */ 162878f87df2SUlf Hansson if (!np) { 1629d2762090SUlf Hansson if (!plat->cd_invert) 1630d2762090SUlf Hansson mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1631d2762090SUlf Hansson mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 163278f87df2SUlf Hansson } 16331c6a0718SPierre Ossman 16349dd8a8b8SUlf Hansson /* We support these capabilities. */ 16359dd8a8b8SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 16369dd8a8b8SUlf Hansson 16378d94b54dSUlf Hansson if (variant->busy_detect) { 16388d94b54dSUlf Hansson mmci_ops.card_busy = mmci_card_busy; 16398d94b54dSUlf Hansson mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 16408d94b54dSUlf Hansson mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 16418d94b54dSUlf Hansson mmc->max_busy_timeout = 0; 16428d94b54dSUlf Hansson } 16438d94b54dSUlf Hansson 16448d94b54dSUlf Hansson mmc->ops = &mmci_ops; 16458d94b54dSUlf Hansson 164670be208fSUlf Hansson /* We support these PM capabilities. */ 164778f87df2SUlf Hansson mmc->pm_caps |= MMC_PM_KEEP_POWER; 164870be208fSUlf Hansson 16491c6a0718SPierre Ossman /* 16501c6a0718SPierre Ossman * We can do SGIO 16511c6a0718SPierre Ossman */ 1652a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 16531c6a0718SPierre Ossman 16541c6a0718SPierre Ossman /* 165508458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 165608458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 165708458ef6SRabin Vincent * single request. 16581c6a0718SPierre Ossman */ 165908458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 16601c6a0718SPierre Ossman 16611c6a0718SPierre Ossman /* 16621c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 16631c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 16641c6a0718SPierre Ossman */ 16651c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 16661c6a0718SPierre Ossman 16671c6a0718SPierre Ossman /* 16681c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 16691c6a0718SPierre Ossman */ 16708f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 16711c6a0718SPierre Ossman 16721c6a0718SPierre Ossman /* 16738f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 16748f7f6b7eSWill Deacon * the maximum request size. 16751c6a0718SPierre Ossman */ 16768f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 16771c6a0718SPierre Ossman 16781c6a0718SPierre Ossman spin_lock_init(&host->lock); 16791c6a0718SPierre Ossman 16801c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 16811c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 16821c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 16831c6a0718SPierre Ossman 1684ce437aa4SLinus Walleij /* 1685ce437aa4SLinus Walleij * If: 1686ce437aa4SLinus Walleij * - not using DT but using a descriptor table, or 1687ce437aa4SLinus Walleij * - using a table of descriptors ALONGSIDE DT, or 1688ce437aa4SLinus Walleij * look up these descriptors named "cd" and "wp" right here, fail 1689ce437aa4SLinus Walleij * silently of these do not exist and proceed to try platform data 1690ce437aa4SLinus Walleij */ 1691ce437aa4SLinus Walleij if (!np) { 169289168b48SLinus Walleij ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1693ce437aa4SLinus Walleij if (ret < 0) { 1694ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1695ce437aa4SLinus Walleij goto clk_disable; 1696ce437aa4SLinus Walleij else if (gpio_is_valid(plat->gpio_cd)) { 1697d2762090SUlf Hansson ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1698d2762090SUlf Hansson if (ret) 1699ef289982SUlf Hansson goto clk_disable; 170089001446SRussell King } 1701ce437aa4SLinus Walleij } 1702ce437aa4SLinus Walleij 170389168b48SLinus Walleij ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1704ce437aa4SLinus Walleij if (ret < 0) { 1705ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 1706ce437aa4SLinus Walleij goto clk_disable; 1707ce437aa4SLinus Walleij else if (gpio_is_valid(plat->gpio_wp)) { 1708d2762090SUlf Hansson ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1709d2762090SUlf Hansson if (ret) 1710ef289982SUlf Hansson goto clk_disable; 171189001446SRussell King } 1712ce437aa4SLinus Walleij } 1713ce437aa4SLinus Walleij } 171489001446SRussell King 1715ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1716ef289982SUlf Hansson DRIVER_NAME " (cmd)", host); 17171c6a0718SPierre Ossman if (ret) 1718ef289982SUlf Hansson goto clk_disable; 17191c6a0718SPierre Ossman 1720dfb85185SRussell King if (!dev->irq[1]) 17212686b4b4SLinus Walleij host->singleirq = true; 17222686b4b4SLinus Walleij else { 1723ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1724ef289982SUlf Hansson IRQF_SHARED, DRIVER_NAME " (pio)", host); 17251c6a0718SPierre Ossman if (ret) 1726ef289982SUlf Hansson goto clk_disable; 17272686b4b4SLinus Walleij } 17281c6a0718SPierre Ossman 17298cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 17301c6a0718SPierre Ossman 17311c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 17321c6a0718SPierre Ossman 1733c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1734c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1735c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1736c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1737c8ebae37SRussell King 1738c8ebae37SRussell King mmci_dma_setup(host); 17391c6a0718SPierre Ossman 17402cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 17412cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 17421c3be369SRussell King 17438c11a94dSRussell King mmc_add_host(mmc); 17448c11a94dSRussell King 17456f2d3c89SUlf Hansson pm_runtime_put(&dev->dev); 17461c6a0718SPierre Ossman return 0; 17471c6a0718SPierre Ossman 17481c6a0718SPierre Ossman clk_disable: 1749ac940938SJulia Lawall clk_disable_unprepare(host->clk); 17501c6a0718SPierre Ossman host_free: 17511c6a0718SPierre Ossman mmc_free_host(mmc); 17521c6a0718SPierre Ossman return ret; 17531c6a0718SPierre Ossman } 17541c6a0718SPierre Ossman 17556e0ee714SBill Pemberton static int mmci_remove(struct amba_device *dev) 17561c6a0718SPierre Ossman { 17571c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 17581c6a0718SPierre Ossman 17591c6a0718SPierre Ossman if (mmc) { 17601c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 17611c6a0718SPierre Ossman 17621c3be369SRussell King /* 17631c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 17641c3be369SRussell King * version here so that we can access the primecell. 17651c3be369SRussell King */ 17661c3be369SRussell King pm_runtime_get_sync(&dev->dev); 17671c3be369SRussell King 17681c6a0718SPierre Ossman mmc_remove_host(mmc); 17691c6a0718SPierre Ossman 17701c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 17711c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 17721c6a0718SPierre Ossman 17731c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 17741c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 17751c6a0718SPierre Ossman 1776c8ebae37SRussell King mmci_dma_release(host); 1777ac940938SJulia Lawall clk_disable_unprepare(host->clk); 17781c6a0718SPierre Ossman mmc_free_host(mmc); 17791c6a0718SPierre Ossman } 17801c6a0718SPierre Ossman 17811c6a0718SPierre Ossman return 0; 17821c6a0718SPierre Ossman } 17831c6a0718SPierre Ossman 1784571dce4fSUlf Hansson #ifdef CONFIG_PM 17851ff44433SUlf Hansson static void mmci_save(struct mmci_host *host) 17861ff44433SUlf Hansson { 17871ff44433SUlf Hansson unsigned long flags; 17881ff44433SUlf Hansson 17891ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 17901ff44433SUlf Hansson 17911ff44433SUlf Hansson writel(0, host->base + MMCIMASK0); 179242dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 17931ff44433SUlf Hansson writel(0, host->base + MMCIDATACTRL); 17941ff44433SUlf Hansson writel(0, host->base + MMCIPOWER); 17951ff44433SUlf Hansson writel(0, host->base + MMCICLOCK); 179642dcc89aSUlf Hansson } 17971ff44433SUlf Hansson mmci_reg_delay(host); 17981ff44433SUlf Hansson 17991ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18001ff44433SUlf Hansson } 18011ff44433SUlf Hansson 18021ff44433SUlf Hansson static void mmci_restore(struct mmci_host *host) 18031ff44433SUlf Hansson { 18041ff44433SUlf Hansson unsigned long flags; 18051ff44433SUlf Hansson 18061ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18071ff44433SUlf Hansson 180842dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18091ff44433SUlf Hansson writel(host->clk_reg, host->base + MMCICLOCK); 18101ff44433SUlf Hansson writel(host->datactrl_reg, host->base + MMCIDATACTRL); 18111ff44433SUlf Hansson writel(host->pwr_reg, host->base + MMCIPOWER); 181242dcc89aSUlf Hansson } 18131ff44433SUlf Hansson writel(MCI_IRQENABLE, host->base + MMCIMASK0); 18141ff44433SUlf Hansson mmci_reg_delay(host); 18151ff44433SUlf Hansson 18161ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18171ff44433SUlf Hansson } 18181ff44433SUlf Hansson 18198259293aSUlf Hansson static int mmci_runtime_suspend(struct device *dev) 18208259293aSUlf Hansson { 18218259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18228259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18238259293aSUlf Hansson 18248259293aSUlf Hansson if (mmc) { 18258259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 1826e36bd9c6SUlf Hansson pinctrl_pm_select_sleep_state(dev); 18271ff44433SUlf Hansson mmci_save(host); 18288259293aSUlf Hansson clk_disable_unprepare(host->clk); 18298259293aSUlf Hansson } 18308259293aSUlf Hansson 18318259293aSUlf Hansson return 0; 18328259293aSUlf Hansson } 18338259293aSUlf Hansson 18348259293aSUlf Hansson static int mmci_runtime_resume(struct device *dev) 18358259293aSUlf Hansson { 18368259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18378259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18388259293aSUlf Hansson 18398259293aSUlf Hansson if (mmc) { 18408259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 18418259293aSUlf Hansson clk_prepare_enable(host->clk); 18421ff44433SUlf Hansson mmci_restore(host); 1843e36bd9c6SUlf Hansson pinctrl_pm_select_default_state(dev); 18448259293aSUlf Hansson } 18458259293aSUlf Hansson 18468259293aSUlf Hansson return 0; 18478259293aSUlf Hansson } 18488259293aSUlf Hansson #endif 18498259293aSUlf Hansson 185048fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 1851f3737fa3SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1852f3737fa3SUlf Hansson pm_runtime_force_resume) 18536ed23b80SRafael J. Wysocki SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 185448fa7003SUlf Hansson }; 185548fa7003SUlf Hansson 18561c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 18571c6a0718SPierre Ossman { 18581c6a0718SPierre Ossman .id = 0x00041180, 1859768fbc18SPawel Moll .mask = 0xff0fffff, 18604956e109SRabin Vincent .data = &variant_arm, 18611c6a0718SPierre Ossman }, 18621c6a0718SPierre Ossman { 1863768fbc18SPawel Moll .id = 0x01041180, 1864768fbc18SPawel Moll .mask = 0xff0fffff, 1865768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1866768fbc18SPawel Moll }, 1867768fbc18SPawel Moll { 18683a37298aSPawel Moll .id = 0x02041180, 18693a37298aSPawel Moll .mask = 0xff0fffff, 18703a37298aSPawel Moll .data = &variant_arm_extended_fifo_hwfc, 18713a37298aSPawel Moll }, 18723a37298aSPawel Moll { 18731c6a0718SPierre Ossman .id = 0x00041181, 18741c6a0718SPierre Ossman .mask = 0x000fffff, 18754956e109SRabin Vincent .data = &variant_arm, 18761c6a0718SPierre Ossman }, 1877cc30d60eSLinus Walleij /* ST Micro variants */ 1878cc30d60eSLinus Walleij { 1879cc30d60eSLinus Walleij .id = 0x00180180, 1880cc30d60eSLinus Walleij .mask = 0x00ffffff, 18814956e109SRabin Vincent .data = &variant_u300, 1882cc30d60eSLinus Walleij }, 1883cc30d60eSLinus Walleij { 188434fd4213SLinus Walleij .id = 0x10180180, 188534fd4213SLinus Walleij .mask = 0xf0ffffff, 188634fd4213SLinus Walleij .data = &variant_nomadik, 188734fd4213SLinus Walleij }, 188834fd4213SLinus Walleij { 1889cc30d60eSLinus Walleij .id = 0x00280180, 1890cc30d60eSLinus Walleij .mask = 0x00ffffff, 18914956e109SRabin Vincent .data = &variant_u300, 18924956e109SRabin Vincent }, 18934956e109SRabin Vincent { 18944956e109SRabin Vincent .id = 0x00480180, 18951784b157SPhilippe Langlais .mask = 0xf0ffffff, 18964956e109SRabin Vincent .data = &variant_ux500, 1897cc30d60eSLinus Walleij }, 18981784b157SPhilippe Langlais { 18991784b157SPhilippe Langlais .id = 0x10480180, 19001784b157SPhilippe Langlais .mask = 0xf0ffffff, 19011784b157SPhilippe Langlais .data = &variant_ux500v2, 19021784b157SPhilippe Langlais }, 190355b604aeSSrinivas Kandagatla /* Qualcomm variants */ 190455b604aeSSrinivas Kandagatla { 190555b604aeSSrinivas Kandagatla .id = 0x00051180, 190655b604aeSSrinivas Kandagatla .mask = 0x000fffff, 190755b604aeSSrinivas Kandagatla .data = &variant_qcom, 190855b604aeSSrinivas Kandagatla }, 19091c6a0718SPierre Ossman { 0, 0 }, 19101c6a0718SPierre Ossman }; 19111c6a0718SPierre Ossman 19129f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 19139f99835fSDave Martin 19141c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 19151c6a0718SPierre Ossman .drv = { 19161c6a0718SPierre Ossman .name = DRIVER_NAME, 191748fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 19181c6a0718SPierre Ossman }, 19191c6a0718SPierre Ossman .probe = mmci_probe, 19200433c143SBill Pemberton .remove = mmci_remove, 19211c6a0718SPierre Ossman .id_table = mmci_ids, 19221c6a0718SPierre Ossman }; 19231c6a0718SPierre Ossman 19249e5ed094Sviresh kumar module_amba_driver(mmci_driver); 19251c6a0718SPierre Ossman 19261c6a0718SPierre Ossman module_param(fmax, uint, 0444); 19271c6a0718SPierre Ossman 19281c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 19291c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1930