11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 81c6a0718SPierre Ossman * published by the Free Software Foundation. 91c6a0718SPierre Ossman */ 101c6a0718SPierre Ossman #include <linux/module.h> 111c6a0718SPierre Ossman #include <linux/moduleparam.h> 121c6a0718SPierre Ossman #include <linux/init.h> 131c6a0718SPierre Ossman #include <linux/ioport.h> 141c6a0718SPierre Ossman #include <linux/device.h> 151c6a0718SPierre Ossman #include <linux/interrupt.h> 161c6a0718SPierre Ossman #include <linux/delay.h> 171c6a0718SPierre Ossman #include <linux/err.h> 181c6a0718SPierre Ossman #include <linux/highmem.h> 19019a5f56SNicolas Pitre #include <linux/log2.h> 201c6a0718SPierre Ossman #include <linux/mmc/host.h> 211c6a0718SPierre Ossman #include <linux/amba/bus.h> 221c6a0718SPierre Ossman #include <linux/clk.h> 23bd6dee6fSJens Axboe #include <linux/scatterlist.h> 241c6a0718SPierre Ossman 251c6a0718SPierre Ossman #include <asm/cacheflush.h> 261c6a0718SPierre Ossman #include <asm/div64.h> 271c6a0718SPierre Ossman #include <asm/io.h> 281c6a0718SPierre Ossman #include <asm/sizes.h> 291c6a0718SPierre Ossman #include <asm/mach/mmc.h> 301c6a0718SPierre Ossman 311c6a0718SPierre Ossman #include "mmci.h" 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define DBG(host,fmt,args...) \ 361c6a0718SPierre Ossman pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args) 371c6a0718SPierre Ossman 381c6a0718SPierre Ossman static unsigned int fmax = 515633; 391c6a0718SPierre Ossman 401c6a0718SPierre Ossman static void 411c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 421c6a0718SPierre Ossman { 431c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman BUG_ON(host->data); 461c6a0718SPierre Ossman 471c6a0718SPierre Ossman host->mrq = NULL; 481c6a0718SPierre Ossman host->cmd = NULL; 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman if (mrq->data) 511c6a0718SPierre Ossman mrq->data->bytes_xfered = host->data_xfered; 521c6a0718SPierre Ossman 531c6a0718SPierre Ossman /* 541c6a0718SPierre Ossman * Need to drop the host lock here; mmc_request_done may call 551c6a0718SPierre Ossman * back into the driver... 561c6a0718SPierre Ossman */ 571c6a0718SPierre Ossman spin_unlock(&host->lock); 581c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 591c6a0718SPierre Ossman spin_lock(&host->lock); 601c6a0718SPierre Ossman } 611c6a0718SPierre Ossman 621c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 631c6a0718SPierre Ossman { 641c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 651c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 661c6a0718SPierre Ossman host->data = NULL; 671c6a0718SPierre Ossman } 681c6a0718SPierre Ossman 691c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 701c6a0718SPierre Ossman { 711c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 721c6a0718SPierre Ossman unsigned long long clks; 731c6a0718SPierre Ossman void __iomem *base; 741c6a0718SPierre Ossman int blksz_bits; 751c6a0718SPierre Ossman 761c6a0718SPierre Ossman DBG(host, "blksz %04x blks %04x flags %08x\n", 771c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 781c6a0718SPierre Ossman 791c6a0718SPierre Ossman host->data = data; 801c6a0718SPierre Ossman host->size = data->blksz; 811c6a0718SPierre Ossman host->data_xfered = 0; 821c6a0718SPierre Ossman 831c6a0718SPierre Ossman mmci_init_sg(host, data); 841c6a0718SPierre Ossman 851c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 861c6a0718SPierre Ossman do_div(clks, 1000000000UL); 871c6a0718SPierre Ossman 881c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 891c6a0718SPierre Ossman 901c6a0718SPierre Ossman base = host->base; 911c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 921c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 931c6a0718SPierre Ossman 941c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 951c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 961c6a0718SPierre Ossman 971c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 981c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) { 991c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 1001c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 1011c6a0718SPierre Ossman 1021c6a0718SPierre Ossman /* 1031c6a0718SPierre Ossman * If we have less than a FIFOSIZE of bytes to transfer, 1041c6a0718SPierre Ossman * trigger a PIO interrupt as soon as any data is available. 1051c6a0718SPierre Ossman */ 1061c6a0718SPierre Ossman if (host->size < MCI_FIFOSIZE) 1071c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 1081c6a0718SPierre Ossman } else { 1091c6a0718SPierre Ossman /* 1101c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 1111c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 1121c6a0718SPierre Ossman */ 1131c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 1141c6a0718SPierre Ossman } 1151c6a0718SPierre Ossman 1161c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 1171c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1181c6a0718SPierre Ossman writel(irqmask, base + MMCIMASK1); 1191c6a0718SPierre Ossman } 1201c6a0718SPierre Ossman 1211c6a0718SPierre Ossman static void 1221c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1231c6a0718SPierre Ossman { 1241c6a0718SPierre Ossman void __iomem *base = host->base; 1251c6a0718SPierre Ossman 1261c6a0718SPierre Ossman DBG(host, "op %02x arg %08x flags %08x\n", 1271c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 1281c6a0718SPierre Ossman 1291c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 1301c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 1311c6a0718SPierre Ossman udelay(1); 1321c6a0718SPierre Ossman } 1331c6a0718SPierre Ossman 1341c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 1351c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 1361c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 1371c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 1381c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 1391c6a0718SPierre Ossman } 1401c6a0718SPierre Ossman if (/*interrupt*/0) 1411c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 1421c6a0718SPierre Ossman 1431c6a0718SPierre Ossman host->cmd = cmd; 1441c6a0718SPierre Ossman 1451c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 1461c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 1471c6a0718SPierre Ossman } 1481c6a0718SPierre Ossman 1491c6a0718SPierre Ossman static void 1501c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1511c6a0718SPierre Ossman unsigned int status) 1521c6a0718SPierre Ossman { 1531c6a0718SPierre Ossman if (status & MCI_DATABLOCKEND) { 1541c6a0718SPierre Ossman host->data_xfered += data->blksz; 1551c6a0718SPierre Ossman } 1561c6a0718SPierre Ossman if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 1571c6a0718SPierre Ossman if (status & MCI_DATACRCFAIL) 15817b0429dSPierre Ossman data->error = -EILSEQ; 1591c6a0718SPierre Ossman else if (status & MCI_DATATIMEOUT) 16017b0429dSPierre Ossman data->error = -ETIMEDOUT; 1611c6a0718SPierre Ossman else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) 16217b0429dSPierre Ossman data->error = -EIO; 1631c6a0718SPierre Ossman status |= MCI_DATAEND; 1641c6a0718SPierre Ossman 1651c6a0718SPierre Ossman /* 1661c6a0718SPierre Ossman * We hit an error condition. Ensure that any data 1671c6a0718SPierre Ossman * partially written to a page is properly coherent. 1681c6a0718SPierre Ossman */ 1691c6a0718SPierre Ossman if (host->sg_len && data->flags & MMC_DATA_READ) 170bd6dee6fSJens Axboe flush_dcache_page(sg_page(host->sg_ptr)); 1711c6a0718SPierre Ossman } 1721c6a0718SPierre Ossman if (status & MCI_DATAEND) { 1731c6a0718SPierre Ossman mmci_stop_data(host); 1741c6a0718SPierre Ossman 1751c6a0718SPierre Ossman if (!data->stop) { 1761c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 1771c6a0718SPierre Ossman } else { 1781c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 1791c6a0718SPierre Ossman } 1801c6a0718SPierre Ossman } 1811c6a0718SPierre Ossman } 1821c6a0718SPierre Ossman 1831c6a0718SPierre Ossman static void 1841c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1851c6a0718SPierre Ossman unsigned int status) 1861c6a0718SPierre Ossman { 1871c6a0718SPierre Ossman void __iomem *base = host->base; 1881c6a0718SPierre Ossman 1891c6a0718SPierre Ossman host->cmd = NULL; 1901c6a0718SPierre Ossman 1911c6a0718SPierre Ossman cmd->resp[0] = readl(base + MMCIRESPONSE0); 1921c6a0718SPierre Ossman cmd->resp[1] = readl(base + MMCIRESPONSE1); 1931c6a0718SPierre Ossman cmd->resp[2] = readl(base + MMCIRESPONSE2); 1941c6a0718SPierre Ossman cmd->resp[3] = readl(base + MMCIRESPONSE3); 1951c6a0718SPierre Ossman 1961c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 19717b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 1981c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 19917b0429dSPierre Ossman cmd->error = -EILSEQ; 2001c6a0718SPierre Ossman } 2011c6a0718SPierre Ossman 20217b0429dSPierre Ossman if (!cmd->data || cmd->error) { 2031c6a0718SPierre Ossman if (host->data) 2041c6a0718SPierre Ossman mmci_stop_data(host); 2051c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 2061c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 2071c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 2081c6a0718SPierre Ossman } 2091c6a0718SPierre Ossman } 2101c6a0718SPierre Ossman 2111c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 2121c6a0718SPierre Ossman { 2131c6a0718SPierre Ossman void __iomem *base = host->base; 2141c6a0718SPierre Ossman char *ptr = buffer; 2151c6a0718SPierre Ossman u32 status; 21626eed9a5SLinus Walleij int host_remain = host->size; 2171c6a0718SPierre Ossman 2181c6a0718SPierre Ossman do { 21926eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 2201c6a0718SPierre Ossman 2211c6a0718SPierre Ossman if (count > remain) 2221c6a0718SPierre Ossman count = remain; 2231c6a0718SPierre Ossman 2241c6a0718SPierre Ossman if (count <= 0) 2251c6a0718SPierre Ossman break; 2261c6a0718SPierre Ossman 2271c6a0718SPierre Ossman readsl(base + MMCIFIFO, ptr, count >> 2); 2281c6a0718SPierre Ossman 2291c6a0718SPierre Ossman ptr += count; 2301c6a0718SPierre Ossman remain -= count; 23126eed9a5SLinus Walleij host_remain -= count; 2321c6a0718SPierre Ossman 2331c6a0718SPierre Ossman if (remain == 0) 2341c6a0718SPierre Ossman break; 2351c6a0718SPierre Ossman 2361c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 2371c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 2381c6a0718SPierre Ossman 2391c6a0718SPierre Ossman return ptr - buffer; 2401c6a0718SPierre Ossman } 2411c6a0718SPierre Ossman 2421c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 2431c6a0718SPierre Ossman { 2441c6a0718SPierre Ossman void __iomem *base = host->base; 2451c6a0718SPierre Ossman char *ptr = buffer; 2461c6a0718SPierre Ossman 2471c6a0718SPierre Ossman do { 2481c6a0718SPierre Ossman unsigned int count, maxcnt; 2491c6a0718SPierre Ossman 2501c6a0718SPierre Ossman maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; 2511c6a0718SPierre Ossman count = min(remain, maxcnt); 2521c6a0718SPierre Ossman 2531c6a0718SPierre Ossman writesl(base + MMCIFIFO, ptr, count >> 2); 2541c6a0718SPierre Ossman 2551c6a0718SPierre Ossman ptr += count; 2561c6a0718SPierre Ossman remain -= count; 2571c6a0718SPierre Ossman 2581c6a0718SPierre Ossman if (remain == 0) 2591c6a0718SPierre Ossman break; 2601c6a0718SPierre Ossman 2611c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 2621c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 2631c6a0718SPierre Ossman 2641c6a0718SPierre Ossman return ptr - buffer; 2651c6a0718SPierre Ossman } 2661c6a0718SPierre Ossman 2671c6a0718SPierre Ossman /* 2681c6a0718SPierre Ossman * PIO data transfer IRQ handler. 2691c6a0718SPierre Ossman */ 2701c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 2711c6a0718SPierre Ossman { 2721c6a0718SPierre Ossman struct mmci_host *host = dev_id; 2731c6a0718SPierre Ossman void __iomem *base = host->base; 2741c6a0718SPierre Ossman u32 status; 2751c6a0718SPierre Ossman 2761c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 2771c6a0718SPierre Ossman 2781c6a0718SPierre Ossman DBG(host, "irq1 %08x\n", status); 2791c6a0718SPierre Ossman 2801c6a0718SPierre Ossman do { 2811c6a0718SPierre Ossman unsigned long flags; 2821c6a0718SPierre Ossman unsigned int remain, len; 2831c6a0718SPierre Ossman char *buffer; 2841c6a0718SPierre Ossman 2851c6a0718SPierre Ossman /* 2861c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 2871c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 2881c6a0718SPierre Ossman * definition it is more than half empty. 2891c6a0718SPierre Ossman * 2901c6a0718SPierre Ossman * For read, check for data available. 2911c6a0718SPierre Ossman */ 2921c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 2931c6a0718SPierre Ossman break; 2941c6a0718SPierre Ossman 2951c6a0718SPierre Ossman /* 2961c6a0718SPierre Ossman * Map the current scatter buffer. 2971c6a0718SPierre Ossman */ 2981c6a0718SPierre Ossman buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; 2991c6a0718SPierre Ossman remain = host->sg_ptr->length - host->sg_off; 3001c6a0718SPierre Ossman 3011c6a0718SPierre Ossman len = 0; 3021c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 3031c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 3041c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 3051c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 3061c6a0718SPierre Ossman 3071c6a0718SPierre Ossman /* 3081c6a0718SPierre Ossman * Unmap the buffer. 3091c6a0718SPierre Ossman */ 3101c6a0718SPierre Ossman mmci_kunmap_atomic(host, buffer, &flags); 3111c6a0718SPierre Ossman 3121c6a0718SPierre Ossman host->sg_off += len; 3131c6a0718SPierre Ossman host->size -= len; 3141c6a0718SPierre Ossman remain -= len; 3151c6a0718SPierre Ossman 3161c6a0718SPierre Ossman if (remain) 3171c6a0718SPierre Ossman break; 3181c6a0718SPierre Ossman 3191c6a0718SPierre Ossman /* 3201c6a0718SPierre Ossman * If we were reading, and we have completed this 3211c6a0718SPierre Ossman * page, ensure that the data cache is coherent. 3221c6a0718SPierre Ossman */ 3231c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 324bd6dee6fSJens Axboe flush_dcache_page(sg_page(host->sg_ptr)); 3251c6a0718SPierre Ossman 3261c6a0718SPierre Ossman if (!mmci_next_sg(host)) 3271c6a0718SPierre Ossman break; 3281c6a0718SPierre Ossman 3291c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 3301c6a0718SPierre Ossman } while (1); 3311c6a0718SPierre Ossman 3321c6a0718SPierre Ossman /* 3331c6a0718SPierre Ossman * If we're nearing the end of the read, switch to 3341c6a0718SPierre Ossman * "any data available" mode. 3351c6a0718SPierre Ossman */ 3361c6a0718SPierre Ossman if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) 3371c6a0718SPierre Ossman writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); 3381c6a0718SPierre Ossman 3391c6a0718SPierre Ossman /* 3401c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 3411c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 3421c6a0718SPierre Ossman * the chip itself has disabled the data path, and 3431c6a0718SPierre Ossman * stops us racing with our data end IRQ. 3441c6a0718SPierre Ossman */ 3451c6a0718SPierre Ossman if (host->size == 0) { 3461c6a0718SPierre Ossman writel(0, base + MMCIMASK1); 3471c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 3481c6a0718SPierre Ossman } 3491c6a0718SPierre Ossman 3501c6a0718SPierre Ossman return IRQ_HANDLED; 3511c6a0718SPierre Ossman } 3521c6a0718SPierre Ossman 3531c6a0718SPierre Ossman /* 3541c6a0718SPierre Ossman * Handle completion of command and data transfers. 3551c6a0718SPierre Ossman */ 3561c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 3571c6a0718SPierre Ossman { 3581c6a0718SPierre Ossman struct mmci_host *host = dev_id; 3591c6a0718SPierre Ossman u32 status; 3601c6a0718SPierre Ossman int ret = 0; 3611c6a0718SPierre Ossman 3621c6a0718SPierre Ossman spin_lock(&host->lock); 3631c6a0718SPierre Ossman 3641c6a0718SPierre Ossman do { 3651c6a0718SPierre Ossman struct mmc_command *cmd; 3661c6a0718SPierre Ossman struct mmc_data *data; 3671c6a0718SPierre Ossman 3681c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 3691c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 3701c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 3711c6a0718SPierre Ossman 3721c6a0718SPierre Ossman DBG(host, "irq0 %08x\n", status); 3731c6a0718SPierre Ossman 3741c6a0718SPierre Ossman data = host->data; 3751c6a0718SPierre Ossman if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 3761c6a0718SPierre Ossman MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 3771c6a0718SPierre Ossman mmci_data_irq(host, data, status); 3781c6a0718SPierre Ossman 3791c6a0718SPierre Ossman cmd = host->cmd; 3801c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 3811c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 3821c6a0718SPierre Ossman 3831c6a0718SPierre Ossman ret = 1; 3841c6a0718SPierre Ossman } while (status); 3851c6a0718SPierre Ossman 3861c6a0718SPierre Ossman spin_unlock(&host->lock); 3871c6a0718SPierre Ossman 3881c6a0718SPierre Ossman return IRQ_RETVAL(ret); 3891c6a0718SPierre Ossman } 3901c6a0718SPierre Ossman 3911c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 3921c6a0718SPierre Ossman { 3931c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 3949e943021SLinus Walleij unsigned long flags; 3951c6a0718SPierre Ossman 3961c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 3971c6a0718SPierre Ossman 398019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 399255d01afSPierre Ossman printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n", 400255d01afSPierre Ossman mmc_hostname(mmc), mrq->data->blksz); 401255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 402255d01afSPierre Ossman mmc_request_done(mmc, mrq); 403255d01afSPierre Ossman return; 404255d01afSPierre Ossman } 405255d01afSPierre Ossman 4069e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 4071c6a0718SPierre Ossman 4081c6a0718SPierre Ossman host->mrq = mrq; 4091c6a0718SPierre Ossman 4101c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 4111c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 4121c6a0718SPierre Ossman 4131c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 4141c6a0718SPierre Ossman 4159e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 4161c6a0718SPierre Ossman } 4171c6a0718SPierre Ossman 4181c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 4191c6a0718SPierre Ossman { 4201c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 4211c6a0718SPierre Ossman u32 clk = 0, pwr = 0; 4221c6a0718SPierre Ossman 4231c6a0718SPierre Ossman if (ios->clock) { 4241c6a0718SPierre Ossman if (ios->clock >= host->mclk) { 4251c6a0718SPierre Ossman clk = MCI_CLK_BYPASS; 4261c6a0718SPierre Ossman host->cclk = host->mclk; 4271c6a0718SPierre Ossman } else { 4281c6a0718SPierre Ossman clk = host->mclk / (2 * ios->clock) - 1; 429c8df9a53SLinus Walleij if (clk >= 256) 4301c6a0718SPierre Ossman clk = 255; 4311c6a0718SPierre Ossman host->cclk = host->mclk / (2 * (clk + 1)); 4321c6a0718SPierre Ossman } 433cc30d60eSLinus Walleij if (host->hw_designer == 0x80) 434cc30d60eSLinus Walleij clk |= MCI_FCEN; /* Bug fix in ST IP block */ 4351c6a0718SPierre Ossman clk |= MCI_CLK_ENABLE; 4361c6a0718SPierre Ossman } 4371c6a0718SPierre Ossman 4381c6a0718SPierre Ossman if (host->plat->translate_vdd) 4391c6a0718SPierre Ossman pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); 4401c6a0718SPierre Ossman 4411c6a0718SPierre Ossman switch (ios->power_mode) { 4421c6a0718SPierre Ossman case MMC_POWER_OFF: 4431c6a0718SPierre Ossman break; 4441c6a0718SPierre Ossman case MMC_POWER_UP: 445cc30d60eSLinus Walleij /* The ST version does not have this, fall through to POWER_ON */ 446cc30d60eSLinus Walleij if (host->hw_designer != 0x80) { 4471c6a0718SPierre Ossman pwr |= MCI_PWR_UP; 4481c6a0718SPierre Ossman break; 449cc30d60eSLinus Walleij } 4501c6a0718SPierre Ossman case MMC_POWER_ON: 4511c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 4521c6a0718SPierre Ossman break; 4531c6a0718SPierre Ossman } 4541c6a0718SPierre Ossman 455cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 456cc30d60eSLinus Walleij if (host->hw_designer != 0x80) 4571c6a0718SPierre Ossman pwr |= MCI_ROD; 458cc30d60eSLinus Walleij else { 459cc30d60eSLinus Walleij /* 460cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 461cc30d60eSLinus Walleij * else and only has OD (Open Drain). 462cc30d60eSLinus Walleij */ 463cc30d60eSLinus Walleij pwr |= MCI_OD; 464cc30d60eSLinus Walleij } 465cc30d60eSLinus Walleij } 4661c6a0718SPierre Ossman 4671c6a0718SPierre Ossman writel(clk, host->base + MMCICLOCK); 4681c6a0718SPierre Ossman 4691c6a0718SPierre Ossman if (host->pwr != pwr) { 4701c6a0718SPierre Ossman host->pwr = pwr; 4711c6a0718SPierre Ossman writel(pwr, host->base + MMCIPOWER); 4721c6a0718SPierre Ossman } 4731c6a0718SPierre Ossman } 4741c6a0718SPierre Ossman 4751c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 4761c6a0718SPierre Ossman .request = mmci_request, 4771c6a0718SPierre Ossman .set_ios = mmci_set_ios, 4781c6a0718SPierre Ossman }; 4791c6a0718SPierre Ossman 4801c6a0718SPierre Ossman static void mmci_check_status(unsigned long data) 4811c6a0718SPierre Ossman { 4821c6a0718SPierre Ossman struct mmci_host *host = (struct mmci_host *)data; 4831c6a0718SPierre Ossman unsigned int status; 4841c6a0718SPierre Ossman 4851c6a0718SPierre Ossman status = host->plat->status(mmc_dev(host->mmc)); 4861c6a0718SPierre Ossman if (status ^ host->oldstat) 4871c6a0718SPierre Ossman mmc_detect_change(host->mmc, 0); 4881c6a0718SPierre Ossman 4891c6a0718SPierre Ossman host->oldstat = status; 4901c6a0718SPierre Ossman mod_timer(&host->timer, jiffies + HZ); 4911c6a0718SPierre Ossman } 4921c6a0718SPierre Ossman 4936dc4a47aSLinus Walleij static int __devinit mmci_probe(struct amba_device *dev, void *id) 4941c6a0718SPierre Ossman { 4951c6a0718SPierre Ossman struct mmc_platform_data *plat = dev->dev.platform_data; 4961c6a0718SPierre Ossman struct mmci_host *host; 4971c6a0718SPierre Ossman struct mmc_host *mmc; 4981c6a0718SPierre Ossman int ret; 4991c6a0718SPierre Ossman 5001c6a0718SPierre Ossman /* must have platform data */ 5011c6a0718SPierre Ossman if (!plat) { 5021c6a0718SPierre Ossman ret = -EINVAL; 5031c6a0718SPierre Ossman goto out; 5041c6a0718SPierre Ossman } 5051c6a0718SPierre Ossman 5061c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 5071c6a0718SPierre Ossman if (ret) 5081c6a0718SPierre Ossman goto out; 5091c6a0718SPierre Ossman 5101c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 5111c6a0718SPierre Ossman if (!mmc) { 5121c6a0718SPierre Ossman ret = -ENOMEM; 5131c6a0718SPierre Ossman goto rel_regions; 5141c6a0718SPierre Ossman } 5151c6a0718SPierre Ossman 5161c6a0718SPierre Ossman host = mmc_priv(mmc); 517cc30d60eSLinus Walleij /* Bits 12 thru 19 is the designer */ 518cc30d60eSLinus Walleij host->hw_designer = (dev->periphid >> 12) & 0xff; 519cc30d60eSLinus Walleij /* Bits 20 thru 23 is the revison */ 520cc30d60eSLinus Walleij host->hw_revision = (dev->periphid >> 20) & 0xf; 521cc30d60eSLinus Walleij DBG(host, "designer ID = 0x%02x\n", host->hw_designer); 522cc30d60eSLinus Walleij DBG(host, "revision = 0x%01x\n", host->hw_revision); 523ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 5241c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 5251c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 5261c6a0718SPierre Ossman host->clk = NULL; 5271c6a0718SPierre Ossman goto host_free; 5281c6a0718SPierre Ossman } 5291c6a0718SPierre Ossman 5301c6a0718SPierre Ossman ret = clk_enable(host->clk); 5311c6a0718SPierre Ossman if (ret) 5321c6a0718SPierre Ossman goto clk_free; 5331c6a0718SPierre Ossman 5341c6a0718SPierre Ossman host->plat = plat; 5351c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 536c8df9a53SLinus Walleij /* 537c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 538c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 539c8df9a53SLinus Walleij * (if possible). 540c8df9a53SLinus Walleij */ 541c8df9a53SLinus Walleij if (host->mclk > 100000000) { 542c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 543c8df9a53SLinus Walleij if (ret < 0) 544c8df9a53SLinus Walleij goto clk_disable; 545c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 546c8df9a53SLinus Walleij DBG(host, "eventual mclk rate: %u Hz\n", host->mclk); 547c8df9a53SLinus Walleij } 5481c6a0718SPierre Ossman host->mmc = mmc; 5491c6a0718SPierre Ossman host->base = ioremap(dev->res.start, SZ_4K); 5501c6a0718SPierre Ossman if (!host->base) { 5511c6a0718SPierre Ossman ret = -ENOMEM; 5521c6a0718SPierre Ossman goto clk_disable; 5531c6a0718SPierre Ossman } 5541c6a0718SPierre Ossman 5551c6a0718SPierre Ossman mmc->ops = &mmci_ops; 5561c6a0718SPierre Ossman mmc->f_min = (host->mclk + 511) / 512; 5571c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 5581c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 5591c6a0718SPierre Ossman 5601c6a0718SPierre Ossman /* 5611c6a0718SPierre Ossman * We can do SGIO 5621c6a0718SPierre Ossman */ 5631c6a0718SPierre Ossman mmc->max_hw_segs = 16; 5641c6a0718SPierre Ossman mmc->max_phys_segs = NR_SG; 5651c6a0718SPierre Ossman 5661c6a0718SPierre Ossman /* 5671c6a0718SPierre Ossman * Since we only have a 16-bit data length register, we must 5681c6a0718SPierre Ossman * ensure that we don't exceed 2^16-1 bytes in a single request. 5691c6a0718SPierre Ossman */ 5701c6a0718SPierre Ossman mmc->max_req_size = 65535; 5711c6a0718SPierre Ossman 5721c6a0718SPierre Ossman /* 5731c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 5741c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 5751c6a0718SPierre Ossman */ 5761c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 5771c6a0718SPierre Ossman 5781c6a0718SPierre Ossman /* 5791c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 5801c6a0718SPierre Ossman */ 5811c6a0718SPierre Ossman mmc->max_blk_size = 2048; 5821c6a0718SPierre Ossman 5831c6a0718SPierre Ossman /* 5841c6a0718SPierre Ossman * No limit on the number of blocks transferred. 5851c6a0718SPierre Ossman */ 5861c6a0718SPierre Ossman mmc->max_blk_count = mmc->max_req_size; 5871c6a0718SPierre Ossman 5881c6a0718SPierre Ossman spin_lock_init(&host->lock); 5891c6a0718SPierre Ossman 5901c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 5911c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 5921c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 5931c6a0718SPierre Ossman 5941c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 5951c6a0718SPierre Ossman if (ret) 5961c6a0718SPierre Ossman goto unmap; 5971c6a0718SPierre Ossman 5981c6a0718SPierre Ossman ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); 5991c6a0718SPierre Ossman if (ret) 6001c6a0718SPierre Ossman goto irq0_free; 6011c6a0718SPierre Ossman 6021c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 6031c6a0718SPierre Ossman 6041c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 6051c6a0718SPierre Ossman 6061c6a0718SPierre Ossman mmc_add_host(mmc); 6071c6a0718SPierre Ossman 6081c6a0718SPierre Ossman printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", 6091c6a0718SPierre Ossman mmc_hostname(mmc), amba_rev(dev), amba_config(dev), 6101c6a0718SPierre Ossman (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 6111c6a0718SPierre Ossman 6121c6a0718SPierre Ossman init_timer(&host->timer); 6131c6a0718SPierre Ossman host->timer.data = (unsigned long)host; 6141c6a0718SPierre Ossman host->timer.function = mmci_check_status; 6151c6a0718SPierre Ossman host->timer.expires = jiffies + HZ; 6161c6a0718SPierre Ossman add_timer(&host->timer); 6171c6a0718SPierre Ossman 6181c6a0718SPierre Ossman return 0; 6191c6a0718SPierre Ossman 6201c6a0718SPierre Ossman irq0_free: 6211c6a0718SPierre Ossman free_irq(dev->irq[0], host); 6221c6a0718SPierre Ossman unmap: 6231c6a0718SPierre Ossman iounmap(host->base); 6241c6a0718SPierre Ossman clk_disable: 6251c6a0718SPierre Ossman clk_disable(host->clk); 6261c6a0718SPierre Ossman clk_free: 6271c6a0718SPierre Ossman clk_put(host->clk); 6281c6a0718SPierre Ossman host_free: 6291c6a0718SPierre Ossman mmc_free_host(mmc); 6301c6a0718SPierre Ossman rel_regions: 6311c6a0718SPierre Ossman amba_release_regions(dev); 6321c6a0718SPierre Ossman out: 6331c6a0718SPierre Ossman return ret; 6341c6a0718SPierre Ossman } 6351c6a0718SPierre Ossman 6366dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 6371c6a0718SPierre Ossman { 6381c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 6391c6a0718SPierre Ossman 6401c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 6411c6a0718SPierre Ossman 6421c6a0718SPierre Ossman if (mmc) { 6431c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 6441c6a0718SPierre Ossman 6451c6a0718SPierre Ossman del_timer_sync(&host->timer); 6461c6a0718SPierre Ossman 6471c6a0718SPierre Ossman mmc_remove_host(mmc); 6481c6a0718SPierre Ossman 6491c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 6501c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 6511c6a0718SPierre Ossman 6521c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 6531c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 6541c6a0718SPierre Ossman 6551c6a0718SPierre Ossman free_irq(dev->irq[0], host); 6561c6a0718SPierre Ossman free_irq(dev->irq[1], host); 6571c6a0718SPierre Ossman 6581c6a0718SPierre Ossman iounmap(host->base); 6591c6a0718SPierre Ossman clk_disable(host->clk); 6601c6a0718SPierre Ossman clk_put(host->clk); 6611c6a0718SPierre Ossman 6621c6a0718SPierre Ossman mmc_free_host(mmc); 6631c6a0718SPierre Ossman 6641c6a0718SPierre Ossman amba_release_regions(dev); 6651c6a0718SPierre Ossman } 6661c6a0718SPierre Ossman 6671c6a0718SPierre Ossman return 0; 6681c6a0718SPierre Ossman } 6691c6a0718SPierre Ossman 6701c6a0718SPierre Ossman #ifdef CONFIG_PM 6711c6a0718SPierre Ossman static int mmci_suspend(struct amba_device *dev, pm_message_t state) 6721c6a0718SPierre Ossman { 6731c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 6741c6a0718SPierre Ossman int ret = 0; 6751c6a0718SPierre Ossman 6761c6a0718SPierre Ossman if (mmc) { 6771c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 6781c6a0718SPierre Ossman 6791c6a0718SPierre Ossman ret = mmc_suspend_host(mmc, state); 6801c6a0718SPierre Ossman if (ret == 0) 6811c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 6821c6a0718SPierre Ossman } 6831c6a0718SPierre Ossman 6841c6a0718SPierre Ossman return ret; 6851c6a0718SPierre Ossman } 6861c6a0718SPierre Ossman 6871c6a0718SPierre Ossman static int mmci_resume(struct amba_device *dev) 6881c6a0718SPierre Ossman { 6891c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 6901c6a0718SPierre Ossman int ret = 0; 6911c6a0718SPierre Ossman 6921c6a0718SPierre Ossman if (mmc) { 6931c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 6941c6a0718SPierre Ossman 6951c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 6961c6a0718SPierre Ossman 6971c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 6981c6a0718SPierre Ossman } 6991c6a0718SPierre Ossman 7001c6a0718SPierre Ossman return ret; 7011c6a0718SPierre Ossman } 7021c6a0718SPierre Ossman #else 7031c6a0718SPierre Ossman #define mmci_suspend NULL 7041c6a0718SPierre Ossman #define mmci_resume NULL 7051c6a0718SPierre Ossman #endif 7061c6a0718SPierre Ossman 7071c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 7081c6a0718SPierre Ossman { 7091c6a0718SPierre Ossman .id = 0x00041180, 7101c6a0718SPierre Ossman .mask = 0x000fffff, 7111c6a0718SPierre Ossman }, 7121c6a0718SPierre Ossman { 7131c6a0718SPierre Ossman .id = 0x00041181, 7141c6a0718SPierre Ossman .mask = 0x000fffff, 7151c6a0718SPierre Ossman }, 716cc30d60eSLinus Walleij /* ST Micro variants */ 717cc30d60eSLinus Walleij { 718cc30d60eSLinus Walleij .id = 0x00180180, 719cc30d60eSLinus Walleij .mask = 0x00ffffff, 720cc30d60eSLinus Walleij }, 721cc30d60eSLinus Walleij { 722cc30d60eSLinus Walleij .id = 0x00280180, 723cc30d60eSLinus Walleij .mask = 0x00ffffff, 724cc30d60eSLinus Walleij }, 7251c6a0718SPierre Ossman { 0, 0 }, 7261c6a0718SPierre Ossman }; 7271c6a0718SPierre Ossman 7281c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 7291c6a0718SPierre Ossman .drv = { 7301c6a0718SPierre Ossman .name = DRIVER_NAME, 7311c6a0718SPierre Ossman }, 7321c6a0718SPierre Ossman .probe = mmci_probe, 7336dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 7341c6a0718SPierre Ossman .suspend = mmci_suspend, 7351c6a0718SPierre Ossman .resume = mmci_resume, 7361c6a0718SPierre Ossman .id_table = mmci_ids, 7371c6a0718SPierre Ossman }; 7381c6a0718SPierre Ossman 7391c6a0718SPierre Ossman static int __init mmci_init(void) 7401c6a0718SPierre Ossman { 7411c6a0718SPierre Ossman return amba_driver_register(&mmci_driver); 7421c6a0718SPierre Ossman } 7431c6a0718SPierre Ossman 7441c6a0718SPierre Ossman static void __exit mmci_exit(void) 7451c6a0718SPierre Ossman { 7461c6a0718SPierre Ossman amba_driver_unregister(&mmci_driver); 7471c6a0718SPierre Ossman } 7481c6a0718SPierre Ossman 7491c6a0718SPierre Ossman module_init(mmci_init); 7501c6a0718SPierre Ossman module_exit(mmci_exit); 7511c6a0718SPierre Ossman module_param(fmax, uint, 0444); 7521c6a0718SPierre Ossman 7531c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 7541c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 755