11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 18000bc9d5SLee Jones #include <linux/slab.h> 191c6a0718SPierre Ossman #include <linux/delay.h> 201c6a0718SPierre Ossman #include <linux/err.h> 211c6a0718SPierre Ossman #include <linux/highmem.h> 22019a5f56SNicolas Pitre #include <linux/log2.h> 2370be208fSUlf Hansson #include <linux/mmc/pm.h> 241c6a0718SPierre Ossman #include <linux/mmc/host.h> 2534177802SLinus Walleij #include <linux/mmc/card.h> 261c6a0718SPierre Ossman #include <linux/amba/bus.h> 271c6a0718SPierre Ossman #include <linux/clk.h> 28bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2989001446SRussell King #include <linux/gpio.h> 309a597016SLee Jones #include <linux/of_gpio.h> 3134e84f39SLinus Walleij #include <linux/regulator/consumer.h> 32c8ebae37SRussell King #include <linux/dmaengine.h> 33c8ebae37SRussell King #include <linux/dma-mapping.h> 34c8ebae37SRussell King #include <linux/amba/mmci.h> 351c3be369SRussell King #include <linux/pm_runtime.h> 36258aea76SViresh Kumar #include <linux/types.h> 37a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 381c6a0718SPierre Ossman 391c6a0718SPierre Ossman #include <asm/div64.h> 401c6a0718SPierre Ossman #include <asm/io.h> 411c6a0718SPierre Ossman #include <asm/sizes.h> 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #include "mmci.h" 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 461c6a0718SPierre Ossman 471c6a0718SPierre Ossman static unsigned int fmax = 515633; 481c6a0718SPierre Ossman 494956e109SRabin Vincent /** 504956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 514956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 524380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 5308458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 548301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 558301bb68SRabin Vincent * is asserted (likewise for RX) 568301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 578301bb68SRabin Vincent * is asserted (likewise for RX) 5834177802SLinus Walleij * @sdio: variant supports SDIO 59b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 601784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 617d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 624d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 63f4670daeSUlf Hansson * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 644956e109SRabin Vincent */ 654956e109SRabin Vincent struct variant_data { 664956e109SRabin Vincent unsigned int clkreg; 674380c14fSRabin Vincent unsigned int clkreg_enable; 6808458ef6SRabin Vincent unsigned int datalength_bits; 698301bb68SRabin Vincent unsigned int fifosize; 708301bb68SRabin Vincent unsigned int fifohalfsize; 7134177802SLinus Walleij bool sdio; 72b70a67f9SLinus Walleij bool st_clkdiv; 731784b157SPhilippe Langlais bool blksz_datactrl16; 747d72a1d4SUlf Hansson u32 pwrreg_powerup; 754d1a3a0dSUlf Hansson bool signal_direction; 76f4670daeSUlf Hansson bool pwrreg_clkgate; 774956e109SRabin Vincent }; 784956e109SRabin Vincent 794956e109SRabin Vincent static struct variant_data variant_arm = { 808301bb68SRabin Vincent .fifosize = 16 * 4, 818301bb68SRabin Vincent .fifohalfsize = 8 * 4, 8208458ef6SRabin Vincent .datalength_bits = 16, 837d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 844956e109SRabin Vincent }; 854956e109SRabin Vincent 86768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 87768fbc18SPawel Moll .fifosize = 128 * 4, 88768fbc18SPawel Moll .fifohalfsize = 64 * 4, 89768fbc18SPawel Moll .datalength_bits = 16, 907d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 91768fbc18SPawel Moll }; 92768fbc18SPawel Moll 933a37298aSPawel Moll static struct variant_data variant_arm_extended_fifo_hwfc = { 943a37298aSPawel Moll .fifosize = 128 * 4, 953a37298aSPawel Moll .fifohalfsize = 64 * 4, 963a37298aSPawel Moll .clkreg_enable = MCI_ARM_HWFCEN, 973a37298aSPawel Moll .datalength_bits = 16, 983a37298aSPawel Moll .pwrreg_powerup = MCI_PWR_UP, 993a37298aSPawel Moll }; 1003a37298aSPawel Moll 1014956e109SRabin Vincent static struct variant_data variant_u300 = { 1028301bb68SRabin Vincent .fifosize = 16 * 4, 1038301bb68SRabin Vincent .fifohalfsize = 8 * 4, 10449ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 10508458ef6SRabin Vincent .datalength_bits = 16, 10634177802SLinus Walleij .sdio = true, 1077d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1084d1a3a0dSUlf Hansson .signal_direction = true, 109f4670daeSUlf Hansson .pwrreg_clkgate = true, 1104956e109SRabin Vincent }; 1114956e109SRabin Vincent 11234fd4213SLinus Walleij static struct variant_data variant_nomadik = { 11334fd4213SLinus Walleij .fifosize = 16 * 4, 11434fd4213SLinus Walleij .fifohalfsize = 8 * 4, 11534fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 11634fd4213SLinus Walleij .datalength_bits = 24, 11734fd4213SLinus Walleij .sdio = true, 11834fd4213SLinus Walleij .st_clkdiv = true, 11934fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 12034fd4213SLinus Walleij .signal_direction = true, 121f4670daeSUlf Hansson .pwrreg_clkgate = true, 12234fd4213SLinus Walleij }; 12334fd4213SLinus Walleij 1244956e109SRabin Vincent static struct variant_data variant_ux500 = { 1258301bb68SRabin Vincent .fifosize = 30 * 4, 1268301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1274956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 12849ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 12908458ef6SRabin Vincent .datalength_bits = 24, 13034177802SLinus Walleij .sdio = true, 131b70a67f9SLinus Walleij .st_clkdiv = true, 1327d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1334d1a3a0dSUlf Hansson .signal_direction = true, 134f4670daeSUlf Hansson .pwrreg_clkgate = true, 1354956e109SRabin Vincent }; 136b70a67f9SLinus Walleij 1371784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1381784b157SPhilippe Langlais .fifosize = 30 * 4, 1391784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1401784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1411784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1421784b157SPhilippe Langlais .datalength_bits = 24, 1431784b157SPhilippe Langlais .sdio = true, 1441784b157SPhilippe Langlais .st_clkdiv = true, 1451784b157SPhilippe Langlais .blksz_datactrl16 = true, 1467d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1474d1a3a0dSUlf Hansson .signal_direction = true, 148f4670daeSUlf Hansson .pwrreg_clkgate = true, 1491784b157SPhilippe Langlais }; 1501784b157SPhilippe Langlais 151a6a6464aSLinus Walleij /* 152653a761eSUlf Hansson * Validate mmc prerequisites 153653a761eSUlf Hansson */ 154653a761eSUlf Hansson static int mmci_validate_data(struct mmci_host *host, 155653a761eSUlf Hansson struct mmc_data *data) 156653a761eSUlf Hansson { 157653a761eSUlf Hansson if (!data) 158653a761eSUlf Hansson return 0; 159653a761eSUlf Hansson 160653a761eSUlf Hansson if (!is_power_of_2(data->blksz)) { 161653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), 162653a761eSUlf Hansson "unsupported block size (%d bytes)\n", data->blksz); 163653a761eSUlf Hansson return -EINVAL; 164653a761eSUlf Hansson } 165653a761eSUlf Hansson 166653a761eSUlf Hansson return 0; 167653a761eSUlf Hansson } 168653a761eSUlf Hansson 169653a761eSUlf Hansson /* 170a6a6464aSLinus Walleij * This must be called with host->lock held 171a6a6464aSLinus Walleij */ 1727437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 1737437cfa5SUlf Hansson { 1747437cfa5SUlf Hansson if (host->clk_reg != clk) { 1757437cfa5SUlf Hansson host->clk_reg = clk; 1767437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 1777437cfa5SUlf Hansson } 1787437cfa5SUlf Hansson } 1797437cfa5SUlf Hansson 1807437cfa5SUlf Hansson /* 1817437cfa5SUlf Hansson * This must be called with host->lock held 1827437cfa5SUlf Hansson */ 1837437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 1847437cfa5SUlf Hansson { 1857437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 1867437cfa5SUlf Hansson host->pwr_reg = pwr; 1877437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 1887437cfa5SUlf Hansson } 1897437cfa5SUlf Hansson } 1907437cfa5SUlf Hansson 1917437cfa5SUlf Hansson /* 1927437cfa5SUlf Hansson * This must be called with host->lock held 1937437cfa5SUlf Hansson */ 194a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 195a6a6464aSLinus Walleij { 1964956e109SRabin Vincent struct variant_data *variant = host->variant; 1974956e109SRabin Vincent u32 clk = variant->clkreg; 198a6a6464aSLinus Walleij 199a6a6464aSLinus Walleij if (desired) { 200a6a6464aSLinus Walleij if (desired >= host->mclk) { 201a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 202399bc486SLinus Walleij if (variant->st_clkdiv) 203399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 204a6a6464aSLinus Walleij host->cclk = host->mclk; 205b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 206b70a67f9SLinus Walleij /* 207b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 208b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 209b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 210b70a67f9SLinus Walleij * frequency 211b70a67f9SLinus Walleij */ 212b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 213b70a67f9SLinus Walleij if (clk >= 256) 214b70a67f9SLinus Walleij clk = 255; 215b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 216a6a6464aSLinus Walleij } else { 217b70a67f9SLinus Walleij /* 218b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 219b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 220b70a67f9SLinus Walleij */ 221a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 222a6a6464aSLinus Walleij if (clk >= 256) 223a6a6464aSLinus Walleij clk = 255; 224a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 225a6a6464aSLinus Walleij } 2264380c14fSRabin Vincent 2274380c14fSRabin Vincent clk |= variant->clkreg_enable; 228a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 229a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 230a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 231a6a6464aSLinus Walleij } 232a6a6464aSLinus Walleij 2339e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 234771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 235771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 236771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 2379e6c82cdSLinus Walleij 2386dbb6ee0SUlf Hansson if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 2396dbb6ee0SUlf Hansson clk |= MCI_ST_UX500_NEG_EDGE; 2406dbb6ee0SUlf Hansson 2417437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 242a6a6464aSLinus Walleij } 243a6a6464aSLinus Walleij 2441c6a0718SPierre Ossman static void 2451c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 2461c6a0718SPierre Ossman { 2471c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 2481c6a0718SPierre Ossman 2491c6a0718SPierre Ossman BUG_ON(host->data); 2501c6a0718SPierre Ossman 2511c6a0718SPierre Ossman host->mrq = NULL; 2521c6a0718SPierre Ossman host->cmd = NULL; 2531c6a0718SPierre Ossman 2541c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2552cd976c4SUlf Hansson 2562cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 2572cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 2581c6a0718SPierre Ossman } 2591c6a0718SPierre Ossman 2602686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 2612686b4b4SLinus Walleij { 2622686b4b4SLinus Walleij void __iomem *base = host->base; 2632686b4b4SLinus Walleij 2642686b4b4SLinus Walleij if (host->singleirq) { 2652686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 2662686b4b4SLinus Walleij 2672686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 2682686b4b4SLinus Walleij mask0 |= mask; 2692686b4b4SLinus Walleij 2702686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 2712686b4b4SLinus Walleij } 2722686b4b4SLinus Walleij 2732686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 2742686b4b4SLinus Walleij } 2752686b4b4SLinus Walleij 2761c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 2771c6a0718SPierre Ossman { 2781c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 2792686b4b4SLinus Walleij mmci_set_mask1(host, 0); 2801c6a0718SPierre Ossman host->data = NULL; 2811c6a0718SPierre Ossman } 2821c6a0718SPierre Ossman 2834ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 2844ce1d6cbSRabin Vincent { 2854ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 2864ce1d6cbSRabin Vincent 2874ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 2884ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 2894ce1d6cbSRabin Vincent else 2904ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 2914ce1d6cbSRabin Vincent 2924ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 2934ce1d6cbSRabin Vincent } 2944ce1d6cbSRabin Vincent 295c8ebae37SRussell King /* 296c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 297c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 298c8ebae37SRussell King * no custom DMA interfaces are supported. 299c8ebae37SRussell King */ 300c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 301c3be1efdSBill Pemberton static void mmci_dma_setup(struct mmci_host *host) 302c8ebae37SRussell King { 303c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 304c8ebae37SRussell King const char *rxname, *txname; 305c8ebae37SRussell King dma_cap_mask_t mask; 306c8ebae37SRussell King 307c8ebae37SRussell King if (!plat || !plat->dma_filter) { 308c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 309c8ebae37SRussell King return; 310c8ebae37SRussell King } 311c8ebae37SRussell King 31258c7ccbfSPer Forlin /* initialize pre request cookie */ 31358c7ccbfSPer Forlin host->next_data.cookie = 1; 31458c7ccbfSPer Forlin 315c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 316c8ebae37SRussell King dma_cap_zero(mask); 317c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 318c8ebae37SRussell King 319c8ebae37SRussell King /* 320c8ebae37SRussell King * If only an RX channel is specified, the driver will 321c8ebae37SRussell King * attempt to use it bidirectionally, however if it is 322c8ebae37SRussell King * is specified but cannot be located, DMA will be disabled. 323c8ebae37SRussell King */ 324c8ebae37SRussell King if (plat->dma_rx_param) { 325c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 326c8ebae37SRussell King plat->dma_filter, 327c8ebae37SRussell King plat->dma_rx_param); 328c8ebae37SRussell King /* E.g if no DMA hardware is present */ 329c8ebae37SRussell King if (!host->dma_rx_channel) 330c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 331c8ebae37SRussell King } 332c8ebae37SRussell King 333c8ebae37SRussell King if (plat->dma_tx_param) { 334c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 335c8ebae37SRussell King plat->dma_filter, 336c8ebae37SRussell King plat->dma_tx_param); 337c8ebae37SRussell King if (!host->dma_tx_channel) 338c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 339c8ebae37SRussell King } else { 340c8ebae37SRussell King host->dma_tx_channel = host->dma_rx_channel; 341c8ebae37SRussell King } 342c8ebae37SRussell King 343c8ebae37SRussell King if (host->dma_rx_channel) 344c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 345c8ebae37SRussell King else 346c8ebae37SRussell King rxname = "none"; 347c8ebae37SRussell King 348c8ebae37SRussell King if (host->dma_tx_channel) 349c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 350c8ebae37SRussell King else 351c8ebae37SRussell King txname = "none"; 352c8ebae37SRussell King 353c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 354c8ebae37SRussell King rxname, txname); 355c8ebae37SRussell King 356c8ebae37SRussell King /* 357c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 358c8ebae37SRussell King * the parameters of the DMA engine device. 359c8ebae37SRussell King */ 360c8ebae37SRussell King if (host->dma_tx_channel) { 361c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 362c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 363c8ebae37SRussell King 364c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 365c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 366c8ebae37SRussell King } 367c8ebae37SRussell King if (host->dma_rx_channel) { 368c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 369c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 370c8ebae37SRussell King 371c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 372c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 373c8ebae37SRussell King } 374c8ebae37SRussell King } 375c8ebae37SRussell King 376c8ebae37SRussell King /* 3776e0ee714SBill Pemberton * This is used in or so inline it 378c8ebae37SRussell King * so it can be discarded. 379c8ebae37SRussell King */ 380c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 381c8ebae37SRussell King { 382c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 383c8ebae37SRussell King 384c8ebae37SRussell King if (host->dma_rx_channel) 385c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 386c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 387c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 388c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 389c8ebae37SRussell King } 390c8ebae37SRussell King 391653a761eSUlf Hansson static void mmci_dma_data_error(struct mmci_host *host) 392653a761eSUlf Hansson { 393653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 394653a761eSUlf Hansson dmaengine_terminate_all(host->dma_current); 395653a761eSUlf Hansson host->dma_current = NULL; 396653a761eSUlf Hansson host->dma_desc_current = NULL; 397653a761eSUlf Hansson host->data->host_cookie = 0; 398653a761eSUlf Hansson } 399653a761eSUlf Hansson 400c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 401c8ebae37SRussell King { 402653a761eSUlf Hansson struct dma_chan *chan; 403c8ebae37SRussell King enum dma_data_direction dir; 404653a761eSUlf Hansson 405653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) { 406653a761eSUlf Hansson dir = DMA_FROM_DEVICE; 407653a761eSUlf Hansson chan = host->dma_rx_channel; 408653a761eSUlf Hansson } else { 409653a761eSUlf Hansson dir = DMA_TO_DEVICE; 410653a761eSUlf Hansson chan = host->dma_tx_channel; 411653a761eSUlf Hansson } 412653a761eSUlf Hansson 413653a761eSUlf Hansson dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 414653a761eSUlf Hansson } 415653a761eSUlf Hansson 416653a761eSUlf Hansson static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 417653a761eSUlf Hansson { 418c8ebae37SRussell King u32 status; 419c8ebae37SRussell King int i; 420c8ebae37SRussell King 421c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 422c8ebae37SRussell King for (i = 0; ; i++) { 423c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 424c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 425c8ebae37SRussell King break; 426c8ebae37SRussell King udelay(10); 427c8ebae37SRussell King } 428c8ebae37SRussell King 429c8ebae37SRussell King /* 430c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 431c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 432c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 433c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 434c8ebae37SRussell King */ 435c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 436653a761eSUlf Hansson mmci_dma_data_error(host); 437c8ebae37SRussell King if (!data->error) 438c8ebae37SRussell King data->error = -EIO; 439c8ebae37SRussell King } 440c8ebae37SRussell King 44158c7ccbfSPer Forlin if (!data->host_cookie) 442653a761eSUlf Hansson mmci_dma_unmap(host, data); 443c8ebae37SRussell King 444c8ebae37SRussell King /* 445c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 446c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 447c8ebae37SRussell King */ 448c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 449c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 450c8ebae37SRussell King mmci_dma_release(host); 451c8ebae37SRussell King } 452653a761eSUlf Hansson 453653a761eSUlf Hansson host->dma_current = NULL; 454653a761eSUlf Hansson host->dma_desc_current = NULL; 455c8ebae37SRussell King } 456c8ebae37SRussell King 457653a761eSUlf Hansson /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 458653a761eSUlf Hansson static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 459653a761eSUlf Hansson struct dma_chan **dma_chan, 460653a761eSUlf Hansson struct dma_async_tx_descriptor **dma_desc) 461c8ebae37SRussell King { 462c8ebae37SRussell King struct variant_data *variant = host->variant; 463c8ebae37SRussell King struct dma_slave_config conf = { 464c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 465c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 466c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 467c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 468c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 469c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 470258aea76SViresh Kumar .device_fc = false, 471c8ebae37SRussell King }; 472c8ebae37SRussell King struct dma_chan *chan; 473c8ebae37SRussell King struct dma_device *device; 474c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 47505f5799cSVinod Koul enum dma_data_direction buffer_dirn; 476c8ebae37SRussell King int nr_sg; 477c8ebae37SRussell King 478c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 47905f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 48005f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 481c8ebae37SRussell King chan = host->dma_rx_channel; 482c8ebae37SRussell King } else { 48305f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 48405f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 485c8ebae37SRussell King chan = host->dma_tx_channel; 486c8ebae37SRussell King } 487c8ebae37SRussell King 488c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 489c8ebae37SRussell King if (!chan) 490c8ebae37SRussell King return -EINVAL; 491c8ebae37SRussell King 492c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 49358c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 494c8ebae37SRussell King return -EINVAL; 495c8ebae37SRussell King 496c8ebae37SRussell King device = chan->device; 49705f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 498c8ebae37SRussell King if (nr_sg == 0) 499c8ebae37SRussell King return -EINVAL; 500c8ebae37SRussell King 501c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 50216052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 503c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 504c8ebae37SRussell King if (!desc) 505c8ebae37SRussell King goto unmap_exit; 506c8ebae37SRussell King 507653a761eSUlf Hansson *dma_chan = chan; 508653a761eSUlf Hansson *dma_desc = desc; 509c8ebae37SRussell King 51058c7ccbfSPer Forlin return 0; 51158c7ccbfSPer Forlin 51258c7ccbfSPer Forlin unmap_exit: 51305f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 51458c7ccbfSPer Forlin return -ENOMEM; 51558c7ccbfSPer Forlin } 51658c7ccbfSPer Forlin 517653a761eSUlf Hansson static inline int mmci_dma_prep_data(struct mmci_host *host, 518653a761eSUlf Hansson struct mmc_data *data) 519653a761eSUlf Hansson { 520653a761eSUlf Hansson /* Check if next job is already prepared. */ 521653a761eSUlf Hansson if (host->dma_current && host->dma_desc_current) 522653a761eSUlf Hansson return 0; 523653a761eSUlf Hansson 524653a761eSUlf Hansson /* No job were prepared thus do it now. */ 525653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &host->dma_current, 526653a761eSUlf Hansson &host->dma_desc_current); 527653a761eSUlf Hansson } 528653a761eSUlf Hansson 529653a761eSUlf Hansson static inline int mmci_dma_prep_next(struct mmci_host *host, 530653a761eSUlf Hansson struct mmc_data *data) 531653a761eSUlf Hansson { 532653a761eSUlf Hansson struct mmci_host_next *nd = &host->next_data; 533653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 534653a761eSUlf Hansson } 535653a761eSUlf Hansson 53658c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 53758c7ccbfSPer Forlin { 53858c7ccbfSPer Forlin int ret; 53958c7ccbfSPer Forlin struct mmc_data *data = host->data; 54058c7ccbfSPer Forlin 541653a761eSUlf Hansson ret = mmci_dma_prep_data(host, host->data); 54258c7ccbfSPer Forlin if (ret) 54358c7ccbfSPer Forlin return ret; 54458c7ccbfSPer Forlin 54558c7ccbfSPer Forlin /* Okay, go for it. */ 546c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 547c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 548c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 54958c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 55058c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 551c8ebae37SRussell King 552c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 553c8ebae37SRussell King 554c8ebae37SRussell King /* Trigger the DMA transfer */ 555c8ebae37SRussell King writel(datactrl, host->base + MMCIDATACTRL); 556c8ebae37SRussell King 557c8ebae37SRussell King /* 558c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 559c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 560c8ebae37SRussell King * call mmci_data_end() 561c8ebae37SRussell King */ 562c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 563c8ebae37SRussell King host->base + MMCIMASK0); 564c8ebae37SRussell King return 0; 565c8ebae37SRussell King } 56658c7ccbfSPer Forlin 56758c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 56858c7ccbfSPer Forlin { 56958c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 57058c7ccbfSPer Forlin 571653a761eSUlf Hansson WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 572653a761eSUlf Hansson WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 57358c7ccbfSPer Forlin 57458c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 57558c7ccbfSPer Forlin host->dma_current = next->dma_chan; 57658c7ccbfSPer Forlin next->dma_desc = NULL; 57758c7ccbfSPer Forlin next->dma_chan = NULL; 57858c7ccbfSPer Forlin } 57958c7ccbfSPer Forlin 58058c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 58158c7ccbfSPer Forlin bool is_first_req) 58258c7ccbfSPer Forlin { 58358c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 58458c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 58558c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 58658c7ccbfSPer Forlin 58758c7ccbfSPer Forlin if (!data) 58858c7ccbfSPer Forlin return; 58958c7ccbfSPer Forlin 590653a761eSUlf Hansson BUG_ON(data->host_cookie); 59158c7ccbfSPer Forlin 592653a761eSUlf Hansson if (mmci_validate_data(host, data)) 593653a761eSUlf Hansson return; 594653a761eSUlf Hansson 595653a761eSUlf Hansson if (!mmci_dma_prep_next(host, data)) 59658c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 59758c7ccbfSPer Forlin } 59858c7ccbfSPer Forlin 59958c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 60058c7ccbfSPer Forlin int err) 60158c7ccbfSPer Forlin { 60258c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 60358c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 60458c7ccbfSPer Forlin 605653a761eSUlf Hansson if (!data || !data->host_cookie) 60658c7ccbfSPer Forlin return; 60758c7ccbfSPer Forlin 608653a761eSUlf Hansson mmci_dma_unmap(host, data); 609653a761eSUlf Hansson 610653a761eSUlf Hansson if (err) { 611653a761eSUlf Hansson struct mmci_host_next *next = &host->next_data; 612653a761eSUlf Hansson struct dma_chan *chan; 613653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) 61458c7ccbfSPer Forlin chan = host->dma_rx_channel; 615653a761eSUlf Hansson else 61658c7ccbfSPer Forlin chan = host->dma_tx_channel; 61758c7ccbfSPer Forlin dmaengine_terminate_all(chan); 618653a761eSUlf Hansson 619653a761eSUlf Hansson next->dma_desc = NULL; 620653a761eSUlf Hansson next->dma_chan = NULL; 62158c7ccbfSPer Forlin } 62258c7ccbfSPer Forlin } 62358c7ccbfSPer Forlin 624c8ebae37SRussell King #else 625c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 62658c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 62758c7ccbfSPer Forlin { 62858c7ccbfSPer Forlin } 629c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 630c8ebae37SRussell King { 631c8ebae37SRussell King } 632c8ebae37SRussell King 633c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 634c8ebae37SRussell King { 635c8ebae37SRussell King } 636c8ebae37SRussell King 637c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 638c8ebae37SRussell King { 639c8ebae37SRussell King } 640c8ebae37SRussell King 641653a761eSUlf Hansson static inline void mmci_dma_finalize(struct mmci_host *host, 642653a761eSUlf Hansson struct mmc_data *data) 643653a761eSUlf Hansson { 644653a761eSUlf Hansson } 645653a761eSUlf Hansson 646c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 647c8ebae37SRussell King { 648c8ebae37SRussell King } 649c8ebae37SRussell King 650c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 651c8ebae37SRussell King { 652c8ebae37SRussell King return -ENOSYS; 653c8ebae37SRussell King } 65458c7ccbfSPer Forlin 65558c7ccbfSPer Forlin #define mmci_pre_request NULL 65658c7ccbfSPer Forlin #define mmci_post_request NULL 65758c7ccbfSPer Forlin 658c8ebae37SRussell King #endif 659c8ebae37SRussell King 6601c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 6611c6a0718SPierre Ossman { 6628301bb68SRabin Vincent struct variant_data *variant = host->variant; 6631c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 6641c6a0718SPierre Ossman unsigned long long clks; 6651c6a0718SPierre Ossman void __iomem *base; 6661c6a0718SPierre Ossman int blksz_bits; 6671c6a0718SPierre Ossman 66864de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 6691c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 6701c6a0718SPierre Ossman 6711c6a0718SPierre Ossman host->data = data; 672528320dbSRabin Vincent host->size = data->blksz * data->blocks; 67351d4375dSRussell King data->bytes_xfered = 0; 6741c6a0718SPierre Ossman 6751c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 6761c6a0718SPierre Ossman do_div(clks, 1000000000UL); 6771c6a0718SPierre Ossman 6781c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 6791c6a0718SPierre Ossman 6801c6a0718SPierre Ossman base = host->base; 6811c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 6821c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 6831c6a0718SPierre Ossman 6841c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 6851c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 6861c6a0718SPierre Ossman 6871784b157SPhilippe Langlais if (variant->blksz_datactrl16) 6881784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 6891784b157SPhilippe Langlais else 6901c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 691c8ebae37SRussell King 692c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 6931c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 694c8ebae37SRussell King 6957258db7eSUlf Hansson /* The ST Micro variants has a special bit to enable SDIO */ 6967258db7eSUlf Hansson if (variant->sdio && host->mmc->card) 69706c1a121SUlf Hansson if (mmc_card_sdio(host->mmc->card)) { 69806c1a121SUlf Hansson /* 69906c1a121SUlf Hansson * The ST Micro variants has a special bit 70006c1a121SUlf Hansson * to enable SDIO. 70106c1a121SUlf Hansson */ 70206c1a121SUlf Hansson u32 clk; 70306c1a121SUlf Hansson 7047258db7eSUlf Hansson datactrl |= MCI_ST_DPSM_SDIOEN; 7057258db7eSUlf Hansson 706c8ebae37SRussell King /* 70770ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 70870ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 70970ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 71070ac0935SUlf Hansson * depends on the rate of MCLK. 71106c1a121SUlf Hansson */ 71270ac0935SUlf Hansson if (data->flags & MMC_DATA_WRITE && 71370ac0935SUlf Hansson (host->size < 8 || 71470ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 71506c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 71606c1a121SUlf Hansson else 71706c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 71806c1a121SUlf Hansson 71906c1a121SUlf Hansson mmci_write_clkreg(host, clk); 72006c1a121SUlf Hansson } 72106c1a121SUlf Hansson 7226dbb6ee0SUlf Hansson if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 7236dbb6ee0SUlf Hansson datactrl |= MCI_ST_DPSM_DDRMODE; 7246dbb6ee0SUlf Hansson 72506c1a121SUlf Hansson /* 726c8ebae37SRussell King * Attempt to use DMA operation mode, if this 727c8ebae37SRussell King * should fail, fall back to PIO mode 728c8ebae37SRussell King */ 729c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 730c8ebae37SRussell King return; 731c8ebae37SRussell King 732c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 733c8ebae37SRussell King mmci_init_sg(host, data); 734c8ebae37SRussell King 735c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 7361c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 7371c6a0718SPierre Ossman 7381c6a0718SPierre Ossman /* 739c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 740c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 741c4d877c1SRussell King * is available. 7421c6a0718SPierre Ossman */ 743c4d877c1SRussell King if (host->size < variant->fifohalfsize) 7441c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 7451c6a0718SPierre Ossman } else { 7461c6a0718SPierre Ossman /* 7471c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 7481c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 7491c6a0718SPierre Ossman */ 7501c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 7511c6a0718SPierre Ossman } 7521c6a0718SPierre Ossman 7531c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 7541c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 7552686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 7561c6a0718SPierre Ossman } 7571c6a0718SPierre Ossman 7581c6a0718SPierre Ossman static void 7591c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 7601c6a0718SPierre Ossman { 7611c6a0718SPierre Ossman void __iomem *base = host->base; 7621c6a0718SPierre Ossman 76364de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 7641c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 7651c6a0718SPierre Ossman 7661c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 7671c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 7681c6a0718SPierre Ossman udelay(1); 7691c6a0718SPierre Ossman } 7701c6a0718SPierre Ossman 7711c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 7721c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 7731c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 7741c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 7751c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 7761c6a0718SPierre Ossman } 7771c6a0718SPierre Ossman if (/*interrupt*/0) 7781c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 7791c6a0718SPierre Ossman 7801c6a0718SPierre Ossman host->cmd = cmd; 7811c6a0718SPierre Ossman 7821c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 7831c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 7841c6a0718SPierre Ossman } 7851c6a0718SPierre Ossman 7861c6a0718SPierre Ossman static void 7871c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 7881c6a0718SPierre Ossman unsigned int status) 7891c6a0718SPierre Ossman { 790f20f8f21SLinus Walleij /* First check for errors */ 791b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 792b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 7938cb28155SLinus Walleij u32 remain, success; 794f20f8f21SLinus Walleij 795c8ebae37SRussell King /* Terminate the DMA transfer */ 796653a761eSUlf Hansson if (dma_inprogress(host)) { 797c8ebae37SRussell King mmci_dma_data_error(host); 798653a761eSUlf Hansson mmci_dma_unmap(host, data); 799653a761eSUlf Hansson } 800c8ebae37SRussell King 801c8afc9d5SRussell King /* 802c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 803c8afc9d5SRussell King * the data counter gives the number of bytes transferred 804c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 805c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 806c8afc9d5SRussell King * matters for FIFO overruns only. 807c8afc9d5SRussell King */ 808f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 8098cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 8108cb28155SLinus Walleij 811c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 812c8afc9d5SRussell King status, success); 8138cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 8148cb28155SLinus Walleij /* Last block was not successful */ 815c8afc9d5SRussell King success -= 1; 81617b0429dSPierre Ossman data->error = -EILSEQ; 8178cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 81817b0429dSPierre Ossman data->error = -ETIMEDOUT; 819757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 820757df746SLinus Walleij data->error = -ECOMM; 821c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 82217b0429dSPierre Ossman data->error = -EIO; 823c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 824c8afc9d5SRussell King if (success > host->variant->fifosize) 825c8afc9d5SRussell King success -= host->variant->fifosize; 826c8afc9d5SRussell King else 827c8afc9d5SRussell King success = 0; 8288cb28155SLinus Walleij data->error = -EIO; 8294ce1d6cbSRabin Vincent } 83051d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 8311c6a0718SPierre Ossman } 832f20f8f21SLinus Walleij 8338cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 8348cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 835f20f8f21SLinus Walleij 836ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 837c8ebae37SRussell King if (dma_inprogress(host)) 838653a761eSUlf Hansson mmci_dma_finalize(host, data); 8391c6a0718SPierre Ossman mmci_stop_data(host); 8401c6a0718SPierre Ossman 8418cb28155SLinus Walleij if (!data->error) 8428cb28155SLinus Walleij /* The error clause is handled above, success! */ 84351d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 844f20f8f21SLinus Walleij 8451c6a0718SPierre Ossman if (!data->stop) { 8461c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 8471c6a0718SPierre Ossman } else { 8481c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 8491c6a0718SPierre Ossman } 8501c6a0718SPierre Ossman } 8511c6a0718SPierre Ossman } 8521c6a0718SPierre Ossman 8531c6a0718SPierre Ossman static void 8541c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 8551c6a0718SPierre Ossman unsigned int status) 8561c6a0718SPierre Ossman { 8571c6a0718SPierre Ossman void __iomem *base = host->base; 8581c6a0718SPierre Ossman 8591c6a0718SPierre Ossman host->cmd = NULL; 8601c6a0718SPierre Ossman 8611c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 86217b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 8631c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 86417b0429dSPierre Ossman cmd->error = -EILSEQ; 8659047b435SRussell King - ARM Linux } else { 8669047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 8679047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 8689047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 8699047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 8701c6a0718SPierre Ossman } 8711c6a0718SPierre Ossman 87217b0429dSPierre Ossman if (!cmd->data || cmd->error) { 8733b6e3c73SUlf Hansson if (host->data) { 8743b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 875653a761eSUlf Hansson if (dma_inprogress(host)) { 8763b6e3c73SUlf Hansson mmci_dma_data_error(host); 877653a761eSUlf Hansson mmci_dma_unmap(host, host->data); 878653a761eSUlf Hansson } 8791c6a0718SPierre Ossman mmci_stop_data(host); 8803b6e3c73SUlf Hansson } 8811c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 8821c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 8831c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 8841c6a0718SPierre Ossman } 8851c6a0718SPierre Ossman } 8861c6a0718SPierre Ossman 8871c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 8881c6a0718SPierre Ossman { 8891c6a0718SPierre Ossman void __iomem *base = host->base; 8901c6a0718SPierre Ossman char *ptr = buffer; 8911c6a0718SPierre Ossman u32 status; 89226eed9a5SLinus Walleij int host_remain = host->size; 8931c6a0718SPierre Ossman 8941c6a0718SPierre Ossman do { 89526eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 8961c6a0718SPierre Ossman 8971c6a0718SPierre Ossman if (count > remain) 8981c6a0718SPierre Ossman count = remain; 8991c6a0718SPierre Ossman 9001c6a0718SPierre Ossman if (count <= 0) 9011c6a0718SPierre Ossman break; 9021c6a0718SPierre Ossman 903393e5e24SUlf Hansson /* 904393e5e24SUlf Hansson * SDIO especially may want to send something that is 905393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 906393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 907393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 908393e5e24SUlf Hansson */ 909393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 910393e5e24SUlf Hansson if (count < 4) { 911393e5e24SUlf Hansson unsigned char buf[4]; 9124b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 913393e5e24SUlf Hansson memcpy(ptr, buf, count); 914393e5e24SUlf Hansson } else { 9154b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 916393e5e24SUlf Hansson count &= ~0x3; 917393e5e24SUlf Hansson } 918393e5e24SUlf Hansson } else { 9194b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 920393e5e24SUlf Hansson } 9211c6a0718SPierre Ossman 9221c6a0718SPierre Ossman ptr += count; 9231c6a0718SPierre Ossman remain -= count; 92426eed9a5SLinus Walleij host_remain -= count; 9251c6a0718SPierre Ossman 9261c6a0718SPierre Ossman if (remain == 0) 9271c6a0718SPierre Ossman break; 9281c6a0718SPierre Ossman 9291c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9301c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 9311c6a0718SPierre Ossman 9321c6a0718SPierre Ossman return ptr - buffer; 9331c6a0718SPierre Ossman } 9341c6a0718SPierre Ossman 9351c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 9361c6a0718SPierre Ossman { 9378301bb68SRabin Vincent struct variant_data *variant = host->variant; 9381c6a0718SPierre Ossman void __iomem *base = host->base; 9391c6a0718SPierre Ossman char *ptr = buffer; 9401c6a0718SPierre Ossman 9411c6a0718SPierre Ossman do { 9421c6a0718SPierre Ossman unsigned int count, maxcnt; 9431c6a0718SPierre Ossman 9448301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 9458301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 9461c6a0718SPierre Ossman count = min(remain, maxcnt); 9471c6a0718SPierre Ossman 94834177802SLinus Walleij /* 94934177802SLinus Walleij * SDIO especially may want to send something that is 95034177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 95134177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 95234177802SLinus Walleij * So compensate by adding +3 on the count, a single 95334177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 95434177802SLinus Walleij * 32bit writes etc. 95534177802SLinus Walleij */ 9564b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 9571c6a0718SPierre Ossman 9581c6a0718SPierre Ossman ptr += count; 9591c6a0718SPierre Ossman remain -= count; 9601c6a0718SPierre Ossman 9611c6a0718SPierre Ossman if (remain == 0) 9621c6a0718SPierre Ossman break; 9631c6a0718SPierre Ossman 9641c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9651c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 9661c6a0718SPierre Ossman 9671c6a0718SPierre Ossman return ptr - buffer; 9681c6a0718SPierre Ossman } 9691c6a0718SPierre Ossman 9701c6a0718SPierre Ossman /* 9711c6a0718SPierre Ossman * PIO data transfer IRQ handler. 9721c6a0718SPierre Ossman */ 9731c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 9741c6a0718SPierre Ossman { 9751c6a0718SPierre Ossman struct mmci_host *host = dev_id; 9764ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 9778301bb68SRabin Vincent struct variant_data *variant = host->variant; 9781c6a0718SPierre Ossman void __iomem *base = host->base; 9794ce1d6cbSRabin Vincent unsigned long flags; 9801c6a0718SPierre Ossman u32 status; 9811c6a0718SPierre Ossman 9821c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9831c6a0718SPierre Ossman 98464de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 9851c6a0718SPierre Ossman 9864ce1d6cbSRabin Vincent local_irq_save(flags); 9874ce1d6cbSRabin Vincent 9881c6a0718SPierre Ossman do { 9891c6a0718SPierre Ossman unsigned int remain, len; 9901c6a0718SPierre Ossman char *buffer; 9911c6a0718SPierre Ossman 9921c6a0718SPierre Ossman /* 9931c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 9941c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 9951c6a0718SPierre Ossman * definition it is more than half empty. 9961c6a0718SPierre Ossman * 9971c6a0718SPierre Ossman * For read, check for data available. 9981c6a0718SPierre Ossman */ 9991c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 10001c6a0718SPierre Ossman break; 10011c6a0718SPierre Ossman 10024ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 10034ce1d6cbSRabin Vincent break; 10044ce1d6cbSRabin Vincent 10054ce1d6cbSRabin Vincent buffer = sg_miter->addr; 10064ce1d6cbSRabin Vincent remain = sg_miter->length; 10071c6a0718SPierre Ossman 10081c6a0718SPierre Ossman len = 0; 10091c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 10101c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 10111c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 10121c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 10131c6a0718SPierre Ossman 10144ce1d6cbSRabin Vincent sg_miter->consumed = len; 10151c6a0718SPierre Ossman 10161c6a0718SPierre Ossman host->size -= len; 10171c6a0718SPierre Ossman remain -= len; 10181c6a0718SPierre Ossman 10191c6a0718SPierre Ossman if (remain) 10201c6a0718SPierre Ossman break; 10211c6a0718SPierre Ossman 10221c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 10231c6a0718SPierre Ossman } while (1); 10241c6a0718SPierre Ossman 10254ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 10264ce1d6cbSRabin Vincent 10274ce1d6cbSRabin Vincent local_irq_restore(flags); 10284ce1d6cbSRabin Vincent 10291c6a0718SPierre Ossman /* 1030c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 1031c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 10321c6a0718SPierre Ossman */ 1033c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 10342686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 10351c6a0718SPierre Ossman 10361c6a0718SPierre Ossman /* 10371c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 10381c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 10391c6a0718SPierre Ossman * the chip itself has disabled the data path, and 10401c6a0718SPierre Ossman * stops us racing with our data end IRQ. 10411c6a0718SPierre Ossman */ 10421c6a0718SPierre Ossman if (host->size == 0) { 10432686b4b4SLinus Walleij mmci_set_mask1(host, 0); 10441c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 10451c6a0718SPierre Ossman } 10461c6a0718SPierre Ossman 10471c6a0718SPierre Ossman return IRQ_HANDLED; 10481c6a0718SPierre Ossman } 10491c6a0718SPierre Ossman 10501c6a0718SPierre Ossman /* 10511c6a0718SPierre Ossman * Handle completion of command and data transfers. 10521c6a0718SPierre Ossman */ 10531c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 10541c6a0718SPierre Ossman { 10551c6a0718SPierre Ossman struct mmci_host *host = dev_id; 10561c6a0718SPierre Ossman u32 status; 10571c6a0718SPierre Ossman int ret = 0; 10581c6a0718SPierre Ossman 10591c6a0718SPierre Ossman spin_lock(&host->lock); 10601c6a0718SPierre Ossman 10611c6a0718SPierre Ossman do { 10621c6a0718SPierre Ossman struct mmc_command *cmd; 10631c6a0718SPierre Ossman struct mmc_data *data; 10641c6a0718SPierre Ossman 10651c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 10662686b4b4SLinus Walleij 10672686b4b4SLinus Walleij if (host->singleirq) { 10682686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 10692686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 10702686b4b4SLinus Walleij 10712686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 10722686b4b4SLinus Walleij } 10732686b4b4SLinus Walleij 10741c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 10751c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 10761c6a0718SPierre Ossman 107764de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 10781c6a0718SPierre Ossman 10791c6a0718SPierre Ossman data = host->data; 1080b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1081b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1082b63038d6SUlf Hansson MCI_DATABLOCKEND) && data) 10831c6a0718SPierre Ossman mmci_data_irq(host, data, status); 10841c6a0718SPierre Ossman 10851c6a0718SPierre Ossman cmd = host->cmd; 10861c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 10871c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 10881c6a0718SPierre Ossman 10891c6a0718SPierre Ossman ret = 1; 10901c6a0718SPierre Ossman } while (status); 10911c6a0718SPierre Ossman 10921c6a0718SPierre Ossman spin_unlock(&host->lock); 10931c6a0718SPierre Ossman 10941c6a0718SPierre Ossman return IRQ_RETVAL(ret); 10951c6a0718SPierre Ossman } 10961c6a0718SPierre Ossman 10971c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 10981c6a0718SPierre Ossman { 10991c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 11009e943021SLinus Walleij unsigned long flags; 11011c6a0718SPierre Ossman 11021c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 11031c6a0718SPierre Ossman 1104653a761eSUlf Hansson mrq->cmd->error = mmci_validate_data(host, mrq->data); 1105653a761eSUlf Hansson if (mrq->cmd->error) { 1106255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1107255d01afSPierre Ossman return; 1108255d01afSPierre Ossman } 1109255d01afSPierre Ossman 11101c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 11111c3be369SRussell King 11129e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 11131c6a0718SPierre Ossman 11141c6a0718SPierre Ossman host->mrq = mrq; 11151c6a0718SPierre Ossman 111658c7ccbfSPer Forlin if (mrq->data) 111758c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 111858c7ccbfSPer Forlin 11191c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 11201c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 11211c6a0718SPierre Ossman 11221c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 11231c6a0718SPierre Ossman 11249e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 11251c6a0718SPierre Ossman } 11261c6a0718SPierre Ossman 11271c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 11281c6a0718SPierre Ossman { 11291c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 11307d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1131a6a6464aSLinus Walleij u32 pwr = 0; 1132a6a6464aSLinus Walleij unsigned long flags; 1133db90f91fSLee Jones int ret; 11341c6a0718SPierre Ossman 11352cd976c4SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 11362cd976c4SUlf Hansson 1137bc521818SUlf Hansson if (host->plat->ios_handler && 1138bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1139bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1140bc521818SUlf Hansson 11411c6a0718SPierre Ossman switch (ios->power_mode) { 11421c6a0718SPierre Ossman case MMC_POWER_OFF: 1143599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1144599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1145237fb5e6SLee Jones 1146237fb5e6SLee Jones if (!IS_ERR(mmc->supply.vqmmc) && 1147237fb5e6SLee Jones regulator_is_enabled(mmc->supply.vqmmc)) 1148237fb5e6SLee Jones regulator_disable(mmc->supply.vqmmc); 1149237fb5e6SLee Jones 11501c6a0718SPierre Ossman break; 11511c6a0718SPierre Ossman case MMC_POWER_UP: 1152599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1153599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1154599c1d5cSUlf Hansson 11557d72a1d4SUlf Hansson /* 11567d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 11577d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 11587d72a1d4SUlf Hansson * configured in the variant data. 11597d72a1d4SUlf Hansson */ 11607d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 11617d72a1d4SUlf Hansson 11621c6a0718SPierre Ossman break; 11631c6a0718SPierre Ossman case MMC_POWER_ON: 1164237fb5e6SLee Jones if (!IS_ERR(mmc->supply.vqmmc) && 1165db90f91fSLee Jones !regulator_is_enabled(mmc->supply.vqmmc)) { 1166db90f91fSLee Jones ret = regulator_enable(mmc->supply.vqmmc); 1167db90f91fSLee Jones if (ret < 0) 1168db90f91fSLee Jones dev_err(mmc_dev(mmc), 1169db90f91fSLee Jones "failed to enable vqmmc regulator\n"); 1170db90f91fSLee Jones } 1171237fb5e6SLee Jones 11721c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 11731c6a0718SPierre Ossman break; 11741c6a0718SPierre Ossman } 11751c6a0718SPierre Ossman 11764d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 11774d1a3a0dSUlf Hansson /* 11784d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 11794d1a3a0dSUlf Hansson * indicating signal direction for the signals in 11804d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 11814d1a3a0dSUlf Hansson */ 11824d1a3a0dSUlf Hansson pwr |= host->plat->sigdir; 11834d1a3a0dSUlf Hansson 11844d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 11854d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 11864d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 11874d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 11884d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 11894d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 11904d1a3a0dSUlf Hansson } 11914d1a3a0dSUlf Hansson 1192cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1193f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 11941c6a0718SPierre Ossman pwr |= MCI_ROD; 1195cc30d60eSLinus Walleij else { 1196cc30d60eSLinus Walleij /* 1197cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1198cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1199cc30d60eSLinus Walleij */ 1200cc30d60eSLinus Walleij pwr |= MCI_OD; 1201cc30d60eSLinus Walleij } 1202cc30d60eSLinus Walleij } 12031c6a0718SPierre Ossman 1204f4670daeSUlf Hansson /* 1205f4670daeSUlf Hansson * If clock = 0 and the variant requires the MMCIPOWER to be used for 1206f4670daeSUlf Hansson * gating the clock, the MCI_PWR_ON bit is cleared. 1207f4670daeSUlf Hansson */ 1208f4670daeSUlf Hansson if (!ios->clock && variant->pwrreg_clkgate) 1209f4670daeSUlf Hansson pwr &= ~MCI_PWR_ON; 1210f4670daeSUlf Hansson 1211a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1212a6a6464aSLinus Walleij 1213a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 12147437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1215a6a6464aSLinus Walleij 1216a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 12172cd976c4SUlf Hansson 12182cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 12192cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 12201c6a0718SPierre Ossman } 12211c6a0718SPierre Ossman 122289001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 122389001446SRussell King { 122489001446SRussell King struct mmci_host *host = mmc_priv(mmc); 122589001446SRussell King 122689001446SRussell King if (host->gpio_wp == -ENOSYS) 122789001446SRussell King return -ENOSYS; 122889001446SRussell King 122918a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 123089001446SRussell King } 123189001446SRussell King 123289001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 123389001446SRussell King { 123489001446SRussell King struct mmci_host *host = mmc_priv(mmc); 123529719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 123689001446SRussell King unsigned int status; 123789001446SRussell King 12384b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 12394b8caec0SRabin Vincent if (!plat->status) 12404b8caec0SRabin Vincent return 1; /* Assume always present */ 12414b8caec0SRabin Vincent 124229719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 12434b8caec0SRabin Vincent } else 124418a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 124518a06301SLinus Walleij ^ plat->cd_invert; 124689001446SRussell King 124774bc8093SRussell King /* 124874bc8093SRussell King * Use positive logic throughout - status is zero for no card, 124974bc8093SRussell King * non-zero for card inserted. 125074bc8093SRussell King */ 125174bc8093SRussell King return status; 125289001446SRussell King } 125389001446SRussell King 1254148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1255148b8b39SRabin Vincent { 1256148b8b39SRabin Vincent struct mmci_host *host = dev_id; 1257148b8b39SRabin Vincent 1258148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1259148b8b39SRabin Vincent 1260148b8b39SRabin Vincent return IRQ_HANDLED; 1261148b8b39SRabin Vincent } 1262148b8b39SRabin Vincent 12631c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 12641c6a0718SPierre Ossman .request = mmci_request, 126558c7ccbfSPer Forlin .pre_req = mmci_pre_request, 126658c7ccbfSPer Forlin .post_req = mmci_post_request, 12671c6a0718SPierre Ossman .set_ios = mmci_set_ios, 126889001446SRussell King .get_ro = mmci_get_ro, 126989001446SRussell King .get_cd = mmci_get_cd, 12701c6a0718SPierre Ossman }; 12711c6a0718SPierre Ossman 1272000bc9d5SLee Jones #ifdef CONFIG_OF 1273000bc9d5SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1274000bc9d5SLee Jones struct mmci_platform_data *pdata) 1275000bc9d5SLee Jones { 1276000bc9d5SLee Jones int bus_width = 0; 1277000bc9d5SLee Jones 12789a597016SLee Jones pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 12799a597016SLee Jones pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1280000bc9d5SLee Jones 1281000bc9d5SLee Jones if (of_get_property(np, "cd-inverted", NULL)) 1282000bc9d5SLee Jones pdata->cd_invert = true; 1283000bc9d5SLee Jones else 1284000bc9d5SLee Jones pdata->cd_invert = false; 1285000bc9d5SLee Jones 1286000bc9d5SLee Jones of_property_read_u32(np, "max-frequency", &pdata->f_max); 1287000bc9d5SLee Jones if (!pdata->f_max) 1288000bc9d5SLee Jones pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1289000bc9d5SLee Jones 1290000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1291000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1292000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1293000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1294000bc9d5SLee Jones 1295000bc9d5SLee Jones of_property_read_u32(np, "bus-width", &bus_width); 1296000bc9d5SLee Jones switch (bus_width) { 1297000bc9d5SLee Jones case 0 : 1298000bc9d5SLee Jones /* No bus-width supplied. */ 1299000bc9d5SLee Jones break; 1300000bc9d5SLee Jones case 4 : 1301000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1302000bc9d5SLee Jones break; 1303000bc9d5SLee Jones case 8 : 1304000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1305000bc9d5SLee Jones break; 1306000bc9d5SLee Jones default : 1307000bc9d5SLee Jones pr_warn("%s: Unsupported bus width\n", np->full_name); 1308000bc9d5SLee Jones } 1309000bc9d5SLee Jones } 1310c0a120a4SLee Jones #else 1311c0a120a4SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1312c0a120a4SLee Jones struct mmci_platform_data *pdata) 1313c0a120a4SLee Jones { 1314c0a120a4SLee Jones return; 1315c0a120a4SLee Jones } 1316000bc9d5SLee Jones #endif 1317000bc9d5SLee Jones 1318c3be1efdSBill Pemberton static int mmci_probe(struct amba_device *dev, 1319aa25afadSRussell King const struct amba_id *id) 13201c6a0718SPierre Ossman { 13216ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1322000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 13234956e109SRabin Vincent struct variant_data *variant = id->data; 13241c6a0718SPierre Ossman struct mmci_host *host; 13251c6a0718SPierre Ossman struct mmc_host *mmc; 13261c6a0718SPierre Ossman int ret; 13271c6a0718SPierre Ossman 1328000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1329000bc9d5SLee Jones if (!plat && !np) { 1330000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1331000bc9d5SLee Jones return -EINVAL; 13321c6a0718SPierre Ossman } 13331c6a0718SPierre Ossman 1334b9b52918SLee Jones if (!plat) { 1335b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1336b9b52918SLee Jones if (!plat) 1337b9b52918SLee Jones return -ENOMEM; 1338b9b52918SLee Jones } 1339b9b52918SLee Jones 1340000bc9d5SLee Jones if (np) 1341000bc9d5SLee Jones mmci_dt_populate_generic_pdata(np, plat); 1342000bc9d5SLee Jones 13431c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 13441c6a0718SPierre Ossman if (ret) 13451c6a0718SPierre Ossman goto out; 13461c6a0718SPierre Ossman 13471c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 13481c6a0718SPierre Ossman if (!mmc) { 13491c6a0718SPierre Ossman ret = -ENOMEM; 13501c6a0718SPierre Ossman goto rel_regions; 13511c6a0718SPierre Ossman } 13521c6a0718SPierre Ossman 13531c6a0718SPierre Ossman host = mmc_priv(mmc); 13544ea580f1SRabin Vincent host->mmc = mmc; 1355012b7d33SRussell King 135689001446SRussell King host->gpio_wp = -ENOSYS; 135789001446SRussell King host->gpio_cd = -ENOSYS; 1358148b8b39SRabin Vincent host->gpio_cd_irq = -1; 135989001446SRussell King 1360012b7d33SRussell King host->hw_designer = amba_manf(dev); 1361012b7d33SRussell King host->hw_revision = amba_rev(dev); 136264de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 136364de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1364012b7d33SRussell King 1365665ba56fSUlf Hansson host->clk = devm_clk_get(&dev->dev, NULL); 13661c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 13671c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 13681c6a0718SPierre Ossman goto host_free; 13691c6a0718SPierre Ossman } 13701c6a0718SPierre Ossman 1371ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 13721c6a0718SPierre Ossman if (ret) 1373665ba56fSUlf Hansson goto host_free; 13741c6a0718SPierre Ossman 13751c6a0718SPierre Ossman host->plat = plat; 13764956e109SRabin Vincent host->variant = variant; 13771c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1378c8df9a53SLinus Walleij /* 1379c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1380c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1381c8df9a53SLinus Walleij * (if possible). 1382c8df9a53SLinus Walleij */ 1383c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1384c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1385c8df9a53SLinus Walleij if (ret < 0) 1386c8df9a53SLinus Walleij goto clk_disable; 1387c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 138864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 138964de0289SLinus Walleij host->mclk); 1390c8df9a53SLinus Walleij } 1391c8ebae37SRussell King host->phybase = dev->res.start; 1392dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 13931c6a0718SPierre Ossman if (!host->base) { 13941c6a0718SPierre Ossman ret = -ENOMEM; 13951c6a0718SPierre Ossman goto clk_disable; 13961c6a0718SPierre Ossman } 13971c6a0718SPierre Ossman 13981c6a0718SPierre Ossman mmc->ops = &mmci_ops; 13997f294e49SLinus Walleij /* 14007f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 14017f294e49SLinus Walleij * clock divider equations which means that the minimum divider 14027f294e49SLinus Walleij * differs too. 14037f294e49SLinus Walleij */ 14047f294e49SLinus Walleij if (variant->st_clkdiv) 14057f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 14067f294e49SLinus Walleij else 14077f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1408808d97ccSLinus Walleij /* 1409808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1410808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1411808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1412808d97ccSLinus Walleij * default value in case it is not specified. Either 1413808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1414808d97ccSLinus Walleij * of course. 1415808d97ccSLinus Walleij */ 1416808d97ccSLinus Walleij if (plat->f_max) 1417808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1418808d97ccSLinus Walleij else 14191c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 142064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 142164de0289SLinus Walleij 1422a9a83785SLinus Walleij host->pinctrl = devm_pinctrl_get(&dev->dev); 1423a9a83785SLinus Walleij if (IS_ERR(host->pinctrl)) { 1424a9a83785SLinus Walleij ret = PTR_ERR(host->pinctrl); 1425a9a83785SLinus Walleij goto clk_disable; 1426a9a83785SLinus Walleij } 1427a9a83785SLinus Walleij 1428a9a83785SLinus Walleij host->pins_default = pinctrl_lookup_state(host->pinctrl, 1429a9a83785SLinus Walleij PINCTRL_STATE_DEFAULT); 1430a9a83785SLinus Walleij 1431a9a83785SLinus Walleij /* enable pins to be muxed in and configured */ 1432a9a83785SLinus Walleij if (!IS_ERR(host->pins_default)) { 1433a9a83785SLinus Walleij ret = pinctrl_select_state(host->pinctrl, host->pins_default); 1434a9a83785SLinus Walleij if (ret) 1435a9a83785SLinus Walleij dev_warn(&dev->dev, "could not set default pins\n"); 1436a9a83785SLinus Walleij } else 1437a9a83785SLinus Walleij dev_warn(&dev->dev, "could not get default pinstate\n"); 1438a9a83785SLinus Walleij 1439599c1d5cSUlf Hansson /* Get regulators and the supported OCR mask */ 1440599c1d5cSUlf Hansson mmc_regulator_get_supply(mmc); 1441599c1d5cSUlf Hansson if (!mmc->ocr_avail) 14421c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 1443599c1d5cSUlf Hansson else if (plat->ocr_mask) 1444599c1d5cSUlf Hansson dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1445599c1d5cSUlf Hansson 14469e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 14475a092627SPer Forlin mmc->caps2 = plat->capabilities2; 14481c6a0718SPierre Ossman 144970be208fSUlf Hansson /* We support these PM capabilities. */ 145070be208fSUlf Hansson mmc->pm_caps = MMC_PM_KEEP_POWER; 145170be208fSUlf Hansson 14521c6a0718SPierre Ossman /* 14531c6a0718SPierre Ossman * We can do SGIO 14541c6a0718SPierre Ossman */ 1455a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 14561c6a0718SPierre Ossman 14571c6a0718SPierre Ossman /* 145808458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 145908458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 146008458ef6SRabin Vincent * single request. 14611c6a0718SPierre Ossman */ 146208458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 14631c6a0718SPierre Ossman 14641c6a0718SPierre Ossman /* 14651c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 14661c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 14671c6a0718SPierre Ossman */ 14681c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 14691c6a0718SPierre Ossman 14701c6a0718SPierre Ossman /* 14711c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 14721c6a0718SPierre Ossman */ 14738f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 14741c6a0718SPierre Ossman 14751c6a0718SPierre Ossman /* 14768f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 14778f7f6b7eSWill Deacon * the maximum request size. 14781c6a0718SPierre Ossman */ 14798f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 14801c6a0718SPierre Ossman 14811c6a0718SPierre Ossman spin_lock_init(&host->lock); 14821c6a0718SPierre Ossman 14831c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14841c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 14851c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 14861c6a0718SPierre Ossman 14872805b9abSRoland Stigge if (plat->gpio_cd == -EPROBE_DEFER) { 14882805b9abSRoland Stigge ret = -EPROBE_DEFER; 14892805b9abSRoland Stigge goto err_gpio_cd; 14902805b9abSRoland Stigge } 149189001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 149289001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 149389001446SRussell King if (ret == 0) 149489001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 149589001446SRussell King if (ret == 0) 149689001446SRussell King host->gpio_cd = plat->gpio_cd; 149789001446SRussell King else if (ret != -ENOSYS) 149889001446SRussell King goto err_gpio_cd; 1499148b8b39SRabin Vincent 150017ee083bSLinus Walleij /* 150117ee083bSLinus Walleij * A gpio pin that will detect cards when inserted and removed 150217ee083bSLinus Walleij * will most likely want to trigger on the edges if it is 150317ee083bSLinus Walleij * 0 when ejected and 1 when inserted (or mutatis mutandis 150417ee083bSLinus Walleij * for the inverted case) so we request triggers on both 150517ee083bSLinus Walleij * edges. 150617ee083bSLinus Walleij */ 1507148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 150817ee083bSLinus Walleij mmci_cd_irq, 150917ee083bSLinus Walleij IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1510148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1511148b8b39SRabin Vincent if (ret >= 0) 1512148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 151389001446SRussell King } 15142805b9abSRoland Stigge if (plat->gpio_wp == -EPROBE_DEFER) { 15152805b9abSRoland Stigge ret = -EPROBE_DEFER; 15162805b9abSRoland Stigge goto err_gpio_wp; 15172805b9abSRoland Stigge } 151889001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 151989001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 152089001446SRussell King if (ret == 0) 152189001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 152289001446SRussell King if (ret == 0) 152389001446SRussell King host->gpio_wp = plat->gpio_wp; 152489001446SRussell King else if (ret != -ENOSYS) 152589001446SRussell King goto err_gpio_wp; 152689001446SRussell King } 152789001446SRussell King 15284b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 15294b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1530148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1531148b8b39SRabin Vincent 15321c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 15331c6a0718SPierre Ossman if (ret) 15341c6a0718SPierre Ossman goto unmap; 15351c6a0718SPierre Ossman 1536dfb85185SRussell King if (!dev->irq[1]) 15372686b4b4SLinus Walleij host->singleirq = true; 15382686b4b4SLinus Walleij else { 15392686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 15402686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 15411c6a0718SPierre Ossman if (ret) 15421c6a0718SPierre Ossman goto irq0_free; 15432686b4b4SLinus Walleij } 15441c6a0718SPierre Ossman 15458cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 15461c6a0718SPierre Ossman 15471c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 15481c6a0718SPierre Ossman 1549c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1550c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1551c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1552c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1553c8ebae37SRussell King 1554c8ebae37SRussell King mmci_dma_setup(host); 15551c6a0718SPierre Ossman 15562cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 15572cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 15581c3be369SRussell King pm_runtime_put(&dev->dev); 15591c3be369SRussell King 15608c11a94dSRussell King mmc_add_host(mmc); 15618c11a94dSRussell King 15621c6a0718SPierre Ossman return 0; 15631c6a0718SPierre Ossman 15641c6a0718SPierre Ossman irq0_free: 15651c6a0718SPierre Ossman free_irq(dev->irq[0], host); 15661c6a0718SPierre Ossman unmap: 156789001446SRussell King if (host->gpio_wp != -ENOSYS) 156889001446SRussell King gpio_free(host->gpio_wp); 156989001446SRussell King err_gpio_wp: 1570148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1571148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 157289001446SRussell King if (host->gpio_cd != -ENOSYS) 157389001446SRussell King gpio_free(host->gpio_cd); 157489001446SRussell King err_gpio_cd: 15751c6a0718SPierre Ossman iounmap(host->base); 15761c6a0718SPierre Ossman clk_disable: 1577ac940938SJulia Lawall clk_disable_unprepare(host->clk); 15781c6a0718SPierre Ossman host_free: 15791c6a0718SPierre Ossman mmc_free_host(mmc); 15801c6a0718SPierre Ossman rel_regions: 15811c6a0718SPierre Ossman amba_release_regions(dev); 15821c6a0718SPierre Ossman out: 15831c6a0718SPierre Ossman return ret; 15841c6a0718SPierre Ossman } 15851c6a0718SPierre Ossman 15866e0ee714SBill Pemberton static int mmci_remove(struct amba_device *dev) 15871c6a0718SPierre Ossman { 15881c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 15891c6a0718SPierre Ossman 15901c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 15911c6a0718SPierre Ossman 15921c6a0718SPierre Ossman if (mmc) { 15931c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15941c6a0718SPierre Ossman 15951c3be369SRussell King /* 15961c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 15971c3be369SRussell King * version here so that we can access the primecell. 15981c3be369SRussell King */ 15991c3be369SRussell King pm_runtime_get_sync(&dev->dev); 16001c3be369SRussell King 16011c6a0718SPierre Ossman mmc_remove_host(mmc); 16021c6a0718SPierre Ossman 16031c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 16041c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 16051c6a0718SPierre Ossman 16061c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 16071c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 16081c6a0718SPierre Ossman 1609c8ebae37SRussell King mmci_dma_release(host); 16101c6a0718SPierre Ossman free_irq(dev->irq[0], host); 16112686b4b4SLinus Walleij if (!host->singleirq) 16121c6a0718SPierre Ossman free_irq(dev->irq[1], host); 16131c6a0718SPierre Ossman 161489001446SRussell King if (host->gpio_wp != -ENOSYS) 161589001446SRussell King gpio_free(host->gpio_wp); 1616148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1617148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 161889001446SRussell King if (host->gpio_cd != -ENOSYS) 161989001446SRussell King gpio_free(host->gpio_cd); 162089001446SRussell King 16211c6a0718SPierre Ossman iounmap(host->base); 1622ac940938SJulia Lawall clk_disable_unprepare(host->clk); 16231c6a0718SPierre Ossman 16241c6a0718SPierre Ossman mmc_free_host(mmc); 16251c6a0718SPierre Ossman 16261c6a0718SPierre Ossman amba_release_regions(dev); 16271c6a0718SPierre Ossman } 16281c6a0718SPierre Ossman 16291c6a0718SPierre Ossman return 0; 16301c6a0718SPierre Ossman } 16311c6a0718SPierre Ossman 163248fa7003SUlf Hansson #ifdef CONFIG_SUSPEND 163348fa7003SUlf Hansson static int mmci_suspend(struct device *dev) 16341c6a0718SPierre Ossman { 163548fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 163648fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 16371c6a0718SPierre Ossman int ret = 0; 16381c6a0718SPierre Ossman 16391c6a0718SPierre Ossman if (mmc) { 16401c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 16411c6a0718SPierre Ossman 16421a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 16432cd976c4SUlf Hansson if (ret == 0) { 16442cd976c4SUlf Hansson pm_runtime_get_sync(dev); 16451c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 16461c6a0718SPierre Ossman } 16472cd976c4SUlf Hansson } 16481c6a0718SPierre Ossman 16491c6a0718SPierre Ossman return ret; 16501c6a0718SPierre Ossman } 16511c6a0718SPierre Ossman 165248fa7003SUlf Hansson static int mmci_resume(struct device *dev) 16531c6a0718SPierre Ossman { 165448fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 165548fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 16561c6a0718SPierre Ossman int ret = 0; 16571c6a0718SPierre Ossman 16581c6a0718SPierre Ossman if (mmc) { 16591c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 16601c6a0718SPierre Ossman 16611c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 16622cd976c4SUlf Hansson pm_runtime_put(dev); 16631c6a0718SPierre Ossman 16641c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 16651c6a0718SPierre Ossman } 16661c6a0718SPierre Ossman 16671c6a0718SPierre Ossman return ret; 16681c6a0718SPierre Ossman } 16691c6a0718SPierre Ossman #endif 16701c6a0718SPierre Ossman 16718259293aSUlf Hansson #ifdef CONFIG_PM_RUNTIME 16728259293aSUlf Hansson static int mmci_runtime_suspend(struct device *dev) 16738259293aSUlf Hansson { 16748259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 16758259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 16768259293aSUlf Hansson 16778259293aSUlf Hansson if (mmc) { 16788259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 16798259293aSUlf Hansson clk_disable_unprepare(host->clk); 16808259293aSUlf Hansson } 16818259293aSUlf Hansson 16828259293aSUlf Hansson return 0; 16838259293aSUlf Hansson } 16848259293aSUlf Hansson 16858259293aSUlf Hansson static int mmci_runtime_resume(struct device *dev) 16868259293aSUlf Hansson { 16878259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 16888259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 16898259293aSUlf Hansson 16908259293aSUlf Hansson if (mmc) { 16918259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 16928259293aSUlf Hansson clk_prepare_enable(host->clk); 16938259293aSUlf Hansson } 16948259293aSUlf Hansson 16958259293aSUlf Hansson return 0; 16968259293aSUlf Hansson } 16978259293aSUlf Hansson #endif 16988259293aSUlf Hansson 169948fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 170048fa7003SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 17018259293aSUlf Hansson SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 170248fa7003SUlf Hansson }; 170348fa7003SUlf Hansson 17041c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 17051c6a0718SPierre Ossman { 17061c6a0718SPierre Ossman .id = 0x00041180, 1707768fbc18SPawel Moll .mask = 0xff0fffff, 17084956e109SRabin Vincent .data = &variant_arm, 17091c6a0718SPierre Ossman }, 17101c6a0718SPierre Ossman { 1711768fbc18SPawel Moll .id = 0x01041180, 1712768fbc18SPawel Moll .mask = 0xff0fffff, 1713768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1714768fbc18SPawel Moll }, 1715768fbc18SPawel Moll { 17163a37298aSPawel Moll .id = 0x02041180, 17173a37298aSPawel Moll .mask = 0xff0fffff, 17183a37298aSPawel Moll .data = &variant_arm_extended_fifo_hwfc, 17193a37298aSPawel Moll }, 17203a37298aSPawel Moll { 17211c6a0718SPierre Ossman .id = 0x00041181, 17221c6a0718SPierre Ossman .mask = 0x000fffff, 17234956e109SRabin Vincent .data = &variant_arm, 17241c6a0718SPierre Ossman }, 1725cc30d60eSLinus Walleij /* ST Micro variants */ 1726cc30d60eSLinus Walleij { 1727cc30d60eSLinus Walleij .id = 0x00180180, 1728cc30d60eSLinus Walleij .mask = 0x00ffffff, 17294956e109SRabin Vincent .data = &variant_u300, 1730cc30d60eSLinus Walleij }, 1731cc30d60eSLinus Walleij { 173234fd4213SLinus Walleij .id = 0x10180180, 173334fd4213SLinus Walleij .mask = 0xf0ffffff, 173434fd4213SLinus Walleij .data = &variant_nomadik, 173534fd4213SLinus Walleij }, 173634fd4213SLinus Walleij { 1737cc30d60eSLinus Walleij .id = 0x00280180, 1738cc30d60eSLinus Walleij .mask = 0x00ffffff, 17394956e109SRabin Vincent .data = &variant_u300, 17404956e109SRabin Vincent }, 17414956e109SRabin Vincent { 17424956e109SRabin Vincent .id = 0x00480180, 17431784b157SPhilippe Langlais .mask = 0xf0ffffff, 17444956e109SRabin Vincent .data = &variant_ux500, 1745cc30d60eSLinus Walleij }, 17461784b157SPhilippe Langlais { 17471784b157SPhilippe Langlais .id = 0x10480180, 17481784b157SPhilippe Langlais .mask = 0xf0ffffff, 17491784b157SPhilippe Langlais .data = &variant_ux500v2, 17501784b157SPhilippe Langlais }, 17511c6a0718SPierre Ossman { 0, 0 }, 17521c6a0718SPierre Ossman }; 17531c6a0718SPierre Ossman 17549f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 17559f99835fSDave Martin 17561c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 17571c6a0718SPierre Ossman .drv = { 17581c6a0718SPierre Ossman .name = DRIVER_NAME, 175948fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 17601c6a0718SPierre Ossman }, 17611c6a0718SPierre Ossman .probe = mmci_probe, 17620433c143SBill Pemberton .remove = mmci_remove, 17631c6a0718SPierre Ossman .id_table = mmci_ids, 17641c6a0718SPierre Ossman }; 17651c6a0718SPierre Ossman 17669e5ed094Sviresh kumar module_amba_driver(mmci_driver); 17671c6a0718SPierre Ossman 17681c6a0718SPierre Ossman module_param(fmax, uint, 0444); 17691c6a0718SPierre Ossman 17701c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 17711c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1772