11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 564de0289SLinus Walleij * Copyright (C) 2010 ST-Ericsson AB. 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 171c6a0718SPierre Ossman #include <linux/delay.h> 181c6a0718SPierre Ossman #include <linux/err.h> 191c6a0718SPierre Ossman #include <linux/highmem.h> 20019a5f56SNicolas Pitre #include <linux/log2.h> 211c6a0718SPierre Ossman #include <linux/mmc/host.h> 221c6a0718SPierre Ossman #include <linux/amba/bus.h> 231c6a0718SPierre Ossman #include <linux/clk.h> 24bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2589001446SRussell King #include <linux/gpio.h> 266ef297f8SLinus Walleij #include <linux/amba/mmci.h> 2734e84f39SLinus Walleij #include <linux/regulator/consumer.h> 281c6a0718SPierre Ossman 291c6a0718SPierre Ossman #include <asm/div64.h> 301c6a0718SPierre Ossman #include <asm/io.h> 311c6a0718SPierre Ossman #include <asm/sizes.h> 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #include "mmci.h" 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman static unsigned int fmax = 515633; 381c6a0718SPierre Ossman 39a6a6464aSLinus Walleij /* 40a6a6464aSLinus Walleij * This must be called with host->lock held 41a6a6464aSLinus Walleij */ 42a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 43a6a6464aSLinus Walleij { 44a6a6464aSLinus Walleij u32 clk = 0; 45a6a6464aSLinus Walleij 46a6a6464aSLinus Walleij if (desired) { 47a6a6464aSLinus Walleij if (desired >= host->mclk) { 48a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 49a6a6464aSLinus Walleij host->cclk = host->mclk; 50a6a6464aSLinus Walleij } else { 51a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 52a6a6464aSLinus Walleij if (clk >= 256) 53a6a6464aSLinus Walleij clk = 255; 54a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 55a6a6464aSLinus Walleij } 56b43149c1SLinus Walleij if (host->hw_designer == AMBA_VENDOR_ST) 57771dc157SLinus Walleij clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */ 58a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 59a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 60a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 61a6a6464aSLinus Walleij } 62a6a6464aSLinus Walleij 639e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 64771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 65771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 66771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 679e6c82cdSLinus Walleij 68a6a6464aSLinus Walleij writel(clk, host->base + MMCICLOCK); 69a6a6464aSLinus Walleij } 70a6a6464aSLinus Walleij 711c6a0718SPierre Ossman static void 721c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 731c6a0718SPierre Ossman { 741c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 751c6a0718SPierre Ossman 761c6a0718SPierre Ossman BUG_ON(host->data); 771c6a0718SPierre Ossman 781c6a0718SPierre Ossman host->mrq = NULL; 791c6a0718SPierre Ossman host->cmd = NULL; 801c6a0718SPierre Ossman 811c6a0718SPierre Ossman if (mrq->data) 821c6a0718SPierre Ossman mrq->data->bytes_xfered = host->data_xfered; 831c6a0718SPierre Ossman 841c6a0718SPierre Ossman /* 851c6a0718SPierre Ossman * Need to drop the host lock here; mmc_request_done may call 861c6a0718SPierre Ossman * back into the driver... 871c6a0718SPierre Ossman */ 881c6a0718SPierre Ossman spin_unlock(&host->lock); 891c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 901c6a0718SPierre Ossman spin_lock(&host->lock); 911c6a0718SPierre Ossman } 921c6a0718SPierre Ossman 931c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 941c6a0718SPierre Ossman { 951c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 961c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 971c6a0718SPierre Ossman host->data = NULL; 981c6a0718SPierre Ossman } 991c6a0718SPierre Ossman 1004ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 1014ce1d6cbSRabin Vincent { 1024ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 1034ce1d6cbSRabin Vincent 1044ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 1054ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 1064ce1d6cbSRabin Vincent else 1074ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 1084ce1d6cbSRabin Vincent 1094ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1104ce1d6cbSRabin Vincent } 1114ce1d6cbSRabin Vincent 1121c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1131c6a0718SPierre Ossman { 1141c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 1151c6a0718SPierre Ossman unsigned long long clks; 1161c6a0718SPierre Ossman void __iomem *base; 1171c6a0718SPierre Ossman int blksz_bits; 1181c6a0718SPierre Ossman 11964de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1201c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 1211c6a0718SPierre Ossman 1221c6a0718SPierre Ossman host->data = data; 123528320dbSRabin Vincent host->size = data->blksz * data->blocks; 1241c6a0718SPierre Ossman host->data_xfered = 0; 1251c6a0718SPierre Ossman 1261c6a0718SPierre Ossman mmci_init_sg(host, data); 1271c6a0718SPierre Ossman 1281c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 1291c6a0718SPierre Ossman do_div(clks, 1000000000UL); 1301c6a0718SPierre Ossman 1311c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 1321c6a0718SPierre Ossman 1331c6a0718SPierre Ossman base = host->base; 1341c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 1351c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 1361c6a0718SPierre Ossman 1371c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 1381c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 1391c6a0718SPierre Ossman 1401c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 1411c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) { 1421c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 1431c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 1441c6a0718SPierre Ossman 1451c6a0718SPierre Ossman /* 1461c6a0718SPierre Ossman * If we have less than a FIFOSIZE of bytes to transfer, 1471c6a0718SPierre Ossman * trigger a PIO interrupt as soon as any data is available. 1481c6a0718SPierre Ossman */ 1491c6a0718SPierre Ossman if (host->size < MCI_FIFOSIZE) 1501c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 1511c6a0718SPierre Ossman } else { 1521c6a0718SPierre Ossman /* 1531c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 1541c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 1551c6a0718SPierre Ossman */ 1561c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 1571c6a0718SPierre Ossman } 1581c6a0718SPierre Ossman 1591c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 1601c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1611c6a0718SPierre Ossman writel(irqmask, base + MMCIMASK1); 1621c6a0718SPierre Ossman } 1631c6a0718SPierre Ossman 1641c6a0718SPierre Ossman static void 1651c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1661c6a0718SPierre Ossman { 1671c6a0718SPierre Ossman void __iomem *base = host->base; 1681c6a0718SPierre Ossman 16964de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1701c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 1711c6a0718SPierre Ossman 1721c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 1731c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 1741c6a0718SPierre Ossman udelay(1); 1751c6a0718SPierre Ossman } 1761c6a0718SPierre Ossman 1771c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 1781c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 1791c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 1801c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 1811c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 1821c6a0718SPierre Ossman } 1831c6a0718SPierre Ossman if (/*interrupt*/0) 1841c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 1851c6a0718SPierre Ossman 1861c6a0718SPierre Ossman host->cmd = cmd; 1871c6a0718SPierre Ossman 1881c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 1891c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 1901c6a0718SPierre Ossman } 1911c6a0718SPierre Ossman 1921c6a0718SPierre Ossman static void 1931c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1941c6a0718SPierre Ossman unsigned int status) 1951c6a0718SPierre Ossman { 1961c6a0718SPierre Ossman if (status & MCI_DATABLOCKEND) { 1971c6a0718SPierre Ossman host->data_xfered += data->blksz; 198f28e8a4dSLinus Walleij #ifdef CONFIG_ARCH_U300 199f28e8a4dSLinus Walleij /* 200f28e8a4dSLinus Walleij * On the U300 some signal or other is 201f28e8a4dSLinus Walleij * badly routed so that a data write does 202f28e8a4dSLinus Walleij * not properly terminate with a MCI_DATAEND 203f28e8a4dSLinus Walleij * status flag. This quirk will make writes 204f28e8a4dSLinus Walleij * work again. 205f28e8a4dSLinus Walleij */ 206f28e8a4dSLinus Walleij if (data->flags & MMC_DATA_WRITE) 207f28e8a4dSLinus Walleij status |= MCI_DATAEND; 208f28e8a4dSLinus Walleij #endif 2091c6a0718SPierre Ossman } 2101c6a0718SPierre Ossman if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 21164de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); 2121c6a0718SPierre Ossman if (status & MCI_DATACRCFAIL) 21317b0429dSPierre Ossman data->error = -EILSEQ; 2141c6a0718SPierre Ossman else if (status & MCI_DATATIMEOUT) 21517b0429dSPierre Ossman data->error = -ETIMEDOUT; 2161c6a0718SPierre Ossman else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) 21717b0429dSPierre Ossman data->error = -EIO; 2181c6a0718SPierre Ossman status |= MCI_DATAEND; 2191c6a0718SPierre Ossman 2201c6a0718SPierre Ossman /* 2211c6a0718SPierre Ossman * We hit an error condition. Ensure that any data 2221c6a0718SPierre Ossman * partially written to a page is properly coherent. 2231c6a0718SPierre Ossman */ 2244ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) { 2254ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 2264ce1d6cbSRabin Vincent unsigned long flags; 2274ce1d6cbSRabin Vincent 2284ce1d6cbSRabin Vincent local_irq_save(flags); 2294ce1d6cbSRabin Vincent if (sg_miter_next(sg_miter)) { 2304ce1d6cbSRabin Vincent flush_dcache_page(sg_miter->page); 2314ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 2324ce1d6cbSRabin Vincent } 2334ce1d6cbSRabin Vincent local_irq_restore(flags); 2344ce1d6cbSRabin Vincent } 2351c6a0718SPierre Ossman } 2361c6a0718SPierre Ossman if (status & MCI_DATAEND) { 2371c6a0718SPierre Ossman mmci_stop_data(host); 2381c6a0718SPierre Ossman 2391c6a0718SPierre Ossman if (!data->stop) { 2401c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 2411c6a0718SPierre Ossman } else { 2421c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 2431c6a0718SPierre Ossman } 2441c6a0718SPierre Ossman } 2451c6a0718SPierre Ossman } 2461c6a0718SPierre Ossman 2471c6a0718SPierre Ossman static void 2481c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 2491c6a0718SPierre Ossman unsigned int status) 2501c6a0718SPierre Ossman { 2511c6a0718SPierre Ossman void __iomem *base = host->base; 2521c6a0718SPierre Ossman 2531c6a0718SPierre Ossman host->cmd = NULL; 2541c6a0718SPierre Ossman 2551c6a0718SPierre Ossman cmd->resp[0] = readl(base + MMCIRESPONSE0); 2561c6a0718SPierre Ossman cmd->resp[1] = readl(base + MMCIRESPONSE1); 2571c6a0718SPierre Ossman cmd->resp[2] = readl(base + MMCIRESPONSE2); 2581c6a0718SPierre Ossman cmd->resp[3] = readl(base + MMCIRESPONSE3); 2591c6a0718SPierre Ossman 2601c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 26117b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 2621c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 26317b0429dSPierre Ossman cmd->error = -EILSEQ; 2641c6a0718SPierre Ossman } 2651c6a0718SPierre Ossman 26617b0429dSPierre Ossman if (!cmd->data || cmd->error) { 2671c6a0718SPierre Ossman if (host->data) 2681c6a0718SPierre Ossman mmci_stop_data(host); 2691c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 2701c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 2711c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 2721c6a0718SPierre Ossman } 2731c6a0718SPierre Ossman } 2741c6a0718SPierre Ossman 2751c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 2761c6a0718SPierre Ossman { 2771c6a0718SPierre Ossman void __iomem *base = host->base; 2781c6a0718SPierre Ossman char *ptr = buffer; 2791c6a0718SPierre Ossman u32 status; 28026eed9a5SLinus Walleij int host_remain = host->size; 2811c6a0718SPierre Ossman 2821c6a0718SPierre Ossman do { 28326eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 2841c6a0718SPierre Ossman 2851c6a0718SPierre Ossman if (count > remain) 2861c6a0718SPierre Ossman count = remain; 2871c6a0718SPierre Ossman 2881c6a0718SPierre Ossman if (count <= 0) 2891c6a0718SPierre Ossman break; 2901c6a0718SPierre Ossman 2911c6a0718SPierre Ossman readsl(base + MMCIFIFO, ptr, count >> 2); 2921c6a0718SPierre Ossman 2931c6a0718SPierre Ossman ptr += count; 2941c6a0718SPierre Ossman remain -= count; 29526eed9a5SLinus Walleij host_remain -= count; 2961c6a0718SPierre Ossman 2971c6a0718SPierre Ossman if (remain == 0) 2981c6a0718SPierre Ossman break; 2991c6a0718SPierre Ossman 3001c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 3011c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 3021c6a0718SPierre Ossman 3031c6a0718SPierre Ossman return ptr - buffer; 3041c6a0718SPierre Ossman } 3051c6a0718SPierre Ossman 3061c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 3071c6a0718SPierre Ossman { 3081c6a0718SPierre Ossman void __iomem *base = host->base; 3091c6a0718SPierre Ossman char *ptr = buffer; 3101c6a0718SPierre Ossman 3111c6a0718SPierre Ossman do { 3121c6a0718SPierre Ossman unsigned int count, maxcnt; 3131c6a0718SPierre Ossman 3141c6a0718SPierre Ossman maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; 3151c6a0718SPierre Ossman count = min(remain, maxcnt); 3161c6a0718SPierre Ossman 3171c6a0718SPierre Ossman writesl(base + MMCIFIFO, ptr, count >> 2); 3181c6a0718SPierre Ossman 3191c6a0718SPierre Ossman ptr += count; 3201c6a0718SPierre Ossman remain -= count; 3211c6a0718SPierre Ossman 3221c6a0718SPierre Ossman if (remain == 0) 3231c6a0718SPierre Ossman break; 3241c6a0718SPierre Ossman 3251c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 3261c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 3271c6a0718SPierre Ossman 3281c6a0718SPierre Ossman return ptr - buffer; 3291c6a0718SPierre Ossman } 3301c6a0718SPierre Ossman 3311c6a0718SPierre Ossman /* 3321c6a0718SPierre Ossman * PIO data transfer IRQ handler. 3331c6a0718SPierre Ossman */ 3341c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 3351c6a0718SPierre Ossman { 3361c6a0718SPierre Ossman struct mmci_host *host = dev_id; 3374ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 3381c6a0718SPierre Ossman void __iomem *base = host->base; 3394ce1d6cbSRabin Vincent unsigned long flags; 3401c6a0718SPierre Ossman u32 status; 3411c6a0718SPierre Ossman 3421c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 3431c6a0718SPierre Ossman 34464de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 3451c6a0718SPierre Ossman 3464ce1d6cbSRabin Vincent local_irq_save(flags); 3474ce1d6cbSRabin Vincent 3481c6a0718SPierre Ossman do { 3491c6a0718SPierre Ossman unsigned int remain, len; 3501c6a0718SPierre Ossman char *buffer; 3511c6a0718SPierre Ossman 3521c6a0718SPierre Ossman /* 3531c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 3541c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 3551c6a0718SPierre Ossman * definition it is more than half empty. 3561c6a0718SPierre Ossman * 3571c6a0718SPierre Ossman * For read, check for data available. 3581c6a0718SPierre Ossman */ 3591c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 3601c6a0718SPierre Ossman break; 3611c6a0718SPierre Ossman 3624ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 3634ce1d6cbSRabin Vincent break; 3644ce1d6cbSRabin Vincent 3654ce1d6cbSRabin Vincent buffer = sg_miter->addr; 3664ce1d6cbSRabin Vincent remain = sg_miter->length; 3671c6a0718SPierre Ossman 3681c6a0718SPierre Ossman len = 0; 3691c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 3701c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 3711c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 3721c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 3731c6a0718SPierre Ossman 3744ce1d6cbSRabin Vincent sg_miter->consumed = len; 3751c6a0718SPierre Ossman 3761c6a0718SPierre Ossman host->size -= len; 3771c6a0718SPierre Ossman remain -= len; 3781c6a0718SPierre Ossman 3791c6a0718SPierre Ossman if (remain) 3801c6a0718SPierre Ossman break; 3811c6a0718SPierre Ossman 3821c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 3834ce1d6cbSRabin Vincent flush_dcache_page(sg_miter->page); 3841c6a0718SPierre Ossman 3851c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 3861c6a0718SPierre Ossman } while (1); 3871c6a0718SPierre Ossman 3884ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 3894ce1d6cbSRabin Vincent 3904ce1d6cbSRabin Vincent local_irq_restore(flags); 3914ce1d6cbSRabin Vincent 3921c6a0718SPierre Ossman /* 3931c6a0718SPierre Ossman * If we're nearing the end of the read, switch to 3941c6a0718SPierre Ossman * "any data available" mode. 3951c6a0718SPierre Ossman */ 3961c6a0718SPierre Ossman if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) 3971c6a0718SPierre Ossman writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); 3981c6a0718SPierre Ossman 3991c6a0718SPierre Ossman /* 4001c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 4011c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 4021c6a0718SPierre Ossman * the chip itself has disabled the data path, and 4031c6a0718SPierre Ossman * stops us racing with our data end IRQ. 4041c6a0718SPierre Ossman */ 4051c6a0718SPierre Ossman if (host->size == 0) { 4061c6a0718SPierre Ossman writel(0, base + MMCIMASK1); 4071c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 4081c6a0718SPierre Ossman } 4091c6a0718SPierre Ossman 4101c6a0718SPierre Ossman return IRQ_HANDLED; 4111c6a0718SPierre Ossman } 4121c6a0718SPierre Ossman 4131c6a0718SPierre Ossman /* 4141c6a0718SPierre Ossman * Handle completion of command and data transfers. 4151c6a0718SPierre Ossman */ 4161c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 4171c6a0718SPierre Ossman { 4181c6a0718SPierre Ossman struct mmci_host *host = dev_id; 4191c6a0718SPierre Ossman u32 status; 4201c6a0718SPierre Ossman int ret = 0; 4211c6a0718SPierre Ossman 4221c6a0718SPierre Ossman spin_lock(&host->lock); 4231c6a0718SPierre Ossman 4241c6a0718SPierre Ossman do { 4251c6a0718SPierre Ossman struct mmc_command *cmd; 4261c6a0718SPierre Ossman struct mmc_data *data; 4271c6a0718SPierre Ossman 4281c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 4291c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 4301c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 4311c6a0718SPierre Ossman 43264de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 4331c6a0718SPierre Ossman 4341c6a0718SPierre Ossman data = host->data; 4351c6a0718SPierre Ossman if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 4361c6a0718SPierre Ossman MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 4371c6a0718SPierre Ossman mmci_data_irq(host, data, status); 4381c6a0718SPierre Ossman 4391c6a0718SPierre Ossman cmd = host->cmd; 4401c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 4411c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 4421c6a0718SPierre Ossman 4431c6a0718SPierre Ossman ret = 1; 4441c6a0718SPierre Ossman } while (status); 4451c6a0718SPierre Ossman 4461c6a0718SPierre Ossman spin_unlock(&host->lock); 4471c6a0718SPierre Ossman 4481c6a0718SPierre Ossman return IRQ_RETVAL(ret); 4491c6a0718SPierre Ossman } 4501c6a0718SPierre Ossman 4511c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 4521c6a0718SPierre Ossman { 4531c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 4549e943021SLinus Walleij unsigned long flags; 4551c6a0718SPierre Ossman 4561c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 4571c6a0718SPierre Ossman 458019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 45964de0289SLinus Walleij dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 46064de0289SLinus Walleij mrq->data->blksz); 461255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 462255d01afSPierre Ossman mmc_request_done(mmc, mrq); 463255d01afSPierre Ossman return; 464255d01afSPierre Ossman } 465255d01afSPierre Ossman 4669e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 4671c6a0718SPierre Ossman 4681c6a0718SPierre Ossman host->mrq = mrq; 4691c6a0718SPierre Ossman 4701c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 4711c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 4721c6a0718SPierre Ossman 4731c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 4741c6a0718SPierre Ossman 4759e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 4761c6a0718SPierre Ossman } 4771c6a0718SPierre Ossman 4781c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 4791c6a0718SPierre Ossman { 4801c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 481a6a6464aSLinus Walleij u32 pwr = 0; 482a6a6464aSLinus Walleij unsigned long flags; 4831c6a0718SPierre Ossman 4841c6a0718SPierre Ossman switch (ios->power_mode) { 4851c6a0718SPierre Ossman case MMC_POWER_OFF: 48634e84f39SLinus Walleij if(host->vcc && 48734e84f39SLinus Walleij regulator_is_enabled(host->vcc)) 48834e84f39SLinus Walleij regulator_disable(host->vcc); 4891c6a0718SPierre Ossman break; 4901c6a0718SPierre Ossman case MMC_POWER_UP: 49134e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 49234e84f39SLinus Walleij if (host->vcc) 49334e84f39SLinus Walleij /* This implicitly enables the regulator */ 49434e84f39SLinus Walleij mmc_regulator_set_ocr(host->vcc, ios->vdd); 49534e84f39SLinus Walleij #endif 49634e84f39SLinus Walleij /* 49734e84f39SLinus Walleij * The translate_vdd function is not used if you have 49834e84f39SLinus Walleij * an external regulator, or your design is really weird. 49934e84f39SLinus Walleij * Using it would mean sending in power control BOTH using 50034e84f39SLinus Walleij * a regulator AND the 4 MMCIPWR bits. If we don't have 50134e84f39SLinus Walleij * a regulator, we might have some other platform specific 50234e84f39SLinus Walleij * power control behind this translate function. 50334e84f39SLinus Walleij */ 50434e84f39SLinus Walleij if (!host->vcc && host->plat->translate_vdd) 50534e84f39SLinus Walleij pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); 506cc30d60eSLinus Walleij /* The ST version does not have this, fall through to POWER_ON */ 507f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) { 5081c6a0718SPierre Ossman pwr |= MCI_PWR_UP; 5091c6a0718SPierre Ossman break; 510cc30d60eSLinus Walleij } 5111c6a0718SPierre Ossman case MMC_POWER_ON: 5121c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 5131c6a0718SPierre Ossman break; 5141c6a0718SPierre Ossman } 5151c6a0718SPierre Ossman 516cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 517f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 5181c6a0718SPierre Ossman pwr |= MCI_ROD; 519cc30d60eSLinus Walleij else { 520cc30d60eSLinus Walleij /* 521cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 522cc30d60eSLinus Walleij * else and only has OD (Open Drain). 523cc30d60eSLinus Walleij */ 524cc30d60eSLinus Walleij pwr |= MCI_OD; 525cc30d60eSLinus Walleij } 526cc30d60eSLinus Walleij } 5271c6a0718SPierre Ossman 528a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 529a6a6464aSLinus Walleij 530a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 5311c6a0718SPierre Ossman 5321c6a0718SPierre Ossman if (host->pwr != pwr) { 5331c6a0718SPierre Ossman host->pwr = pwr; 5341c6a0718SPierre Ossman writel(pwr, host->base + MMCIPOWER); 5351c6a0718SPierre Ossman } 536a6a6464aSLinus Walleij 537a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 5381c6a0718SPierre Ossman } 5391c6a0718SPierre Ossman 54089001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 54189001446SRussell King { 54289001446SRussell King struct mmci_host *host = mmc_priv(mmc); 54389001446SRussell King 54489001446SRussell King if (host->gpio_wp == -ENOSYS) 54589001446SRussell King return -ENOSYS; 54689001446SRussell King 54789001446SRussell King return gpio_get_value(host->gpio_wp); 54889001446SRussell King } 54989001446SRussell King 55089001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 55189001446SRussell King { 55289001446SRussell King struct mmci_host *host = mmc_priv(mmc); 55389001446SRussell King unsigned int status; 55489001446SRussell King 55589001446SRussell King if (host->gpio_cd == -ENOSYS) 55689001446SRussell King status = host->plat->status(mmc_dev(host->mmc)); 55789001446SRussell King else 55889001446SRussell King status = gpio_get_value(host->gpio_cd); 55989001446SRussell King 56089001446SRussell King return !status; 56189001446SRussell King } 56289001446SRussell King 5631c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 5641c6a0718SPierre Ossman .request = mmci_request, 5651c6a0718SPierre Ossman .set_ios = mmci_set_ios, 56689001446SRussell King .get_ro = mmci_get_ro, 56789001446SRussell King .get_cd = mmci_get_cd, 5681c6a0718SPierre Ossman }; 5691c6a0718SPierre Ossman 5701c6a0718SPierre Ossman static void mmci_check_status(unsigned long data) 5711c6a0718SPierre Ossman { 5721c6a0718SPierre Ossman struct mmci_host *host = (struct mmci_host *)data; 57389001446SRussell King unsigned int status = mmci_get_cd(host->mmc); 5741c6a0718SPierre Ossman 5751c6a0718SPierre Ossman if (status ^ host->oldstat) 5761c6a0718SPierre Ossman mmc_detect_change(host->mmc, 0); 5771c6a0718SPierre Ossman 5781c6a0718SPierre Ossman host->oldstat = status; 5791c6a0718SPierre Ossman mod_timer(&host->timer, jiffies + HZ); 5801c6a0718SPierre Ossman } 5811c6a0718SPierre Ossman 58203fbdb15SAlessandro Rubini static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) 5831c6a0718SPierre Ossman { 5846ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 5851c6a0718SPierre Ossman struct mmci_host *host; 5861c6a0718SPierre Ossman struct mmc_host *mmc; 5871c6a0718SPierre Ossman int ret; 5881c6a0718SPierre Ossman 5891c6a0718SPierre Ossman /* must have platform data */ 5901c6a0718SPierre Ossman if (!plat) { 5911c6a0718SPierre Ossman ret = -EINVAL; 5921c6a0718SPierre Ossman goto out; 5931c6a0718SPierre Ossman } 5941c6a0718SPierre Ossman 5951c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 5961c6a0718SPierre Ossman if (ret) 5971c6a0718SPierre Ossman goto out; 5981c6a0718SPierre Ossman 5991c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 6001c6a0718SPierre Ossman if (!mmc) { 6011c6a0718SPierre Ossman ret = -ENOMEM; 6021c6a0718SPierre Ossman goto rel_regions; 6031c6a0718SPierre Ossman } 6041c6a0718SPierre Ossman 6051c6a0718SPierre Ossman host = mmc_priv(mmc); 6064ea580f1SRabin Vincent host->mmc = mmc; 607012b7d33SRussell King 60889001446SRussell King host->gpio_wp = -ENOSYS; 60989001446SRussell King host->gpio_cd = -ENOSYS; 61089001446SRussell King 611012b7d33SRussell King host->hw_designer = amba_manf(dev); 612012b7d33SRussell King host->hw_revision = amba_rev(dev); 61364de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 61464de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 615012b7d33SRussell King 616ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 6171c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 6181c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 6191c6a0718SPierre Ossman host->clk = NULL; 6201c6a0718SPierre Ossman goto host_free; 6211c6a0718SPierre Ossman } 6221c6a0718SPierre Ossman 6231c6a0718SPierre Ossman ret = clk_enable(host->clk); 6241c6a0718SPierre Ossman if (ret) 6251c6a0718SPierre Ossman goto clk_free; 6261c6a0718SPierre Ossman 6271c6a0718SPierre Ossman host->plat = plat; 6281c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 629c8df9a53SLinus Walleij /* 630c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 631c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 632c8df9a53SLinus Walleij * (if possible). 633c8df9a53SLinus Walleij */ 634c8df9a53SLinus Walleij if (host->mclk > 100000000) { 635c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 636c8df9a53SLinus Walleij if (ret < 0) 637c8df9a53SLinus Walleij goto clk_disable; 638c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 63964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 64064de0289SLinus Walleij host->mclk); 641c8df9a53SLinus Walleij } 642dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 6431c6a0718SPierre Ossman if (!host->base) { 6441c6a0718SPierre Ossman ret = -ENOMEM; 6451c6a0718SPierre Ossman goto clk_disable; 6461c6a0718SPierre Ossman } 6471c6a0718SPierre Ossman 6481c6a0718SPierre Ossman mmc->ops = &mmci_ops; 6491c6a0718SPierre Ossman mmc->f_min = (host->mclk + 511) / 512; 650808d97ccSLinus Walleij /* 651808d97ccSLinus Walleij * If the platform data supplies a maximum operating 652808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 653808d97ccSLinus Walleij * to using the module parameter, which has a (low) 654808d97ccSLinus Walleij * default value in case it is not specified. Either 655808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 656808d97ccSLinus Walleij * of course. 657808d97ccSLinus Walleij */ 658808d97ccSLinus Walleij if (plat->f_max) 659808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 660808d97ccSLinus Walleij else 6611c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 66264de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 66364de0289SLinus Walleij 66434e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 66534e84f39SLinus Walleij /* If we're using the regulator framework, try to fetch a regulator */ 66634e84f39SLinus Walleij host->vcc = regulator_get(&dev->dev, "vmmc"); 66734e84f39SLinus Walleij if (IS_ERR(host->vcc)) 66834e84f39SLinus Walleij host->vcc = NULL; 66934e84f39SLinus Walleij else { 67034e84f39SLinus Walleij int mask = mmc_regulator_get_ocrmask(host->vcc); 67134e84f39SLinus Walleij 67234e84f39SLinus Walleij if (mask < 0) 67334e84f39SLinus Walleij dev_err(&dev->dev, "error getting OCR mask (%d)\n", 67434e84f39SLinus Walleij mask); 67534e84f39SLinus Walleij else { 67634e84f39SLinus Walleij host->mmc->ocr_avail = (u32) mask; 67734e84f39SLinus Walleij if (plat->ocr_mask) 67834e84f39SLinus Walleij dev_warn(&dev->dev, 67934e84f39SLinus Walleij "Provided ocr_mask/setpower will not be used " 68034e84f39SLinus Walleij "(using regulator instead)\n"); 68134e84f39SLinus Walleij } 68234e84f39SLinus Walleij } 68334e84f39SLinus Walleij #endif 68434e84f39SLinus Walleij /* Fall back to platform data if no regulator is found */ 68534e84f39SLinus Walleij if (host->vcc == NULL) 6861c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 6879e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 6881c6a0718SPierre Ossman 6891c6a0718SPierre Ossman /* 6901c6a0718SPierre Ossman * We can do SGIO 6911c6a0718SPierre Ossman */ 6921c6a0718SPierre Ossman mmc->max_hw_segs = 16; 6931c6a0718SPierre Ossman mmc->max_phys_segs = NR_SG; 6941c6a0718SPierre Ossman 6951c6a0718SPierre Ossman /* 6961c6a0718SPierre Ossman * Since we only have a 16-bit data length register, we must 6971c6a0718SPierre Ossman * ensure that we don't exceed 2^16-1 bytes in a single request. 6981c6a0718SPierre Ossman */ 6991c6a0718SPierre Ossman mmc->max_req_size = 65535; 7001c6a0718SPierre Ossman 7011c6a0718SPierre Ossman /* 7021c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 7031c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 7041c6a0718SPierre Ossman */ 7051c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 7061c6a0718SPierre Ossman 7071c6a0718SPierre Ossman /* 7081c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 7091c6a0718SPierre Ossman */ 7101c6a0718SPierre Ossman mmc->max_blk_size = 2048; 7111c6a0718SPierre Ossman 7121c6a0718SPierre Ossman /* 7131c6a0718SPierre Ossman * No limit on the number of blocks transferred. 7141c6a0718SPierre Ossman */ 7151c6a0718SPierre Ossman mmc->max_blk_count = mmc->max_req_size; 7161c6a0718SPierre Ossman 7171c6a0718SPierre Ossman spin_lock_init(&host->lock); 7181c6a0718SPierre Ossman 7191c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 7201c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 7211c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 7221c6a0718SPierre Ossman 72389001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 72489001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 72589001446SRussell King if (ret == 0) 72689001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 72789001446SRussell King if (ret == 0) 72889001446SRussell King host->gpio_cd = plat->gpio_cd; 72989001446SRussell King else if (ret != -ENOSYS) 73089001446SRussell King goto err_gpio_cd; 73189001446SRussell King } 73289001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 73389001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 73489001446SRussell King if (ret == 0) 73589001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 73689001446SRussell King if (ret == 0) 73789001446SRussell King host->gpio_wp = plat->gpio_wp; 73889001446SRussell King else if (ret != -ENOSYS) 73989001446SRussell King goto err_gpio_wp; 74089001446SRussell King } 74189001446SRussell King 7421c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 7431c6a0718SPierre Ossman if (ret) 7441c6a0718SPierre Ossman goto unmap; 7451c6a0718SPierre Ossman 7461c6a0718SPierre Ossman ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); 7471c6a0718SPierre Ossman if (ret) 7481c6a0718SPierre Ossman goto irq0_free; 7491c6a0718SPierre Ossman 7501c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 7511c6a0718SPierre Ossman 7521c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 75389001446SRussell King host->oldstat = mmci_get_cd(host->mmc); 7541c6a0718SPierre Ossman 7551c6a0718SPierre Ossman mmc_add_host(mmc); 7561c6a0718SPierre Ossman 75764de0289SLinus Walleij dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", 7581c6a0718SPierre Ossman mmc_hostname(mmc), amba_rev(dev), amba_config(dev), 7591c6a0718SPierre Ossman (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 7601c6a0718SPierre Ossman 7611c6a0718SPierre Ossman init_timer(&host->timer); 7621c6a0718SPierre Ossman host->timer.data = (unsigned long)host; 7631c6a0718SPierre Ossman host->timer.function = mmci_check_status; 7641c6a0718SPierre Ossman host->timer.expires = jiffies + HZ; 7651c6a0718SPierre Ossman add_timer(&host->timer); 7661c6a0718SPierre Ossman 7671c6a0718SPierre Ossman return 0; 7681c6a0718SPierre Ossman 7691c6a0718SPierre Ossman irq0_free: 7701c6a0718SPierre Ossman free_irq(dev->irq[0], host); 7711c6a0718SPierre Ossman unmap: 77289001446SRussell King if (host->gpio_wp != -ENOSYS) 77389001446SRussell King gpio_free(host->gpio_wp); 77489001446SRussell King err_gpio_wp: 77589001446SRussell King if (host->gpio_cd != -ENOSYS) 77689001446SRussell King gpio_free(host->gpio_cd); 77789001446SRussell King err_gpio_cd: 7781c6a0718SPierre Ossman iounmap(host->base); 7791c6a0718SPierre Ossman clk_disable: 7801c6a0718SPierre Ossman clk_disable(host->clk); 7811c6a0718SPierre Ossman clk_free: 7821c6a0718SPierre Ossman clk_put(host->clk); 7831c6a0718SPierre Ossman host_free: 7841c6a0718SPierre Ossman mmc_free_host(mmc); 7851c6a0718SPierre Ossman rel_regions: 7861c6a0718SPierre Ossman amba_release_regions(dev); 7871c6a0718SPierre Ossman out: 7881c6a0718SPierre Ossman return ret; 7891c6a0718SPierre Ossman } 7901c6a0718SPierre Ossman 7916dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 7921c6a0718SPierre Ossman { 7931c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 7941c6a0718SPierre Ossman 7951c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 7961c6a0718SPierre Ossman 7971c6a0718SPierre Ossman if (mmc) { 7981c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 7991c6a0718SPierre Ossman 8001c6a0718SPierre Ossman del_timer_sync(&host->timer); 8011c6a0718SPierre Ossman 8021c6a0718SPierre Ossman mmc_remove_host(mmc); 8031c6a0718SPierre Ossman 8041c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 8051c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 8061c6a0718SPierre Ossman 8071c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 8081c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 8091c6a0718SPierre Ossman 8101c6a0718SPierre Ossman free_irq(dev->irq[0], host); 8111c6a0718SPierre Ossman free_irq(dev->irq[1], host); 8121c6a0718SPierre Ossman 81389001446SRussell King if (host->gpio_wp != -ENOSYS) 81489001446SRussell King gpio_free(host->gpio_wp); 81589001446SRussell King if (host->gpio_cd != -ENOSYS) 81689001446SRussell King gpio_free(host->gpio_cd); 81789001446SRussell King 8181c6a0718SPierre Ossman iounmap(host->base); 8191c6a0718SPierre Ossman clk_disable(host->clk); 8201c6a0718SPierre Ossman clk_put(host->clk); 8211c6a0718SPierre Ossman 82234e84f39SLinus Walleij if (regulator_is_enabled(host->vcc)) 82334e84f39SLinus Walleij regulator_disable(host->vcc); 82434e84f39SLinus Walleij regulator_put(host->vcc); 82534e84f39SLinus Walleij 8261c6a0718SPierre Ossman mmc_free_host(mmc); 8271c6a0718SPierre Ossman 8281c6a0718SPierre Ossman amba_release_regions(dev); 8291c6a0718SPierre Ossman } 8301c6a0718SPierre Ossman 8311c6a0718SPierre Ossman return 0; 8321c6a0718SPierre Ossman } 8331c6a0718SPierre Ossman 8341c6a0718SPierre Ossman #ifdef CONFIG_PM 8351c6a0718SPierre Ossman static int mmci_suspend(struct amba_device *dev, pm_message_t state) 8361c6a0718SPierre Ossman { 8371c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 8381c6a0718SPierre Ossman int ret = 0; 8391c6a0718SPierre Ossman 8401c6a0718SPierre Ossman if (mmc) { 8411c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 8421c6a0718SPierre Ossman 8431a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 8441c6a0718SPierre Ossman if (ret == 0) 8451c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 8461c6a0718SPierre Ossman } 8471c6a0718SPierre Ossman 8481c6a0718SPierre Ossman return ret; 8491c6a0718SPierre Ossman } 8501c6a0718SPierre Ossman 8511c6a0718SPierre Ossman static int mmci_resume(struct amba_device *dev) 8521c6a0718SPierre Ossman { 8531c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 8541c6a0718SPierre Ossman int ret = 0; 8551c6a0718SPierre Ossman 8561c6a0718SPierre Ossman if (mmc) { 8571c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 8581c6a0718SPierre Ossman 8591c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 8601c6a0718SPierre Ossman 8611c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 8621c6a0718SPierre Ossman } 8631c6a0718SPierre Ossman 8641c6a0718SPierre Ossman return ret; 8651c6a0718SPierre Ossman } 8661c6a0718SPierre Ossman #else 8671c6a0718SPierre Ossman #define mmci_suspend NULL 8681c6a0718SPierre Ossman #define mmci_resume NULL 8691c6a0718SPierre Ossman #endif 8701c6a0718SPierre Ossman 8711c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 8721c6a0718SPierre Ossman { 8731c6a0718SPierre Ossman .id = 0x00041180, 8741c6a0718SPierre Ossman .mask = 0x000fffff, 8751c6a0718SPierre Ossman }, 8761c6a0718SPierre Ossman { 8771c6a0718SPierre Ossman .id = 0x00041181, 8781c6a0718SPierre Ossman .mask = 0x000fffff, 8791c6a0718SPierre Ossman }, 880cc30d60eSLinus Walleij /* ST Micro variants */ 881cc30d60eSLinus Walleij { 882cc30d60eSLinus Walleij .id = 0x00180180, 883cc30d60eSLinus Walleij .mask = 0x00ffffff, 884cc30d60eSLinus Walleij }, 885cc30d60eSLinus Walleij { 886cc30d60eSLinus Walleij .id = 0x00280180, 887cc30d60eSLinus Walleij .mask = 0x00ffffff, 888cc30d60eSLinus Walleij }, 8891c6a0718SPierre Ossman { 0, 0 }, 8901c6a0718SPierre Ossman }; 8911c6a0718SPierre Ossman 8921c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 8931c6a0718SPierre Ossman .drv = { 8941c6a0718SPierre Ossman .name = DRIVER_NAME, 8951c6a0718SPierre Ossman }, 8961c6a0718SPierre Ossman .probe = mmci_probe, 8976dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 8981c6a0718SPierre Ossman .suspend = mmci_suspend, 8991c6a0718SPierre Ossman .resume = mmci_resume, 9001c6a0718SPierre Ossman .id_table = mmci_ids, 9011c6a0718SPierre Ossman }; 9021c6a0718SPierre Ossman 9031c6a0718SPierre Ossman static int __init mmci_init(void) 9041c6a0718SPierre Ossman { 9051c6a0718SPierre Ossman return amba_driver_register(&mmci_driver); 9061c6a0718SPierre Ossman } 9071c6a0718SPierre Ossman 9081c6a0718SPierre Ossman static void __exit mmci_exit(void) 9091c6a0718SPierre Ossman { 9101c6a0718SPierre Ossman amba_driver_unregister(&mmci_driver); 9111c6a0718SPierre Ossman } 9121c6a0718SPierre Ossman 9131c6a0718SPierre Ossman module_init(mmci_init); 9141c6a0718SPierre Ossman module_exit(mmci_exit); 9151c6a0718SPierre Ossman module_param(fmax, uint, 0444); 9161c6a0718SPierre Ossman 9171c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 9181c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 919