11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 18000bc9d5SLee Jones #include <linux/slab.h> 191c6a0718SPierre Ossman #include <linux/delay.h> 201c6a0718SPierre Ossman #include <linux/err.h> 211c6a0718SPierre Ossman #include <linux/highmem.h> 22019a5f56SNicolas Pitre #include <linux/log2.h> 231c6a0718SPierre Ossman #include <linux/mmc/host.h> 2434177802SLinus Walleij #include <linux/mmc/card.h> 251c6a0718SPierre Ossman #include <linux/amba/bus.h> 261c6a0718SPierre Ossman #include <linux/clk.h> 27bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2889001446SRussell King #include <linux/gpio.h> 299a597016SLee Jones #include <linux/of_gpio.h> 3034e84f39SLinus Walleij #include <linux/regulator/consumer.h> 31c8ebae37SRussell King #include <linux/dmaengine.h> 32c8ebae37SRussell King #include <linux/dma-mapping.h> 33c8ebae37SRussell King #include <linux/amba/mmci.h> 341c3be369SRussell King #include <linux/pm_runtime.h> 35258aea76SViresh Kumar #include <linux/types.h> 36a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 371c6a0718SPierre Ossman 381c6a0718SPierre Ossman #include <asm/div64.h> 391c6a0718SPierre Ossman #include <asm/io.h> 401c6a0718SPierre Ossman #include <asm/sizes.h> 411c6a0718SPierre Ossman 421c6a0718SPierre Ossman #include "mmci.h" 431c6a0718SPierre Ossman 441c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 451c6a0718SPierre Ossman 461c6a0718SPierre Ossman static unsigned int fmax = 515633; 471c6a0718SPierre Ossman 484956e109SRabin Vincent /** 494956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 504956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 514380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 5208458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 538301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 548301bb68SRabin Vincent * is asserted (likewise for RX) 558301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 568301bb68SRabin Vincent * is asserted (likewise for RX) 5734177802SLinus Walleij * @sdio: variant supports SDIO 58b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 591784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 607d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 614d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 624956e109SRabin Vincent */ 634956e109SRabin Vincent struct variant_data { 644956e109SRabin Vincent unsigned int clkreg; 654380c14fSRabin Vincent unsigned int clkreg_enable; 6608458ef6SRabin Vincent unsigned int datalength_bits; 678301bb68SRabin Vincent unsigned int fifosize; 688301bb68SRabin Vincent unsigned int fifohalfsize; 6934177802SLinus Walleij bool sdio; 70b70a67f9SLinus Walleij bool st_clkdiv; 711784b157SPhilippe Langlais bool blksz_datactrl16; 727d72a1d4SUlf Hansson u32 pwrreg_powerup; 734d1a3a0dSUlf Hansson bool signal_direction; 744956e109SRabin Vincent }; 754956e109SRabin Vincent 764956e109SRabin Vincent static struct variant_data variant_arm = { 778301bb68SRabin Vincent .fifosize = 16 * 4, 788301bb68SRabin Vincent .fifohalfsize = 8 * 4, 7908458ef6SRabin Vincent .datalength_bits = 16, 807d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 814956e109SRabin Vincent }; 824956e109SRabin Vincent 83768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 84768fbc18SPawel Moll .fifosize = 128 * 4, 85768fbc18SPawel Moll .fifohalfsize = 64 * 4, 86768fbc18SPawel Moll .datalength_bits = 16, 877d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 88768fbc18SPawel Moll }; 89768fbc18SPawel Moll 904956e109SRabin Vincent static struct variant_data variant_u300 = { 918301bb68SRabin Vincent .fifosize = 16 * 4, 928301bb68SRabin Vincent .fifohalfsize = 8 * 4, 9349ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 9408458ef6SRabin Vincent .datalength_bits = 16, 9534177802SLinus Walleij .sdio = true, 967d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 974d1a3a0dSUlf Hansson .signal_direction = true, 984956e109SRabin Vincent }; 994956e109SRabin Vincent 10034fd4213SLinus Walleij static struct variant_data variant_nomadik = { 10134fd4213SLinus Walleij .fifosize = 16 * 4, 10234fd4213SLinus Walleij .fifohalfsize = 8 * 4, 10334fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 10434fd4213SLinus Walleij .datalength_bits = 24, 10534fd4213SLinus Walleij .sdio = true, 10634fd4213SLinus Walleij .st_clkdiv = true, 10734fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 10834fd4213SLinus Walleij .signal_direction = true, 10934fd4213SLinus Walleij }; 11034fd4213SLinus Walleij 1114956e109SRabin Vincent static struct variant_data variant_ux500 = { 1128301bb68SRabin Vincent .fifosize = 30 * 4, 1138301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1144956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 11549ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 11608458ef6SRabin Vincent .datalength_bits = 24, 11734177802SLinus Walleij .sdio = true, 118b70a67f9SLinus Walleij .st_clkdiv = true, 1197d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1204d1a3a0dSUlf Hansson .signal_direction = true, 1214956e109SRabin Vincent }; 122b70a67f9SLinus Walleij 1231784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1241784b157SPhilippe Langlais .fifosize = 30 * 4, 1251784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1261784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1271784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1281784b157SPhilippe Langlais .datalength_bits = 24, 1291784b157SPhilippe Langlais .sdio = true, 1301784b157SPhilippe Langlais .st_clkdiv = true, 1311784b157SPhilippe Langlais .blksz_datactrl16 = true, 1327d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1334d1a3a0dSUlf Hansson .signal_direction = true, 1341784b157SPhilippe Langlais }; 1351784b157SPhilippe Langlais 136a6a6464aSLinus Walleij /* 137a6a6464aSLinus Walleij * This must be called with host->lock held 138a6a6464aSLinus Walleij */ 1397437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 1407437cfa5SUlf Hansson { 1417437cfa5SUlf Hansson if (host->clk_reg != clk) { 1427437cfa5SUlf Hansson host->clk_reg = clk; 1437437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 1447437cfa5SUlf Hansson } 1457437cfa5SUlf Hansson } 1467437cfa5SUlf Hansson 1477437cfa5SUlf Hansson /* 1487437cfa5SUlf Hansson * This must be called with host->lock held 1497437cfa5SUlf Hansson */ 1507437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 1517437cfa5SUlf Hansson { 1527437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 1537437cfa5SUlf Hansson host->pwr_reg = pwr; 1547437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 1557437cfa5SUlf Hansson } 1567437cfa5SUlf Hansson } 1577437cfa5SUlf Hansson 1587437cfa5SUlf Hansson /* 1597437cfa5SUlf Hansson * This must be called with host->lock held 1607437cfa5SUlf Hansson */ 161a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 162a6a6464aSLinus Walleij { 1634956e109SRabin Vincent struct variant_data *variant = host->variant; 1644956e109SRabin Vincent u32 clk = variant->clkreg; 165a6a6464aSLinus Walleij 166a6a6464aSLinus Walleij if (desired) { 167a6a6464aSLinus Walleij if (desired >= host->mclk) { 168a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 169399bc486SLinus Walleij if (variant->st_clkdiv) 170399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 171a6a6464aSLinus Walleij host->cclk = host->mclk; 172b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 173b70a67f9SLinus Walleij /* 174b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 175b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 176b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 177b70a67f9SLinus Walleij * frequency 178b70a67f9SLinus Walleij */ 179b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 180b70a67f9SLinus Walleij if (clk >= 256) 181b70a67f9SLinus Walleij clk = 255; 182b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 183a6a6464aSLinus Walleij } else { 184b70a67f9SLinus Walleij /* 185b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 186b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 187b70a67f9SLinus Walleij */ 188a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 189a6a6464aSLinus Walleij if (clk >= 256) 190a6a6464aSLinus Walleij clk = 255; 191a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 192a6a6464aSLinus Walleij } 1934380c14fSRabin Vincent 1944380c14fSRabin Vincent clk |= variant->clkreg_enable; 195a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 196a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 197a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 198a6a6464aSLinus Walleij } 199a6a6464aSLinus Walleij 2009e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 201771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 202771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 203771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 2049e6c82cdSLinus Walleij 2057437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 206a6a6464aSLinus Walleij } 207a6a6464aSLinus Walleij 2081c6a0718SPierre Ossman static void 2091c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 2101c6a0718SPierre Ossman { 2111c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 2121c6a0718SPierre Ossman 2131c6a0718SPierre Ossman BUG_ON(host->data); 2141c6a0718SPierre Ossman 2151c6a0718SPierre Ossman host->mrq = NULL; 2161c6a0718SPierre Ossman host->cmd = NULL; 2171c6a0718SPierre Ossman 2181c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 2192cd976c4SUlf Hansson 2202cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 2212cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 2221c6a0718SPierre Ossman } 2231c6a0718SPierre Ossman 2242686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 2252686b4b4SLinus Walleij { 2262686b4b4SLinus Walleij void __iomem *base = host->base; 2272686b4b4SLinus Walleij 2282686b4b4SLinus Walleij if (host->singleirq) { 2292686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 2302686b4b4SLinus Walleij 2312686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 2322686b4b4SLinus Walleij mask0 |= mask; 2332686b4b4SLinus Walleij 2342686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 2352686b4b4SLinus Walleij } 2362686b4b4SLinus Walleij 2372686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 2382686b4b4SLinus Walleij } 2392686b4b4SLinus Walleij 2401c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 2411c6a0718SPierre Ossman { 2421c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 2432686b4b4SLinus Walleij mmci_set_mask1(host, 0); 2441c6a0718SPierre Ossman host->data = NULL; 2451c6a0718SPierre Ossman } 2461c6a0718SPierre Ossman 2474ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 2484ce1d6cbSRabin Vincent { 2494ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 2504ce1d6cbSRabin Vincent 2514ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 2524ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 2534ce1d6cbSRabin Vincent else 2544ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 2554ce1d6cbSRabin Vincent 2564ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 2574ce1d6cbSRabin Vincent } 2584ce1d6cbSRabin Vincent 259c8ebae37SRussell King /* 260c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 261c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 262c8ebae37SRussell King * no custom DMA interfaces are supported. 263c8ebae37SRussell King */ 264c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 265c8ebae37SRussell King static void __devinit mmci_dma_setup(struct mmci_host *host) 266c8ebae37SRussell King { 267c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 268c8ebae37SRussell King const char *rxname, *txname; 269c8ebae37SRussell King dma_cap_mask_t mask; 270c8ebae37SRussell King 271c8ebae37SRussell King if (!plat || !plat->dma_filter) { 272c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 273c8ebae37SRussell King return; 274c8ebae37SRussell King } 275c8ebae37SRussell King 27658c7ccbfSPer Forlin /* initialize pre request cookie */ 27758c7ccbfSPer Forlin host->next_data.cookie = 1; 27858c7ccbfSPer Forlin 279c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 280c8ebae37SRussell King dma_cap_zero(mask); 281c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 282c8ebae37SRussell King 283c8ebae37SRussell King /* 284c8ebae37SRussell King * If only an RX channel is specified, the driver will 285c8ebae37SRussell King * attempt to use it bidirectionally, however if it is 286c8ebae37SRussell King * is specified but cannot be located, DMA will be disabled. 287c8ebae37SRussell King */ 288c8ebae37SRussell King if (plat->dma_rx_param) { 289c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 290c8ebae37SRussell King plat->dma_filter, 291c8ebae37SRussell King plat->dma_rx_param); 292c8ebae37SRussell King /* E.g if no DMA hardware is present */ 293c8ebae37SRussell King if (!host->dma_rx_channel) 294c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 295c8ebae37SRussell King } 296c8ebae37SRussell King 297c8ebae37SRussell King if (plat->dma_tx_param) { 298c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 299c8ebae37SRussell King plat->dma_filter, 300c8ebae37SRussell King plat->dma_tx_param); 301c8ebae37SRussell King if (!host->dma_tx_channel) 302c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 303c8ebae37SRussell King } else { 304c8ebae37SRussell King host->dma_tx_channel = host->dma_rx_channel; 305c8ebae37SRussell King } 306c8ebae37SRussell King 307c8ebae37SRussell King if (host->dma_rx_channel) 308c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 309c8ebae37SRussell King else 310c8ebae37SRussell King rxname = "none"; 311c8ebae37SRussell King 312c8ebae37SRussell King if (host->dma_tx_channel) 313c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 314c8ebae37SRussell King else 315c8ebae37SRussell King txname = "none"; 316c8ebae37SRussell King 317c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 318c8ebae37SRussell King rxname, txname); 319c8ebae37SRussell King 320c8ebae37SRussell King /* 321c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 322c8ebae37SRussell King * the parameters of the DMA engine device. 323c8ebae37SRussell King */ 324c8ebae37SRussell King if (host->dma_tx_channel) { 325c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 326c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 327c8ebae37SRussell King 328c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 329c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 330c8ebae37SRussell King } 331c8ebae37SRussell King if (host->dma_rx_channel) { 332c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 333c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 334c8ebae37SRussell King 335c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 336c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 337c8ebae37SRussell King } 338c8ebae37SRussell King } 339c8ebae37SRussell King 340c8ebae37SRussell King /* 341c8ebae37SRussell King * This is used in __devinit or __devexit so inline it 342c8ebae37SRussell King * so it can be discarded. 343c8ebae37SRussell King */ 344c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 345c8ebae37SRussell King { 346c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 347c8ebae37SRussell King 348c8ebae37SRussell King if (host->dma_rx_channel) 349c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 350c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 351c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 352c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 353c8ebae37SRussell King } 354c8ebae37SRussell King 355c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 356c8ebae37SRussell King { 357c8ebae37SRussell King struct dma_chan *chan = host->dma_current; 358c8ebae37SRussell King enum dma_data_direction dir; 359c8ebae37SRussell King u32 status; 360c8ebae37SRussell King int i; 361c8ebae37SRussell King 362c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 363c8ebae37SRussell King for (i = 0; ; i++) { 364c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 365c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 366c8ebae37SRussell King break; 367c8ebae37SRussell King udelay(10); 368c8ebae37SRussell King } 369c8ebae37SRussell King 370c8ebae37SRussell King /* 371c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 372c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 373c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 374c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 375c8ebae37SRussell King */ 376c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 377c8ebae37SRussell King dmaengine_terminate_all(chan); 378c8ebae37SRussell King if (!data->error) 379c8ebae37SRussell King data->error = -EIO; 380c8ebae37SRussell King } 381c8ebae37SRussell King 382c8ebae37SRussell King if (data->flags & MMC_DATA_WRITE) { 383c8ebae37SRussell King dir = DMA_TO_DEVICE; 384c8ebae37SRussell King } else { 385c8ebae37SRussell King dir = DMA_FROM_DEVICE; 386c8ebae37SRussell King } 387c8ebae37SRussell King 38858c7ccbfSPer Forlin if (!data->host_cookie) 389c8ebae37SRussell King dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 390c8ebae37SRussell King 391c8ebae37SRussell King /* 392c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 393c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 394c8ebae37SRussell King */ 395c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 396c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 397c8ebae37SRussell King mmci_dma_release(host); 398c8ebae37SRussell King } 399c8ebae37SRussell King } 400c8ebae37SRussell King 401c8ebae37SRussell King static void mmci_dma_data_error(struct mmci_host *host) 402c8ebae37SRussell King { 403c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 404c8ebae37SRussell King dmaengine_terminate_all(host->dma_current); 405c8ebae37SRussell King } 406c8ebae37SRussell King 40758c7ccbfSPer Forlin static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 40858c7ccbfSPer Forlin struct mmci_host_next *next) 409c8ebae37SRussell King { 410c8ebae37SRussell King struct variant_data *variant = host->variant; 411c8ebae37SRussell King struct dma_slave_config conf = { 412c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 413c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 414c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 415c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 416c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 417c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 418258aea76SViresh Kumar .device_fc = false, 419c8ebae37SRussell King }; 420c8ebae37SRussell King struct dma_chan *chan; 421c8ebae37SRussell King struct dma_device *device; 422c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 42305f5799cSVinod Koul enum dma_data_direction buffer_dirn; 424c8ebae37SRussell King int nr_sg; 425c8ebae37SRussell King 42658c7ccbfSPer Forlin /* Check if next job is already prepared */ 42758c7ccbfSPer Forlin if (data->host_cookie && !next && 42858c7ccbfSPer Forlin host->dma_current && host->dma_desc_current) 42958c7ccbfSPer Forlin return 0; 43058c7ccbfSPer Forlin 43158c7ccbfSPer Forlin if (!next) { 432c8ebae37SRussell King host->dma_current = NULL; 43358c7ccbfSPer Forlin host->dma_desc_current = NULL; 43458c7ccbfSPer Forlin } 435c8ebae37SRussell King 436c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 43705f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 43805f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 439c8ebae37SRussell King chan = host->dma_rx_channel; 440c8ebae37SRussell King } else { 44105f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 44205f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 443c8ebae37SRussell King chan = host->dma_tx_channel; 444c8ebae37SRussell King } 445c8ebae37SRussell King 446c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 447c8ebae37SRussell King if (!chan) 448c8ebae37SRussell King return -EINVAL; 449c8ebae37SRussell King 450c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 45158c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 452c8ebae37SRussell King return -EINVAL; 453c8ebae37SRussell King 454c8ebae37SRussell King device = chan->device; 45505f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 456c8ebae37SRussell King if (nr_sg == 0) 457c8ebae37SRussell King return -EINVAL; 458c8ebae37SRussell King 459c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 46016052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 461c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 462c8ebae37SRussell King if (!desc) 463c8ebae37SRussell King goto unmap_exit; 464c8ebae37SRussell King 46558c7ccbfSPer Forlin if (next) { 46658c7ccbfSPer Forlin next->dma_chan = chan; 46758c7ccbfSPer Forlin next->dma_desc = desc; 46858c7ccbfSPer Forlin } else { 469c8ebae37SRussell King host->dma_current = chan; 47058c7ccbfSPer Forlin host->dma_desc_current = desc; 47158c7ccbfSPer Forlin } 472c8ebae37SRussell King 47358c7ccbfSPer Forlin return 0; 47458c7ccbfSPer Forlin 47558c7ccbfSPer Forlin unmap_exit: 47658c7ccbfSPer Forlin if (!next) 47758c7ccbfSPer Forlin dmaengine_terminate_all(chan); 47805f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 47958c7ccbfSPer Forlin return -ENOMEM; 48058c7ccbfSPer Forlin } 48158c7ccbfSPer Forlin 48258c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 48358c7ccbfSPer Forlin { 48458c7ccbfSPer Forlin int ret; 48558c7ccbfSPer Forlin struct mmc_data *data = host->data; 48658c7ccbfSPer Forlin 48758c7ccbfSPer Forlin ret = mmci_dma_prep_data(host, host->data, NULL); 48858c7ccbfSPer Forlin if (ret) 48958c7ccbfSPer Forlin return ret; 49058c7ccbfSPer Forlin 49158c7ccbfSPer Forlin /* Okay, go for it. */ 492c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 493c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 494c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 49558c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 49658c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 497c8ebae37SRussell King 498c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 499c8ebae37SRussell King 500c8ebae37SRussell King /* Trigger the DMA transfer */ 501c8ebae37SRussell King writel(datactrl, host->base + MMCIDATACTRL); 502c8ebae37SRussell King 503c8ebae37SRussell King /* 504c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 505c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 506c8ebae37SRussell King * call mmci_data_end() 507c8ebae37SRussell King */ 508c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 509c8ebae37SRussell King host->base + MMCIMASK0); 510c8ebae37SRussell King return 0; 511c8ebae37SRussell King } 51258c7ccbfSPer Forlin 51358c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 51458c7ccbfSPer Forlin { 51558c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 51658c7ccbfSPer Forlin 51758c7ccbfSPer Forlin if (data->host_cookie && data->host_cookie != next->cookie) { 518a3c76eb9SGirish K S pr_warning("[%s] invalid cookie: data->host_cookie %d" 51958c7ccbfSPer Forlin " host->next_data.cookie %d\n", 52058c7ccbfSPer Forlin __func__, data->host_cookie, host->next_data.cookie); 52158c7ccbfSPer Forlin data->host_cookie = 0; 52258c7ccbfSPer Forlin } 52358c7ccbfSPer Forlin 52458c7ccbfSPer Forlin if (!data->host_cookie) 52558c7ccbfSPer Forlin return; 52658c7ccbfSPer Forlin 52758c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 52858c7ccbfSPer Forlin host->dma_current = next->dma_chan; 52958c7ccbfSPer Forlin 53058c7ccbfSPer Forlin next->dma_desc = NULL; 53158c7ccbfSPer Forlin next->dma_chan = NULL; 53258c7ccbfSPer Forlin } 53358c7ccbfSPer Forlin 53458c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 53558c7ccbfSPer Forlin bool is_first_req) 53658c7ccbfSPer Forlin { 53758c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 53858c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 53958c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 54058c7ccbfSPer Forlin 54158c7ccbfSPer Forlin if (!data) 54258c7ccbfSPer Forlin return; 54358c7ccbfSPer Forlin 54458c7ccbfSPer Forlin if (data->host_cookie) { 54558c7ccbfSPer Forlin data->host_cookie = 0; 54658c7ccbfSPer Forlin return; 54758c7ccbfSPer Forlin } 54858c7ccbfSPer Forlin 54958c7ccbfSPer Forlin /* if config for dma */ 55058c7ccbfSPer Forlin if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 55158c7ccbfSPer Forlin ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 55258c7ccbfSPer Forlin if (mmci_dma_prep_data(host, data, nd)) 55358c7ccbfSPer Forlin data->host_cookie = 0; 55458c7ccbfSPer Forlin else 55558c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 55658c7ccbfSPer Forlin } 55758c7ccbfSPer Forlin } 55858c7ccbfSPer Forlin 55958c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 56058c7ccbfSPer Forlin int err) 56158c7ccbfSPer Forlin { 56258c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 56358c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 56458c7ccbfSPer Forlin struct dma_chan *chan; 56558c7ccbfSPer Forlin enum dma_data_direction dir; 56658c7ccbfSPer Forlin 56758c7ccbfSPer Forlin if (!data) 56858c7ccbfSPer Forlin return; 56958c7ccbfSPer Forlin 57058c7ccbfSPer Forlin if (data->flags & MMC_DATA_READ) { 57158c7ccbfSPer Forlin dir = DMA_FROM_DEVICE; 57258c7ccbfSPer Forlin chan = host->dma_rx_channel; 57358c7ccbfSPer Forlin } else { 57458c7ccbfSPer Forlin dir = DMA_TO_DEVICE; 57558c7ccbfSPer Forlin chan = host->dma_tx_channel; 57658c7ccbfSPer Forlin } 57758c7ccbfSPer Forlin 57858c7ccbfSPer Forlin 57958c7ccbfSPer Forlin /* if config for dma */ 58058c7ccbfSPer Forlin if (chan) { 58158c7ccbfSPer Forlin if (err) 58258c7ccbfSPer Forlin dmaengine_terminate_all(chan); 5838e3336b1SPer Forlin if (data->host_cookie) 58458c7ccbfSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 58558c7ccbfSPer Forlin data->sg_len, dir); 58658c7ccbfSPer Forlin mrq->data->host_cookie = 0; 58758c7ccbfSPer Forlin } 58858c7ccbfSPer Forlin } 58958c7ccbfSPer Forlin 590c8ebae37SRussell King #else 591c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 59258c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 59358c7ccbfSPer Forlin { 59458c7ccbfSPer Forlin } 595c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 596c8ebae37SRussell King { 597c8ebae37SRussell King } 598c8ebae37SRussell King 599c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 600c8ebae37SRussell King { 601c8ebae37SRussell King } 602c8ebae37SRussell King 603c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 604c8ebae37SRussell King { 605c8ebae37SRussell King } 606c8ebae37SRussell King 607c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 608c8ebae37SRussell King { 609c8ebae37SRussell King } 610c8ebae37SRussell King 611c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 612c8ebae37SRussell King { 613c8ebae37SRussell King return -ENOSYS; 614c8ebae37SRussell King } 61558c7ccbfSPer Forlin 61658c7ccbfSPer Forlin #define mmci_pre_request NULL 61758c7ccbfSPer Forlin #define mmci_post_request NULL 61858c7ccbfSPer Forlin 619c8ebae37SRussell King #endif 620c8ebae37SRussell King 6211c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 6221c6a0718SPierre Ossman { 6238301bb68SRabin Vincent struct variant_data *variant = host->variant; 6241c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 6251c6a0718SPierre Ossman unsigned long long clks; 6261c6a0718SPierre Ossman void __iomem *base; 6271c6a0718SPierre Ossman int blksz_bits; 6281c6a0718SPierre Ossman 62964de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 6301c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 6311c6a0718SPierre Ossman 6321c6a0718SPierre Ossman host->data = data; 633528320dbSRabin Vincent host->size = data->blksz * data->blocks; 63451d4375dSRussell King data->bytes_xfered = 0; 6351c6a0718SPierre Ossman 6361c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 6371c6a0718SPierre Ossman do_div(clks, 1000000000UL); 6381c6a0718SPierre Ossman 6391c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 6401c6a0718SPierre Ossman 6411c6a0718SPierre Ossman base = host->base; 6421c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 6431c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 6441c6a0718SPierre Ossman 6451c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 6461c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 6471c6a0718SPierre Ossman 6481784b157SPhilippe Langlais if (variant->blksz_datactrl16) 6491784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 6501784b157SPhilippe Langlais else 6511c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 652c8ebae37SRussell King 653c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 6541c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 655c8ebae37SRussell King 6567258db7eSUlf Hansson /* The ST Micro variants has a special bit to enable SDIO */ 6577258db7eSUlf Hansson if (variant->sdio && host->mmc->card) 65806c1a121SUlf Hansson if (mmc_card_sdio(host->mmc->card)) { 65906c1a121SUlf Hansson /* 66006c1a121SUlf Hansson * The ST Micro variants has a special bit 66106c1a121SUlf Hansson * to enable SDIO. 66206c1a121SUlf Hansson */ 66306c1a121SUlf Hansson u32 clk; 66406c1a121SUlf Hansson 6657258db7eSUlf Hansson datactrl |= MCI_ST_DPSM_SDIOEN; 6667258db7eSUlf Hansson 667c8ebae37SRussell King /* 66870ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 66970ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 67070ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 67170ac0935SUlf Hansson * depends on the rate of MCLK. 67206c1a121SUlf Hansson */ 67370ac0935SUlf Hansson if (data->flags & MMC_DATA_WRITE && 67470ac0935SUlf Hansson (host->size < 8 || 67570ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 67606c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 67706c1a121SUlf Hansson else 67806c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 67906c1a121SUlf Hansson 68006c1a121SUlf Hansson mmci_write_clkreg(host, clk); 68106c1a121SUlf Hansson } 68206c1a121SUlf Hansson 68306c1a121SUlf Hansson /* 684c8ebae37SRussell King * Attempt to use DMA operation mode, if this 685c8ebae37SRussell King * should fail, fall back to PIO mode 686c8ebae37SRussell King */ 687c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 688c8ebae37SRussell King return; 689c8ebae37SRussell King 690c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 691c8ebae37SRussell King mmci_init_sg(host, data); 692c8ebae37SRussell King 693c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 6941c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 6951c6a0718SPierre Ossman 6961c6a0718SPierre Ossman /* 697c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 698c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 699c4d877c1SRussell King * is available. 7001c6a0718SPierre Ossman */ 701c4d877c1SRussell King if (host->size < variant->fifohalfsize) 7021c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 7031c6a0718SPierre Ossman } else { 7041c6a0718SPierre Ossman /* 7051c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 7061c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 7071c6a0718SPierre Ossman */ 7081c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 7091c6a0718SPierre Ossman } 7101c6a0718SPierre Ossman 7111c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 7121c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 7132686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 7141c6a0718SPierre Ossman } 7151c6a0718SPierre Ossman 7161c6a0718SPierre Ossman static void 7171c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 7181c6a0718SPierre Ossman { 7191c6a0718SPierre Ossman void __iomem *base = host->base; 7201c6a0718SPierre Ossman 72164de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 7221c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 7231c6a0718SPierre Ossman 7241c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 7251c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 7261c6a0718SPierre Ossman udelay(1); 7271c6a0718SPierre Ossman } 7281c6a0718SPierre Ossman 7291c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 7301c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 7311c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 7321c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 7331c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 7341c6a0718SPierre Ossman } 7351c6a0718SPierre Ossman if (/*interrupt*/0) 7361c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 7371c6a0718SPierre Ossman 7381c6a0718SPierre Ossman host->cmd = cmd; 7391c6a0718SPierre Ossman 7401c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 7411c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 7421c6a0718SPierre Ossman } 7431c6a0718SPierre Ossman 7441c6a0718SPierre Ossman static void 7451c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 7461c6a0718SPierre Ossman unsigned int status) 7471c6a0718SPierre Ossman { 748f20f8f21SLinus Walleij /* First check for errors */ 749b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 750b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 7518cb28155SLinus Walleij u32 remain, success; 752f20f8f21SLinus Walleij 753c8ebae37SRussell King /* Terminate the DMA transfer */ 754c8ebae37SRussell King if (dma_inprogress(host)) 755c8ebae37SRussell King mmci_dma_data_error(host); 756c8ebae37SRussell King 757c8afc9d5SRussell King /* 758c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 759c8afc9d5SRussell King * the data counter gives the number of bytes transferred 760c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 761c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 762c8afc9d5SRussell King * matters for FIFO overruns only. 763c8afc9d5SRussell King */ 764f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 7658cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 7668cb28155SLinus Walleij 767c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 768c8afc9d5SRussell King status, success); 7698cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 7708cb28155SLinus Walleij /* Last block was not successful */ 771c8afc9d5SRussell King success -= 1; 77217b0429dSPierre Ossman data->error = -EILSEQ; 7738cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 77417b0429dSPierre Ossman data->error = -ETIMEDOUT; 775757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 776757df746SLinus Walleij data->error = -ECOMM; 777c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 77817b0429dSPierre Ossman data->error = -EIO; 779c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 780c8afc9d5SRussell King if (success > host->variant->fifosize) 781c8afc9d5SRussell King success -= host->variant->fifosize; 782c8afc9d5SRussell King else 783c8afc9d5SRussell King success = 0; 7848cb28155SLinus Walleij data->error = -EIO; 7854ce1d6cbSRabin Vincent } 78651d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 7871c6a0718SPierre Ossman } 788f20f8f21SLinus Walleij 7898cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 7908cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 791f20f8f21SLinus Walleij 792ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 793c8ebae37SRussell King if (dma_inprogress(host)) 794c8ebae37SRussell King mmci_dma_unmap(host, data); 7951c6a0718SPierre Ossman mmci_stop_data(host); 7961c6a0718SPierre Ossman 7978cb28155SLinus Walleij if (!data->error) 7988cb28155SLinus Walleij /* The error clause is handled above, success! */ 79951d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 800f20f8f21SLinus Walleij 8011c6a0718SPierre Ossman if (!data->stop) { 8021c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 8031c6a0718SPierre Ossman } else { 8041c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 8051c6a0718SPierre Ossman } 8061c6a0718SPierre Ossman } 8071c6a0718SPierre Ossman } 8081c6a0718SPierre Ossman 8091c6a0718SPierre Ossman static void 8101c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 8111c6a0718SPierre Ossman unsigned int status) 8121c6a0718SPierre Ossman { 8131c6a0718SPierre Ossman void __iomem *base = host->base; 8141c6a0718SPierre Ossman 8151c6a0718SPierre Ossman host->cmd = NULL; 8161c6a0718SPierre Ossman 8171c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 81817b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 8191c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 82017b0429dSPierre Ossman cmd->error = -EILSEQ; 8219047b435SRussell King - ARM Linux } else { 8229047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 8239047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 8249047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 8259047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 8261c6a0718SPierre Ossman } 8271c6a0718SPierre Ossman 82817b0429dSPierre Ossman if (!cmd->data || cmd->error) { 8293b6e3c73SUlf Hansson if (host->data) { 8303b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 8313b6e3c73SUlf Hansson if (dma_inprogress(host)) 8323b6e3c73SUlf Hansson mmci_dma_data_error(host); 8331c6a0718SPierre Ossman mmci_stop_data(host); 8343b6e3c73SUlf Hansson } 8351c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 8361c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 8371c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 8381c6a0718SPierre Ossman } 8391c6a0718SPierre Ossman } 8401c6a0718SPierre Ossman 8411c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 8421c6a0718SPierre Ossman { 8431c6a0718SPierre Ossman void __iomem *base = host->base; 8441c6a0718SPierre Ossman char *ptr = buffer; 8451c6a0718SPierre Ossman u32 status; 84626eed9a5SLinus Walleij int host_remain = host->size; 8471c6a0718SPierre Ossman 8481c6a0718SPierre Ossman do { 84926eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 8501c6a0718SPierre Ossman 8511c6a0718SPierre Ossman if (count > remain) 8521c6a0718SPierre Ossman count = remain; 8531c6a0718SPierre Ossman 8541c6a0718SPierre Ossman if (count <= 0) 8551c6a0718SPierre Ossman break; 8561c6a0718SPierre Ossman 857393e5e24SUlf Hansson /* 858393e5e24SUlf Hansson * SDIO especially may want to send something that is 859393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 860393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 861393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 862393e5e24SUlf Hansson */ 863393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 864393e5e24SUlf Hansson if (count < 4) { 865393e5e24SUlf Hansson unsigned char buf[4]; 8664b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 867393e5e24SUlf Hansson memcpy(ptr, buf, count); 868393e5e24SUlf Hansson } else { 8694b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 870393e5e24SUlf Hansson count &= ~0x3; 871393e5e24SUlf Hansson } 872393e5e24SUlf Hansson } else { 8734b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 874393e5e24SUlf Hansson } 8751c6a0718SPierre Ossman 8761c6a0718SPierre Ossman ptr += count; 8771c6a0718SPierre Ossman remain -= count; 87826eed9a5SLinus Walleij host_remain -= count; 8791c6a0718SPierre Ossman 8801c6a0718SPierre Ossman if (remain == 0) 8811c6a0718SPierre Ossman break; 8821c6a0718SPierre Ossman 8831c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8841c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 8851c6a0718SPierre Ossman 8861c6a0718SPierre Ossman return ptr - buffer; 8871c6a0718SPierre Ossman } 8881c6a0718SPierre Ossman 8891c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 8901c6a0718SPierre Ossman { 8918301bb68SRabin Vincent struct variant_data *variant = host->variant; 8921c6a0718SPierre Ossman void __iomem *base = host->base; 8931c6a0718SPierre Ossman char *ptr = buffer; 8941c6a0718SPierre Ossman 8951c6a0718SPierre Ossman do { 8961c6a0718SPierre Ossman unsigned int count, maxcnt; 8971c6a0718SPierre Ossman 8988301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 8998301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 9001c6a0718SPierre Ossman count = min(remain, maxcnt); 9011c6a0718SPierre Ossman 90234177802SLinus Walleij /* 90334177802SLinus Walleij * SDIO especially may want to send something that is 90434177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 90534177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 90634177802SLinus Walleij * So compensate by adding +3 on the count, a single 90734177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 90834177802SLinus Walleij * 32bit writes etc. 90934177802SLinus Walleij */ 9104b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 9111c6a0718SPierre Ossman 9121c6a0718SPierre Ossman ptr += count; 9131c6a0718SPierre Ossman remain -= count; 9141c6a0718SPierre Ossman 9151c6a0718SPierre Ossman if (remain == 0) 9161c6a0718SPierre Ossman break; 9171c6a0718SPierre Ossman 9181c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9191c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 9201c6a0718SPierre Ossman 9211c6a0718SPierre Ossman return ptr - buffer; 9221c6a0718SPierre Ossman } 9231c6a0718SPierre Ossman 9241c6a0718SPierre Ossman /* 9251c6a0718SPierre Ossman * PIO data transfer IRQ handler. 9261c6a0718SPierre Ossman */ 9271c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 9281c6a0718SPierre Ossman { 9291c6a0718SPierre Ossman struct mmci_host *host = dev_id; 9304ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 9318301bb68SRabin Vincent struct variant_data *variant = host->variant; 9321c6a0718SPierre Ossman void __iomem *base = host->base; 9334ce1d6cbSRabin Vincent unsigned long flags; 9341c6a0718SPierre Ossman u32 status; 9351c6a0718SPierre Ossman 9361c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9371c6a0718SPierre Ossman 93864de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 9391c6a0718SPierre Ossman 9404ce1d6cbSRabin Vincent local_irq_save(flags); 9414ce1d6cbSRabin Vincent 9421c6a0718SPierre Ossman do { 9431c6a0718SPierre Ossman unsigned int remain, len; 9441c6a0718SPierre Ossman char *buffer; 9451c6a0718SPierre Ossman 9461c6a0718SPierre Ossman /* 9471c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 9481c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 9491c6a0718SPierre Ossman * definition it is more than half empty. 9501c6a0718SPierre Ossman * 9511c6a0718SPierre Ossman * For read, check for data available. 9521c6a0718SPierre Ossman */ 9531c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 9541c6a0718SPierre Ossman break; 9551c6a0718SPierre Ossman 9564ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 9574ce1d6cbSRabin Vincent break; 9584ce1d6cbSRabin Vincent 9594ce1d6cbSRabin Vincent buffer = sg_miter->addr; 9604ce1d6cbSRabin Vincent remain = sg_miter->length; 9611c6a0718SPierre Ossman 9621c6a0718SPierre Ossman len = 0; 9631c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 9641c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 9651c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 9661c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 9671c6a0718SPierre Ossman 9684ce1d6cbSRabin Vincent sg_miter->consumed = len; 9691c6a0718SPierre Ossman 9701c6a0718SPierre Ossman host->size -= len; 9711c6a0718SPierre Ossman remain -= len; 9721c6a0718SPierre Ossman 9731c6a0718SPierre Ossman if (remain) 9741c6a0718SPierre Ossman break; 9751c6a0718SPierre Ossman 9761c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9771c6a0718SPierre Ossman } while (1); 9781c6a0718SPierre Ossman 9794ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 9804ce1d6cbSRabin Vincent 9814ce1d6cbSRabin Vincent local_irq_restore(flags); 9824ce1d6cbSRabin Vincent 9831c6a0718SPierre Ossman /* 984c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 985c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 9861c6a0718SPierre Ossman */ 987c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 9882686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 9891c6a0718SPierre Ossman 9901c6a0718SPierre Ossman /* 9911c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 9921c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 9931c6a0718SPierre Ossman * the chip itself has disabled the data path, and 9941c6a0718SPierre Ossman * stops us racing with our data end IRQ. 9951c6a0718SPierre Ossman */ 9961c6a0718SPierre Ossman if (host->size == 0) { 9972686b4b4SLinus Walleij mmci_set_mask1(host, 0); 9981c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 9991c6a0718SPierre Ossman } 10001c6a0718SPierre Ossman 10011c6a0718SPierre Ossman return IRQ_HANDLED; 10021c6a0718SPierre Ossman } 10031c6a0718SPierre Ossman 10041c6a0718SPierre Ossman /* 10051c6a0718SPierre Ossman * Handle completion of command and data transfers. 10061c6a0718SPierre Ossman */ 10071c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 10081c6a0718SPierre Ossman { 10091c6a0718SPierre Ossman struct mmci_host *host = dev_id; 10101c6a0718SPierre Ossman u32 status; 10111c6a0718SPierre Ossman int ret = 0; 10121c6a0718SPierre Ossman 10131c6a0718SPierre Ossman spin_lock(&host->lock); 10141c6a0718SPierre Ossman 10151c6a0718SPierre Ossman do { 10161c6a0718SPierre Ossman struct mmc_command *cmd; 10171c6a0718SPierre Ossman struct mmc_data *data; 10181c6a0718SPierre Ossman 10191c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 10202686b4b4SLinus Walleij 10212686b4b4SLinus Walleij if (host->singleirq) { 10222686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 10232686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 10242686b4b4SLinus Walleij 10252686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 10262686b4b4SLinus Walleij } 10272686b4b4SLinus Walleij 10281c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 10291c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 10301c6a0718SPierre Ossman 103164de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 10321c6a0718SPierre Ossman 10331c6a0718SPierre Ossman data = host->data; 1034b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1035b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1036b63038d6SUlf Hansson MCI_DATABLOCKEND) && data) 10371c6a0718SPierre Ossman mmci_data_irq(host, data, status); 10381c6a0718SPierre Ossman 10391c6a0718SPierre Ossman cmd = host->cmd; 10401c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 10411c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 10421c6a0718SPierre Ossman 10431c6a0718SPierre Ossman ret = 1; 10441c6a0718SPierre Ossman } while (status); 10451c6a0718SPierre Ossman 10461c6a0718SPierre Ossman spin_unlock(&host->lock); 10471c6a0718SPierre Ossman 10481c6a0718SPierre Ossman return IRQ_RETVAL(ret); 10491c6a0718SPierre Ossman } 10501c6a0718SPierre Ossman 10511c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 10521c6a0718SPierre Ossman { 10531c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10549e943021SLinus Walleij unsigned long flags; 10551c6a0718SPierre Ossman 10561c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 10571c6a0718SPierre Ossman 1058019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 105964de0289SLinus Walleij dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 106064de0289SLinus Walleij mrq->data->blksz); 1061255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 1062255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1063255d01afSPierre Ossman return; 1064255d01afSPierre Ossman } 1065255d01afSPierre Ossman 10661c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 10671c3be369SRussell King 10689e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 10691c6a0718SPierre Ossman 10701c6a0718SPierre Ossman host->mrq = mrq; 10711c6a0718SPierre Ossman 107258c7ccbfSPer Forlin if (mrq->data) 107358c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 107458c7ccbfSPer Forlin 10751c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 10761c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 10771c6a0718SPierre Ossman 10781c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 10791c6a0718SPierre Ossman 10809e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 10811c6a0718SPierre Ossman } 10821c6a0718SPierre Ossman 10831c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 10841c6a0718SPierre Ossman { 10851c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10867d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1087a6a6464aSLinus Walleij u32 pwr = 0; 1088a6a6464aSLinus Walleij unsigned long flags; 108999fc5131SLinus Walleij int ret; 10901c6a0718SPierre Ossman 10912cd976c4SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 10922cd976c4SUlf Hansson 1093bc521818SUlf Hansson if (host->plat->ios_handler && 1094bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1095bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1096bc521818SUlf Hansson 10971c6a0718SPierre Ossman switch (ios->power_mode) { 10981c6a0718SPierre Ossman case MMC_POWER_OFF: 109999fc5131SLinus Walleij if (host->vcc) 110099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 11011c6a0718SPierre Ossman break; 11021c6a0718SPierre Ossman case MMC_POWER_UP: 110399fc5131SLinus Walleij if (host->vcc) { 110499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 110599fc5131SLinus Walleij if (ret) { 110699fc5131SLinus Walleij dev_err(mmc_dev(mmc), "unable to set OCR\n"); 110799fc5131SLinus Walleij /* 110899fc5131SLinus Walleij * The .set_ios() function in the mmc_host_ops 110999fc5131SLinus Walleij * struct return void, and failing to set the 111099fc5131SLinus Walleij * power should be rare so we print an error 111199fc5131SLinus Walleij * and return here. 111299fc5131SLinus Walleij */ 11132cd976c4SUlf Hansson goto out; 111499fc5131SLinus Walleij } 111599fc5131SLinus Walleij } 11167d72a1d4SUlf Hansson /* 11177d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 11187d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 11197d72a1d4SUlf Hansson * configured in the variant data. 11207d72a1d4SUlf Hansson */ 11217d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 11227d72a1d4SUlf Hansson 11231c6a0718SPierre Ossman break; 11241c6a0718SPierre Ossman case MMC_POWER_ON: 11251c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 11261c6a0718SPierre Ossman break; 11271c6a0718SPierre Ossman } 11281c6a0718SPierre Ossman 11294d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 11304d1a3a0dSUlf Hansson /* 11314d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 11324d1a3a0dSUlf Hansson * indicating signal direction for the signals in 11334d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 11344d1a3a0dSUlf Hansson */ 11354d1a3a0dSUlf Hansson pwr |= host->plat->sigdir; 11364d1a3a0dSUlf Hansson 11374d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 11384d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 11394d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 11404d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 11414d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 11424d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 11434d1a3a0dSUlf Hansson } 11444d1a3a0dSUlf Hansson 1145cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1146f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 11471c6a0718SPierre Ossman pwr |= MCI_ROD; 1148cc30d60eSLinus Walleij else { 1149cc30d60eSLinus Walleij /* 1150cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1151cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1152cc30d60eSLinus Walleij */ 1153cc30d60eSLinus Walleij pwr |= MCI_OD; 1154cc30d60eSLinus Walleij } 1155cc30d60eSLinus Walleij } 11561c6a0718SPierre Ossman 1157a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1158a6a6464aSLinus Walleij 1159a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 11607437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1161a6a6464aSLinus Walleij 1162a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 11632cd976c4SUlf Hansson 11642cd976c4SUlf Hansson out: 11652cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 11662cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 11671c6a0718SPierre Ossman } 11681c6a0718SPierre Ossman 116989001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 117089001446SRussell King { 117189001446SRussell King struct mmci_host *host = mmc_priv(mmc); 117289001446SRussell King 117389001446SRussell King if (host->gpio_wp == -ENOSYS) 117489001446SRussell King return -ENOSYS; 117589001446SRussell King 117618a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 117789001446SRussell King } 117889001446SRussell King 117989001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 118089001446SRussell King { 118189001446SRussell King struct mmci_host *host = mmc_priv(mmc); 118229719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 118389001446SRussell King unsigned int status; 118489001446SRussell King 11854b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 11864b8caec0SRabin Vincent if (!plat->status) 11874b8caec0SRabin Vincent return 1; /* Assume always present */ 11884b8caec0SRabin Vincent 118929719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 11904b8caec0SRabin Vincent } else 119118a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 119218a06301SLinus Walleij ^ plat->cd_invert; 119389001446SRussell King 119474bc8093SRussell King /* 119574bc8093SRussell King * Use positive logic throughout - status is zero for no card, 119674bc8093SRussell King * non-zero for card inserted. 119774bc8093SRussell King */ 119874bc8093SRussell King return status; 119989001446SRussell King } 120089001446SRussell King 1201148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1202148b8b39SRabin Vincent { 1203148b8b39SRabin Vincent struct mmci_host *host = dev_id; 1204148b8b39SRabin Vincent 1205148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1206148b8b39SRabin Vincent 1207148b8b39SRabin Vincent return IRQ_HANDLED; 1208148b8b39SRabin Vincent } 1209148b8b39SRabin Vincent 12101c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 12111c6a0718SPierre Ossman .request = mmci_request, 121258c7ccbfSPer Forlin .pre_req = mmci_pre_request, 121358c7ccbfSPer Forlin .post_req = mmci_post_request, 12141c6a0718SPierre Ossman .set_ios = mmci_set_ios, 121589001446SRussell King .get_ro = mmci_get_ro, 121689001446SRussell King .get_cd = mmci_get_cd, 12171c6a0718SPierre Ossman }; 12181c6a0718SPierre Ossman 1219000bc9d5SLee Jones #ifdef CONFIG_OF 1220000bc9d5SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1221000bc9d5SLee Jones struct mmci_platform_data *pdata) 1222000bc9d5SLee Jones { 1223000bc9d5SLee Jones int bus_width = 0; 1224000bc9d5SLee Jones 12259a597016SLee Jones pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 12269a597016SLee Jones pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1227000bc9d5SLee Jones 1228000bc9d5SLee Jones if (of_get_property(np, "cd-inverted", NULL)) 1229000bc9d5SLee Jones pdata->cd_invert = true; 1230000bc9d5SLee Jones else 1231000bc9d5SLee Jones pdata->cd_invert = false; 1232000bc9d5SLee Jones 1233000bc9d5SLee Jones of_property_read_u32(np, "max-frequency", &pdata->f_max); 1234000bc9d5SLee Jones if (!pdata->f_max) 1235000bc9d5SLee Jones pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1236000bc9d5SLee Jones 1237000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1238000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1239000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1240000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1241000bc9d5SLee Jones 1242000bc9d5SLee Jones of_property_read_u32(np, "bus-width", &bus_width); 1243000bc9d5SLee Jones switch (bus_width) { 1244000bc9d5SLee Jones case 0 : 1245000bc9d5SLee Jones /* No bus-width supplied. */ 1246000bc9d5SLee Jones break; 1247000bc9d5SLee Jones case 4 : 1248000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1249000bc9d5SLee Jones break; 1250000bc9d5SLee Jones case 8 : 1251000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1252000bc9d5SLee Jones break; 1253000bc9d5SLee Jones default : 1254000bc9d5SLee Jones pr_warn("%s: Unsupported bus width\n", np->full_name); 1255000bc9d5SLee Jones } 1256000bc9d5SLee Jones } 1257c0a120a4SLee Jones #else 1258c0a120a4SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1259c0a120a4SLee Jones struct mmci_platform_data *pdata) 1260c0a120a4SLee Jones { 1261c0a120a4SLee Jones return; 1262c0a120a4SLee Jones } 1263000bc9d5SLee Jones #endif 1264000bc9d5SLee Jones 1265aa25afadSRussell King static int __devinit mmci_probe(struct amba_device *dev, 1266aa25afadSRussell King const struct amba_id *id) 12671c6a0718SPierre Ossman { 12686ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1269000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 12704956e109SRabin Vincent struct variant_data *variant = id->data; 12711c6a0718SPierre Ossman struct mmci_host *host; 12721c6a0718SPierre Ossman struct mmc_host *mmc; 12731c6a0718SPierre Ossman int ret; 12741c6a0718SPierre Ossman 1275000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1276000bc9d5SLee Jones if (!plat && !np) { 1277000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1278000bc9d5SLee Jones return -EINVAL; 12791c6a0718SPierre Ossman } 12801c6a0718SPierre Ossman 1281b9b52918SLee Jones if (!plat) { 1282b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1283b9b52918SLee Jones if (!plat) 1284b9b52918SLee Jones return -ENOMEM; 1285b9b52918SLee Jones } 1286b9b52918SLee Jones 1287000bc9d5SLee Jones if (np) 1288000bc9d5SLee Jones mmci_dt_populate_generic_pdata(np, plat); 1289000bc9d5SLee Jones 12901c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 12911c6a0718SPierre Ossman if (ret) 12921c6a0718SPierre Ossman goto out; 12931c6a0718SPierre Ossman 12941c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 12951c6a0718SPierre Ossman if (!mmc) { 12961c6a0718SPierre Ossman ret = -ENOMEM; 12971c6a0718SPierre Ossman goto rel_regions; 12981c6a0718SPierre Ossman } 12991c6a0718SPierre Ossman 13001c6a0718SPierre Ossman host = mmc_priv(mmc); 13014ea580f1SRabin Vincent host->mmc = mmc; 1302012b7d33SRussell King 130389001446SRussell King host->gpio_wp = -ENOSYS; 130489001446SRussell King host->gpio_cd = -ENOSYS; 1305148b8b39SRabin Vincent host->gpio_cd_irq = -1; 130689001446SRussell King 1307012b7d33SRussell King host->hw_designer = amba_manf(dev); 1308012b7d33SRussell King host->hw_revision = amba_rev(dev); 130964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 131064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1311012b7d33SRussell King 1312ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 13131c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 13141c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 13151c6a0718SPierre Ossman host->clk = NULL; 13161c6a0718SPierre Ossman goto host_free; 13171c6a0718SPierre Ossman } 13181c6a0718SPierre Ossman 1319ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 13201c6a0718SPierre Ossman if (ret) 13211c6a0718SPierre Ossman goto clk_free; 13221c6a0718SPierre Ossman 13231c6a0718SPierre Ossman host->plat = plat; 13244956e109SRabin Vincent host->variant = variant; 13251c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1326c8df9a53SLinus Walleij /* 1327c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1328c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1329c8df9a53SLinus Walleij * (if possible). 1330c8df9a53SLinus Walleij */ 1331c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1332c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1333c8df9a53SLinus Walleij if (ret < 0) 1334c8df9a53SLinus Walleij goto clk_disable; 1335c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 133664de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 133764de0289SLinus Walleij host->mclk); 1338c8df9a53SLinus Walleij } 1339c8ebae37SRussell King host->phybase = dev->res.start; 1340dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 13411c6a0718SPierre Ossman if (!host->base) { 13421c6a0718SPierre Ossman ret = -ENOMEM; 13431c6a0718SPierre Ossman goto clk_disable; 13441c6a0718SPierre Ossman } 13451c6a0718SPierre Ossman 13461c6a0718SPierre Ossman mmc->ops = &mmci_ops; 13477f294e49SLinus Walleij /* 13487f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 13497f294e49SLinus Walleij * clock divider equations which means that the minimum divider 13507f294e49SLinus Walleij * differs too. 13517f294e49SLinus Walleij */ 13527f294e49SLinus Walleij if (variant->st_clkdiv) 13537f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 13547f294e49SLinus Walleij else 13557f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1356808d97ccSLinus Walleij /* 1357808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1358808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1359808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1360808d97ccSLinus Walleij * default value in case it is not specified. Either 1361808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1362808d97ccSLinus Walleij * of course. 1363808d97ccSLinus Walleij */ 1364808d97ccSLinus Walleij if (plat->f_max) 1365808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1366808d97ccSLinus Walleij else 13671c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 136864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 136964de0289SLinus Walleij 1370a9a83785SLinus Walleij host->pinctrl = devm_pinctrl_get(&dev->dev); 1371a9a83785SLinus Walleij if (IS_ERR(host->pinctrl)) { 1372a9a83785SLinus Walleij ret = PTR_ERR(host->pinctrl); 1373a9a83785SLinus Walleij goto clk_disable; 1374a9a83785SLinus Walleij } 1375a9a83785SLinus Walleij 1376a9a83785SLinus Walleij host->pins_default = pinctrl_lookup_state(host->pinctrl, 1377a9a83785SLinus Walleij PINCTRL_STATE_DEFAULT); 1378a9a83785SLinus Walleij 1379a9a83785SLinus Walleij /* enable pins to be muxed in and configured */ 1380a9a83785SLinus Walleij if (!IS_ERR(host->pins_default)) { 1381a9a83785SLinus Walleij ret = pinctrl_select_state(host->pinctrl, host->pins_default); 1382a9a83785SLinus Walleij if (ret) 1383a9a83785SLinus Walleij dev_warn(&dev->dev, "could not set default pins\n"); 1384a9a83785SLinus Walleij } else 1385a9a83785SLinus Walleij dev_warn(&dev->dev, "could not get default pinstate\n"); 1386a9a83785SLinus Walleij 138734e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 138834e84f39SLinus Walleij /* If we're using the regulator framework, try to fetch a regulator */ 138934e84f39SLinus Walleij host->vcc = regulator_get(&dev->dev, "vmmc"); 139034e84f39SLinus Walleij if (IS_ERR(host->vcc)) 139134e84f39SLinus Walleij host->vcc = NULL; 139234e84f39SLinus Walleij else { 139334e84f39SLinus Walleij int mask = mmc_regulator_get_ocrmask(host->vcc); 139434e84f39SLinus Walleij 139534e84f39SLinus Walleij if (mask < 0) 139634e84f39SLinus Walleij dev_err(&dev->dev, "error getting OCR mask (%d)\n", 139734e84f39SLinus Walleij mask); 139834e84f39SLinus Walleij else { 139934e84f39SLinus Walleij host->mmc->ocr_avail = (u32) mask; 140034e84f39SLinus Walleij if (plat->ocr_mask) 140134e84f39SLinus Walleij dev_warn(&dev->dev, 140234e84f39SLinus Walleij "Provided ocr_mask/setpower will not be used " 140334e84f39SLinus Walleij "(using regulator instead)\n"); 140434e84f39SLinus Walleij } 140534e84f39SLinus Walleij } 140634e84f39SLinus Walleij #endif 140734e84f39SLinus Walleij /* Fall back to platform data if no regulator is found */ 140834e84f39SLinus Walleij if (host->vcc == NULL) 14091c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 14109e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 14115a092627SPer Forlin mmc->caps2 = plat->capabilities2; 14121c6a0718SPierre Ossman 14131c6a0718SPierre Ossman /* 14141c6a0718SPierre Ossman * We can do SGIO 14151c6a0718SPierre Ossman */ 1416a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 14171c6a0718SPierre Ossman 14181c6a0718SPierre Ossman /* 141908458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 142008458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 142108458ef6SRabin Vincent * single request. 14221c6a0718SPierre Ossman */ 142308458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 14241c6a0718SPierre Ossman 14251c6a0718SPierre Ossman /* 14261c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 14271c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 14281c6a0718SPierre Ossman */ 14291c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 14301c6a0718SPierre Ossman 14311c6a0718SPierre Ossman /* 14321c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 14331c6a0718SPierre Ossman */ 14348f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 14351c6a0718SPierre Ossman 14361c6a0718SPierre Ossman /* 14378f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 14388f7f6b7eSWill Deacon * the maximum request size. 14391c6a0718SPierre Ossman */ 14408f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 14411c6a0718SPierre Ossman 14421c6a0718SPierre Ossman spin_lock_init(&host->lock); 14431c6a0718SPierre Ossman 14441c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14451c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 14461c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 14471c6a0718SPierre Ossman 14482805b9abSRoland Stigge if (plat->gpio_cd == -EPROBE_DEFER) { 14492805b9abSRoland Stigge ret = -EPROBE_DEFER; 14502805b9abSRoland Stigge goto err_gpio_cd; 14512805b9abSRoland Stigge } 145289001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 145389001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 145489001446SRussell King if (ret == 0) 145589001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 145689001446SRussell King if (ret == 0) 145789001446SRussell King host->gpio_cd = plat->gpio_cd; 145889001446SRussell King else if (ret != -ENOSYS) 145989001446SRussell King goto err_gpio_cd; 1460148b8b39SRabin Vincent 146117ee083bSLinus Walleij /* 146217ee083bSLinus Walleij * A gpio pin that will detect cards when inserted and removed 146317ee083bSLinus Walleij * will most likely want to trigger on the edges if it is 146417ee083bSLinus Walleij * 0 when ejected and 1 when inserted (or mutatis mutandis 146517ee083bSLinus Walleij * for the inverted case) so we request triggers on both 146617ee083bSLinus Walleij * edges. 146717ee083bSLinus Walleij */ 1468148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 146917ee083bSLinus Walleij mmci_cd_irq, 147017ee083bSLinus Walleij IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1471148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1472148b8b39SRabin Vincent if (ret >= 0) 1473148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 147489001446SRussell King } 14752805b9abSRoland Stigge if (plat->gpio_wp == -EPROBE_DEFER) { 14762805b9abSRoland Stigge ret = -EPROBE_DEFER; 14772805b9abSRoland Stigge goto err_gpio_wp; 14782805b9abSRoland Stigge } 147989001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 148089001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 148189001446SRussell King if (ret == 0) 148289001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 148389001446SRussell King if (ret == 0) 148489001446SRussell King host->gpio_wp = plat->gpio_wp; 148589001446SRussell King else if (ret != -ENOSYS) 148689001446SRussell King goto err_gpio_wp; 148789001446SRussell King } 148889001446SRussell King 14894b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 14904b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1491148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1492148b8b39SRabin Vincent 14931c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 14941c6a0718SPierre Ossman if (ret) 14951c6a0718SPierre Ossman goto unmap; 14961c6a0718SPierre Ossman 1497dfb85185SRussell King if (!dev->irq[1]) 14982686b4b4SLinus Walleij host->singleirq = true; 14992686b4b4SLinus Walleij else { 15002686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 15012686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 15021c6a0718SPierre Ossman if (ret) 15031c6a0718SPierre Ossman goto irq0_free; 15042686b4b4SLinus Walleij } 15051c6a0718SPierre Ossman 15068cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 15071c6a0718SPierre Ossman 15081c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 15091c6a0718SPierre Ossman 1510c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1511c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1512c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1513c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1514c8ebae37SRussell King 1515c8ebae37SRussell King mmci_dma_setup(host); 15161c6a0718SPierre Ossman 15172cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 15182cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 15191c3be369SRussell King pm_runtime_put(&dev->dev); 15201c3be369SRussell King 15218c11a94dSRussell King mmc_add_host(mmc); 15228c11a94dSRussell King 15231c6a0718SPierre Ossman return 0; 15241c6a0718SPierre Ossman 15251c6a0718SPierre Ossman irq0_free: 15261c6a0718SPierre Ossman free_irq(dev->irq[0], host); 15271c6a0718SPierre Ossman unmap: 152889001446SRussell King if (host->gpio_wp != -ENOSYS) 152989001446SRussell King gpio_free(host->gpio_wp); 153089001446SRussell King err_gpio_wp: 1531148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1532148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 153389001446SRussell King if (host->gpio_cd != -ENOSYS) 153489001446SRussell King gpio_free(host->gpio_cd); 153589001446SRussell King err_gpio_cd: 15361c6a0718SPierre Ossman iounmap(host->base); 15371c6a0718SPierre Ossman clk_disable: 1538ac940938SJulia Lawall clk_disable_unprepare(host->clk); 15391c6a0718SPierre Ossman clk_free: 15401c6a0718SPierre Ossman clk_put(host->clk); 15411c6a0718SPierre Ossman host_free: 15421c6a0718SPierre Ossman mmc_free_host(mmc); 15431c6a0718SPierre Ossman rel_regions: 15441c6a0718SPierre Ossman amba_release_regions(dev); 15451c6a0718SPierre Ossman out: 15461c6a0718SPierre Ossman return ret; 15471c6a0718SPierre Ossman } 15481c6a0718SPierre Ossman 15496dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 15501c6a0718SPierre Ossman { 15511c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 15521c6a0718SPierre Ossman 15531c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 15541c6a0718SPierre Ossman 15551c6a0718SPierre Ossman if (mmc) { 15561c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15571c6a0718SPierre Ossman 15581c3be369SRussell King /* 15591c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 15601c3be369SRussell King * version here so that we can access the primecell. 15611c3be369SRussell King */ 15621c3be369SRussell King pm_runtime_get_sync(&dev->dev); 15631c3be369SRussell King 15641c6a0718SPierre Ossman mmc_remove_host(mmc); 15651c6a0718SPierre Ossman 15661c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 15671c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 15681c6a0718SPierre Ossman 15691c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 15701c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 15711c6a0718SPierre Ossman 1572c8ebae37SRussell King mmci_dma_release(host); 15731c6a0718SPierre Ossman free_irq(dev->irq[0], host); 15742686b4b4SLinus Walleij if (!host->singleirq) 15751c6a0718SPierre Ossman free_irq(dev->irq[1], host); 15761c6a0718SPierre Ossman 157789001446SRussell King if (host->gpio_wp != -ENOSYS) 157889001446SRussell King gpio_free(host->gpio_wp); 1579148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1580148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 158189001446SRussell King if (host->gpio_cd != -ENOSYS) 158289001446SRussell King gpio_free(host->gpio_cd); 158389001446SRussell King 15841c6a0718SPierre Ossman iounmap(host->base); 1585ac940938SJulia Lawall clk_disable_unprepare(host->clk); 15861c6a0718SPierre Ossman clk_put(host->clk); 15871c6a0718SPierre Ossman 158899fc5131SLinus Walleij if (host->vcc) 158999fc5131SLinus Walleij mmc_regulator_set_ocr(mmc, host->vcc, 0); 159034e84f39SLinus Walleij regulator_put(host->vcc); 159134e84f39SLinus Walleij 15921c6a0718SPierre Ossman mmc_free_host(mmc); 15931c6a0718SPierre Ossman 15941c6a0718SPierre Ossman amba_release_regions(dev); 15951c6a0718SPierre Ossman } 15961c6a0718SPierre Ossman 15971c6a0718SPierre Ossman return 0; 15981c6a0718SPierre Ossman } 15991c6a0718SPierre Ossman 160048fa7003SUlf Hansson #ifdef CONFIG_SUSPEND 160148fa7003SUlf Hansson static int mmci_suspend(struct device *dev) 16021c6a0718SPierre Ossman { 160348fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 160448fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 16051c6a0718SPierre Ossman int ret = 0; 16061c6a0718SPierre Ossman 16071c6a0718SPierre Ossman if (mmc) { 16081c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 16091c6a0718SPierre Ossman 16101a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 16112cd976c4SUlf Hansson if (ret == 0) { 16122cd976c4SUlf Hansson pm_runtime_get_sync(dev); 16131c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 16141c6a0718SPierre Ossman } 16152cd976c4SUlf Hansson } 16161c6a0718SPierre Ossman 16171c6a0718SPierre Ossman return ret; 16181c6a0718SPierre Ossman } 16191c6a0718SPierre Ossman 162048fa7003SUlf Hansson static int mmci_resume(struct device *dev) 16211c6a0718SPierre Ossman { 162248fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 162348fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 16241c6a0718SPierre Ossman int ret = 0; 16251c6a0718SPierre Ossman 16261c6a0718SPierre Ossman if (mmc) { 16271c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 16281c6a0718SPierre Ossman 16291c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 16302cd976c4SUlf Hansson pm_runtime_put(dev); 16311c6a0718SPierre Ossman 16321c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 16331c6a0718SPierre Ossman } 16341c6a0718SPierre Ossman 16351c6a0718SPierre Ossman return ret; 16361c6a0718SPierre Ossman } 16371c6a0718SPierre Ossman #endif 16381c6a0718SPierre Ossman 163948fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 164048fa7003SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 164148fa7003SUlf Hansson }; 164248fa7003SUlf Hansson 16431c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 16441c6a0718SPierre Ossman { 16451c6a0718SPierre Ossman .id = 0x00041180, 1646768fbc18SPawel Moll .mask = 0xff0fffff, 16474956e109SRabin Vincent .data = &variant_arm, 16481c6a0718SPierre Ossman }, 16491c6a0718SPierre Ossman { 1650768fbc18SPawel Moll .id = 0x01041180, 1651768fbc18SPawel Moll .mask = 0xff0fffff, 1652768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1653768fbc18SPawel Moll }, 1654768fbc18SPawel Moll { 16551c6a0718SPierre Ossman .id = 0x00041181, 16561c6a0718SPierre Ossman .mask = 0x000fffff, 16574956e109SRabin Vincent .data = &variant_arm, 16581c6a0718SPierre Ossman }, 1659cc30d60eSLinus Walleij /* ST Micro variants */ 1660cc30d60eSLinus Walleij { 1661cc30d60eSLinus Walleij .id = 0x00180180, 1662cc30d60eSLinus Walleij .mask = 0x00ffffff, 16634956e109SRabin Vincent .data = &variant_u300, 1664cc30d60eSLinus Walleij }, 1665cc30d60eSLinus Walleij { 166634fd4213SLinus Walleij .id = 0x10180180, 166734fd4213SLinus Walleij .mask = 0xf0ffffff, 166834fd4213SLinus Walleij .data = &variant_nomadik, 166934fd4213SLinus Walleij }, 167034fd4213SLinus Walleij { 1671cc30d60eSLinus Walleij .id = 0x00280180, 1672cc30d60eSLinus Walleij .mask = 0x00ffffff, 16734956e109SRabin Vincent .data = &variant_u300, 16744956e109SRabin Vincent }, 16754956e109SRabin Vincent { 16764956e109SRabin Vincent .id = 0x00480180, 16771784b157SPhilippe Langlais .mask = 0xf0ffffff, 16784956e109SRabin Vincent .data = &variant_ux500, 1679cc30d60eSLinus Walleij }, 16801784b157SPhilippe Langlais { 16811784b157SPhilippe Langlais .id = 0x10480180, 16821784b157SPhilippe Langlais .mask = 0xf0ffffff, 16831784b157SPhilippe Langlais .data = &variant_ux500v2, 16841784b157SPhilippe Langlais }, 16851c6a0718SPierre Ossman { 0, 0 }, 16861c6a0718SPierre Ossman }; 16871c6a0718SPierre Ossman 16889f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 16899f99835fSDave Martin 16901c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 16911c6a0718SPierre Ossman .drv = { 16921c6a0718SPierre Ossman .name = DRIVER_NAME, 169348fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 16941c6a0718SPierre Ossman }, 16951c6a0718SPierre Ossman .probe = mmci_probe, 16966dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 16971c6a0718SPierre Ossman .id_table = mmci_ids, 16981c6a0718SPierre Ossman }; 16991c6a0718SPierre Ossman 17009e5ed094Sviresh kumar module_amba_driver(mmci_driver); 17011c6a0718SPierre Ossman 17021c6a0718SPierre Ossman module_param(fmax, uint, 0444); 17031c6a0718SPierre Ossman 17041c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 17051c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1706