11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 18000bc9d5SLee Jones #include <linux/slab.h> 191c6a0718SPierre Ossman #include <linux/delay.h> 201c6a0718SPierre Ossman #include <linux/err.h> 211c6a0718SPierre Ossman #include <linux/highmem.h> 22019a5f56SNicolas Pitre #include <linux/log2.h> 2370be208fSUlf Hansson #include <linux/mmc/pm.h> 241c6a0718SPierre Ossman #include <linux/mmc/host.h> 2534177802SLinus Walleij #include <linux/mmc/card.h> 261c6a0718SPierre Ossman #include <linux/amba/bus.h> 271c6a0718SPierre Ossman #include <linux/clk.h> 28bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2989001446SRussell King #include <linux/gpio.h> 309a597016SLee Jones #include <linux/of_gpio.h> 3134e84f39SLinus Walleij #include <linux/regulator/consumer.h> 32c8ebae37SRussell King #include <linux/dmaengine.h> 33c8ebae37SRussell King #include <linux/dma-mapping.h> 34c8ebae37SRussell King #include <linux/amba/mmci.h> 351c3be369SRussell King #include <linux/pm_runtime.h> 36258aea76SViresh Kumar #include <linux/types.h> 37a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 381c6a0718SPierre Ossman 391c6a0718SPierre Ossman #include <asm/div64.h> 401c6a0718SPierre Ossman #include <asm/io.h> 411c6a0718SPierre Ossman #include <asm/sizes.h> 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #include "mmci.h" 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 461c6a0718SPierre Ossman 471c6a0718SPierre Ossman static unsigned int fmax = 515633; 481c6a0718SPierre Ossman 494956e109SRabin Vincent /** 504956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 514956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 524380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 5308458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 548301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 558301bb68SRabin Vincent * is asserted (likewise for RX) 568301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 578301bb68SRabin Vincent * is asserted (likewise for RX) 5834177802SLinus Walleij * @sdio: variant supports SDIO 59b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 601784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 617d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 624d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 63f4670daeSUlf Hansson * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 6401259620SUlf Hansson * @busy_detect: true if busy detection on dat0 is supported 651ff44433SUlf Hansson * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 664956e109SRabin Vincent */ 674956e109SRabin Vincent struct variant_data { 684956e109SRabin Vincent unsigned int clkreg; 694380c14fSRabin Vincent unsigned int clkreg_enable; 7008458ef6SRabin Vincent unsigned int datalength_bits; 718301bb68SRabin Vincent unsigned int fifosize; 728301bb68SRabin Vincent unsigned int fifohalfsize; 7334177802SLinus Walleij bool sdio; 74b70a67f9SLinus Walleij bool st_clkdiv; 751784b157SPhilippe Langlais bool blksz_datactrl16; 767d72a1d4SUlf Hansson u32 pwrreg_powerup; 774d1a3a0dSUlf Hansson bool signal_direction; 78f4670daeSUlf Hansson bool pwrreg_clkgate; 7901259620SUlf Hansson bool busy_detect; 801ff44433SUlf Hansson bool pwrreg_nopower; 814956e109SRabin Vincent }; 824956e109SRabin Vincent 834956e109SRabin Vincent static struct variant_data variant_arm = { 848301bb68SRabin Vincent .fifosize = 16 * 4, 858301bb68SRabin Vincent .fifohalfsize = 8 * 4, 8608458ef6SRabin Vincent .datalength_bits = 16, 877d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 884956e109SRabin Vincent }; 894956e109SRabin Vincent 90768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 91768fbc18SPawel Moll .fifosize = 128 * 4, 92768fbc18SPawel Moll .fifohalfsize = 64 * 4, 93768fbc18SPawel Moll .datalength_bits = 16, 947d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 95768fbc18SPawel Moll }; 96768fbc18SPawel Moll 973a37298aSPawel Moll static struct variant_data variant_arm_extended_fifo_hwfc = { 983a37298aSPawel Moll .fifosize = 128 * 4, 993a37298aSPawel Moll .fifohalfsize = 64 * 4, 1003a37298aSPawel Moll .clkreg_enable = MCI_ARM_HWFCEN, 1013a37298aSPawel Moll .datalength_bits = 16, 1023a37298aSPawel Moll .pwrreg_powerup = MCI_PWR_UP, 1033a37298aSPawel Moll }; 1043a37298aSPawel Moll 1054956e109SRabin Vincent static struct variant_data variant_u300 = { 1068301bb68SRabin Vincent .fifosize = 16 * 4, 1078301bb68SRabin Vincent .fifohalfsize = 8 * 4, 10849ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 10908458ef6SRabin Vincent .datalength_bits = 16, 11034177802SLinus Walleij .sdio = true, 1117d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1124d1a3a0dSUlf Hansson .signal_direction = true, 113f4670daeSUlf Hansson .pwrreg_clkgate = true, 1141ff44433SUlf Hansson .pwrreg_nopower = true, 1154956e109SRabin Vincent }; 1164956e109SRabin Vincent 11734fd4213SLinus Walleij static struct variant_data variant_nomadik = { 11834fd4213SLinus Walleij .fifosize = 16 * 4, 11934fd4213SLinus Walleij .fifohalfsize = 8 * 4, 12034fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 12134fd4213SLinus Walleij .datalength_bits = 24, 12234fd4213SLinus Walleij .sdio = true, 12334fd4213SLinus Walleij .st_clkdiv = true, 12434fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 12534fd4213SLinus Walleij .signal_direction = true, 126f4670daeSUlf Hansson .pwrreg_clkgate = true, 1271ff44433SUlf Hansson .pwrreg_nopower = true, 12834fd4213SLinus Walleij }; 12934fd4213SLinus Walleij 1304956e109SRabin Vincent static struct variant_data variant_ux500 = { 1318301bb68SRabin Vincent .fifosize = 30 * 4, 1328301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1334956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 13449ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 13508458ef6SRabin Vincent .datalength_bits = 24, 13634177802SLinus Walleij .sdio = true, 137b70a67f9SLinus Walleij .st_clkdiv = true, 1387d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1394d1a3a0dSUlf Hansson .signal_direction = true, 140f4670daeSUlf Hansson .pwrreg_clkgate = true, 14101259620SUlf Hansson .busy_detect = true, 1421ff44433SUlf Hansson .pwrreg_nopower = true, 1434956e109SRabin Vincent }; 144b70a67f9SLinus Walleij 1451784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1461784b157SPhilippe Langlais .fifosize = 30 * 4, 1471784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1481784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1491784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1501784b157SPhilippe Langlais .datalength_bits = 24, 1511784b157SPhilippe Langlais .sdio = true, 1521784b157SPhilippe Langlais .st_clkdiv = true, 1531784b157SPhilippe Langlais .blksz_datactrl16 = true, 1547d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1554d1a3a0dSUlf Hansson .signal_direction = true, 156f4670daeSUlf Hansson .pwrreg_clkgate = true, 15701259620SUlf Hansson .busy_detect = true, 1581ff44433SUlf Hansson .pwrreg_nopower = true, 1591784b157SPhilippe Langlais }; 1601784b157SPhilippe Langlais 16101259620SUlf Hansson static int mmci_card_busy(struct mmc_host *mmc) 16201259620SUlf Hansson { 16301259620SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 16401259620SUlf Hansson unsigned long flags; 16501259620SUlf Hansson int busy = 0; 16601259620SUlf Hansson 16701259620SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 16801259620SUlf Hansson 16901259620SUlf Hansson spin_lock_irqsave(&host->lock, flags); 17001259620SUlf Hansson if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 17101259620SUlf Hansson busy = 1; 17201259620SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 17301259620SUlf Hansson 17401259620SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 17501259620SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 17601259620SUlf Hansson 17701259620SUlf Hansson return busy; 17801259620SUlf Hansson } 17901259620SUlf Hansson 180a6a6464aSLinus Walleij /* 181653a761eSUlf Hansson * Validate mmc prerequisites 182653a761eSUlf Hansson */ 183653a761eSUlf Hansson static int mmci_validate_data(struct mmci_host *host, 184653a761eSUlf Hansson struct mmc_data *data) 185653a761eSUlf Hansson { 186653a761eSUlf Hansson if (!data) 187653a761eSUlf Hansson return 0; 188653a761eSUlf Hansson 189653a761eSUlf Hansson if (!is_power_of_2(data->blksz)) { 190653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), 191653a761eSUlf Hansson "unsupported block size (%d bytes)\n", data->blksz); 192653a761eSUlf Hansson return -EINVAL; 193653a761eSUlf Hansson } 194653a761eSUlf Hansson 195653a761eSUlf Hansson return 0; 196653a761eSUlf Hansson } 197653a761eSUlf Hansson 198f829c042SUlf Hansson static void mmci_reg_delay(struct mmci_host *host) 199f829c042SUlf Hansson { 200f829c042SUlf Hansson /* 201f829c042SUlf Hansson * According to the spec, at least three feedback clock cycles 202f829c042SUlf Hansson * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 203f829c042SUlf Hansson * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 204f829c042SUlf Hansson * Worst delay time during card init is at 100 kHz => 30 us. 205f829c042SUlf Hansson * Worst delay time when up and running is at 25 MHz => 120 ns. 206f829c042SUlf Hansson */ 207f829c042SUlf Hansson if (host->cclk < 25000000) 208f829c042SUlf Hansson udelay(30); 209f829c042SUlf Hansson else 210f829c042SUlf Hansson ndelay(120); 211f829c042SUlf Hansson } 212f829c042SUlf Hansson 213653a761eSUlf Hansson /* 214a6a6464aSLinus Walleij * This must be called with host->lock held 215a6a6464aSLinus Walleij */ 2167437cfa5SUlf Hansson static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 2177437cfa5SUlf Hansson { 2187437cfa5SUlf Hansson if (host->clk_reg != clk) { 2197437cfa5SUlf Hansson host->clk_reg = clk; 2207437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 2217437cfa5SUlf Hansson } 2227437cfa5SUlf Hansson } 2237437cfa5SUlf Hansson 2247437cfa5SUlf Hansson /* 2257437cfa5SUlf Hansson * This must be called with host->lock held 2267437cfa5SUlf Hansson */ 2277437cfa5SUlf Hansson static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 2287437cfa5SUlf Hansson { 2297437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 2307437cfa5SUlf Hansson host->pwr_reg = pwr; 2317437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 2327437cfa5SUlf Hansson } 2337437cfa5SUlf Hansson } 2347437cfa5SUlf Hansson 2357437cfa5SUlf Hansson /* 2367437cfa5SUlf Hansson * This must be called with host->lock held 2377437cfa5SUlf Hansson */ 2389cc639a2SUlf Hansson static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 2399cc639a2SUlf Hansson { 24001259620SUlf Hansson /* Keep ST Micro busy mode if enabled */ 24101259620SUlf Hansson datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 24201259620SUlf Hansson 2439cc639a2SUlf Hansson if (host->datactrl_reg != datactrl) { 2449cc639a2SUlf Hansson host->datactrl_reg = datactrl; 2459cc639a2SUlf Hansson writel(datactrl, host->base + MMCIDATACTRL); 2469cc639a2SUlf Hansson } 2479cc639a2SUlf Hansson } 2489cc639a2SUlf Hansson 2499cc639a2SUlf Hansson /* 2509cc639a2SUlf Hansson * This must be called with host->lock held 2519cc639a2SUlf Hansson */ 252a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 253a6a6464aSLinus Walleij { 2544956e109SRabin Vincent struct variant_data *variant = host->variant; 2554956e109SRabin Vincent u32 clk = variant->clkreg; 256a6a6464aSLinus Walleij 257c58a8509SUlf Hansson /* Make sure cclk reflects the current calculated clock */ 258c58a8509SUlf Hansson host->cclk = 0; 259c58a8509SUlf Hansson 260a6a6464aSLinus Walleij if (desired) { 261a6a6464aSLinus Walleij if (desired >= host->mclk) { 262a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 263399bc486SLinus Walleij if (variant->st_clkdiv) 264399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 265a6a6464aSLinus Walleij host->cclk = host->mclk; 266b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 267b70a67f9SLinus Walleij /* 268b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 269b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 270b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 271b70a67f9SLinus Walleij * frequency 272b70a67f9SLinus Walleij */ 273b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 274b70a67f9SLinus Walleij if (clk >= 256) 275b70a67f9SLinus Walleij clk = 255; 276b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 277a6a6464aSLinus Walleij } else { 278b70a67f9SLinus Walleij /* 279b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 280b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 281b70a67f9SLinus Walleij */ 282a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 283a6a6464aSLinus Walleij if (clk >= 256) 284a6a6464aSLinus Walleij clk = 255; 285a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 286a6a6464aSLinus Walleij } 2874380c14fSRabin Vincent 2884380c14fSRabin Vincent clk |= variant->clkreg_enable; 289a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 290a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 291a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 292a6a6464aSLinus Walleij } 293a6a6464aSLinus Walleij 294c58a8509SUlf Hansson /* Set actual clock for debug */ 295c58a8509SUlf Hansson host->mmc->actual_clock = host->cclk; 296c58a8509SUlf Hansson 2979e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 298771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 299771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 300771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 3019e6c82cdSLinus Walleij 3026dbb6ee0SUlf Hansson if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 3036dbb6ee0SUlf Hansson clk |= MCI_ST_UX500_NEG_EDGE; 3046dbb6ee0SUlf Hansson 3057437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 306a6a6464aSLinus Walleij } 307a6a6464aSLinus Walleij 3081c6a0718SPierre Ossman static void 3091c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 3101c6a0718SPierre Ossman { 3111c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 3121c6a0718SPierre Ossman 3131c6a0718SPierre Ossman BUG_ON(host->data); 3141c6a0718SPierre Ossman 3151c6a0718SPierre Ossman host->mrq = NULL; 3161c6a0718SPierre Ossman host->cmd = NULL; 3171c6a0718SPierre Ossman 3181c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 3192cd976c4SUlf Hansson 3202cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 3212cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 3221c6a0718SPierre Ossman } 3231c6a0718SPierre Ossman 3242686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 3252686b4b4SLinus Walleij { 3262686b4b4SLinus Walleij void __iomem *base = host->base; 3272686b4b4SLinus Walleij 3282686b4b4SLinus Walleij if (host->singleirq) { 3292686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 3302686b4b4SLinus Walleij 3312686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 3322686b4b4SLinus Walleij mask0 |= mask; 3332686b4b4SLinus Walleij 3342686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 3352686b4b4SLinus Walleij } 3362686b4b4SLinus Walleij 3372686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 3382686b4b4SLinus Walleij } 3392686b4b4SLinus Walleij 3401c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 3411c6a0718SPierre Ossman { 3429cc639a2SUlf Hansson mmci_write_datactrlreg(host, 0); 3432686b4b4SLinus Walleij mmci_set_mask1(host, 0); 3441c6a0718SPierre Ossman host->data = NULL; 3451c6a0718SPierre Ossman } 3461c6a0718SPierre Ossman 3474ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 3484ce1d6cbSRabin Vincent { 3494ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 3504ce1d6cbSRabin Vincent 3514ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 3524ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 3534ce1d6cbSRabin Vincent else 3544ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 3554ce1d6cbSRabin Vincent 3564ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 3574ce1d6cbSRabin Vincent } 3584ce1d6cbSRabin Vincent 359c8ebae37SRussell King /* 360c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 361c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 362c8ebae37SRussell King * no custom DMA interfaces are supported. 363c8ebae37SRussell King */ 364c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 365c3be1efdSBill Pemberton static void mmci_dma_setup(struct mmci_host *host) 366c8ebae37SRussell King { 367c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 368c8ebae37SRussell King const char *rxname, *txname; 369c8ebae37SRussell King dma_cap_mask_t mask; 370c8ebae37SRussell King 3711fd83f0eSLee Jones host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 3721fd83f0eSLee Jones host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 373c8ebae37SRussell King 37458c7ccbfSPer Forlin /* initialize pre request cookie */ 37558c7ccbfSPer Forlin host->next_data.cookie = 1; 37658c7ccbfSPer Forlin 377c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 378c8ebae37SRussell King dma_cap_zero(mask); 379c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 380c8ebae37SRussell King 3811fd83f0eSLee Jones if (plat && plat->dma_filter) { 3821fd83f0eSLee Jones if (!host->dma_rx_channel && plat->dma_rx_param) { 383c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 384c8ebae37SRussell King plat->dma_filter, 385c8ebae37SRussell King plat->dma_rx_param); 386c8ebae37SRussell King /* E.g if no DMA hardware is present */ 387c8ebae37SRussell King if (!host->dma_rx_channel) 388c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 389c8ebae37SRussell King } 390c8ebae37SRussell King 3911fd83f0eSLee Jones if (!host->dma_tx_channel && plat->dma_tx_param) { 392c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 393c8ebae37SRussell King plat->dma_filter, 394c8ebae37SRussell King plat->dma_tx_param); 395c8ebae37SRussell King if (!host->dma_tx_channel) 396c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 397c8ebae37SRussell King } 3981fd83f0eSLee Jones } 3991fd83f0eSLee Jones 4001fd83f0eSLee Jones /* 4011fd83f0eSLee Jones * If only an RX channel is specified, the driver will 4021fd83f0eSLee Jones * attempt to use it bidirectionally, however if it is 4031fd83f0eSLee Jones * is specified but cannot be located, DMA will be disabled. 4041fd83f0eSLee Jones */ 4051fd83f0eSLee Jones if (host->dma_rx_channel && !host->dma_tx_channel) 4061fd83f0eSLee Jones host->dma_tx_channel = host->dma_rx_channel; 407c8ebae37SRussell King 408c8ebae37SRussell King if (host->dma_rx_channel) 409c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 410c8ebae37SRussell King else 411c8ebae37SRussell King rxname = "none"; 412c8ebae37SRussell King 413c8ebae37SRussell King if (host->dma_tx_channel) 414c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 415c8ebae37SRussell King else 416c8ebae37SRussell King txname = "none"; 417c8ebae37SRussell King 418c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 419c8ebae37SRussell King rxname, txname); 420c8ebae37SRussell King 421c8ebae37SRussell King /* 422c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 423c8ebae37SRussell King * the parameters of the DMA engine device. 424c8ebae37SRussell King */ 425c8ebae37SRussell King if (host->dma_tx_channel) { 426c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 427c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 428c8ebae37SRussell King 429c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 430c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 431c8ebae37SRussell King } 432c8ebae37SRussell King if (host->dma_rx_channel) { 433c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 434c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 435c8ebae37SRussell King 436c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 437c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 438c8ebae37SRussell King } 439c8ebae37SRussell King } 440c8ebae37SRussell King 441c8ebae37SRussell King /* 4426e0ee714SBill Pemberton * This is used in or so inline it 443c8ebae37SRussell King * so it can be discarded. 444c8ebae37SRussell King */ 445c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 446c8ebae37SRussell King { 447c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 448c8ebae37SRussell King 449c8ebae37SRussell King if (host->dma_rx_channel) 450c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 451c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 452c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 453c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 454c8ebae37SRussell King } 455c8ebae37SRussell King 456653a761eSUlf Hansson static void mmci_dma_data_error(struct mmci_host *host) 457653a761eSUlf Hansson { 458653a761eSUlf Hansson dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 459653a761eSUlf Hansson dmaengine_terminate_all(host->dma_current); 460653a761eSUlf Hansson host->dma_current = NULL; 461653a761eSUlf Hansson host->dma_desc_current = NULL; 462653a761eSUlf Hansson host->data->host_cookie = 0; 463653a761eSUlf Hansson } 464653a761eSUlf Hansson 465c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 466c8ebae37SRussell King { 467653a761eSUlf Hansson struct dma_chan *chan; 468c8ebae37SRussell King enum dma_data_direction dir; 469653a761eSUlf Hansson 470653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) { 471653a761eSUlf Hansson dir = DMA_FROM_DEVICE; 472653a761eSUlf Hansson chan = host->dma_rx_channel; 473653a761eSUlf Hansson } else { 474653a761eSUlf Hansson dir = DMA_TO_DEVICE; 475653a761eSUlf Hansson chan = host->dma_tx_channel; 476653a761eSUlf Hansson } 477653a761eSUlf Hansson 478653a761eSUlf Hansson dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 479653a761eSUlf Hansson } 480653a761eSUlf Hansson 481653a761eSUlf Hansson static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 482653a761eSUlf Hansson { 483c8ebae37SRussell King u32 status; 484c8ebae37SRussell King int i; 485c8ebae37SRussell King 486c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 487c8ebae37SRussell King for (i = 0; ; i++) { 488c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 489c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 490c8ebae37SRussell King break; 491c8ebae37SRussell King udelay(10); 492c8ebae37SRussell King } 493c8ebae37SRussell King 494c8ebae37SRussell King /* 495c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 496c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 497c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 498c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 499c8ebae37SRussell King */ 500c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 501653a761eSUlf Hansson mmci_dma_data_error(host); 502c8ebae37SRussell King if (!data->error) 503c8ebae37SRussell King data->error = -EIO; 504c8ebae37SRussell King } 505c8ebae37SRussell King 50658c7ccbfSPer Forlin if (!data->host_cookie) 507653a761eSUlf Hansson mmci_dma_unmap(host, data); 508c8ebae37SRussell King 509c8ebae37SRussell King /* 510c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 511c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 512c8ebae37SRussell King */ 513c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 514c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 515c8ebae37SRussell King mmci_dma_release(host); 516c8ebae37SRussell King } 517653a761eSUlf Hansson 518653a761eSUlf Hansson host->dma_current = NULL; 519653a761eSUlf Hansson host->dma_desc_current = NULL; 520c8ebae37SRussell King } 521c8ebae37SRussell King 522653a761eSUlf Hansson /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 523653a761eSUlf Hansson static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 524653a761eSUlf Hansson struct dma_chan **dma_chan, 525653a761eSUlf Hansson struct dma_async_tx_descriptor **dma_desc) 526c8ebae37SRussell King { 527c8ebae37SRussell King struct variant_data *variant = host->variant; 528c8ebae37SRussell King struct dma_slave_config conf = { 529c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 530c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 531c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 532c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 533c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 534c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 535258aea76SViresh Kumar .device_fc = false, 536c8ebae37SRussell King }; 537c8ebae37SRussell King struct dma_chan *chan; 538c8ebae37SRussell King struct dma_device *device; 539c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 54005f5799cSVinod Koul enum dma_data_direction buffer_dirn; 541c8ebae37SRussell King int nr_sg; 542c8ebae37SRussell King 543c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 54405f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 54505f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 546c8ebae37SRussell King chan = host->dma_rx_channel; 547c8ebae37SRussell King } else { 54805f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 54905f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 550c8ebae37SRussell King chan = host->dma_tx_channel; 551c8ebae37SRussell King } 552c8ebae37SRussell King 553c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 554c8ebae37SRussell King if (!chan) 555c8ebae37SRussell King return -EINVAL; 556c8ebae37SRussell King 557c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 55858c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 559c8ebae37SRussell King return -EINVAL; 560c8ebae37SRussell King 561c8ebae37SRussell King device = chan->device; 56205f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 563c8ebae37SRussell King if (nr_sg == 0) 564c8ebae37SRussell King return -EINVAL; 565c8ebae37SRussell King 566c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 56716052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 568c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 569c8ebae37SRussell King if (!desc) 570c8ebae37SRussell King goto unmap_exit; 571c8ebae37SRussell King 572653a761eSUlf Hansson *dma_chan = chan; 573653a761eSUlf Hansson *dma_desc = desc; 574c8ebae37SRussell King 57558c7ccbfSPer Forlin return 0; 57658c7ccbfSPer Forlin 57758c7ccbfSPer Forlin unmap_exit: 57805f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 57958c7ccbfSPer Forlin return -ENOMEM; 58058c7ccbfSPer Forlin } 58158c7ccbfSPer Forlin 582653a761eSUlf Hansson static inline int mmci_dma_prep_data(struct mmci_host *host, 583653a761eSUlf Hansson struct mmc_data *data) 584653a761eSUlf Hansson { 585653a761eSUlf Hansson /* Check if next job is already prepared. */ 586653a761eSUlf Hansson if (host->dma_current && host->dma_desc_current) 587653a761eSUlf Hansson return 0; 588653a761eSUlf Hansson 589653a761eSUlf Hansson /* No job were prepared thus do it now. */ 590653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &host->dma_current, 591653a761eSUlf Hansson &host->dma_desc_current); 592653a761eSUlf Hansson } 593653a761eSUlf Hansson 594653a761eSUlf Hansson static inline int mmci_dma_prep_next(struct mmci_host *host, 595653a761eSUlf Hansson struct mmc_data *data) 596653a761eSUlf Hansson { 597653a761eSUlf Hansson struct mmci_host_next *nd = &host->next_data; 598653a761eSUlf Hansson return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 599653a761eSUlf Hansson } 600653a761eSUlf Hansson 60158c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 60258c7ccbfSPer Forlin { 60358c7ccbfSPer Forlin int ret; 60458c7ccbfSPer Forlin struct mmc_data *data = host->data; 60558c7ccbfSPer Forlin 606653a761eSUlf Hansson ret = mmci_dma_prep_data(host, host->data); 60758c7ccbfSPer Forlin if (ret) 60858c7ccbfSPer Forlin return ret; 60958c7ccbfSPer Forlin 61058c7ccbfSPer Forlin /* Okay, go for it. */ 611c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 612c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 613c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 61458c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 61558c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 616c8ebae37SRussell King 617c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 618c8ebae37SRussell King 619c8ebae37SRussell King /* Trigger the DMA transfer */ 6209cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 621c8ebae37SRussell King 622c8ebae37SRussell King /* 623c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 624c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 625c8ebae37SRussell King * call mmci_data_end() 626c8ebae37SRussell King */ 627c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 628c8ebae37SRussell King host->base + MMCIMASK0); 629c8ebae37SRussell King return 0; 630c8ebae37SRussell King } 63158c7ccbfSPer Forlin 63258c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 63358c7ccbfSPer Forlin { 63458c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 63558c7ccbfSPer Forlin 636653a761eSUlf Hansson WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 637653a761eSUlf Hansson WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 63858c7ccbfSPer Forlin 63958c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 64058c7ccbfSPer Forlin host->dma_current = next->dma_chan; 64158c7ccbfSPer Forlin next->dma_desc = NULL; 64258c7ccbfSPer Forlin next->dma_chan = NULL; 64358c7ccbfSPer Forlin } 64458c7ccbfSPer Forlin 64558c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 64658c7ccbfSPer Forlin bool is_first_req) 64758c7ccbfSPer Forlin { 64858c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 64958c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 65058c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 65158c7ccbfSPer Forlin 65258c7ccbfSPer Forlin if (!data) 65358c7ccbfSPer Forlin return; 65458c7ccbfSPer Forlin 655653a761eSUlf Hansson BUG_ON(data->host_cookie); 65658c7ccbfSPer Forlin 657653a761eSUlf Hansson if (mmci_validate_data(host, data)) 658653a761eSUlf Hansson return; 659653a761eSUlf Hansson 660653a761eSUlf Hansson if (!mmci_dma_prep_next(host, data)) 66158c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 66258c7ccbfSPer Forlin } 66358c7ccbfSPer Forlin 66458c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 66558c7ccbfSPer Forlin int err) 66658c7ccbfSPer Forlin { 66758c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 66858c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 66958c7ccbfSPer Forlin 670653a761eSUlf Hansson if (!data || !data->host_cookie) 67158c7ccbfSPer Forlin return; 67258c7ccbfSPer Forlin 673653a761eSUlf Hansson mmci_dma_unmap(host, data); 674653a761eSUlf Hansson 675653a761eSUlf Hansson if (err) { 676653a761eSUlf Hansson struct mmci_host_next *next = &host->next_data; 677653a761eSUlf Hansson struct dma_chan *chan; 678653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) 67958c7ccbfSPer Forlin chan = host->dma_rx_channel; 680653a761eSUlf Hansson else 68158c7ccbfSPer Forlin chan = host->dma_tx_channel; 68258c7ccbfSPer Forlin dmaengine_terminate_all(chan); 683653a761eSUlf Hansson 684653a761eSUlf Hansson next->dma_desc = NULL; 685653a761eSUlf Hansson next->dma_chan = NULL; 68658c7ccbfSPer Forlin } 68758c7ccbfSPer Forlin } 68858c7ccbfSPer Forlin 689c8ebae37SRussell King #else 690c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 69158c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 69258c7ccbfSPer Forlin { 69358c7ccbfSPer Forlin } 694c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 695c8ebae37SRussell King { 696c8ebae37SRussell King } 697c8ebae37SRussell King 698c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 699c8ebae37SRussell King { 700c8ebae37SRussell King } 701c8ebae37SRussell King 702c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 703c8ebae37SRussell King { 704c8ebae37SRussell King } 705c8ebae37SRussell King 706653a761eSUlf Hansson static inline void mmci_dma_finalize(struct mmci_host *host, 707653a761eSUlf Hansson struct mmc_data *data) 708653a761eSUlf Hansson { 709653a761eSUlf Hansson } 710653a761eSUlf Hansson 711c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 712c8ebae37SRussell King { 713c8ebae37SRussell King } 714c8ebae37SRussell King 715c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 716c8ebae37SRussell King { 717c8ebae37SRussell King return -ENOSYS; 718c8ebae37SRussell King } 71958c7ccbfSPer Forlin 72058c7ccbfSPer Forlin #define mmci_pre_request NULL 72158c7ccbfSPer Forlin #define mmci_post_request NULL 72258c7ccbfSPer Forlin 723c8ebae37SRussell King #endif 724c8ebae37SRussell King 7251c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 7261c6a0718SPierre Ossman { 7278301bb68SRabin Vincent struct variant_data *variant = host->variant; 7281c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 7291c6a0718SPierre Ossman unsigned long long clks; 7301c6a0718SPierre Ossman void __iomem *base; 7311c6a0718SPierre Ossman int blksz_bits; 7321c6a0718SPierre Ossman 73364de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 7341c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 7351c6a0718SPierre Ossman 7361c6a0718SPierre Ossman host->data = data; 737528320dbSRabin Vincent host->size = data->blksz * data->blocks; 73851d4375dSRussell King data->bytes_xfered = 0; 7391c6a0718SPierre Ossman 7401c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 7411c6a0718SPierre Ossman do_div(clks, 1000000000UL); 7421c6a0718SPierre Ossman 7431c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 7441c6a0718SPierre Ossman 7451c6a0718SPierre Ossman base = host->base; 7461c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 7471c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 7481c6a0718SPierre Ossman 7491c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 7501c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 7511c6a0718SPierre Ossman 7521784b157SPhilippe Langlais if (variant->blksz_datactrl16) 7531784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 7541784b157SPhilippe Langlais else 7551c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 756c8ebae37SRussell King 757c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 7581c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 759c8ebae37SRussell King 7607258db7eSUlf Hansson /* The ST Micro variants has a special bit to enable SDIO */ 7617258db7eSUlf Hansson if (variant->sdio && host->mmc->card) 76206c1a121SUlf Hansson if (mmc_card_sdio(host->mmc->card)) { 76306c1a121SUlf Hansson /* 76406c1a121SUlf Hansson * The ST Micro variants has a special bit 76506c1a121SUlf Hansson * to enable SDIO. 76606c1a121SUlf Hansson */ 76706c1a121SUlf Hansson u32 clk; 76806c1a121SUlf Hansson 7697258db7eSUlf Hansson datactrl |= MCI_ST_DPSM_SDIOEN; 7707258db7eSUlf Hansson 771c8ebae37SRussell King /* 77270ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 77370ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 77470ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 77570ac0935SUlf Hansson * depends on the rate of MCLK. 77606c1a121SUlf Hansson */ 77770ac0935SUlf Hansson if (data->flags & MMC_DATA_WRITE && 77870ac0935SUlf Hansson (host->size < 8 || 77970ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 78006c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 78106c1a121SUlf Hansson else 78206c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 78306c1a121SUlf Hansson 78406c1a121SUlf Hansson mmci_write_clkreg(host, clk); 78506c1a121SUlf Hansson } 78606c1a121SUlf Hansson 7876dbb6ee0SUlf Hansson if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 7886dbb6ee0SUlf Hansson datactrl |= MCI_ST_DPSM_DDRMODE; 7896dbb6ee0SUlf Hansson 79006c1a121SUlf Hansson /* 791c8ebae37SRussell King * Attempt to use DMA operation mode, if this 792c8ebae37SRussell King * should fail, fall back to PIO mode 793c8ebae37SRussell King */ 794c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 795c8ebae37SRussell King return; 796c8ebae37SRussell King 797c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 798c8ebae37SRussell King mmci_init_sg(host, data); 799c8ebae37SRussell King 800c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 8011c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 8021c6a0718SPierre Ossman 8031c6a0718SPierre Ossman /* 804c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 805c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 806c4d877c1SRussell King * is available. 8071c6a0718SPierre Ossman */ 808c4d877c1SRussell King if (host->size < variant->fifohalfsize) 8091c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 8101c6a0718SPierre Ossman } else { 8111c6a0718SPierre Ossman /* 8121c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 8131c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 8141c6a0718SPierre Ossman */ 8151c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 8161c6a0718SPierre Ossman } 8171c6a0718SPierre Ossman 8189cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 8191c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 8202686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 8211c6a0718SPierre Ossman } 8221c6a0718SPierre Ossman 8231c6a0718SPierre Ossman static void 8241c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 8251c6a0718SPierre Ossman { 8261c6a0718SPierre Ossman void __iomem *base = host->base; 8271c6a0718SPierre Ossman 82864de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 8291c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 8301c6a0718SPierre Ossman 8311c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 8321c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 8331c6a0718SPierre Ossman udelay(1); 8341c6a0718SPierre Ossman } 8351c6a0718SPierre Ossman 8361c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 8371c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 8381c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 8391c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 8401c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 8411c6a0718SPierre Ossman } 8421c6a0718SPierre Ossman if (/*interrupt*/0) 8431c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 8441c6a0718SPierre Ossman 8451c6a0718SPierre Ossman host->cmd = cmd; 8461c6a0718SPierre Ossman 8471c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 8481c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 8491c6a0718SPierre Ossman } 8501c6a0718SPierre Ossman 8511c6a0718SPierre Ossman static void 8521c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 8531c6a0718SPierre Ossman unsigned int status) 8541c6a0718SPierre Ossman { 855f20f8f21SLinus Walleij /* First check for errors */ 856b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 857b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 8588cb28155SLinus Walleij u32 remain, success; 859f20f8f21SLinus Walleij 860c8ebae37SRussell King /* Terminate the DMA transfer */ 861653a761eSUlf Hansson if (dma_inprogress(host)) { 862c8ebae37SRussell King mmci_dma_data_error(host); 863653a761eSUlf Hansson mmci_dma_unmap(host, data); 864653a761eSUlf Hansson } 865c8ebae37SRussell King 866c8afc9d5SRussell King /* 867c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 868c8afc9d5SRussell King * the data counter gives the number of bytes transferred 869c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 870c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 871c8afc9d5SRussell King * matters for FIFO overruns only. 872c8afc9d5SRussell King */ 873f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 8748cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 8758cb28155SLinus Walleij 876c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 877c8afc9d5SRussell King status, success); 8788cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 8798cb28155SLinus Walleij /* Last block was not successful */ 880c8afc9d5SRussell King success -= 1; 88117b0429dSPierre Ossman data->error = -EILSEQ; 8828cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 88317b0429dSPierre Ossman data->error = -ETIMEDOUT; 884757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 885757df746SLinus Walleij data->error = -ECOMM; 886c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 88717b0429dSPierre Ossman data->error = -EIO; 888c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 889c8afc9d5SRussell King if (success > host->variant->fifosize) 890c8afc9d5SRussell King success -= host->variant->fifosize; 891c8afc9d5SRussell King else 892c8afc9d5SRussell King success = 0; 8938cb28155SLinus Walleij data->error = -EIO; 8944ce1d6cbSRabin Vincent } 89551d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 8961c6a0718SPierre Ossman } 897f20f8f21SLinus Walleij 8988cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 8998cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 900f20f8f21SLinus Walleij 901ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 902c8ebae37SRussell King if (dma_inprogress(host)) 903653a761eSUlf Hansson mmci_dma_finalize(host, data); 9041c6a0718SPierre Ossman mmci_stop_data(host); 9051c6a0718SPierre Ossman 9068cb28155SLinus Walleij if (!data->error) 9078cb28155SLinus Walleij /* The error clause is handled above, success! */ 90851d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 909f20f8f21SLinus Walleij 910024629c6SUlf Hansson if (!data->stop || host->mrq->sbc) { 9111c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 9121c6a0718SPierre Ossman } else { 9131c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 9141c6a0718SPierre Ossman } 9151c6a0718SPierre Ossman } 9161c6a0718SPierre Ossman } 9171c6a0718SPierre Ossman 9181c6a0718SPierre Ossman static void 9191c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 9201c6a0718SPierre Ossman unsigned int status) 9211c6a0718SPierre Ossman { 9221c6a0718SPierre Ossman void __iomem *base = host->base; 923024629c6SUlf Hansson bool sbc = (cmd == host->mrq->sbc); 9248d94b54dSUlf Hansson bool busy_resp = host->variant->busy_detect && 9258d94b54dSUlf Hansson (cmd->flags & MMC_RSP_BUSY); 9268d94b54dSUlf Hansson 9278d94b54dSUlf Hansson /* Check if we need to wait for busy completion. */ 9288d94b54dSUlf Hansson if (host->busy_status && (status & MCI_ST_CARDBUSY)) 9298d94b54dSUlf Hansson return; 9308d94b54dSUlf Hansson 9318d94b54dSUlf Hansson /* Enable busy completion if needed and supported. */ 9328d94b54dSUlf Hansson if (!host->busy_status && busy_resp && 9338d94b54dSUlf Hansson !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 9348d94b54dSUlf Hansson (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 9358d94b54dSUlf Hansson writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 9368d94b54dSUlf Hansson base + MMCIMASK0); 9378d94b54dSUlf Hansson host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 9388d94b54dSUlf Hansson return; 9398d94b54dSUlf Hansson } 9408d94b54dSUlf Hansson 9418d94b54dSUlf Hansson /* At busy completion, mask the IRQ and complete the request. */ 9428d94b54dSUlf Hansson if (host->busy_status) { 9438d94b54dSUlf Hansson writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 9448d94b54dSUlf Hansson base + MMCIMASK0); 9458d94b54dSUlf Hansson host->busy_status = 0; 9468d94b54dSUlf Hansson } 9471c6a0718SPierre Ossman 9481c6a0718SPierre Ossman host->cmd = NULL; 9491c6a0718SPierre Ossman 9501c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 95117b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 9521c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 95317b0429dSPierre Ossman cmd->error = -EILSEQ; 9549047b435SRussell King - ARM Linux } else { 9559047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 9569047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 9579047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 9589047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 9591c6a0718SPierre Ossman } 9601c6a0718SPierre Ossman 961024629c6SUlf Hansson if ((!sbc && !cmd->data) || cmd->error) { 9623b6e3c73SUlf Hansson if (host->data) { 9633b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 964653a761eSUlf Hansson if (dma_inprogress(host)) { 9653b6e3c73SUlf Hansson mmci_dma_data_error(host); 966653a761eSUlf Hansson mmci_dma_unmap(host, host->data); 967653a761eSUlf Hansson } 9681c6a0718SPierre Ossman mmci_stop_data(host); 9693b6e3c73SUlf Hansson } 970024629c6SUlf Hansson mmci_request_end(host, host->mrq); 971024629c6SUlf Hansson } else if (sbc) { 972024629c6SUlf Hansson mmci_start_command(host, host->mrq->cmd, 0); 9731c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 9741c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 9751c6a0718SPierre Ossman } 9761c6a0718SPierre Ossman } 9771c6a0718SPierre Ossman 9781c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 9791c6a0718SPierre Ossman { 9801c6a0718SPierre Ossman void __iomem *base = host->base; 9811c6a0718SPierre Ossman char *ptr = buffer; 9821c6a0718SPierre Ossman u32 status; 98326eed9a5SLinus Walleij int host_remain = host->size; 9841c6a0718SPierre Ossman 9851c6a0718SPierre Ossman do { 98626eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 9871c6a0718SPierre Ossman 9881c6a0718SPierre Ossman if (count > remain) 9891c6a0718SPierre Ossman count = remain; 9901c6a0718SPierre Ossman 9911c6a0718SPierre Ossman if (count <= 0) 9921c6a0718SPierre Ossman break; 9931c6a0718SPierre Ossman 994393e5e24SUlf Hansson /* 995393e5e24SUlf Hansson * SDIO especially may want to send something that is 996393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 997393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 998393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 999393e5e24SUlf Hansson */ 1000393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 1001393e5e24SUlf Hansson if (count < 4) { 1002393e5e24SUlf Hansson unsigned char buf[4]; 10034b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 1004393e5e24SUlf Hansson memcpy(ptr, buf, count); 1005393e5e24SUlf Hansson } else { 10064b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1007393e5e24SUlf Hansson count &= ~0x3; 1008393e5e24SUlf Hansson } 1009393e5e24SUlf Hansson } else { 10104b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1011393e5e24SUlf Hansson } 10121c6a0718SPierre Ossman 10131c6a0718SPierre Ossman ptr += count; 10141c6a0718SPierre Ossman remain -= count; 101526eed9a5SLinus Walleij host_remain -= count; 10161c6a0718SPierre Ossman 10171c6a0718SPierre Ossman if (remain == 0) 10181c6a0718SPierre Ossman break; 10191c6a0718SPierre Ossman 10201c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 10211c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 10221c6a0718SPierre Ossman 10231c6a0718SPierre Ossman return ptr - buffer; 10241c6a0718SPierre Ossman } 10251c6a0718SPierre Ossman 10261c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 10271c6a0718SPierre Ossman { 10288301bb68SRabin Vincent struct variant_data *variant = host->variant; 10291c6a0718SPierre Ossman void __iomem *base = host->base; 10301c6a0718SPierre Ossman char *ptr = buffer; 10311c6a0718SPierre Ossman 10321c6a0718SPierre Ossman do { 10331c6a0718SPierre Ossman unsigned int count, maxcnt; 10341c6a0718SPierre Ossman 10358301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 10368301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 10371c6a0718SPierre Ossman count = min(remain, maxcnt); 10381c6a0718SPierre Ossman 103934177802SLinus Walleij /* 104034177802SLinus Walleij * SDIO especially may want to send something that is 104134177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 104234177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 104334177802SLinus Walleij * So compensate by adding +3 on the count, a single 104434177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 104534177802SLinus Walleij * 32bit writes etc. 104634177802SLinus Walleij */ 10474b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 10481c6a0718SPierre Ossman 10491c6a0718SPierre Ossman ptr += count; 10501c6a0718SPierre Ossman remain -= count; 10511c6a0718SPierre Ossman 10521c6a0718SPierre Ossman if (remain == 0) 10531c6a0718SPierre Ossman break; 10541c6a0718SPierre Ossman 10551c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 10561c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 10571c6a0718SPierre Ossman 10581c6a0718SPierre Ossman return ptr - buffer; 10591c6a0718SPierre Ossman } 10601c6a0718SPierre Ossman 10611c6a0718SPierre Ossman /* 10621c6a0718SPierre Ossman * PIO data transfer IRQ handler. 10631c6a0718SPierre Ossman */ 10641c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 10651c6a0718SPierre Ossman { 10661c6a0718SPierre Ossman struct mmci_host *host = dev_id; 10674ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 10688301bb68SRabin Vincent struct variant_data *variant = host->variant; 10691c6a0718SPierre Ossman void __iomem *base = host->base; 10704ce1d6cbSRabin Vincent unsigned long flags; 10711c6a0718SPierre Ossman u32 status; 10721c6a0718SPierre Ossman 10731c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 10741c6a0718SPierre Ossman 107564de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 10761c6a0718SPierre Ossman 10774ce1d6cbSRabin Vincent local_irq_save(flags); 10784ce1d6cbSRabin Vincent 10791c6a0718SPierre Ossman do { 10801c6a0718SPierre Ossman unsigned int remain, len; 10811c6a0718SPierre Ossman char *buffer; 10821c6a0718SPierre Ossman 10831c6a0718SPierre Ossman /* 10841c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 10851c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 10861c6a0718SPierre Ossman * definition it is more than half empty. 10871c6a0718SPierre Ossman * 10881c6a0718SPierre Ossman * For read, check for data available. 10891c6a0718SPierre Ossman */ 10901c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 10911c6a0718SPierre Ossman break; 10921c6a0718SPierre Ossman 10934ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 10944ce1d6cbSRabin Vincent break; 10954ce1d6cbSRabin Vincent 10964ce1d6cbSRabin Vincent buffer = sg_miter->addr; 10974ce1d6cbSRabin Vincent remain = sg_miter->length; 10981c6a0718SPierre Ossman 10991c6a0718SPierre Ossman len = 0; 11001c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 11011c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 11021c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 11031c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 11041c6a0718SPierre Ossman 11054ce1d6cbSRabin Vincent sg_miter->consumed = len; 11061c6a0718SPierre Ossman 11071c6a0718SPierre Ossman host->size -= len; 11081c6a0718SPierre Ossman remain -= len; 11091c6a0718SPierre Ossman 11101c6a0718SPierre Ossman if (remain) 11111c6a0718SPierre Ossman break; 11121c6a0718SPierre Ossman 11131c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 11141c6a0718SPierre Ossman } while (1); 11151c6a0718SPierre Ossman 11164ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 11174ce1d6cbSRabin Vincent 11184ce1d6cbSRabin Vincent local_irq_restore(flags); 11194ce1d6cbSRabin Vincent 11201c6a0718SPierre Ossman /* 1121c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 1122c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 11231c6a0718SPierre Ossman */ 1124c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 11252686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 11261c6a0718SPierre Ossman 11271c6a0718SPierre Ossman /* 11281c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 11291c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 11301c6a0718SPierre Ossman * the chip itself has disabled the data path, and 11311c6a0718SPierre Ossman * stops us racing with our data end IRQ. 11321c6a0718SPierre Ossman */ 11331c6a0718SPierre Ossman if (host->size == 0) { 11342686b4b4SLinus Walleij mmci_set_mask1(host, 0); 11351c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 11361c6a0718SPierre Ossman } 11371c6a0718SPierre Ossman 11381c6a0718SPierre Ossman return IRQ_HANDLED; 11391c6a0718SPierre Ossman } 11401c6a0718SPierre Ossman 11411c6a0718SPierre Ossman /* 11421c6a0718SPierre Ossman * Handle completion of command and data transfers. 11431c6a0718SPierre Ossman */ 11441c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 11451c6a0718SPierre Ossman { 11461c6a0718SPierre Ossman struct mmci_host *host = dev_id; 11471c6a0718SPierre Ossman u32 status; 11481c6a0718SPierre Ossman int ret = 0; 11491c6a0718SPierre Ossman 11501c6a0718SPierre Ossman spin_lock(&host->lock); 11511c6a0718SPierre Ossman 11521c6a0718SPierre Ossman do { 11531c6a0718SPierre Ossman struct mmc_command *cmd; 11541c6a0718SPierre Ossman struct mmc_data *data; 11551c6a0718SPierre Ossman 11561c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 11572686b4b4SLinus Walleij 11582686b4b4SLinus Walleij if (host->singleirq) { 11592686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 11602686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 11612686b4b4SLinus Walleij 11622686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 11632686b4b4SLinus Walleij } 11642686b4b4SLinus Walleij 11658d94b54dSUlf Hansson /* 11668d94b54dSUlf Hansson * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 11678d94b54dSUlf Hansson * enabled) since the HW seems to be triggering the IRQ on both 11688d94b54dSUlf Hansson * edges while monitoring DAT0 for busy completion. 11698d94b54dSUlf Hansson */ 11701c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 11711c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 11721c6a0718SPierre Ossman 117364de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 11741c6a0718SPierre Ossman 1175e7f3d222SUlf Hansson cmd = host->cmd; 11768d94b54dSUlf Hansson if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 11778d94b54dSUlf Hansson MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1178e7f3d222SUlf Hansson mmci_cmd_irq(host, cmd, status); 1179e7f3d222SUlf Hansson 11801c6a0718SPierre Ossman data = host->data; 1181b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1182b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1183b63038d6SUlf Hansson MCI_DATABLOCKEND) && data) 11841c6a0718SPierre Ossman mmci_data_irq(host, data, status); 11851c6a0718SPierre Ossman 11868d94b54dSUlf Hansson /* Don't poll for busy completion in irq context. */ 11878d94b54dSUlf Hansson if (host->busy_status) 11888d94b54dSUlf Hansson status &= ~MCI_ST_CARDBUSY; 11898d94b54dSUlf Hansson 11901c6a0718SPierre Ossman ret = 1; 11911c6a0718SPierre Ossman } while (status); 11921c6a0718SPierre Ossman 11931c6a0718SPierre Ossman spin_unlock(&host->lock); 11941c6a0718SPierre Ossman 11951c6a0718SPierre Ossman return IRQ_RETVAL(ret); 11961c6a0718SPierre Ossman } 11971c6a0718SPierre Ossman 11981c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 11991c6a0718SPierre Ossman { 12001c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 12019e943021SLinus Walleij unsigned long flags; 12021c6a0718SPierre Ossman 12031c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 12041c6a0718SPierre Ossman 1205653a761eSUlf Hansson mrq->cmd->error = mmci_validate_data(host, mrq->data); 1206653a761eSUlf Hansson if (mrq->cmd->error) { 1207255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1208255d01afSPierre Ossman return; 1209255d01afSPierre Ossman } 1210255d01afSPierre Ossman 12111c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 12121c3be369SRussell King 12139e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 12141c6a0718SPierre Ossman 12151c6a0718SPierre Ossman host->mrq = mrq; 12161c6a0718SPierre Ossman 121758c7ccbfSPer Forlin if (mrq->data) 121858c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 121958c7ccbfSPer Forlin 12201c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 12211c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 12221c6a0718SPierre Ossman 1223024629c6SUlf Hansson if (mrq->sbc) 1224024629c6SUlf Hansson mmci_start_command(host, mrq->sbc, 0); 1225024629c6SUlf Hansson else 12261c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 12271c6a0718SPierre Ossman 12289e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 12291c6a0718SPierre Ossman } 12301c6a0718SPierre Ossman 12311c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 12321c6a0718SPierre Ossman { 12331c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 12347d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1235a6a6464aSLinus Walleij u32 pwr = 0; 1236a6a6464aSLinus Walleij unsigned long flags; 1237db90f91fSLee Jones int ret; 12381c6a0718SPierre Ossman 12392cd976c4SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 12402cd976c4SUlf Hansson 1241bc521818SUlf Hansson if (host->plat->ios_handler && 1242bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1243bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1244bc521818SUlf Hansson 12451c6a0718SPierre Ossman switch (ios->power_mode) { 12461c6a0718SPierre Ossman case MMC_POWER_OFF: 1247599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1248599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1249237fb5e6SLee Jones 12507c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1251237fb5e6SLee Jones regulator_disable(mmc->supply.vqmmc); 12527c0136efSUlf Hansson host->vqmmc_enabled = false; 12537c0136efSUlf Hansson } 1254237fb5e6SLee Jones 12551c6a0718SPierre Ossman break; 12561c6a0718SPierre Ossman case MMC_POWER_UP: 1257599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1258599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1259599c1d5cSUlf Hansson 12607d72a1d4SUlf Hansson /* 12617d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 12627d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 12637d72a1d4SUlf Hansson * configured in the variant data. 12647d72a1d4SUlf Hansson */ 12657d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 12667d72a1d4SUlf Hansson 12671c6a0718SPierre Ossman break; 12681c6a0718SPierre Ossman case MMC_POWER_ON: 12697c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1270db90f91fSLee Jones ret = regulator_enable(mmc->supply.vqmmc); 1271db90f91fSLee Jones if (ret < 0) 1272db90f91fSLee Jones dev_err(mmc_dev(mmc), 1273db90f91fSLee Jones "failed to enable vqmmc regulator\n"); 12747c0136efSUlf Hansson else 12757c0136efSUlf Hansson host->vqmmc_enabled = true; 1276db90f91fSLee Jones } 1277237fb5e6SLee Jones 12781c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 12791c6a0718SPierre Ossman break; 12801c6a0718SPierre Ossman } 12811c6a0718SPierre Ossman 12824d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 12834d1a3a0dSUlf Hansson /* 12844d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 12854d1a3a0dSUlf Hansson * indicating signal direction for the signals in 12864d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 12874d1a3a0dSUlf Hansson */ 12884d1a3a0dSUlf Hansson pwr |= host->plat->sigdir; 12894d1a3a0dSUlf Hansson 12904d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 12914d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 12924d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 12934d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 12944d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 12954d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 12964d1a3a0dSUlf Hansson } 12974d1a3a0dSUlf Hansson 1298cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1299f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 13001c6a0718SPierre Ossman pwr |= MCI_ROD; 1301cc30d60eSLinus Walleij else { 1302cc30d60eSLinus Walleij /* 1303cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1304cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1305cc30d60eSLinus Walleij */ 1306cc30d60eSLinus Walleij pwr |= MCI_OD; 1307cc30d60eSLinus Walleij } 1308cc30d60eSLinus Walleij } 13091c6a0718SPierre Ossman 1310f4670daeSUlf Hansson /* 1311f4670daeSUlf Hansson * If clock = 0 and the variant requires the MMCIPOWER to be used for 1312f4670daeSUlf Hansson * gating the clock, the MCI_PWR_ON bit is cleared. 1313f4670daeSUlf Hansson */ 1314f4670daeSUlf Hansson if (!ios->clock && variant->pwrreg_clkgate) 1315f4670daeSUlf Hansson pwr &= ~MCI_PWR_ON; 1316f4670daeSUlf Hansson 1317a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1318a6a6464aSLinus Walleij 1319a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 13207437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1321f829c042SUlf Hansson mmci_reg_delay(host); 1322a6a6464aSLinus Walleij 1323a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 13242cd976c4SUlf Hansson 13252cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 13262cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 13271c6a0718SPierre Ossman } 13281c6a0718SPierre Ossman 132989001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 133089001446SRussell King { 133189001446SRussell King struct mmci_host *host = mmc_priv(mmc); 133289001446SRussell King 133389001446SRussell King if (host->gpio_wp == -ENOSYS) 133489001446SRussell King return -ENOSYS; 133589001446SRussell King 133618a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 133789001446SRussell King } 133889001446SRussell King 133989001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 134089001446SRussell King { 134189001446SRussell King struct mmci_host *host = mmc_priv(mmc); 134229719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 134389001446SRussell King unsigned int status; 134489001446SRussell King 13454b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 13464b8caec0SRabin Vincent if (!plat->status) 13474b8caec0SRabin Vincent return 1; /* Assume always present */ 13484b8caec0SRabin Vincent 134929719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 13504b8caec0SRabin Vincent } else 135118a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 135218a06301SLinus Walleij ^ plat->cd_invert; 135389001446SRussell King 135474bc8093SRussell King /* 135574bc8093SRussell King * Use positive logic throughout - status is zero for no card, 135674bc8093SRussell King * non-zero for card inserted. 135774bc8093SRussell King */ 135874bc8093SRussell King return status; 135989001446SRussell King } 136089001446SRussell King 13610f3ed7f7SUlf Hansson static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 13620f3ed7f7SUlf Hansson { 13630f3ed7f7SUlf Hansson int ret = 0; 13640f3ed7f7SUlf Hansson 13650f3ed7f7SUlf Hansson if (!IS_ERR(mmc->supply.vqmmc)) { 13660f3ed7f7SUlf Hansson 13670f3ed7f7SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 13680f3ed7f7SUlf Hansson 13690f3ed7f7SUlf Hansson switch (ios->signal_voltage) { 13700f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_330: 13710f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 13720f3ed7f7SUlf Hansson 2700000, 3600000); 13730f3ed7f7SUlf Hansson break; 13740f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_180: 13750f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 13760f3ed7f7SUlf Hansson 1700000, 1950000); 13770f3ed7f7SUlf Hansson break; 13780f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_120: 13790f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 13800f3ed7f7SUlf Hansson 1100000, 1300000); 13810f3ed7f7SUlf Hansson break; 13820f3ed7f7SUlf Hansson } 13830f3ed7f7SUlf Hansson 13840f3ed7f7SUlf Hansson if (ret) 13850f3ed7f7SUlf Hansson dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 13860f3ed7f7SUlf Hansson 13870f3ed7f7SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 13880f3ed7f7SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 13890f3ed7f7SUlf Hansson } 13900f3ed7f7SUlf Hansson 13910f3ed7f7SUlf Hansson return ret; 13920f3ed7f7SUlf Hansson } 13930f3ed7f7SUlf Hansson 1394148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1395148b8b39SRabin Vincent { 1396148b8b39SRabin Vincent struct mmci_host *host = dev_id; 1397148b8b39SRabin Vincent 1398148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1399148b8b39SRabin Vincent 1400148b8b39SRabin Vincent return IRQ_HANDLED; 1401148b8b39SRabin Vincent } 1402148b8b39SRabin Vincent 140301259620SUlf Hansson static struct mmc_host_ops mmci_ops = { 14041c6a0718SPierre Ossman .request = mmci_request, 140558c7ccbfSPer Forlin .pre_req = mmci_pre_request, 140658c7ccbfSPer Forlin .post_req = mmci_post_request, 14071c6a0718SPierre Ossman .set_ios = mmci_set_ios, 140889001446SRussell King .get_ro = mmci_get_ro, 140989001446SRussell King .get_cd = mmci_get_cd, 14100f3ed7f7SUlf Hansson .start_signal_voltage_switch = mmci_sig_volt_switch, 14111c6a0718SPierre Ossman }; 14121c6a0718SPierre Ossman 1413000bc9d5SLee Jones #ifdef CONFIG_OF 1414000bc9d5SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1415000bc9d5SLee Jones struct mmci_platform_data *pdata) 1416000bc9d5SLee Jones { 1417000bc9d5SLee Jones int bus_width = 0; 1418000bc9d5SLee Jones 14199a597016SLee Jones pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 14209a597016SLee Jones pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1421000bc9d5SLee Jones 1422000bc9d5SLee Jones if (of_get_property(np, "cd-inverted", NULL)) 1423000bc9d5SLee Jones pdata->cd_invert = true; 1424000bc9d5SLee Jones else 1425000bc9d5SLee Jones pdata->cd_invert = false; 1426000bc9d5SLee Jones 1427000bc9d5SLee Jones of_property_read_u32(np, "max-frequency", &pdata->f_max); 1428000bc9d5SLee Jones if (!pdata->f_max) 1429000bc9d5SLee Jones pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1430000bc9d5SLee Jones 1431000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1432000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1433000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1434000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1435000bc9d5SLee Jones 1436000bc9d5SLee Jones of_property_read_u32(np, "bus-width", &bus_width); 1437000bc9d5SLee Jones switch (bus_width) { 1438000bc9d5SLee Jones case 0 : 1439000bc9d5SLee Jones /* No bus-width supplied. */ 1440000bc9d5SLee Jones break; 1441000bc9d5SLee Jones case 4 : 1442000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1443000bc9d5SLee Jones break; 1444000bc9d5SLee Jones case 8 : 1445000bc9d5SLee Jones pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1446000bc9d5SLee Jones break; 1447000bc9d5SLee Jones default : 1448000bc9d5SLee Jones pr_warn("%s: Unsupported bus width\n", np->full_name); 1449000bc9d5SLee Jones } 1450000bc9d5SLee Jones } 1451c0a120a4SLee Jones #else 1452c0a120a4SLee Jones static void mmci_dt_populate_generic_pdata(struct device_node *np, 1453c0a120a4SLee Jones struct mmci_platform_data *pdata) 1454c0a120a4SLee Jones { 1455c0a120a4SLee Jones return; 1456c0a120a4SLee Jones } 1457000bc9d5SLee Jones #endif 1458000bc9d5SLee Jones 1459c3be1efdSBill Pemberton static int mmci_probe(struct amba_device *dev, 1460aa25afadSRussell King const struct amba_id *id) 14611c6a0718SPierre Ossman { 14626ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1463000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 14644956e109SRabin Vincent struct variant_data *variant = id->data; 14651c6a0718SPierre Ossman struct mmci_host *host; 14661c6a0718SPierre Ossman struct mmc_host *mmc; 14671c6a0718SPierre Ossman int ret; 14681c6a0718SPierre Ossman 1469000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1470000bc9d5SLee Jones if (!plat && !np) { 1471000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1472000bc9d5SLee Jones return -EINVAL; 14731c6a0718SPierre Ossman } 14741c6a0718SPierre Ossman 1475b9b52918SLee Jones if (!plat) { 1476b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1477b9b52918SLee Jones if (!plat) 1478b9b52918SLee Jones return -ENOMEM; 1479b9b52918SLee Jones } 1480b9b52918SLee Jones 1481000bc9d5SLee Jones if (np) 1482000bc9d5SLee Jones mmci_dt_populate_generic_pdata(np, plat); 1483000bc9d5SLee Jones 14841c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 14851c6a0718SPierre Ossman if (ret) 14861c6a0718SPierre Ossman goto out; 14871c6a0718SPierre Ossman 14881c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 14891c6a0718SPierre Ossman if (!mmc) { 14901c6a0718SPierre Ossman ret = -ENOMEM; 14911c6a0718SPierre Ossman goto rel_regions; 14921c6a0718SPierre Ossman } 14931c6a0718SPierre Ossman 14941c6a0718SPierre Ossman host = mmc_priv(mmc); 14954ea580f1SRabin Vincent host->mmc = mmc; 1496012b7d33SRussell King 149789001446SRussell King host->gpio_wp = -ENOSYS; 149889001446SRussell King host->gpio_cd = -ENOSYS; 1499148b8b39SRabin Vincent host->gpio_cd_irq = -1; 150089001446SRussell King 1501012b7d33SRussell King host->hw_designer = amba_manf(dev); 1502012b7d33SRussell King host->hw_revision = amba_rev(dev); 150364de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 150464de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1505012b7d33SRussell King 1506665ba56fSUlf Hansson host->clk = devm_clk_get(&dev->dev, NULL); 15071c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 15081c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 15091c6a0718SPierre Ossman goto host_free; 15101c6a0718SPierre Ossman } 15111c6a0718SPierre Ossman 1512ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 15131c6a0718SPierre Ossman if (ret) 1514665ba56fSUlf Hansson goto host_free; 15151c6a0718SPierre Ossman 15161c6a0718SPierre Ossman host->plat = plat; 15174956e109SRabin Vincent host->variant = variant; 15181c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1519c8df9a53SLinus Walleij /* 1520c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1521c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1522c8df9a53SLinus Walleij * (if possible). 1523c8df9a53SLinus Walleij */ 1524c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1525c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1526c8df9a53SLinus Walleij if (ret < 0) 1527c8df9a53SLinus Walleij goto clk_disable; 1528c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 152964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 153064de0289SLinus Walleij host->mclk); 1531c8df9a53SLinus Walleij } 1532c8ebae37SRussell King host->phybase = dev->res.start; 1533dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 15341c6a0718SPierre Ossman if (!host->base) { 15351c6a0718SPierre Ossman ret = -ENOMEM; 15361c6a0718SPierre Ossman goto clk_disable; 15371c6a0718SPierre Ossman } 15381c6a0718SPierre Ossman 15397f294e49SLinus Walleij /* 15407f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 15417f294e49SLinus Walleij * clock divider equations which means that the minimum divider 15427f294e49SLinus Walleij * differs too. 15437f294e49SLinus Walleij */ 15447f294e49SLinus Walleij if (variant->st_clkdiv) 15457f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 15467f294e49SLinus Walleij else 15477f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1548808d97ccSLinus Walleij /* 1549808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1550808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1551808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1552808d97ccSLinus Walleij * default value in case it is not specified. Either 1553808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1554808d97ccSLinus Walleij * of course. 1555808d97ccSLinus Walleij */ 1556808d97ccSLinus Walleij if (plat->f_max) 1557808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1558808d97ccSLinus Walleij else 15591c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 156064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 156164de0289SLinus Walleij 1562599c1d5cSUlf Hansson /* Get regulators and the supported OCR mask */ 1563599c1d5cSUlf Hansson mmc_regulator_get_supply(mmc); 1564599c1d5cSUlf Hansson if (!mmc->ocr_avail) 15651c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 1566599c1d5cSUlf Hansson else if (plat->ocr_mask) 1567599c1d5cSUlf Hansson dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1568599c1d5cSUlf Hansson 15699e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 15705a092627SPer Forlin mmc->caps2 = plat->capabilities2; 15711c6a0718SPierre Ossman 15728d94b54dSUlf Hansson if (variant->busy_detect) { 15738d94b54dSUlf Hansson mmci_ops.card_busy = mmci_card_busy; 15748d94b54dSUlf Hansson mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 15758d94b54dSUlf Hansson mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 15768d94b54dSUlf Hansson mmc->max_busy_timeout = 0; 15778d94b54dSUlf Hansson } 15788d94b54dSUlf Hansson 15798d94b54dSUlf Hansson mmc->ops = &mmci_ops; 15808d94b54dSUlf Hansson 158170be208fSUlf Hansson /* We support these PM capabilities. */ 158270be208fSUlf Hansson mmc->pm_caps = MMC_PM_KEEP_POWER; 158370be208fSUlf Hansson 15841c6a0718SPierre Ossman /* 15851c6a0718SPierre Ossman * We can do SGIO 15861c6a0718SPierre Ossman */ 1587a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 15881c6a0718SPierre Ossman 15891c6a0718SPierre Ossman /* 159008458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 159108458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 159208458ef6SRabin Vincent * single request. 15931c6a0718SPierre Ossman */ 159408458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 15951c6a0718SPierre Ossman 15961c6a0718SPierre Ossman /* 15971c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 15981c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 15991c6a0718SPierre Ossman */ 16001c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 16011c6a0718SPierre Ossman 16021c6a0718SPierre Ossman /* 16031c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 16041c6a0718SPierre Ossman */ 16058f7f6b7eSWill Deacon mmc->max_blk_size = 1 << 11; 16061c6a0718SPierre Ossman 16071c6a0718SPierre Ossman /* 16088f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 16098f7f6b7eSWill Deacon * the maximum request size. 16101c6a0718SPierre Ossman */ 16118f7f6b7eSWill Deacon mmc->max_blk_count = mmc->max_req_size >> 11; 16121c6a0718SPierre Ossman 16131c6a0718SPierre Ossman spin_lock_init(&host->lock); 16141c6a0718SPierre Ossman 16151c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 16161c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 16171c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 16181c6a0718SPierre Ossman 16192805b9abSRoland Stigge if (plat->gpio_cd == -EPROBE_DEFER) { 16202805b9abSRoland Stigge ret = -EPROBE_DEFER; 16212805b9abSRoland Stigge goto err_gpio_cd; 16222805b9abSRoland Stigge } 162389001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 162489001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 162589001446SRussell King if (ret == 0) 162689001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 162789001446SRussell King if (ret == 0) 162889001446SRussell King host->gpio_cd = plat->gpio_cd; 162989001446SRussell King else if (ret != -ENOSYS) 163089001446SRussell King goto err_gpio_cd; 1631148b8b39SRabin Vincent 163217ee083bSLinus Walleij /* 163317ee083bSLinus Walleij * A gpio pin that will detect cards when inserted and removed 163417ee083bSLinus Walleij * will most likely want to trigger on the edges if it is 163517ee083bSLinus Walleij * 0 when ejected and 1 when inserted (or mutatis mutandis 163617ee083bSLinus Walleij * for the inverted case) so we request triggers on both 163717ee083bSLinus Walleij * edges. 163817ee083bSLinus Walleij */ 1639148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 164017ee083bSLinus Walleij mmci_cd_irq, 164117ee083bSLinus Walleij IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1642148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1643148b8b39SRabin Vincent if (ret >= 0) 1644148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 164589001446SRussell King } 16462805b9abSRoland Stigge if (plat->gpio_wp == -EPROBE_DEFER) { 16472805b9abSRoland Stigge ret = -EPROBE_DEFER; 16482805b9abSRoland Stigge goto err_gpio_wp; 16492805b9abSRoland Stigge } 165089001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 165189001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 165289001446SRussell King if (ret == 0) 165389001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 165489001446SRussell King if (ret == 0) 165589001446SRussell King host->gpio_wp = plat->gpio_wp; 165689001446SRussell King else if (ret != -ENOSYS) 165789001446SRussell King goto err_gpio_wp; 165889001446SRussell King } 165989001446SRussell King 16604b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 16614b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1662148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1663148b8b39SRabin Vincent 16641c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 16651c6a0718SPierre Ossman if (ret) 16661c6a0718SPierre Ossman goto unmap; 16671c6a0718SPierre Ossman 1668dfb85185SRussell King if (!dev->irq[1]) 16692686b4b4SLinus Walleij host->singleirq = true; 16702686b4b4SLinus Walleij else { 16712686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 16722686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 16731c6a0718SPierre Ossman if (ret) 16741c6a0718SPierre Ossman goto irq0_free; 16752686b4b4SLinus Walleij } 16761c6a0718SPierre Ossman 16778cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 16781c6a0718SPierre Ossman 16791c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 16801c6a0718SPierre Ossman 1681c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1682c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1683c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1684c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1685c8ebae37SRussell King 1686c8ebae37SRussell King mmci_dma_setup(host); 16871c6a0718SPierre Ossman 16882cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 16892cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 16901c3be369SRussell King pm_runtime_put(&dev->dev); 16911c3be369SRussell King 16928c11a94dSRussell King mmc_add_host(mmc); 16938c11a94dSRussell King 16941c6a0718SPierre Ossman return 0; 16951c6a0718SPierre Ossman 16961c6a0718SPierre Ossman irq0_free: 16971c6a0718SPierre Ossman free_irq(dev->irq[0], host); 16981c6a0718SPierre Ossman unmap: 169989001446SRussell King if (host->gpio_wp != -ENOSYS) 170089001446SRussell King gpio_free(host->gpio_wp); 170189001446SRussell King err_gpio_wp: 1702148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1703148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 170489001446SRussell King if (host->gpio_cd != -ENOSYS) 170589001446SRussell King gpio_free(host->gpio_cd); 170689001446SRussell King err_gpio_cd: 17071c6a0718SPierre Ossman iounmap(host->base); 17081c6a0718SPierre Ossman clk_disable: 1709ac940938SJulia Lawall clk_disable_unprepare(host->clk); 17101c6a0718SPierre Ossman host_free: 17111c6a0718SPierre Ossman mmc_free_host(mmc); 17121c6a0718SPierre Ossman rel_regions: 17131c6a0718SPierre Ossman amba_release_regions(dev); 17141c6a0718SPierre Ossman out: 17151c6a0718SPierre Ossman return ret; 17161c6a0718SPierre Ossman } 17171c6a0718SPierre Ossman 17186e0ee714SBill Pemberton static int mmci_remove(struct amba_device *dev) 17191c6a0718SPierre Ossman { 17201c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 17211c6a0718SPierre Ossman 17221c6a0718SPierre Ossman if (mmc) { 17231c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 17241c6a0718SPierre Ossman 17251c3be369SRussell King /* 17261c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 17271c3be369SRussell King * version here so that we can access the primecell. 17281c3be369SRussell King */ 17291c3be369SRussell King pm_runtime_get_sync(&dev->dev); 17301c3be369SRussell King 17311c6a0718SPierre Ossman mmc_remove_host(mmc); 17321c6a0718SPierre Ossman 17331c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 17341c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 17351c6a0718SPierre Ossman 17361c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 17371c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 17381c6a0718SPierre Ossman 1739c8ebae37SRussell King mmci_dma_release(host); 17401c6a0718SPierre Ossman free_irq(dev->irq[0], host); 17412686b4b4SLinus Walleij if (!host->singleirq) 17421c6a0718SPierre Ossman free_irq(dev->irq[1], host); 17431c6a0718SPierre Ossman 174489001446SRussell King if (host->gpio_wp != -ENOSYS) 174589001446SRussell King gpio_free(host->gpio_wp); 1746148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1747148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 174889001446SRussell King if (host->gpio_cd != -ENOSYS) 174989001446SRussell King gpio_free(host->gpio_cd); 175089001446SRussell King 17511c6a0718SPierre Ossman iounmap(host->base); 1752ac940938SJulia Lawall clk_disable_unprepare(host->clk); 17531c6a0718SPierre Ossman 17541c6a0718SPierre Ossman mmc_free_host(mmc); 17551c6a0718SPierre Ossman 17561c6a0718SPierre Ossman amba_release_regions(dev); 17571c6a0718SPierre Ossman } 17581c6a0718SPierre Ossman 17591c6a0718SPierre Ossman return 0; 17601c6a0718SPierre Ossman } 17611c6a0718SPierre Ossman 176248fa7003SUlf Hansson #ifdef CONFIG_SUSPEND 176348fa7003SUlf Hansson static int mmci_suspend(struct device *dev) 17641c6a0718SPierre Ossman { 176548fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 176648fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 17671c6a0718SPierre Ossman 17681c6a0718SPierre Ossman if (mmc) { 17691c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 17702cd976c4SUlf Hansson pm_runtime_get_sync(dev); 17711c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 17721c6a0718SPierre Ossman } 17731c6a0718SPierre Ossman 1774578aebc7SUlf Hansson return 0; 17751c6a0718SPierre Ossman } 17761c6a0718SPierre Ossman 177748fa7003SUlf Hansson static int mmci_resume(struct device *dev) 17781c6a0718SPierre Ossman { 177948fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 178048fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 17811c6a0718SPierre Ossman 17821c6a0718SPierre Ossman if (mmc) { 17831c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 17841c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 17852cd976c4SUlf Hansson pm_runtime_put(dev); 17861c6a0718SPierre Ossman } 17871c6a0718SPierre Ossman 1788578aebc7SUlf Hansson return 0; 17891c6a0718SPierre Ossman } 17901c6a0718SPierre Ossman #endif 17911c6a0718SPierre Ossman 17928259293aSUlf Hansson #ifdef CONFIG_PM_RUNTIME 17931ff44433SUlf Hansson static void mmci_save(struct mmci_host *host) 17941ff44433SUlf Hansson { 17951ff44433SUlf Hansson unsigned long flags; 17961ff44433SUlf Hansson 17971ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 17981ff44433SUlf Hansson 17991ff44433SUlf Hansson writel(0, host->base + MMCIMASK0); 180042dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18011ff44433SUlf Hansson writel(0, host->base + MMCIDATACTRL); 18021ff44433SUlf Hansson writel(0, host->base + MMCIPOWER); 18031ff44433SUlf Hansson writel(0, host->base + MMCICLOCK); 180442dcc89aSUlf Hansson } 18051ff44433SUlf Hansson mmci_reg_delay(host); 18061ff44433SUlf Hansson 18071ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18081ff44433SUlf Hansson } 18091ff44433SUlf Hansson 18101ff44433SUlf Hansson static void mmci_restore(struct mmci_host *host) 18111ff44433SUlf Hansson { 18121ff44433SUlf Hansson unsigned long flags; 18131ff44433SUlf Hansson 18141ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 18151ff44433SUlf Hansson 181642dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 18171ff44433SUlf Hansson writel(host->clk_reg, host->base + MMCICLOCK); 18181ff44433SUlf Hansson writel(host->datactrl_reg, host->base + MMCIDATACTRL); 18191ff44433SUlf Hansson writel(host->pwr_reg, host->base + MMCIPOWER); 182042dcc89aSUlf Hansson } 18211ff44433SUlf Hansson writel(MCI_IRQENABLE, host->base + MMCIMASK0); 18221ff44433SUlf Hansson mmci_reg_delay(host); 18231ff44433SUlf Hansson 18241ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 18251ff44433SUlf Hansson } 18261ff44433SUlf Hansson 18278259293aSUlf Hansson static int mmci_runtime_suspend(struct device *dev) 18288259293aSUlf Hansson { 18298259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18308259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18318259293aSUlf Hansson 18328259293aSUlf Hansson if (mmc) { 18338259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 1834e36bd9c6SUlf Hansson pinctrl_pm_select_sleep_state(dev); 18351ff44433SUlf Hansson mmci_save(host); 18368259293aSUlf Hansson clk_disable_unprepare(host->clk); 18378259293aSUlf Hansson } 18388259293aSUlf Hansson 18398259293aSUlf Hansson return 0; 18408259293aSUlf Hansson } 18418259293aSUlf Hansson 18428259293aSUlf Hansson static int mmci_runtime_resume(struct device *dev) 18438259293aSUlf Hansson { 18448259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 18458259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 18468259293aSUlf Hansson 18478259293aSUlf Hansson if (mmc) { 18488259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 18498259293aSUlf Hansson clk_prepare_enable(host->clk); 18501ff44433SUlf Hansson mmci_restore(host); 1851e36bd9c6SUlf Hansson pinctrl_pm_select_default_state(dev); 18528259293aSUlf Hansson } 18538259293aSUlf Hansson 18548259293aSUlf Hansson return 0; 18558259293aSUlf Hansson } 18568259293aSUlf Hansson #endif 18578259293aSUlf Hansson 185848fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 185948fa7003SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 18608259293aSUlf Hansson SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 186148fa7003SUlf Hansson }; 186248fa7003SUlf Hansson 18631c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 18641c6a0718SPierre Ossman { 18651c6a0718SPierre Ossman .id = 0x00041180, 1866768fbc18SPawel Moll .mask = 0xff0fffff, 18674956e109SRabin Vincent .data = &variant_arm, 18681c6a0718SPierre Ossman }, 18691c6a0718SPierre Ossman { 1870768fbc18SPawel Moll .id = 0x01041180, 1871768fbc18SPawel Moll .mask = 0xff0fffff, 1872768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1873768fbc18SPawel Moll }, 1874768fbc18SPawel Moll { 18753a37298aSPawel Moll .id = 0x02041180, 18763a37298aSPawel Moll .mask = 0xff0fffff, 18773a37298aSPawel Moll .data = &variant_arm_extended_fifo_hwfc, 18783a37298aSPawel Moll }, 18793a37298aSPawel Moll { 18801c6a0718SPierre Ossman .id = 0x00041181, 18811c6a0718SPierre Ossman .mask = 0x000fffff, 18824956e109SRabin Vincent .data = &variant_arm, 18831c6a0718SPierre Ossman }, 1884cc30d60eSLinus Walleij /* ST Micro variants */ 1885cc30d60eSLinus Walleij { 1886cc30d60eSLinus Walleij .id = 0x00180180, 1887cc30d60eSLinus Walleij .mask = 0x00ffffff, 18884956e109SRabin Vincent .data = &variant_u300, 1889cc30d60eSLinus Walleij }, 1890cc30d60eSLinus Walleij { 189134fd4213SLinus Walleij .id = 0x10180180, 189234fd4213SLinus Walleij .mask = 0xf0ffffff, 189334fd4213SLinus Walleij .data = &variant_nomadik, 189434fd4213SLinus Walleij }, 189534fd4213SLinus Walleij { 1896cc30d60eSLinus Walleij .id = 0x00280180, 1897cc30d60eSLinus Walleij .mask = 0x00ffffff, 18984956e109SRabin Vincent .data = &variant_u300, 18994956e109SRabin Vincent }, 19004956e109SRabin Vincent { 19014956e109SRabin Vincent .id = 0x00480180, 19021784b157SPhilippe Langlais .mask = 0xf0ffffff, 19034956e109SRabin Vincent .data = &variant_ux500, 1904cc30d60eSLinus Walleij }, 19051784b157SPhilippe Langlais { 19061784b157SPhilippe Langlais .id = 0x10480180, 19071784b157SPhilippe Langlais .mask = 0xf0ffffff, 19081784b157SPhilippe Langlais .data = &variant_ux500v2, 19091784b157SPhilippe Langlais }, 19101c6a0718SPierre Ossman { 0, 0 }, 19111c6a0718SPierre Ossman }; 19121c6a0718SPierre Ossman 19139f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 19149f99835fSDave Martin 19151c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 19161c6a0718SPierre Ossman .drv = { 19171c6a0718SPierre Ossman .name = DRIVER_NAME, 191848fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 19191c6a0718SPierre Ossman }, 19201c6a0718SPierre Ossman .probe = mmci_probe, 19210433c143SBill Pemberton .remove = mmci_remove, 19221c6a0718SPierre Ossman .id_table = mmci_ids, 19231c6a0718SPierre Ossman }; 19241c6a0718SPierre Ossman 19259e5ed094Sviresh kumar module_amba_driver(mmci_driver); 19261c6a0718SPierre Ossman 19271c6a0718SPierre Ossman module_param(fmax, uint, 0444); 19281c6a0718SPierre Ossman 19291c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 19301c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1931