11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 181c6a0718SPierre Ossman #include <linux/delay.h> 191c6a0718SPierre Ossman #include <linux/err.h> 201c6a0718SPierre Ossman #include <linux/highmem.h> 21019a5f56SNicolas Pitre #include <linux/log2.h> 221c6a0718SPierre Ossman #include <linux/mmc/host.h> 2334177802SLinus Walleij #include <linux/mmc/card.h> 241c6a0718SPierre Ossman #include <linux/amba/bus.h> 251c6a0718SPierre Ossman #include <linux/clk.h> 26bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2789001446SRussell King #include <linux/gpio.h> 2834e84f39SLinus Walleij #include <linux/regulator/consumer.h> 29c8ebae37SRussell King #include <linux/dmaengine.h> 30c8ebae37SRussell King #include <linux/dma-mapping.h> 31c8ebae37SRussell King #include <linux/amba/mmci.h> 321c3be369SRussell King #include <linux/pm_runtime.h> 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #include <asm/div64.h> 351c6a0718SPierre Ossman #include <asm/io.h> 361c6a0718SPierre Ossman #include <asm/sizes.h> 371c6a0718SPierre Ossman 381c6a0718SPierre Ossman #include "mmci.h" 391c6a0718SPierre Ossman 401c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 411c6a0718SPierre Ossman 421c6a0718SPierre Ossman static unsigned int fmax = 515633; 431c6a0718SPierre Ossman 444956e109SRabin Vincent /** 454956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 464956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 474380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 4808458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 498301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 508301bb68SRabin Vincent * is asserted (likewise for RX) 518301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 528301bb68SRabin Vincent * is asserted (likewise for RX) 5334177802SLinus Walleij * @sdio: variant supports SDIO 54b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 551784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 567d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 574d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 584956e109SRabin Vincent */ 594956e109SRabin Vincent struct variant_data { 604956e109SRabin Vincent unsigned int clkreg; 614380c14fSRabin Vincent unsigned int clkreg_enable; 6208458ef6SRabin Vincent unsigned int datalength_bits; 638301bb68SRabin Vincent unsigned int fifosize; 648301bb68SRabin Vincent unsigned int fifohalfsize; 6534177802SLinus Walleij bool sdio; 66b70a67f9SLinus Walleij bool st_clkdiv; 671784b157SPhilippe Langlais bool blksz_datactrl16; 687d72a1d4SUlf Hansson u32 pwrreg_powerup; 694d1a3a0dSUlf Hansson bool signal_direction; 704956e109SRabin Vincent }; 714956e109SRabin Vincent 724956e109SRabin Vincent static struct variant_data variant_arm = { 738301bb68SRabin Vincent .fifosize = 16 * 4, 748301bb68SRabin Vincent .fifohalfsize = 8 * 4, 7508458ef6SRabin Vincent .datalength_bits = 16, 767d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 774956e109SRabin Vincent }; 784956e109SRabin Vincent 79768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 80768fbc18SPawel Moll .fifosize = 128 * 4, 81768fbc18SPawel Moll .fifohalfsize = 64 * 4, 82768fbc18SPawel Moll .datalength_bits = 16, 837d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 84768fbc18SPawel Moll }; 85768fbc18SPawel Moll 864956e109SRabin Vincent static struct variant_data variant_u300 = { 878301bb68SRabin Vincent .fifosize = 16 * 4, 888301bb68SRabin Vincent .fifohalfsize = 8 * 4, 8949ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 9008458ef6SRabin Vincent .datalength_bits = 16, 9134177802SLinus Walleij .sdio = true, 927d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 934d1a3a0dSUlf Hansson .signal_direction = true, 944956e109SRabin Vincent }; 954956e109SRabin Vincent 964956e109SRabin Vincent static struct variant_data variant_ux500 = { 978301bb68SRabin Vincent .fifosize = 30 * 4, 988301bb68SRabin Vincent .fifohalfsize = 8 * 4, 994956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 10049ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 10108458ef6SRabin Vincent .datalength_bits = 24, 10234177802SLinus Walleij .sdio = true, 103b70a67f9SLinus Walleij .st_clkdiv = true, 1047d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1054d1a3a0dSUlf Hansson .signal_direction = true, 1064956e109SRabin Vincent }; 107b70a67f9SLinus Walleij 1081784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1091784b157SPhilippe Langlais .fifosize = 30 * 4, 1101784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1111784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1121784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1131784b157SPhilippe Langlais .datalength_bits = 24, 1141784b157SPhilippe Langlais .sdio = true, 1151784b157SPhilippe Langlais .st_clkdiv = true, 1161784b157SPhilippe Langlais .blksz_datactrl16 = true, 1177d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1184d1a3a0dSUlf Hansson .signal_direction = true, 1191784b157SPhilippe Langlais }; 1201784b157SPhilippe Langlais 121a6a6464aSLinus Walleij /* 122a6a6464aSLinus Walleij * This must be called with host->lock held 123a6a6464aSLinus Walleij */ 124a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 125a6a6464aSLinus Walleij { 1264956e109SRabin Vincent struct variant_data *variant = host->variant; 1274956e109SRabin Vincent u32 clk = variant->clkreg; 128a6a6464aSLinus Walleij 129a6a6464aSLinus Walleij if (desired) { 130a6a6464aSLinus Walleij if (desired >= host->mclk) { 131a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 132399bc486SLinus Walleij if (variant->st_clkdiv) 133399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 134a6a6464aSLinus Walleij host->cclk = host->mclk; 135b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 136b70a67f9SLinus Walleij /* 137b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 138b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 139b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 140b70a67f9SLinus Walleij * frequency 141b70a67f9SLinus Walleij */ 142b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 143b70a67f9SLinus Walleij if (clk >= 256) 144b70a67f9SLinus Walleij clk = 255; 145b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 146a6a6464aSLinus Walleij } else { 147b70a67f9SLinus Walleij /* 148b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 149b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 150b70a67f9SLinus Walleij */ 151a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 152a6a6464aSLinus Walleij if (clk >= 256) 153a6a6464aSLinus Walleij clk = 255; 154a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 155a6a6464aSLinus Walleij } 1564380c14fSRabin Vincent 1574380c14fSRabin Vincent clk |= variant->clkreg_enable; 158a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 159a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 160a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 161a6a6464aSLinus Walleij } 162a6a6464aSLinus Walleij 1639e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 164771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 165771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 166771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 1679e6c82cdSLinus Walleij 168a6a6464aSLinus Walleij writel(clk, host->base + MMCICLOCK); 169a6a6464aSLinus Walleij } 170a6a6464aSLinus Walleij 1711c6a0718SPierre Ossman static void 1721c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 1731c6a0718SPierre Ossman { 1741c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 1751c6a0718SPierre Ossman 1761c6a0718SPierre Ossman BUG_ON(host->data); 1771c6a0718SPierre Ossman 1781c6a0718SPierre Ossman host->mrq = NULL; 1791c6a0718SPierre Ossman host->cmd = NULL; 1801c6a0718SPierre Ossman 1811c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 1822cd976c4SUlf Hansson 1832cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 1842cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 1851c6a0718SPierre Ossman } 1861c6a0718SPierre Ossman 1872686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 1882686b4b4SLinus Walleij { 1892686b4b4SLinus Walleij void __iomem *base = host->base; 1902686b4b4SLinus Walleij 1912686b4b4SLinus Walleij if (host->singleirq) { 1922686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 1932686b4b4SLinus Walleij 1942686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 1952686b4b4SLinus Walleij mask0 |= mask; 1962686b4b4SLinus Walleij 1972686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 1982686b4b4SLinus Walleij } 1992686b4b4SLinus Walleij 2002686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 2012686b4b4SLinus Walleij } 2022686b4b4SLinus Walleij 2031c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 2041c6a0718SPierre Ossman { 2051c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 2062686b4b4SLinus Walleij mmci_set_mask1(host, 0); 2071c6a0718SPierre Ossman host->data = NULL; 2081c6a0718SPierre Ossman } 2091c6a0718SPierre Ossman 2104ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 2114ce1d6cbSRabin Vincent { 2124ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 2134ce1d6cbSRabin Vincent 2144ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 2154ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 2164ce1d6cbSRabin Vincent else 2174ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 2184ce1d6cbSRabin Vincent 2194ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 2204ce1d6cbSRabin Vincent } 2214ce1d6cbSRabin Vincent 222c8ebae37SRussell King /* 223c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 224c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 225c8ebae37SRussell King * no custom DMA interfaces are supported. 226c8ebae37SRussell King */ 227c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 228c8ebae37SRussell King static void __devinit mmci_dma_setup(struct mmci_host *host) 229c8ebae37SRussell King { 230c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 231c8ebae37SRussell King const char *rxname, *txname; 232c8ebae37SRussell King dma_cap_mask_t mask; 233c8ebae37SRussell King 234c8ebae37SRussell King if (!plat || !plat->dma_filter) { 235c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 236c8ebae37SRussell King return; 237c8ebae37SRussell King } 238c8ebae37SRussell King 23958c7ccbfSPer Forlin /* initialize pre request cookie */ 24058c7ccbfSPer Forlin host->next_data.cookie = 1; 24158c7ccbfSPer Forlin 242c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 243c8ebae37SRussell King dma_cap_zero(mask); 244c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 245c8ebae37SRussell King 246c8ebae37SRussell King /* 247c8ebae37SRussell King * If only an RX channel is specified, the driver will 248c8ebae37SRussell King * attempt to use it bidirectionally, however if it is 249c8ebae37SRussell King * is specified but cannot be located, DMA will be disabled. 250c8ebae37SRussell King */ 251c8ebae37SRussell King if (plat->dma_rx_param) { 252c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 253c8ebae37SRussell King plat->dma_filter, 254c8ebae37SRussell King plat->dma_rx_param); 255c8ebae37SRussell King /* E.g if no DMA hardware is present */ 256c8ebae37SRussell King if (!host->dma_rx_channel) 257c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 258c8ebae37SRussell King } 259c8ebae37SRussell King 260c8ebae37SRussell King if (plat->dma_tx_param) { 261c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 262c8ebae37SRussell King plat->dma_filter, 263c8ebae37SRussell King plat->dma_tx_param); 264c8ebae37SRussell King if (!host->dma_tx_channel) 265c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 266c8ebae37SRussell King } else { 267c8ebae37SRussell King host->dma_tx_channel = host->dma_rx_channel; 268c8ebae37SRussell King } 269c8ebae37SRussell King 270c8ebae37SRussell King if (host->dma_rx_channel) 271c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 272c8ebae37SRussell King else 273c8ebae37SRussell King rxname = "none"; 274c8ebae37SRussell King 275c8ebae37SRussell King if (host->dma_tx_channel) 276c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 277c8ebae37SRussell King else 278c8ebae37SRussell King txname = "none"; 279c8ebae37SRussell King 280c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 281c8ebae37SRussell King rxname, txname); 282c8ebae37SRussell King 283c8ebae37SRussell King /* 284c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 285c8ebae37SRussell King * the parameters of the DMA engine device. 286c8ebae37SRussell King */ 287c8ebae37SRussell King if (host->dma_tx_channel) { 288c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 289c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 290c8ebae37SRussell King 291c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 292c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 293c8ebae37SRussell King } 294c8ebae37SRussell King if (host->dma_rx_channel) { 295c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 296c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 297c8ebae37SRussell King 298c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 299c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 300c8ebae37SRussell King } 301c8ebae37SRussell King } 302c8ebae37SRussell King 303c8ebae37SRussell King /* 304c8ebae37SRussell King * This is used in __devinit or __devexit so inline it 305c8ebae37SRussell King * so it can be discarded. 306c8ebae37SRussell King */ 307c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 308c8ebae37SRussell King { 309c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 310c8ebae37SRussell King 311c8ebae37SRussell King if (host->dma_rx_channel) 312c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 313c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 314c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 315c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 316c8ebae37SRussell King } 317c8ebae37SRussell King 318c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 319c8ebae37SRussell King { 320c8ebae37SRussell King struct dma_chan *chan = host->dma_current; 321c8ebae37SRussell King enum dma_data_direction dir; 322c8ebae37SRussell King u32 status; 323c8ebae37SRussell King int i; 324c8ebae37SRussell King 325c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 326c8ebae37SRussell King for (i = 0; ; i++) { 327c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 328c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 329c8ebae37SRussell King break; 330c8ebae37SRussell King udelay(10); 331c8ebae37SRussell King } 332c8ebae37SRussell King 333c8ebae37SRussell King /* 334c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 335c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 336c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 337c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 338c8ebae37SRussell King */ 339c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 340c8ebae37SRussell King dmaengine_terminate_all(chan); 341c8ebae37SRussell King if (!data->error) 342c8ebae37SRussell King data->error = -EIO; 343c8ebae37SRussell King } 344c8ebae37SRussell King 345c8ebae37SRussell King if (data->flags & MMC_DATA_WRITE) { 346c8ebae37SRussell King dir = DMA_TO_DEVICE; 347c8ebae37SRussell King } else { 348c8ebae37SRussell King dir = DMA_FROM_DEVICE; 349c8ebae37SRussell King } 350c8ebae37SRussell King 35158c7ccbfSPer Forlin if (!data->host_cookie) 352c8ebae37SRussell King dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 353c8ebae37SRussell King 354c8ebae37SRussell King /* 355c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 356c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 357c8ebae37SRussell King */ 358c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 359c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 360c8ebae37SRussell King mmci_dma_release(host); 361c8ebae37SRussell King } 362c8ebae37SRussell King } 363c8ebae37SRussell King 364c8ebae37SRussell King static void mmci_dma_data_error(struct mmci_host *host) 365c8ebae37SRussell King { 366c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 367c8ebae37SRussell King dmaengine_terminate_all(host->dma_current); 368c8ebae37SRussell King } 369c8ebae37SRussell King 37058c7ccbfSPer Forlin static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 37158c7ccbfSPer Forlin struct mmci_host_next *next) 372c8ebae37SRussell King { 373c8ebae37SRussell King struct variant_data *variant = host->variant; 374c8ebae37SRussell King struct dma_slave_config conf = { 375c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 376c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 377c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 378c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 379c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 380c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 381c8ebae37SRussell King }; 382c8ebae37SRussell King struct dma_chan *chan; 383c8ebae37SRussell King struct dma_device *device; 384c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 38505f5799cSVinod Koul enum dma_data_direction buffer_dirn; 386c8ebae37SRussell King int nr_sg; 387c8ebae37SRussell King 38858c7ccbfSPer Forlin /* Check if next job is already prepared */ 38958c7ccbfSPer Forlin if (data->host_cookie && !next && 39058c7ccbfSPer Forlin host->dma_current && host->dma_desc_current) 39158c7ccbfSPer Forlin return 0; 39258c7ccbfSPer Forlin 39358c7ccbfSPer Forlin if (!next) { 394c8ebae37SRussell King host->dma_current = NULL; 39558c7ccbfSPer Forlin host->dma_desc_current = NULL; 39658c7ccbfSPer Forlin } 397c8ebae37SRussell King 398c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 39905f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 40005f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 401c8ebae37SRussell King chan = host->dma_rx_channel; 402c8ebae37SRussell King } else { 40305f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 40405f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 405c8ebae37SRussell King chan = host->dma_tx_channel; 406c8ebae37SRussell King } 407c8ebae37SRussell King 408c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 409c8ebae37SRussell King if (!chan) 410c8ebae37SRussell King return -EINVAL; 411c8ebae37SRussell King 412c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 41358c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 414c8ebae37SRussell King return -EINVAL; 415c8ebae37SRussell King 416c8ebae37SRussell King device = chan->device; 41705f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 418c8ebae37SRussell King if (nr_sg == 0) 419c8ebae37SRussell King return -EINVAL; 420c8ebae37SRussell King 421c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 422c8ebae37SRussell King desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, 423c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 424c8ebae37SRussell King if (!desc) 425c8ebae37SRussell King goto unmap_exit; 426c8ebae37SRussell King 42758c7ccbfSPer Forlin if (next) { 42858c7ccbfSPer Forlin next->dma_chan = chan; 42958c7ccbfSPer Forlin next->dma_desc = desc; 43058c7ccbfSPer Forlin } else { 431c8ebae37SRussell King host->dma_current = chan; 43258c7ccbfSPer Forlin host->dma_desc_current = desc; 43358c7ccbfSPer Forlin } 434c8ebae37SRussell King 43558c7ccbfSPer Forlin return 0; 43658c7ccbfSPer Forlin 43758c7ccbfSPer Forlin unmap_exit: 43858c7ccbfSPer Forlin if (!next) 43958c7ccbfSPer Forlin dmaengine_terminate_all(chan); 44005f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 44158c7ccbfSPer Forlin return -ENOMEM; 44258c7ccbfSPer Forlin } 44358c7ccbfSPer Forlin 44458c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 44558c7ccbfSPer Forlin { 44658c7ccbfSPer Forlin int ret; 44758c7ccbfSPer Forlin struct mmc_data *data = host->data; 44858c7ccbfSPer Forlin 44958c7ccbfSPer Forlin ret = mmci_dma_prep_data(host, host->data, NULL); 45058c7ccbfSPer Forlin if (ret) 45158c7ccbfSPer Forlin return ret; 45258c7ccbfSPer Forlin 45358c7ccbfSPer Forlin /* Okay, go for it. */ 454c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 455c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 456c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 45758c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 45858c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 459c8ebae37SRussell King 460c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 461c8ebae37SRussell King 462c8ebae37SRussell King /* Trigger the DMA transfer */ 463c8ebae37SRussell King writel(datactrl, host->base + MMCIDATACTRL); 464c8ebae37SRussell King 465c8ebae37SRussell King /* 466c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 467c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 468c8ebae37SRussell King * call mmci_data_end() 469c8ebae37SRussell King */ 470c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 471c8ebae37SRussell King host->base + MMCIMASK0); 472c8ebae37SRussell King return 0; 473c8ebae37SRussell King } 47458c7ccbfSPer Forlin 47558c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 47658c7ccbfSPer Forlin { 47758c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 47858c7ccbfSPer Forlin 47958c7ccbfSPer Forlin if (data->host_cookie && data->host_cookie != next->cookie) { 480a3c76eb9SGirish K S pr_warning("[%s] invalid cookie: data->host_cookie %d" 48158c7ccbfSPer Forlin " host->next_data.cookie %d\n", 48258c7ccbfSPer Forlin __func__, data->host_cookie, host->next_data.cookie); 48358c7ccbfSPer Forlin data->host_cookie = 0; 48458c7ccbfSPer Forlin } 48558c7ccbfSPer Forlin 48658c7ccbfSPer Forlin if (!data->host_cookie) 48758c7ccbfSPer Forlin return; 48858c7ccbfSPer Forlin 48958c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 49058c7ccbfSPer Forlin host->dma_current = next->dma_chan; 49158c7ccbfSPer Forlin 49258c7ccbfSPer Forlin next->dma_desc = NULL; 49358c7ccbfSPer Forlin next->dma_chan = NULL; 49458c7ccbfSPer Forlin } 49558c7ccbfSPer Forlin 49658c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 49758c7ccbfSPer Forlin bool is_first_req) 49858c7ccbfSPer Forlin { 49958c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 50058c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 50158c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 50258c7ccbfSPer Forlin 50358c7ccbfSPer Forlin if (!data) 50458c7ccbfSPer Forlin return; 50558c7ccbfSPer Forlin 50658c7ccbfSPer Forlin if (data->host_cookie) { 50758c7ccbfSPer Forlin data->host_cookie = 0; 50858c7ccbfSPer Forlin return; 50958c7ccbfSPer Forlin } 51058c7ccbfSPer Forlin 51158c7ccbfSPer Forlin /* if config for dma */ 51258c7ccbfSPer Forlin if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 51358c7ccbfSPer Forlin ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 51458c7ccbfSPer Forlin if (mmci_dma_prep_data(host, data, nd)) 51558c7ccbfSPer Forlin data->host_cookie = 0; 51658c7ccbfSPer Forlin else 51758c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 51858c7ccbfSPer Forlin } 51958c7ccbfSPer Forlin } 52058c7ccbfSPer Forlin 52158c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 52258c7ccbfSPer Forlin int err) 52358c7ccbfSPer Forlin { 52458c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 52558c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 52658c7ccbfSPer Forlin struct dma_chan *chan; 52758c7ccbfSPer Forlin enum dma_data_direction dir; 52858c7ccbfSPer Forlin 52958c7ccbfSPer Forlin if (!data) 53058c7ccbfSPer Forlin return; 53158c7ccbfSPer Forlin 53258c7ccbfSPer Forlin if (data->flags & MMC_DATA_READ) { 53358c7ccbfSPer Forlin dir = DMA_FROM_DEVICE; 53458c7ccbfSPer Forlin chan = host->dma_rx_channel; 53558c7ccbfSPer Forlin } else { 53658c7ccbfSPer Forlin dir = DMA_TO_DEVICE; 53758c7ccbfSPer Forlin chan = host->dma_tx_channel; 53858c7ccbfSPer Forlin } 53958c7ccbfSPer Forlin 54058c7ccbfSPer Forlin 54158c7ccbfSPer Forlin /* if config for dma */ 54258c7ccbfSPer Forlin if (chan) { 54358c7ccbfSPer Forlin if (err) 54458c7ccbfSPer Forlin dmaengine_terminate_all(chan); 5458e3336b1SPer Forlin if (data->host_cookie) 54658c7ccbfSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 54758c7ccbfSPer Forlin data->sg_len, dir); 54858c7ccbfSPer Forlin mrq->data->host_cookie = 0; 54958c7ccbfSPer Forlin } 55058c7ccbfSPer Forlin } 55158c7ccbfSPer Forlin 552c8ebae37SRussell King #else 553c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 55458c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 55558c7ccbfSPer Forlin { 55658c7ccbfSPer Forlin } 557c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 558c8ebae37SRussell King { 559c8ebae37SRussell King } 560c8ebae37SRussell King 561c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 562c8ebae37SRussell King { 563c8ebae37SRussell King } 564c8ebae37SRussell King 565c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 566c8ebae37SRussell King { 567c8ebae37SRussell King } 568c8ebae37SRussell King 569c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 570c8ebae37SRussell King { 571c8ebae37SRussell King } 572c8ebae37SRussell King 573c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 574c8ebae37SRussell King { 575c8ebae37SRussell King return -ENOSYS; 576c8ebae37SRussell King } 57758c7ccbfSPer Forlin 57858c7ccbfSPer Forlin #define mmci_pre_request NULL 57958c7ccbfSPer Forlin #define mmci_post_request NULL 58058c7ccbfSPer Forlin 581c8ebae37SRussell King #endif 582c8ebae37SRussell King 5831c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 5841c6a0718SPierre Ossman { 5858301bb68SRabin Vincent struct variant_data *variant = host->variant; 5861c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 5871c6a0718SPierre Ossman unsigned long long clks; 5881c6a0718SPierre Ossman void __iomem *base; 5891c6a0718SPierre Ossman int blksz_bits; 5901c6a0718SPierre Ossman 59164de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 5921c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 5931c6a0718SPierre Ossman 5941c6a0718SPierre Ossman host->data = data; 595528320dbSRabin Vincent host->size = data->blksz * data->blocks; 59651d4375dSRussell King data->bytes_xfered = 0; 5971c6a0718SPierre Ossman 5981c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 5991c6a0718SPierre Ossman do_div(clks, 1000000000UL); 6001c6a0718SPierre Ossman 6011c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 6021c6a0718SPierre Ossman 6031c6a0718SPierre Ossman base = host->base; 6041c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 6051c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 6061c6a0718SPierre Ossman 6071c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 6081c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 6091c6a0718SPierre Ossman 6101784b157SPhilippe Langlais if (variant->blksz_datactrl16) 6111784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 6121784b157SPhilippe Langlais else 6131c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 614c8ebae37SRussell King 615c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 6161c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 617c8ebae37SRussell King 618c8ebae37SRussell King /* 619c8ebae37SRussell King * Attempt to use DMA operation mode, if this 620c8ebae37SRussell King * should fail, fall back to PIO mode 621c8ebae37SRussell King */ 622c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 623c8ebae37SRussell King return; 624c8ebae37SRussell King 625c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 626c8ebae37SRussell King mmci_init_sg(host, data); 627c8ebae37SRussell King 628c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 6291c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 6301c6a0718SPierre Ossman 6311c6a0718SPierre Ossman /* 632c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 633c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 634c4d877c1SRussell King * is available. 6351c6a0718SPierre Ossman */ 636c4d877c1SRussell King if (host->size < variant->fifohalfsize) 6371c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 6381c6a0718SPierre Ossman } else { 6391c6a0718SPierre Ossman /* 6401c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 6411c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 6421c6a0718SPierre Ossman */ 6431c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 6441c6a0718SPierre Ossman } 6451c6a0718SPierre Ossman 64634177802SLinus Walleij /* The ST Micro variants has a special bit to enable SDIO */ 64734177802SLinus Walleij if (variant->sdio && host->mmc->card) 64834177802SLinus Walleij if (mmc_card_sdio(host->mmc->card)) 64934177802SLinus Walleij datactrl |= MCI_ST_DPSM_SDIOEN; 65034177802SLinus Walleij 6511c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 6521c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 6532686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 6541c6a0718SPierre Ossman } 6551c6a0718SPierre Ossman 6561c6a0718SPierre Ossman static void 6571c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 6581c6a0718SPierre Ossman { 6591c6a0718SPierre Ossman void __iomem *base = host->base; 6601c6a0718SPierre Ossman 66164de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 6621c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 6631c6a0718SPierre Ossman 6641c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 6651c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 6661c6a0718SPierre Ossman udelay(1); 6671c6a0718SPierre Ossman } 6681c6a0718SPierre Ossman 6691c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 6701c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 6711c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 6721c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 6731c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 6741c6a0718SPierre Ossman } 6751c6a0718SPierre Ossman if (/*interrupt*/0) 6761c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 6771c6a0718SPierre Ossman 6781c6a0718SPierre Ossman host->cmd = cmd; 6791c6a0718SPierre Ossman 6801c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 6811c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 6821c6a0718SPierre Ossman } 6831c6a0718SPierre Ossman 6841c6a0718SPierre Ossman static void 6851c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 6861c6a0718SPierre Ossman unsigned int status) 6871c6a0718SPierre Ossman { 688f20f8f21SLinus Walleij /* First check for errors */ 689b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 690b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 6918cb28155SLinus Walleij u32 remain, success; 692f20f8f21SLinus Walleij 693c8ebae37SRussell King /* Terminate the DMA transfer */ 694c8ebae37SRussell King if (dma_inprogress(host)) 695c8ebae37SRussell King mmci_dma_data_error(host); 696c8ebae37SRussell King 697c8afc9d5SRussell King /* 698c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 699c8afc9d5SRussell King * the data counter gives the number of bytes transferred 700c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 701c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 702c8afc9d5SRussell King * matters for FIFO overruns only. 703c8afc9d5SRussell King */ 704f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 7058cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 7068cb28155SLinus Walleij 707c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 708c8afc9d5SRussell King status, success); 7098cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 7108cb28155SLinus Walleij /* Last block was not successful */ 711c8afc9d5SRussell King success -= 1; 71217b0429dSPierre Ossman data->error = -EILSEQ; 7138cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 71417b0429dSPierre Ossman data->error = -ETIMEDOUT; 715757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 716757df746SLinus Walleij data->error = -ECOMM; 717c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 71817b0429dSPierre Ossman data->error = -EIO; 719c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 720c8afc9d5SRussell King if (success > host->variant->fifosize) 721c8afc9d5SRussell King success -= host->variant->fifosize; 722c8afc9d5SRussell King else 723c8afc9d5SRussell King success = 0; 7248cb28155SLinus Walleij data->error = -EIO; 7254ce1d6cbSRabin Vincent } 72651d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 7271c6a0718SPierre Ossman } 728f20f8f21SLinus Walleij 7298cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 7308cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 731f20f8f21SLinus Walleij 732ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 733c8ebae37SRussell King if (dma_inprogress(host)) 734c8ebae37SRussell King mmci_dma_unmap(host, data); 7351c6a0718SPierre Ossman mmci_stop_data(host); 7361c6a0718SPierre Ossman 7378cb28155SLinus Walleij if (!data->error) 7388cb28155SLinus Walleij /* The error clause is handled above, success! */ 73951d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 740f20f8f21SLinus Walleij 7411c6a0718SPierre Ossman if (!data->stop) { 7421c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 7431c6a0718SPierre Ossman } else { 7441c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 7451c6a0718SPierre Ossman } 7461c6a0718SPierre Ossman } 7471c6a0718SPierre Ossman } 7481c6a0718SPierre Ossman 7491c6a0718SPierre Ossman static void 7501c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 7511c6a0718SPierre Ossman unsigned int status) 7521c6a0718SPierre Ossman { 7531c6a0718SPierre Ossman void __iomem *base = host->base; 7541c6a0718SPierre Ossman 7551c6a0718SPierre Ossman host->cmd = NULL; 7561c6a0718SPierre Ossman 7571c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 75817b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 7591c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 76017b0429dSPierre Ossman cmd->error = -EILSEQ; 7619047b435SRussell King - ARM Linux } else { 7629047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 7639047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 7649047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 7659047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 7661c6a0718SPierre Ossman } 7671c6a0718SPierre Ossman 76817b0429dSPierre Ossman if (!cmd->data || cmd->error) { 7693b6e3c73SUlf Hansson if (host->data) { 7703b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 7713b6e3c73SUlf Hansson if (dma_inprogress(host)) 7723b6e3c73SUlf Hansson mmci_dma_data_error(host); 7731c6a0718SPierre Ossman mmci_stop_data(host); 7743b6e3c73SUlf Hansson } 7751c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 7761c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 7771c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 7781c6a0718SPierre Ossman } 7791c6a0718SPierre Ossman } 7801c6a0718SPierre Ossman 7811c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 7821c6a0718SPierre Ossman { 7831c6a0718SPierre Ossman void __iomem *base = host->base; 7841c6a0718SPierre Ossman char *ptr = buffer; 7851c6a0718SPierre Ossman u32 status; 78626eed9a5SLinus Walleij int host_remain = host->size; 7871c6a0718SPierre Ossman 7881c6a0718SPierre Ossman do { 78926eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 7901c6a0718SPierre Ossman 7911c6a0718SPierre Ossman if (count > remain) 7921c6a0718SPierre Ossman count = remain; 7931c6a0718SPierre Ossman 7941c6a0718SPierre Ossman if (count <= 0) 7951c6a0718SPierre Ossman break; 7961c6a0718SPierre Ossman 7971c6a0718SPierre Ossman readsl(base + MMCIFIFO, ptr, count >> 2); 7981c6a0718SPierre Ossman 7991c6a0718SPierre Ossman ptr += count; 8001c6a0718SPierre Ossman remain -= count; 80126eed9a5SLinus Walleij host_remain -= count; 8021c6a0718SPierre Ossman 8031c6a0718SPierre Ossman if (remain == 0) 8041c6a0718SPierre Ossman break; 8051c6a0718SPierre Ossman 8061c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8071c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 8081c6a0718SPierre Ossman 8091c6a0718SPierre Ossman return ptr - buffer; 8101c6a0718SPierre Ossman } 8111c6a0718SPierre Ossman 8121c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 8131c6a0718SPierre Ossman { 8148301bb68SRabin Vincent struct variant_data *variant = host->variant; 8151c6a0718SPierre Ossman void __iomem *base = host->base; 8161c6a0718SPierre Ossman char *ptr = buffer; 8171c6a0718SPierre Ossman 8181c6a0718SPierre Ossman do { 8191c6a0718SPierre Ossman unsigned int count, maxcnt; 8201c6a0718SPierre Ossman 8218301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 8228301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 8231c6a0718SPierre Ossman count = min(remain, maxcnt); 8241c6a0718SPierre Ossman 82534177802SLinus Walleij /* 82634177802SLinus Walleij * The ST Micro variant for SDIO transfer sizes 82734177802SLinus Walleij * less then 8 bytes should have clock H/W flow 82834177802SLinus Walleij * control disabled. 82934177802SLinus Walleij */ 83034177802SLinus Walleij if (variant->sdio && 83134177802SLinus Walleij mmc_card_sdio(host->mmc->card)) { 83234177802SLinus Walleij if (count < 8) 83334177802SLinus Walleij writel(readl(host->base + MMCICLOCK) & 83434177802SLinus Walleij ~variant->clkreg_enable, 83534177802SLinus Walleij host->base + MMCICLOCK); 83634177802SLinus Walleij else 83734177802SLinus Walleij writel(readl(host->base + MMCICLOCK) | 83834177802SLinus Walleij variant->clkreg_enable, 83934177802SLinus Walleij host->base + MMCICLOCK); 84034177802SLinus Walleij } 84134177802SLinus Walleij 84234177802SLinus Walleij /* 84334177802SLinus Walleij * SDIO especially may want to send something that is 84434177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 84534177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 84634177802SLinus Walleij * So compensate by adding +3 on the count, a single 84734177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 84834177802SLinus Walleij * 32bit writes etc. 84934177802SLinus Walleij */ 85034177802SLinus Walleij writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 8511c6a0718SPierre Ossman 8521c6a0718SPierre Ossman ptr += count; 8531c6a0718SPierre Ossman remain -= count; 8541c6a0718SPierre Ossman 8551c6a0718SPierre Ossman if (remain == 0) 8561c6a0718SPierre Ossman break; 8571c6a0718SPierre Ossman 8581c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8591c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 8601c6a0718SPierre Ossman 8611c6a0718SPierre Ossman return ptr - buffer; 8621c6a0718SPierre Ossman } 8631c6a0718SPierre Ossman 8641c6a0718SPierre Ossman /* 8651c6a0718SPierre Ossman * PIO data transfer IRQ handler. 8661c6a0718SPierre Ossman */ 8671c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 8681c6a0718SPierre Ossman { 8691c6a0718SPierre Ossman struct mmci_host *host = dev_id; 8704ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 8718301bb68SRabin Vincent struct variant_data *variant = host->variant; 8721c6a0718SPierre Ossman void __iomem *base = host->base; 8734ce1d6cbSRabin Vincent unsigned long flags; 8741c6a0718SPierre Ossman u32 status; 8751c6a0718SPierre Ossman 8761c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8771c6a0718SPierre Ossman 87864de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 8791c6a0718SPierre Ossman 8804ce1d6cbSRabin Vincent local_irq_save(flags); 8814ce1d6cbSRabin Vincent 8821c6a0718SPierre Ossman do { 8831c6a0718SPierre Ossman unsigned int remain, len; 8841c6a0718SPierre Ossman char *buffer; 8851c6a0718SPierre Ossman 8861c6a0718SPierre Ossman /* 8871c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 8881c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 8891c6a0718SPierre Ossman * definition it is more than half empty. 8901c6a0718SPierre Ossman * 8911c6a0718SPierre Ossman * For read, check for data available. 8921c6a0718SPierre Ossman */ 8931c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 8941c6a0718SPierre Ossman break; 8951c6a0718SPierre Ossman 8964ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 8974ce1d6cbSRabin Vincent break; 8984ce1d6cbSRabin Vincent 8994ce1d6cbSRabin Vincent buffer = sg_miter->addr; 9004ce1d6cbSRabin Vincent remain = sg_miter->length; 9011c6a0718SPierre Ossman 9021c6a0718SPierre Ossman len = 0; 9031c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 9041c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 9051c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 9061c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 9071c6a0718SPierre Ossman 9084ce1d6cbSRabin Vincent sg_miter->consumed = len; 9091c6a0718SPierre Ossman 9101c6a0718SPierre Ossman host->size -= len; 9111c6a0718SPierre Ossman remain -= len; 9121c6a0718SPierre Ossman 9131c6a0718SPierre Ossman if (remain) 9141c6a0718SPierre Ossman break; 9151c6a0718SPierre Ossman 9161c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9171c6a0718SPierre Ossman } while (1); 9181c6a0718SPierre Ossman 9194ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 9204ce1d6cbSRabin Vincent 9214ce1d6cbSRabin Vincent local_irq_restore(flags); 9224ce1d6cbSRabin Vincent 9231c6a0718SPierre Ossman /* 924c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 925c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 9261c6a0718SPierre Ossman */ 927c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 9282686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 9291c6a0718SPierre Ossman 9301c6a0718SPierre Ossman /* 9311c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 9321c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 9331c6a0718SPierre Ossman * the chip itself has disabled the data path, and 9341c6a0718SPierre Ossman * stops us racing with our data end IRQ. 9351c6a0718SPierre Ossman */ 9361c6a0718SPierre Ossman if (host->size == 0) { 9372686b4b4SLinus Walleij mmci_set_mask1(host, 0); 9381c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 9391c6a0718SPierre Ossman } 9401c6a0718SPierre Ossman 9411c6a0718SPierre Ossman return IRQ_HANDLED; 9421c6a0718SPierre Ossman } 9431c6a0718SPierre Ossman 9441c6a0718SPierre Ossman /* 9451c6a0718SPierre Ossman * Handle completion of command and data transfers. 9461c6a0718SPierre Ossman */ 9471c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 9481c6a0718SPierre Ossman { 9491c6a0718SPierre Ossman struct mmci_host *host = dev_id; 9501c6a0718SPierre Ossman u32 status; 9511c6a0718SPierre Ossman int ret = 0; 9521c6a0718SPierre Ossman 9531c6a0718SPierre Ossman spin_lock(&host->lock); 9541c6a0718SPierre Ossman 9551c6a0718SPierre Ossman do { 9561c6a0718SPierre Ossman struct mmc_command *cmd; 9571c6a0718SPierre Ossman struct mmc_data *data; 9581c6a0718SPierre Ossman 9591c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 9602686b4b4SLinus Walleij 9612686b4b4SLinus Walleij if (host->singleirq) { 9622686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 9632686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 9642686b4b4SLinus Walleij 9652686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 9662686b4b4SLinus Walleij } 9672686b4b4SLinus Walleij 9681c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 9691c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 9701c6a0718SPierre Ossman 97164de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 9721c6a0718SPierre Ossman 9731c6a0718SPierre Ossman data = host->data; 974b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 975b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 976b63038d6SUlf Hansson MCI_DATABLOCKEND) && data) 9771c6a0718SPierre Ossman mmci_data_irq(host, data, status); 9781c6a0718SPierre Ossman 9791c6a0718SPierre Ossman cmd = host->cmd; 9801c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 9811c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 9821c6a0718SPierre Ossman 9831c6a0718SPierre Ossman ret = 1; 9841c6a0718SPierre Ossman } while (status); 9851c6a0718SPierre Ossman 9861c6a0718SPierre Ossman spin_unlock(&host->lock); 9871c6a0718SPierre Ossman 9881c6a0718SPierre Ossman return IRQ_RETVAL(ret); 9891c6a0718SPierre Ossman } 9901c6a0718SPierre Ossman 9911c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 9921c6a0718SPierre Ossman { 9931c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 9949e943021SLinus Walleij unsigned long flags; 9951c6a0718SPierre Ossman 9961c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 9971c6a0718SPierre Ossman 998019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 99964de0289SLinus Walleij dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 100064de0289SLinus Walleij mrq->data->blksz); 1001255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 1002255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1003255d01afSPierre Ossman return; 1004255d01afSPierre Ossman } 1005255d01afSPierre Ossman 10061c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 10071c3be369SRussell King 10089e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 10091c6a0718SPierre Ossman 10101c6a0718SPierre Ossman host->mrq = mrq; 10111c6a0718SPierre Ossman 101258c7ccbfSPer Forlin if (mrq->data) 101358c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 101458c7ccbfSPer Forlin 10151c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 10161c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 10171c6a0718SPierre Ossman 10181c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 10191c6a0718SPierre Ossman 10209e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 10211c6a0718SPierre Ossman } 10221c6a0718SPierre Ossman 10231c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 10241c6a0718SPierre Ossman { 10251c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10267d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1027a6a6464aSLinus Walleij u32 pwr = 0; 1028a6a6464aSLinus Walleij unsigned long flags; 102999fc5131SLinus Walleij int ret; 10301c6a0718SPierre Ossman 10312cd976c4SUlf Hansson pm_runtime_get_sync(mmc_dev(mmc)); 10322cd976c4SUlf Hansson 1033bc521818SUlf Hansson if (host->plat->ios_handler && 1034bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1035bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1036bc521818SUlf Hansson 10371c6a0718SPierre Ossman switch (ios->power_mode) { 10381c6a0718SPierre Ossman case MMC_POWER_OFF: 103999fc5131SLinus Walleij if (host->vcc) 104099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 10411c6a0718SPierre Ossman break; 10421c6a0718SPierre Ossman case MMC_POWER_UP: 104399fc5131SLinus Walleij if (host->vcc) { 104499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 104599fc5131SLinus Walleij if (ret) { 104699fc5131SLinus Walleij dev_err(mmc_dev(mmc), "unable to set OCR\n"); 104799fc5131SLinus Walleij /* 104899fc5131SLinus Walleij * The .set_ios() function in the mmc_host_ops 104999fc5131SLinus Walleij * struct return void, and failing to set the 105099fc5131SLinus Walleij * power should be rare so we print an error 105199fc5131SLinus Walleij * and return here. 105299fc5131SLinus Walleij */ 10532cd976c4SUlf Hansson goto out; 105499fc5131SLinus Walleij } 105599fc5131SLinus Walleij } 10567d72a1d4SUlf Hansson /* 10577d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 10587d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 10597d72a1d4SUlf Hansson * configured in the variant data. 10607d72a1d4SUlf Hansson */ 10617d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 10627d72a1d4SUlf Hansson 10631c6a0718SPierre Ossman break; 10641c6a0718SPierre Ossman case MMC_POWER_ON: 10651c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 10661c6a0718SPierre Ossman break; 10671c6a0718SPierre Ossman } 10681c6a0718SPierre Ossman 10694d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 10704d1a3a0dSUlf Hansson /* 10714d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 10724d1a3a0dSUlf Hansson * indicating signal direction for the signals in 10734d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 10744d1a3a0dSUlf Hansson */ 10754d1a3a0dSUlf Hansson pwr |= host->plat->sigdir; 10764d1a3a0dSUlf Hansson 10774d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 10784d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 10794d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 10804d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 10814d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 10824d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 10834d1a3a0dSUlf Hansson } 10844d1a3a0dSUlf Hansson 1085cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1086f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 10871c6a0718SPierre Ossman pwr |= MCI_ROD; 1088cc30d60eSLinus Walleij else { 1089cc30d60eSLinus Walleij /* 1090cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1091cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1092cc30d60eSLinus Walleij */ 1093cc30d60eSLinus Walleij pwr |= MCI_OD; 1094cc30d60eSLinus Walleij } 1095cc30d60eSLinus Walleij } 10961c6a0718SPierre Ossman 1097a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1098a6a6464aSLinus Walleij 1099a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 11001c6a0718SPierre Ossman 11011c6a0718SPierre Ossman if (host->pwr != pwr) { 11021c6a0718SPierre Ossman host->pwr = pwr; 11031c6a0718SPierre Ossman writel(pwr, host->base + MMCIPOWER); 11041c6a0718SPierre Ossman } 1105a6a6464aSLinus Walleij 1106a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 11072cd976c4SUlf Hansson 11082cd976c4SUlf Hansson out: 11092cd976c4SUlf Hansson pm_runtime_mark_last_busy(mmc_dev(mmc)); 11102cd976c4SUlf Hansson pm_runtime_put_autosuspend(mmc_dev(mmc)); 11111c6a0718SPierre Ossman } 11121c6a0718SPierre Ossman 111389001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 111489001446SRussell King { 111589001446SRussell King struct mmci_host *host = mmc_priv(mmc); 111689001446SRussell King 111789001446SRussell King if (host->gpio_wp == -ENOSYS) 111889001446SRussell King return -ENOSYS; 111989001446SRussell King 112018a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 112189001446SRussell King } 112289001446SRussell King 112389001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 112489001446SRussell King { 112589001446SRussell King struct mmci_host *host = mmc_priv(mmc); 112629719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 112789001446SRussell King unsigned int status; 112889001446SRussell King 11294b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 11304b8caec0SRabin Vincent if (!plat->status) 11314b8caec0SRabin Vincent return 1; /* Assume always present */ 11324b8caec0SRabin Vincent 113329719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 11344b8caec0SRabin Vincent } else 113518a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 113618a06301SLinus Walleij ^ plat->cd_invert; 113789001446SRussell King 113874bc8093SRussell King /* 113974bc8093SRussell King * Use positive logic throughout - status is zero for no card, 114074bc8093SRussell King * non-zero for card inserted. 114174bc8093SRussell King */ 114274bc8093SRussell King return status; 114389001446SRussell King } 114489001446SRussell King 1145148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1146148b8b39SRabin Vincent { 1147148b8b39SRabin Vincent struct mmci_host *host = dev_id; 1148148b8b39SRabin Vincent 1149148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1150148b8b39SRabin Vincent 1151148b8b39SRabin Vincent return IRQ_HANDLED; 1152148b8b39SRabin Vincent } 1153148b8b39SRabin Vincent 11541c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 11551c6a0718SPierre Ossman .request = mmci_request, 115658c7ccbfSPer Forlin .pre_req = mmci_pre_request, 115758c7ccbfSPer Forlin .post_req = mmci_post_request, 11581c6a0718SPierre Ossman .set_ios = mmci_set_ios, 115989001446SRussell King .get_ro = mmci_get_ro, 116089001446SRussell King .get_cd = mmci_get_cd, 11611c6a0718SPierre Ossman }; 11621c6a0718SPierre Ossman 1163aa25afadSRussell King static int __devinit mmci_probe(struct amba_device *dev, 1164aa25afadSRussell King const struct amba_id *id) 11651c6a0718SPierre Ossman { 11666ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 11674956e109SRabin Vincent struct variant_data *variant = id->data; 11681c6a0718SPierre Ossman struct mmci_host *host; 11691c6a0718SPierre Ossman struct mmc_host *mmc; 11701c6a0718SPierre Ossman int ret; 11711c6a0718SPierre Ossman 11721c6a0718SPierre Ossman /* must have platform data */ 11731c6a0718SPierre Ossman if (!plat) { 11741c6a0718SPierre Ossman ret = -EINVAL; 11751c6a0718SPierre Ossman goto out; 11761c6a0718SPierre Ossman } 11771c6a0718SPierre Ossman 11781c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 11791c6a0718SPierre Ossman if (ret) 11801c6a0718SPierre Ossman goto out; 11811c6a0718SPierre Ossman 11821c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 11831c6a0718SPierre Ossman if (!mmc) { 11841c6a0718SPierre Ossman ret = -ENOMEM; 11851c6a0718SPierre Ossman goto rel_regions; 11861c6a0718SPierre Ossman } 11871c6a0718SPierre Ossman 11881c6a0718SPierre Ossman host = mmc_priv(mmc); 11894ea580f1SRabin Vincent host->mmc = mmc; 1190012b7d33SRussell King 119189001446SRussell King host->gpio_wp = -ENOSYS; 119289001446SRussell King host->gpio_cd = -ENOSYS; 1193148b8b39SRabin Vincent host->gpio_cd_irq = -1; 119489001446SRussell King 1195012b7d33SRussell King host->hw_designer = amba_manf(dev); 1196012b7d33SRussell King host->hw_revision = amba_rev(dev); 119764de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 119864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1199012b7d33SRussell King 1200ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 12011c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 12021c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 12031c6a0718SPierre Ossman host->clk = NULL; 12041c6a0718SPierre Ossman goto host_free; 12051c6a0718SPierre Ossman } 12061c6a0718SPierre Ossman 120752ca0f3aSRussell King ret = clk_prepare(host->clk); 12081c6a0718SPierre Ossman if (ret) 12091c6a0718SPierre Ossman goto clk_free; 12101c6a0718SPierre Ossman 121152ca0f3aSRussell King ret = clk_enable(host->clk); 121252ca0f3aSRussell King if (ret) 121352ca0f3aSRussell King goto clk_unprep; 121452ca0f3aSRussell King 12151c6a0718SPierre Ossman host->plat = plat; 12164956e109SRabin Vincent host->variant = variant; 12171c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1218c8df9a53SLinus Walleij /* 1219c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1220c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1221c8df9a53SLinus Walleij * (if possible). 1222c8df9a53SLinus Walleij */ 1223c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1224c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1225c8df9a53SLinus Walleij if (ret < 0) 1226c8df9a53SLinus Walleij goto clk_disable; 1227c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 122864de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 122964de0289SLinus Walleij host->mclk); 1230c8df9a53SLinus Walleij } 1231c8ebae37SRussell King host->phybase = dev->res.start; 1232dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 12331c6a0718SPierre Ossman if (!host->base) { 12341c6a0718SPierre Ossman ret = -ENOMEM; 12351c6a0718SPierre Ossman goto clk_disable; 12361c6a0718SPierre Ossman } 12371c6a0718SPierre Ossman 12381c6a0718SPierre Ossman mmc->ops = &mmci_ops; 12397f294e49SLinus Walleij /* 12407f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 12417f294e49SLinus Walleij * clock divider equations which means that the minimum divider 12427f294e49SLinus Walleij * differs too. 12437f294e49SLinus Walleij */ 12447f294e49SLinus Walleij if (variant->st_clkdiv) 12457f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 12467f294e49SLinus Walleij else 12477f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1248808d97ccSLinus Walleij /* 1249808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1250808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1251808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1252808d97ccSLinus Walleij * default value in case it is not specified. Either 1253808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1254808d97ccSLinus Walleij * of course. 1255808d97ccSLinus Walleij */ 1256808d97ccSLinus Walleij if (plat->f_max) 1257808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1258808d97ccSLinus Walleij else 12591c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 126064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 126164de0289SLinus Walleij 126234e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 126334e84f39SLinus Walleij /* If we're using the regulator framework, try to fetch a regulator */ 126434e84f39SLinus Walleij host->vcc = regulator_get(&dev->dev, "vmmc"); 126534e84f39SLinus Walleij if (IS_ERR(host->vcc)) 126634e84f39SLinus Walleij host->vcc = NULL; 126734e84f39SLinus Walleij else { 126834e84f39SLinus Walleij int mask = mmc_regulator_get_ocrmask(host->vcc); 126934e84f39SLinus Walleij 127034e84f39SLinus Walleij if (mask < 0) 127134e84f39SLinus Walleij dev_err(&dev->dev, "error getting OCR mask (%d)\n", 127234e84f39SLinus Walleij mask); 127334e84f39SLinus Walleij else { 127434e84f39SLinus Walleij host->mmc->ocr_avail = (u32) mask; 127534e84f39SLinus Walleij if (plat->ocr_mask) 127634e84f39SLinus Walleij dev_warn(&dev->dev, 127734e84f39SLinus Walleij "Provided ocr_mask/setpower will not be used " 127834e84f39SLinus Walleij "(using regulator instead)\n"); 127934e84f39SLinus Walleij } 128034e84f39SLinus Walleij } 128134e84f39SLinus Walleij #endif 128234e84f39SLinus Walleij /* Fall back to platform data if no regulator is found */ 128334e84f39SLinus Walleij if (host->vcc == NULL) 12841c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 12859e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 12865a092627SPer Forlin mmc->caps2 = plat->capabilities2; 12871c6a0718SPierre Ossman 12881c6a0718SPierre Ossman /* 12891c6a0718SPierre Ossman * We can do SGIO 12901c6a0718SPierre Ossman */ 1291a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 12921c6a0718SPierre Ossman 12931c6a0718SPierre Ossman /* 129408458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 129508458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 129608458ef6SRabin Vincent * single request. 12971c6a0718SPierre Ossman */ 129808458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 12991c6a0718SPierre Ossman 13001c6a0718SPierre Ossman /* 13011c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 13021c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 13031c6a0718SPierre Ossman */ 13041c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 13051c6a0718SPierre Ossman 13061c6a0718SPierre Ossman /* 13071c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 13081c6a0718SPierre Ossman */ 13091c6a0718SPierre Ossman mmc->max_blk_size = 2048; 13101c6a0718SPierre Ossman 13111c6a0718SPierre Ossman /* 13121c6a0718SPierre Ossman * No limit on the number of blocks transferred. 13131c6a0718SPierre Ossman */ 13141c6a0718SPierre Ossman mmc->max_blk_count = mmc->max_req_size; 13151c6a0718SPierre Ossman 13161c6a0718SPierre Ossman spin_lock_init(&host->lock); 13171c6a0718SPierre Ossman 13181c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 13191c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 13201c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 13211c6a0718SPierre Ossman 132289001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 132389001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 132489001446SRussell King if (ret == 0) 132589001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 132689001446SRussell King if (ret == 0) 132789001446SRussell King host->gpio_cd = plat->gpio_cd; 132889001446SRussell King else if (ret != -ENOSYS) 132989001446SRussell King goto err_gpio_cd; 1330148b8b39SRabin Vincent 133117ee083bSLinus Walleij /* 133217ee083bSLinus Walleij * A gpio pin that will detect cards when inserted and removed 133317ee083bSLinus Walleij * will most likely want to trigger on the edges if it is 133417ee083bSLinus Walleij * 0 when ejected and 1 when inserted (or mutatis mutandis 133517ee083bSLinus Walleij * for the inverted case) so we request triggers on both 133617ee083bSLinus Walleij * edges. 133717ee083bSLinus Walleij */ 1338148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 133917ee083bSLinus Walleij mmci_cd_irq, 134017ee083bSLinus Walleij IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1341148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1342148b8b39SRabin Vincent if (ret >= 0) 1343148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 134489001446SRussell King } 134589001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 134689001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 134789001446SRussell King if (ret == 0) 134889001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 134989001446SRussell King if (ret == 0) 135089001446SRussell King host->gpio_wp = plat->gpio_wp; 135189001446SRussell King else if (ret != -ENOSYS) 135289001446SRussell King goto err_gpio_wp; 135389001446SRussell King } 135489001446SRussell King 13554b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 13564b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1357148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1358148b8b39SRabin Vincent 13591c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 13601c6a0718SPierre Ossman if (ret) 13611c6a0718SPierre Ossman goto unmap; 13621c6a0718SPierre Ossman 13632686b4b4SLinus Walleij if (dev->irq[1] == NO_IRQ) 13642686b4b4SLinus Walleij host->singleirq = true; 13652686b4b4SLinus Walleij else { 13662686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 13672686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 13681c6a0718SPierre Ossman if (ret) 13691c6a0718SPierre Ossman goto irq0_free; 13702686b4b4SLinus Walleij } 13711c6a0718SPierre Ossman 13728cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 13731c6a0718SPierre Ossman 13741c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 13751c6a0718SPierre Ossman 1376c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1377c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1378c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1379c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1380c8ebae37SRussell King 1381c8ebae37SRussell King mmci_dma_setup(host); 13821c6a0718SPierre Ossman 13832cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 13842cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 13851c3be369SRussell King pm_runtime_put(&dev->dev); 13861c3be369SRussell King 13878c11a94dSRussell King mmc_add_host(mmc); 13888c11a94dSRussell King 13891c6a0718SPierre Ossman return 0; 13901c6a0718SPierre Ossman 13911c6a0718SPierre Ossman irq0_free: 13921c6a0718SPierre Ossman free_irq(dev->irq[0], host); 13931c6a0718SPierre Ossman unmap: 139489001446SRussell King if (host->gpio_wp != -ENOSYS) 139589001446SRussell King gpio_free(host->gpio_wp); 139689001446SRussell King err_gpio_wp: 1397148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1398148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 139989001446SRussell King if (host->gpio_cd != -ENOSYS) 140089001446SRussell King gpio_free(host->gpio_cd); 140189001446SRussell King err_gpio_cd: 14021c6a0718SPierre Ossman iounmap(host->base); 14031c6a0718SPierre Ossman clk_disable: 14041c6a0718SPierre Ossman clk_disable(host->clk); 140552ca0f3aSRussell King clk_unprep: 140652ca0f3aSRussell King clk_unprepare(host->clk); 14071c6a0718SPierre Ossman clk_free: 14081c6a0718SPierre Ossman clk_put(host->clk); 14091c6a0718SPierre Ossman host_free: 14101c6a0718SPierre Ossman mmc_free_host(mmc); 14111c6a0718SPierre Ossman rel_regions: 14121c6a0718SPierre Ossman amba_release_regions(dev); 14131c6a0718SPierre Ossman out: 14141c6a0718SPierre Ossman return ret; 14151c6a0718SPierre Ossman } 14161c6a0718SPierre Ossman 14176dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 14181c6a0718SPierre Ossman { 14191c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 14201c6a0718SPierre Ossman 14211c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 14221c6a0718SPierre Ossman 14231c6a0718SPierre Ossman if (mmc) { 14241c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 14251c6a0718SPierre Ossman 14261c3be369SRussell King /* 14271c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 14281c3be369SRussell King * version here so that we can access the primecell. 14291c3be369SRussell King */ 14301c3be369SRussell King pm_runtime_get_sync(&dev->dev); 14311c3be369SRussell King 14321c6a0718SPierre Ossman mmc_remove_host(mmc); 14331c6a0718SPierre Ossman 14341c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14351c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 14361c6a0718SPierre Ossman 14371c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 14381c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 14391c6a0718SPierre Ossman 1440c8ebae37SRussell King mmci_dma_release(host); 14411c6a0718SPierre Ossman free_irq(dev->irq[0], host); 14422686b4b4SLinus Walleij if (!host->singleirq) 14431c6a0718SPierre Ossman free_irq(dev->irq[1], host); 14441c6a0718SPierre Ossman 144589001446SRussell King if (host->gpio_wp != -ENOSYS) 144689001446SRussell King gpio_free(host->gpio_wp); 1447148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1448148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 144989001446SRussell King if (host->gpio_cd != -ENOSYS) 145089001446SRussell King gpio_free(host->gpio_cd); 145189001446SRussell King 14521c6a0718SPierre Ossman iounmap(host->base); 14531c6a0718SPierre Ossman clk_disable(host->clk); 145452ca0f3aSRussell King clk_unprepare(host->clk); 14551c6a0718SPierre Ossman clk_put(host->clk); 14561c6a0718SPierre Ossman 145799fc5131SLinus Walleij if (host->vcc) 145899fc5131SLinus Walleij mmc_regulator_set_ocr(mmc, host->vcc, 0); 145934e84f39SLinus Walleij regulator_put(host->vcc); 146034e84f39SLinus Walleij 14611c6a0718SPierre Ossman mmc_free_host(mmc); 14621c6a0718SPierre Ossman 14631c6a0718SPierre Ossman amba_release_regions(dev); 14641c6a0718SPierre Ossman } 14651c6a0718SPierre Ossman 14661c6a0718SPierre Ossman return 0; 14671c6a0718SPierre Ossman } 14681c6a0718SPierre Ossman 146948fa7003SUlf Hansson #ifdef CONFIG_SUSPEND 147048fa7003SUlf Hansson static int mmci_suspend(struct device *dev) 14711c6a0718SPierre Ossman { 147248fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 147348fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 14741c6a0718SPierre Ossman int ret = 0; 14751c6a0718SPierre Ossman 14761c6a0718SPierre Ossman if (mmc) { 14771c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 14781c6a0718SPierre Ossman 14791a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 14802cd976c4SUlf Hansson if (ret == 0) { 14812cd976c4SUlf Hansson pm_runtime_get_sync(dev); 14821c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14831c6a0718SPierre Ossman } 14842cd976c4SUlf Hansson } 14851c6a0718SPierre Ossman 14861c6a0718SPierre Ossman return ret; 14871c6a0718SPierre Ossman } 14881c6a0718SPierre Ossman 148948fa7003SUlf Hansson static int mmci_resume(struct device *dev) 14901c6a0718SPierre Ossman { 149148fa7003SUlf Hansson struct amba_device *adev = to_amba_device(dev); 149248fa7003SUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 14931c6a0718SPierre Ossman int ret = 0; 14941c6a0718SPierre Ossman 14951c6a0718SPierre Ossman if (mmc) { 14961c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 14971c6a0718SPierre Ossman 14981c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 14992cd976c4SUlf Hansson pm_runtime_put(dev); 15001c6a0718SPierre Ossman 15011c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 15021c6a0718SPierre Ossman } 15031c6a0718SPierre Ossman 15041c6a0718SPierre Ossman return ret; 15051c6a0718SPierre Ossman } 15061c6a0718SPierre Ossman #endif 15071c6a0718SPierre Ossman 150848fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 150948fa7003SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 151048fa7003SUlf Hansson }; 151148fa7003SUlf Hansson 15121c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 15131c6a0718SPierre Ossman { 15141c6a0718SPierre Ossman .id = 0x00041180, 1515768fbc18SPawel Moll .mask = 0xff0fffff, 15164956e109SRabin Vincent .data = &variant_arm, 15171c6a0718SPierre Ossman }, 15181c6a0718SPierre Ossman { 1519768fbc18SPawel Moll .id = 0x01041180, 1520768fbc18SPawel Moll .mask = 0xff0fffff, 1521768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1522768fbc18SPawel Moll }, 1523768fbc18SPawel Moll { 15241c6a0718SPierre Ossman .id = 0x00041181, 15251c6a0718SPierre Ossman .mask = 0x000fffff, 15264956e109SRabin Vincent .data = &variant_arm, 15271c6a0718SPierre Ossman }, 1528cc30d60eSLinus Walleij /* ST Micro variants */ 1529cc30d60eSLinus Walleij { 1530cc30d60eSLinus Walleij .id = 0x00180180, 1531cc30d60eSLinus Walleij .mask = 0x00ffffff, 15324956e109SRabin Vincent .data = &variant_u300, 1533cc30d60eSLinus Walleij }, 1534cc30d60eSLinus Walleij { 1535cc30d60eSLinus Walleij .id = 0x00280180, 1536cc30d60eSLinus Walleij .mask = 0x00ffffff, 15374956e109SRabin Vincent .data = &variant_u300, 15384956e109SRabin Vincent }, 15394956e109SRabin Vincent { 15404956e109SRabin Vincent .id = 0x00480180, 15411784b157SPhilippe Langlais .mask = 0xf0ffffff, 15424956e109SRabin Vincent .data = &variant_ux500, 1543cc30d60eSLinus Walleij }, 15441784b157SPhilippe Langlais { 15451784b157SPhilippe Langlais .id = 0x10480180, 15461784b157SPhilippe Langlais .mask = 0xf0ffffff, 15471784b157SPhilippe Langlais .data = &variant_ux500v2, 15481784b157SPhilippe Langlais }, 15491c6a0718SPierre Ossman { 0, 0 }, 15501c6a0718SPierre Ossman }; 15511c6a0718SPierre Ossman 15529f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 15539f99835fSDave Martin 15541c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 15551c6a0718SPierre Ossman .drv = { 15561c6a0718SPierre Ossman .name = DRIVER_NAME, 155748fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 15581c6a0718SPierre Ossman }, 15591c6a0718SPierre Ossman .probe = mmci_probe, 15606dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 15611c6a0718SPierre Ossman .id_table = mmci_ids, 15621c6a0718SPierre Ossman }; 15631c6a0718SPierre Ossman 15641c6a0718SPierre Ossman static int __init mmci_init(void) 15651c6a0718SPierre Ossman { 15661c6a0718SPierre Ossman return amba_driver_register(&mmci_driver); 15671c6a0718SPierre Ossman } 15681c6a0718SPierre Ossman 15691c6a0718SPierre Ossman static void __exit mmci_exit(void) 15701c6a0718SPierre Ossman { 15711c6a0718SPierre Ossman amba_driver_unregister(&mmci_driver); 15721c6a0718SPierre Ossman } 15731c6a0718SPierre Ossman 15741c6a0718SPierre Ossman module_init(mmci_init); 15751c6a0718SPierre Ossman module_exit(mmci_exit); 15761c6a0718SPierre Ossman module_param(fmax, uint, 0444); 15771c6a0718SPierre Ossman 15781c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 15791c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1580