11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 181c6a0718SPierre Ossman #include <linux/delay.h> 191c6a0718SPierre Ossman #include <linux/err.h> 201c6a0718SPierre Ossman #include <linux/highmem.h> 21019a5f56SNicolas Pitre #include <linux/log2.h> 221c6a0718SPierre Ossman #include <linux/mmc/host.h> 2334177802SLinus Walleij #include <linux/mmc/card.h> 241c6a0718SPierre Ossman #include <linux/amba/bus.h> 251c6a0718SPierre Ossman #include <linux/clk.h> 26bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2789001446SRussell King #include <linux/gpio.h> 2834e84f39SLinus Walleij #include <linux/regulator/consumer.h> 29c8ebae37SRussell King #include <linux/dmaengine.h> 30c8ebae37SRussell King #include <linux/dma-mapping.h> 31c8ebae37SRussell King #include <linux/amba/mmci.h> 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #include <asm/div64.h> 341c6a0718SPierre Ossman #include <asm/io.h> 351c6a0718SPierre Ossman #include <asm/sizes.h> 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #include "mmci.h" 381c6a0718SPierre Ossman 391c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 401c6a0718SPierre Ossman 411c6a0718SPierre Ossman static unsigned int fmax = 515633; 421c6a0718SPierre Ossman 434956e109SRabin Vincent /** 444956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 454956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 464380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 4708458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 488301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 498301bb68SRabin Vincent * is asserted (likewise for RX) 508301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 518301bb68SRabin Vincent * is asserted (likewise for RX) 5234177802SLinus Walleij * @sdio: variant supports SDIO 53b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 541784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 554956e109SRabin Vincent */ 564956e109SRabin Vincent struct variant_data { 574956e109SRabin Vincent unsigned int clkreg; 584380c14fSRabin Vincent unsigned int clkreg_enable; 5908458ef6SRabin Vincent unsigned int datalength_bits; 608301bb68SRabin Vincent unsigned int fifosize; 618301bb68SRabin Vincent unsigned int fifohalfsize; 6234177802SLinus Walleij bool sdio; 63b70a67f9SLinus Walleij bool st_clkdiv; 641784b157SPhilippe Langlais bool blksz_datactrl16; 654956e109SRabin Vincent }; 664956e109SRabin Vincent 674956e109SRabin Vincent static struct variant_data variant_arm = { 688301bb68SRabin Vincent .fifosize = 16 * 4, 698301bb68SRabin Vincent .fifohalfsize = 8 * 4, 7008458ef6SRabin Vincent .datalength_bits = 16, 714956e109SRabin Vincent }; 724956e109SRabin Vincent 73768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 74768fbc18SPawel Moll .fifosize = 128 * 4, 75768fbc18SPawel Moll .fifohalfsize = 64 * 4, 76768fbc18SPawel Moll .datalength_bits = 16, 77768fbc18SPawel Moll }; 78768fbc18SPawel Moll 794956e109SRabin Vincent static struct variant_data variant_u300 = { 808301bb68SRabin Vincent .fifosize = 16 * 4, 818301bb68SRabin Vincent .fifohalfsize = 8 * 4, 8249ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 8308458ef6SRabin Vincent .datalength_bits = 16, 8434177802SLinus Walleij .sdio = true, 854956e109SRabin Vincent }; 864956e109SRabin Vincent 874956e109SRabin Vincent static struct variant_data variant_ux500 = { 888301bb68SRabin Vincent .fifosize = 30 * 4, 898301bb68SRabin Vincent .fifohalfsize = 8 * 4, 904956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 9149ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 9208458ef6SRabin Vincent .datalength_bits = 24, 9334177802SLinus Walleij .sdio = true, 94b70a67f9SLinus Walleij .st_clkdiv = true, 954956e109SRabin Vincent }; 96b70a67f9SLinus Walleij 971784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 981784b157SPhilippe Langlais .fifosize = 30 * 4, 991784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1001784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1011784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1021784b157SPhilippe Langlais .datalength_bits = 24, 1031784b157SPhilippe Langlais .sdio = true, 1041784b157SPhilippe Langlais .st_clkdiv = true, 1051784b157SPhilippe Langlais .blksz_datactrl16 = true, 1061784b157SPhilippe Langlais }; 1071784b157SPhilippe Langlais 108a6a6464aSLinus Walleij /* 109a6a6464aSLinus Walleij * This must be called with host->lock held 110a6a6464aSLinus Walleij */ 111a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 112a6a6464aSLinus Walleij { 1134956e109SRabin Vincent struct variant_data *variant = host->variant; 1144956e109SRabin Vincent u32 clk = variant->clkreg; 115a6a6464aSLinus Walleij 116a6a6464aSLinus Walleij if (desired) { 117a6a6464aSLinus Walleij if (desired >= host->mclk) { 118a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 119399bc486SLinus Walleij if (variant->st_clkdiv) 120399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 121a6a6464aSLinus Walleij host->cclk = host->mclk; 122b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 123b70a67f9SLinus Walleij /* 124b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 125b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 126b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 127b70a67f9SLinus Walleij * frequency 128b70a67f9SLinus Walleij */ 129b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 130b70a67f9SLinus Walleij if (clk >= 256) 131b70a67f9SLinus Walleij clk = 255; 132b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 133a6a6464aSLinus Walleij } else { 134b70a67f9SLinus Walleij /* 135b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 136b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 137b70a67f9SLinus Walleij */ 138a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 139a6a6464aSLinus Walleij if (clk >= 256) 140a6a6464aSLinus Walleij clk = 255; 141a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 142a6a6464aSLinus Walleij } 1434380c14fSRabin Vincent 1444380c14fSRabin Vincent clk |= variant->clkreg_enable; 145a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 146a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 147a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 148a6a6464aSLinus Walleij } 149a6a6464aSLinus Walleij 1509e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 151771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 152771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 153771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 1549e6c82cdSLinus Walleij 155a6a6464aSLinus Walleij writel(clk, host->base + MMCICLOCK); 156a6a6464aSLinus Walleij } 157a6a6464aSLinus Walleij 1581c6a0718SPierre Ossman static void 1591c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 1601c6a0718SPierre Ossman { 1611c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 1621c6a0718SPierre Ossman 1631c6a0718SPierre Ossman BUG_ON(host->data); 1641c6a0718SPierre Ossman 1651c6a0718SPierre Ossman host->mrq = NULL; 1661c6a0718SPierre Ossman host->cmd = NULL; 1671c6a0718SPierre Ossman 1681c6a0718SPierre Ossman /* 1691c6a0718SPierre Ossman * Need to drop the host lock here; mmc_request_done may call 1701c6a0718SPierre Ossman * back into the driver... 1711c6a0718SPierre Ossman */ 1721c6a0718SPierre Ossman spin_unlock(&host->lock); 1731c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 1741c6a0718SPierre Ossman spin_lock(&host->lock); 1751c6a0718SPierre Ossman } 1761c6a0718SPierre Ossman 1772686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 1782686b4b4SLinus Walleij { 1792686b4b4SLinus Walleij void __iomem *base = host->base; 1802686b4b4SLinus Walleij 1812686b4b4SLinus Walleij if (host->singleirq) { 1822686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 1832686b4b4SLinus Walleij 1842686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 1852686b4b4SLinus Walleij mask0 |= mask; 1862686b4b4SLinus Walleij 1872686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 1882686b4b4SLinus Walleij } 1892686b4b4SLinus Walleij 1902686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 1912686b4b4SLinus Walleij } 1922686b4b4SLinus Walleij 1931c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 1941c6a0718SPierre Ossman { 1951c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 1962686b4b4SLinus Walleij mmci_set_mask1(host, 0); 1971c6a0718SPierre Ossman host->data = NULL; 1981c6a0718SPierre Ossman } 1991c6a0718SPierre Ossman 2004ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 2014ce1d6cbSRabin Vincent { 2024ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 2034ce1d6cbSRabin Vincent 2044ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 2054ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 2064ce1d6cbSRabin Vincent else 2074ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 2084ce1d6cbSRabin Vincent 2094ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 2104ce1d6cbSRabin Vincent } 2114ce1d6cbSRabin Vincent 212c8ebae37SRussell King /* 213c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 214c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 215c8ebae37SRussell King * no custom DMA interfaces are supported. 216c8ebae37SRussell King */ 217c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 218c8ebae37SRussell King static void __devinit mmci_dma_setup(struct mmci_host *host) 219c8ebae37SRussell King { 220c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 221c8ebae37SRussell King const char *rxname, *txname; 222c8ebae37SRussell King dma_cap_mask_t mask; 223c8ebae37SRussell King 224c8ebae37SRussell King if (!plat || !plat->dma_filter) { 225c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 226c8ebae37SRussell King return; 227c8ebae37SRussell King } 228c8ebae37SRussell King 229c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 230c8ebae37SRussell King dma_cap_zero(mask); 231c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 232c8ebae37SRussell King 233c8ebae37SRussell King /* 234c8ebae37SRussell King * If only an RX channel is specified, the driver will 235c8ebae37SRussell King * attempt to use it bidirectionally, however if it is 236c8ebae37SRussell King * is specified but cannot be located, DMA will be disabled. 237c8ebae37SRussell King */ 238c8ebae37SRussell King if (plat->dma_rx_param) { 239c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 240c8ebae37SRussell King plat->dma_filter, 241c8ebae37SRussell King plat->dma_rx_param); 242c8ebae37SRussell King /* E.g if no DMA hardware is present */ 243c8ebae37SRussell King if (!host->dma_rx_channel) 244c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 245c8ebae37SRussell King } 246c8ebae37SRussell King 247c8ebae37SRussell King if (plat->dma_tx_param) { 248c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 249c8ebae37SRussell King plat->dma_filter, 250c8ebae37SRussell King plat->dma_tx_param); 251c8ebae37SRussell King if (!host->dma_tx_channel) 252c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 253c8ebae37SRussell King } else { 254c8ebae37SRussell King host->dma_tx_channel = host->dma_rx_channel; 255c8ebae37SRussell King } 256c8ebae37SRussell King 257c8ebae37SRussell King if (host->dma_rx_channel) 258c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 259c8ebae37SRussell King else 260c8ebae37SRussell King rxname = "none"; 261c8ebae37SRussell King 262c8ebae37SRussell King if (host->dma_tx_channel) 263c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 264c8ebae37SRussell King else 265c8ebae37SRussell King txname = "none"; 266c8ebae37SRussell King 267c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 268c8ebae37SRussell King rxname, txname); 269c8ebae37SRussell King 270c8ebae37SRussell King /* 271c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 272c8ebae37SRussell King * the parameters of the DMA engine device. 273c8ebae37SRussell King */ 274c8ebae37SRussell King if (host->dma_tx_channel) { 275c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 276c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 277c8ebae37SRussell King 278c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 279c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 280c8ebae37SRussell King } 281c8ebae37SRussell King if (host->dma_rx_channel) { 282c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 283c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 284c8ebae37SRussell King 285c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 286c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 287c8ebae37SRussell King } 288c8ebae37SRussell King } 289c8ebae37SRussell King 290c8ebae37SRussell King /* 291c8ebae37SRussell King * This is used in __devinit or __devexit so inline it 292c8ebae37SRussell King * so it can be discarded. 293c8ebae37SRussell King */ 294c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 295c8ebae37SRussell King { 296c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 297c8ebae37SRussell King 298c8ebae37SRussell King if (host->dma_rx_channel) 299c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 300c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 301c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 302c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 303c8ebae37SRussell King } 304c8ebae37SRussell King 305c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 306c8ebae37SRussell King { 307c8ebae37SRussell King struct dma_chan *chan = host->dma_current; 308c8ebae37SRussell King enum dma_data_direction dir; 309c8ebae37SRussell King u32 status; 310c8ebae37SRussell King int i; 311c8ebae37SRussell King 312c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 313c8ebae37SRussell King for (i = 0; ; i++) { 314c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 315c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 316c8ebae37SRussell King break; 317c8ebae37SRussell King udelay(10); 318c8ebae37SRussell King } 319c8ebae37SRussell King 320c8ebae37SRussell King /* 321c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 322c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 323c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 324c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 325c8ebae37SRussell King */ 326c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 327c8ebae37SRussell King dmaengine_terminate_all(chan); 328c8ebae37SRussell King if (!data->error) 329c8ebae37SRussell King data->error = -EIO; 330c8ebae37SRussell King } 331c8ebae37SRussell King 332c8ebae37SRussell King if (data->flags & MMC_DATA_WRITE) { 333c8ebae37SRussell King dir = DMA_TO_DEVICE; 334c8ebae37SRussell King } else { 335c8ebae37SRussell King dir = DMA_FROM_DEVICE; 336c8ebae37SRussell King } 337c8ebae37SRussell King 338c8ebae37SRussell King dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 339c8ebae37SRussell King 340c8ebae37SRussell King /* 341c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 342c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 343c8ebae37SRussell King */ 344c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 345c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 346c8ebae37SRussell King mmci_dma_release(host); 347c8ebae37SRussell King } 348c8ebae37SRussell King } 349c8ebae37SRussell King 350c8ebae37SRussell King static void mmci_dma_data_error(struct mmci_host *host) 351c8ebae37SRussell King { 352c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 353c8ebae37SRussell King dmaengine_terminate_all(host->dma_current); 354c8ebae37SRussell King } 355c8ebae37SRussell King 356c8ebae37SRussell King static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 357c8ebae37SRussell King { 358c8ebae37SRussell King struct variant_data *variant = host->variant; 359c8ebae37SRussell King struct dma_slave_config conf = { 360c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 361c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 362c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 363c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 364c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 365c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 366c8ebae37SRussell King }; 367c8ebae37SRussell King struct mmc_data *data = host->data; 368c8ebae37SRussell King struct dma_chan *chan; 369c8ebae37SRussell King struct dma_device *device; 370c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 371c8ebae37SRussell King int nr_sg; 372c8ebae37SRussell King 373c8ebae37SRussell King host->dma_current = NULL; 374c8ebae37SRussell King 375c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 376c8ebae37SRussell King conf.direction = DMA_FROM_DEVICE; 377c8ebae37SRussell King chan = host->dma_rx_channel; 378c8ebae37SRussell King } else { 379c8ebae37SRussell King conf.direction = DMA_TO_DEVICE; 380c8ebae37SRussell King chan = host->dma_tx_channel; 381c8ebae37SRussell King } 382c8ebae37SRussell King 383c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 384c8ebae37SRussell King if (!chan) 385c8ebae37SRussell King return -EINVAL; 386c8ebae37SRussell King 387c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 388c8ebae37SRussell King if (host->size <= variant->fifosize) 389c8ebae37SRussell King return -EINVAL; 390c8ebae37SRussell King 391c8ebae37SRussell King device = chan->device; 392c8ebae37SRussell King nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction); 393c8ebae37SRussell King if (nr_sg == 0) 394c8ebae37SRussell King return -EINVAL; 395c8ebae37SRussell King 396c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 397c8ebae37SRussell King desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, 398c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 399c8ebae37SRussell King if (!desc) 400c8ebae37SRussell King goto unmap_exit; 401c8ebae37SRussell King 402c8ebae37SRussell King /* Okay, go for it. */ 403c8ebae37SRussell King host->dma_current = chan; 404c8ebae37SRussell King 405c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 406c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 407c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 408c8ebae37SRussell King dmaengine_submit(desc); 409c8ebae37SRussell King dma_async_issue_pending(chan); 410c8ebae37SRussell King 411c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 412c8ebae37SRussell King 413c8ebae37SRussell King /* Trigger the DMA transfer */ 414c8ebae37SRussell King writel(datactrl, host->base + MMCIDATACTRL); 415c8ebae37SRussell King 416c8ebae37SRussell King /* 417c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 418c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 419c8ebae37SRussell King * call mmci_data_end() 420c8ebae37SRussell King */ 421c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 422c8ebae37SRussell King host->base + MMCIMASK0); 423c8ebae37SRussell King return 0; 424c8ebae37SRussell King 425c8ebae37SRussell King unmap_exit: 426c8ebae37SRussell King dmaengine_terminate_all(chan); 427c8ebae37SRussell King dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction); 428c8ebae37SRussell King return -ENOMEM; 429c8ebae37SRussell King } 430c8ebae37SRussell King #else 431c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 432c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 433c8ebae37SRussell King { 434c8ebae37SRussell King } 435c8ebae37SRussell King 436c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 437c8ebae37SRussell King { 438c8ebae37SRussell King } 439c8ebae37SRussell King 440c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 441c8ebae37SRussell King { 442c8ebae37SRussell King } 443c8ebae37SRussell King 444c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 445c8ebae37SRussell King { 446c8ebae37SRussell King } 447c8ebae37SRussell King 448c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 449c8ebae37SRussell King { 450c8ebae37SRussell King return -ENOSYS; 451c8ebae37SRussell King } 452c8ebae37SRussell King #endif 453c8ebae37SRussell King 4541c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 4551c6a0718SPierre Ossman { 4568301bb68SRabin Vincent struct variant_data *variant = host->variant; 4571c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 4581c6a0718SPierre Ossman unsigned long long clks; 4591c6a0718SPierre Ossman void __iomem *base; 4601c6a0718SPierre Ossman int blksz_bits; 4611c6a0718SPierre Ossman 46264de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 4631c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 4641c6a0718SPierre Ossman 4651c6a0718SPierre Ossman host->data = data; 466528320dbSRabin Vincent host->size = data->blksz * data->blocks; 46751d4375dSRussell King data->bytes_xfered = 0; 4681c6a0718SPierre Ossman 4691c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 4701c6a0718SPierre Ossman do_div(clks, 1000000000UL); 4711c6a0718SPierre Ossman 4721c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 4731c6a0718SPierre Ossman 4741c6a0718SPierre Ossman base = host->base; 4751c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 4761c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 4771c6a0718SPierre Ossman 4781c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 4791c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 4801c6a0718SPierre Ossman 4811784b157SPhilippe Langlais if (variant->blksz_datactrl16) 4821784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 4831784b157SPhilippe Langlais else 4841c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 485c8ebae37SRussell King 486c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 4871c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 488c8ebae37SRussell King 489c8ebae37SRussell King /* 490c8ebae37SRussell King * Attempt to use DMA operation mode, if this 491c8ebae37SRussell King * should fail, fall back to PIO mode 492c8ebae37SRussell King */ 493c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 494c8ebae37SRussell King return; 495c8ebae37SRussell King 496c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 497c8ebae37SRussell King mmci_init_sg(host, data); 498c8ebae37SRussell King 499c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 5001c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 5011c6a0718SPierre Ossman 5021c6a0718SPierre Ossman /* 503c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 504c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 505c4d877c1SRussell King * is available. 5061c6a0718SPierre Ossman */ 507c4d877c1SRussell King if (host->size < variant->fifohalfsize) 5081c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 5091c6a0718SPierre Ossman } else { 5101c6a0718SPierre Ossman /* 5111c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 5121c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 5131c6a0718SPierre Ossman */ 5141c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 5151c6a0718SPierre Ossman } 5161c6a0718SPierre Ossman 51734177802SLinus Walleij /* The ST Micro variants has a special bit to enable SDIO */ 51834177802SLinus Walleij if (variant->sdio && host->mmc->card) 51934177802SLinus Walleij if (mmc_card_sdio(host->mmc->card)) 52034177802SLinus Walleij datactrl |= MCI_ST_DPSM_SDIOEN; 52134177802SLinus Walleij 5221c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 5231c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 5242686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 5251c6a0718SPierre Ossman } 5261c6a0718SPierre Ossman 5271c6a0718SPierre Ossman static void 5281c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 5291c6a0718SPierre Ossman { 5301c6a0718SPierre Ossman void __iomem *base = host->base; 5311c6a0718SPierre Ossman 53264de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 5331c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 5341c6a0718SPierre Ossman 5351c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 5361c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 5371c6a0718SPierre Ossman udelay(1); 5381c6a0718SPierre Ossman } 5391c6a0718SPierre Ossman 5401c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 5411c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 5421c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 5431c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 5441c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 5451c6a0718SPierre Ossman } 5461c6a0718SPierre Ossman if (/*interrupt*/0) 5471c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 5481c6a0718SPierre Ossman 5491c6a0718SPierre Ossman host->cmd = cmd; 5501c6a0718SPierre Ossman 5511c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 5521c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 5531c6a0718SPierre Ossman } 5541c6a0718SPierre Ossman 5551c6a0718SPierre Ossman static void 5561c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 5571c6a0718SPierre Ossman unsigned int status) 5581c6a0718SPierre Ossman { 559f20f8f21SLinus Walleij /* First check for errors */ 5601c6a0718SPierre Ossman if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 5618cb28155SLinus Walleij u32 remain, success; 562f20f8f21SLinus Walleij 563c8ebae37SRussell King /* Terminate the DMA transfer */ 564c8ebae37SRussell King if (dma_inprogress(host)) 565c8ebae37SRussell King mmci_dma_data_error(host); 566c8ebae37SRussell King 567c8afc9d5SRussell King /* 568c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 569c8afc9d5SRussell King * the data counter gives the number of bytes transferred 570c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 571c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 572c8afc9d5SRussell King * matters for FIFO overruns only. 573c8afc9d5SRussell King */ 574f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 5758cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 5768cb28155SLinus Walleij 577c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 578c8afc9d5SRussell King status, success); 5798cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 5808cb28155SLinus Walleij /* Last block was not successful */ 581c8afc9d5SRussell King success -= 1; 58217b0429dSPierre Ossman data->error = -EILSEQ; 5838cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 58417b0429dSPierre Ossman data->error = -ETIMEDOUT; 585c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 58617b0429dSPierre Ossman data->error = -EIO; 587c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 588c8afc9d5SRussell King if (success > host->variant->fifosize) 589c8afc9d5SRussell King success -= host->variant->fifosize; 590c8afc9d5SRussell King else 591c8afc9d5SRussell King success = 0; 5928cb28155SLinus Walleij data->error = -EIO; 5934ce1d6cbSRabin Vincent } 59451d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 5951c6a0718SPierre Ossman } 596f20f8f21SLinus Walleij 5978cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 5988cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 599f20f8f21SLinus Walleij 600ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 601c8ebae37SRussell King if (dma_inprogress(host)) 602c8ebae37SRussell King mmci_dma_unmap(host, data); 6031c6a0718SPierre Ossman mmci_stop_data(host); 6041c6a0718SPierre Ossman 6058cb28155SLinus Walleij if (!data->error) 6068cb28155SLinus Walleij /* The error clause is handled above, success! */ 60751d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 608f20f8f21SLinus Walleij 6091c6a0718SPierre Ossman if (!data->stop) { 6101c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 6111c6a0718SPierre Ossman } else { 6121c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 6131c6a0718SPierre Ossman } 6141c6a0718SPierre Ossman } 6151c6a0718SPierre Ossman } 6161c6a0718SPierre Ossman 6171c6a0718SPierre Ossman static void 6181c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 6191c6a0718SPierre Ossman unsigned int status) 6201c6a0718SPierre Ossman { 6211c6a0718SPierre Ossman void __iomem *base = host->base; 6221c6a0718SPierre Ossman 6231c6a0718SPierre Ossman host->cmd = NULL; 6241c6a0718SPierre Ossman 6251c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 62617b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 6271c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 62817b0429dSPierre Ossman cmd->error = -EILSEQ; 6299047b435SRussell King - ARM Linux } else { 6309047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 6319047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 6329047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 6339047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 6341c6a0718SPierre Ossman } 6351c6a0718SPierre Ossman 63617b0429dSPierre Ossman if (!cmd->data || cmd->error) { 6371c6a0718SPierre Ossman if (host->data) 6381c6a0718SPierre Ossman mmci_stop_data(host); 6391c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 6401c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 6411c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 6421c6a0718SPierre Ossman } 6431c6a0718SPierre Ossman } 6441c6a0718SPierre Ossman 6451c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 6461c6a0718SPierre Ossman { 6471c6a0718SPierre Ossman void __iomem *base = host->base; 6481c6a0718SPierre Ossman char *ptr = buffer; 6491c6a0718SPierre Ossman u32 status; 65026eed9a5SLinus Walleij int host_remain = host->size; 6511c6a0718SPierre Ossman 6521c6a0718SPierre Ossman do { 65326eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 6541c6a0718SPierre Ossman 6551c6a0718SPierre Ossman if (count > remain) 6561c6a0718SPierre Ossman count = remain; 6571c6a0718SPierre Ossman 6581c6a0718SPierre Ossman if (count <= 0) 6591c6a0718SPierre Ossman break; 6601c6a0718SPierre Ossman 6611c6a0718SPierre Ossman readsl(base + MMCIFIFO, ptr, count >> 2); 6621c6a0718SPierre Ossman 6631c6a0718SPierre Ossman ptr += count; 6641c6a0718SPierre Ossman remain -= count; 66526eed9a5SLinus Walleij host_remain -= count; 6661c6a0718SPierre Ossman 6671c6a0718SPierre Ossman if (remain == 0) 6681c6a0718SPierre Ossman break; 6691c6a0718SPierre Ossman 6701c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 6711c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 6721c6a0718SPierre Ossman 6731c6a0718SPierre Ossman return ptr - buffer; 6741c6a0718SPierre Ossman } 6751c6a0718SPierre Ossman 6761c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 6771c6a0718SPierre Ossman { 6788301bb68SRabin Vincent struct variant_data *variant = host->variant; 6791c6a0718SPierre Ossman void __iomem *base = host->base; 6801c6a0718SPierre Ossman char *ptr = buffer; 6811c6a0718SPierre Ossman 6821c6a0718SPierre Ossman do { 6831c6a0718SPierre Ossman unsigned int count, maxcnt; 6841c6a0718SPierre Ossman 6858301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 6868301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 6871c6a0718SPierre Ossman count = min(remain, maxcnt); 6881c6a0718SPierre Ossman 68934177802SLinus Walleij /* 69034177802SLinus Walleij * The ST Micro variant for SDIO transfer sizes 69134177802SLinus Walleij * less then 8 bytes should have clock H/W flow 69234177802SLinus Walleij * control disabled. 69334177802SLinus Walleij */ 69434177802SLinus Walleij if (variant->sdio && 69534177802SLinus Walleij mmc_card_sdio(host->mmc->card)) { 69634177802SLinus Walleij if (count < 8) 69734177802SLinus Walleij writel(readl(host->base + MMCICLOCK) & 69834177802SLinus Walleij ~variant->clkreg_enable, 69934177802SLinus Walleij host->base + MMCICLOCK); 70034177802SLinus Walleij else 70134177802SLinus Walleij writel(readl(host->base + MMCICLOCK) | 70234177802SLinus Walleij variant->clkreg_enable, 70334177802SLinus Walleij host->base + MMCICLOCK); 70434177802SLinus Walleij } 70534177802SLinus Walleij 70634177802SLinus Walleij /* 70734177802SLinus Walleij * SDIO especially may want to send something that is 70834177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 70934177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 71034177802SLinus Walleij * So compensate by adding +3 on the count, a single 71134177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 71234177802SLinus Walleij * 32bit writes etc. 71334177802SLinus Walleij */ 71434177802SLinus Walleij writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 7151c6a0718SPierre Ossman 7161c6a0718SPierre Ossman ptr += count; 7171c6a0718SPierre Ossman remain -= count; 7181c6a0718SPierre Ossman 7191c6a0718SPierre Ossman if (remain == 0) 7201c6a0718SPierre Ossman break; 7211c6a0718SPierre Ossman 7221c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 7231c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 7241c6a0718SPierre Ossman 7251c6a0718SPierre Ossman return ptr - buffer; 7261c6a0718SPierre Ossman } 7271c6a0718SPierre Ossman 7281c6a0718SPierre Ossman /* 7291c6a0718SPierre Ossman * PIO data transfer IRQ handler. 7301c6a0718SPierre Ossman */ 7311c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 7321c6a0718SPierre Ossman { 7331c6a0718SPierre Ossman struct mmci_host *host = dev_id; 7344ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 7358301bb68SRabin Vincent struct variant_data *variant = host->variant; 7361c6a0718SPierre Ossman void __iomem *base = host->base; 7374ce1d6cbSRabin Vincent unsigned long flags; 7381c6a0718SPierre Ossman u32 status; 7391c6a0718SPierre Ossman 7401c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 7411c6a0718SPierre Ossman 74264de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 7431c6a0718SPierre Ossman 7444ce1d6cbSRabin Vincent local_irq_save(flags); 7454ce1d6cbSRabin Vincent 7461c6a0718SPierre Ossman do { 7471c6a0718SPierre Ossman unsigned int remain, len; 7481c6a0718SPierre Ossman char *buffer; 7491c6a0718SPierre Ossman 7501c6a0718SPierre Ossman /* 7511c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 7521c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 7531c6a0718SPierre Ossman * definition it is more than half empty. 7541c6a0718SPierre Ossman * 7551c6a0718SPierre Ossman * For read, check for data available. 7561c6a0718SPierre Ossman */ 7571c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 7581c6a0718SPierre Ossman break; 7591c6a0718SPierre Ossman 7604ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 7614ce1d6cbSRabin Vincent break; 7624ce1d6cbSRabin Vincent 7634ce1d6cbSRabin Vincent buffer = sg_miter->addr; 7644ce1d6cbSRabin Vincent remain = sg_miter->length; 7651c6a0718SPierre Ossman 7661c6a0718SPierre Ossman len = 0; 7671c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 7681c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 7691c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 7701c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 7711c6a0718SPierre Ossman 7724ce1d6cbSRabin Vincent sg_miter->consumed = len; 7731c6a0718SPierre Ossman 7741c6a0718SPierre Ossman host->size -= len; 7751c6a0718SPierre Ossman remain -= len; 7761c6a0718SPierre Ossman 7771c6a0718SPierre Ossman if (remain) 7781c6a0718SPierre Ossman break; 7791c6a0718SPierre Ossman 7801c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 7811c6a0718SPierre Ossman } while (1); 7821c6a0718SPierre Ossman 7834ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 7844ce1d6cbSRabin Vincent 7854ce1d6cbSRabin Vincent local_irq_restore(flags); 7864ce1d6cbSRabin Vincent 7871c6a0718SPierre Ossman /* 788c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 789c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 7901c6a0718SPierre Ossman */ 791c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 7922686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 7931c6a0718SPierre Ossman 7941c6a0718SPierre Ossman /* 7951c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 7961c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 7971c6a0718SPierre Ossman * the chip itself has disabled the data path, and 7981c6a0718SPierre Ossman * stops us racing with our data end IRQ. 7991c6a0718SPierre Ossman */ 8001c6a0718SPierre Ossman if (host->size == 0) { 8012686b4b4SLinus Walleij mmci_set_mask1(host, 0); 8021c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 8031c6a0718SPierre Ossman } 8041c6a0718SPierre Ossman 8051c6a0718SPierre Ossman return IRQ_HANDLED; 8061c6a0718SPierre Ossman } 8071c6a0718SPierre Ossman 8081c6a0718SPierre Ossman /* 8091c6a0718SPierre Ossman * Handle completion of command and data transfers. 8101c6a0718SPierre Ossman */ 8111c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 8121c6a0718SPierre Ossman { 8131c6a0718SPierre Ossman struct mmci_host *host = dev_id; 8141c6a0718SPierre Ossman u32 status; 8151c6a0718SPierre Ossman int ret = 0; 8161c6a0718SPierre Ossman 8171c6a0718SPierre Ossman spin_lock(&host->lock); 8181c6a0718SPierre Ossman 8191c6a0718SPierre Ossman do { 8201c6a0718SPierre Ossman struct mmc_command *cmd; 8211c6a0718SPierre Ossman struct mmc_data *data; 8221c6a0718SPierre Ossman 8231c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 8242686b4b4SLinus Walleij 8252686b4b4SLinus Walleij if (host->singleirq) { 8262686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 8272686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 8282686b4b4SLinus Walleij 8292686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 8302686b4b4SLinus Walleij } 8312686b4b4SLinus Walleij 8321c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 8331c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 8341c6a0718SPierre Ossman 83564de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 8361c6a0718SPierre Ossman 8371c6a0718SPierre Ossman data = host->data; 8381c6a0718SPierre Ossman if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 8391c6a0718SPierre Ossman MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 8401c6a0718SPierre Ossman mmci_data_irq(host, data, status); 8411c6a0718SPierre Ossman 8421c6a0718SPierre Ossman cmd = host->cmd; 8431c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 8441c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 8451c6a0718SPierre Ossman 8461c6a0718SPierre Ossman ret = 1; 8471c6a0718SPierre Ossman } while (status); 8481c6a0718SPierre Ossman 8491c6a0718SPierre Ossman spin_unlock(&host->lock); 8501c6a0718SPierre Ossman 8511c6a0718SPierre Ossman return IRQ_RETVAL(ret); 8521c6a0718SPierre Ossman } 8531c6a0718SPierre Ossman 8541c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 8551c6a0718SPierre Ossman { 8561c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 8579e943021SLinus Walleij unsigned long flags; 8581c6a0718SPierre Ossman 8591c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 8601c6a0718SPierre Ossman 861019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 86264de0289SLinus Walleij dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 86364de0289SLinus Walleij mrq->data->blksz); 864255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 865255d01afSPierre Ossman mmc_request_done(mmc, mrq); 866255d01afSPierre Ossman return; 867255d01afSPierre Ossman } 868255d01afSPierre Ossman 8699e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 8701c6a0718SPierre Ossman 8711c6a0718SPierre Ossman host->mrq = mrq; 8721c6a0718SPierre Ossman 8731c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 8741c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 8751c6a0718SPierre Ossman 8761c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 8771c6a0718SPierre Ossman 8789e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 8791c6a0718SPierre Ossman } 8801c6a0718SPierre Ossman 8811c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 8821c6a0718SPierre Ossman { 8831c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 884a6a6464aSLinus Walleij u32 pwr = 0; 885a6a6464aSLinus Walleij unsigned long flags; 88699fc5131SLinus Walleij int ret; 8871c6a0718SPierre Ossman 8881c6a0718SPierre Ossman switch (ios->power_mode) { 8891c6a0718SPierre Ossman case MMC_POWER_OFF: 89099fc5131SLinus Walleij if (host->vcc) 89199fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 8921c6a0718SPierre Ossman break; 8931c6a0718SPierre Ossman case MMC_POWER_UP: 89499fc5131SLinus Walleij if (host->vcc) { 89599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 89699fc5131SLinus Walleij if (ret) { 89799fc5131SLinus Walleij dev_err(mmc_dev(mmc), "unable to set OCR\n"); 89899fc5131SLinus Walleij /* 89999fc5131SLinus Walleij * The .set_ios() function in the mmc_host_ops 90099fc5131SLinus Walleij * struct return void, and failing to set the 90199fc5131SLinus Walleij * power should be rare so we print an error 90299fc5131SLinus Walleij * and return here. 90399fc5131SLinus Walleij */ 90499fc5131SLinus Walleij return; 90599fc5131SLinus Walleij } 90699fc5131SLinus Walleij } 907bb8f563cSRabin Vincent if (host->plat->vdd_handler) 908bb8f563cSRabin Vincent pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, 909bb8f563cSRabin Vincent ios->power_mode); 910cc30d60eSLinus Walleij /* The ST version does not have this, fall through to POWER_ON */ 911f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) { 9121c6a0718SPierre Ossman pwr |= MCI_PWR_UP; 9131c6a0718SPierre Ossman break; 914cc30d60eSLinus Walleij } 9151c6a0718SPierre Ossman case MMC_POWER_ON: 9161c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 9171c6a0718SPierre Ossman break; 9181c6a0718SPierre Ossman } 9191c6a0718SPierre Ossman 920cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 921f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 9221c6a0718SPierre Ossman pwr |= MCI_ROD; 923cc30d60eSLinus Walleij else { 924cc30d60eSLinus Walleij /* 925cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 926cc30d60eSLinus Walleij * else and only has OD (Open Drain). 927cc30d60eSLinus Walleij */ 928cc30d60eSLinus Walleij pwr |= MCI_OD; 929cc30d60eSLinus Walleij } 930cc30d60eSLinus Walleij } 9311c6a0718SPierre Ossman 932a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 933a6a6464aSLinus Walleij 934a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 9351c6a0718SPierre Ossman 9361c6a0718SPierre Ossman if (host->pwr != pwr) { 9371c6a0718SPierre Ossman host->pwr = pwr; 9381c6a0718SPierre Ossman writel(pwr, host->base + MMCIPOWER); 9391c6a0718SPierre Ossman } 940a6a6464aSLinus Walleij 941a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 9421c6a0718SPierre Ossman } 9431c6a0718SPierre Ossman 94489001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 94589001446SRussell King { 94689001446SRussell King struct mmci_host *host = mmc_priv(mmc); 94789001446SRussell King 94889001446SRussell King if (host->gpio_wp == -ENOSYS) 94989001446SRussell King return -ENOSYS; 95089001446SRussell King 95118a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 95289001446SRussell King } 95389001446SRussell King 95489001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 95589001446SRussell King { 95689001446SRussell King struct mmci_host *host = mmc_priv(mmc); 95729719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 95889001446SRussell King unsigned int status; 95989001446SRussell King 9604b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 9614b8caec0SRabin Vincent if (!plat->status) 9624b8caec0SRabin Vincent return 1; /* Assume always present */ 9634b8caec0SRabin Vincent 96429719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 9654b8caec0SRabin Vincent } else 96618a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 96718a06301SLinus Walleij ^ plat->cd_invert; 96889001446SRussell King 96974bc8093SRussell King /* 97074bc8093SRussell King * Use positive logic throughout - status is zero for no card, 97174bc8093SRussell King * non-zero for card inserted. 97274bc8093SRussell King */ 97374bc8093SRussell King return status; 97489001446SRussell King } 97589001446SRussell King 976148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 977148b8b39SRabin Vincent { 978148b8b39SRabin Vincent struct mmci_host *host = dev_id; 979148b8b39SRabin Vincent 980148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 981148b8b39SRabin Vincent 982148b8b39SRabin Vincent return IRQ_HANDLED; 983148b8b39SRabin Vincent } 984148b8b39SRabin Vincent 9851c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 9861c6a0718SPierre Ossman .request = mmci_request, 9871c6a0718SPierre Ossman .set_ios = mmci_set_ios, 98889001446SRussell King .get_ro = mmci_get_ro, 98989001446SRussell King .get_cd = mmci_get_cd, 9901c6a0718SPierre Ossman }; 9911c6a0718SPierre Ossman 992aa25afadSRussell King static int __devinit mmci_probe(struct amba_device *dev, 993aa25afadSRussell King const struct amba_id *id) 9941c6a0718SPierre Ossman { 9956ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 9964956e109SRabin Vincent struct variant_data *variant = id->data; 9971c6a0718SPierre Ossman struct mmci_host *host; 9981c6a0718SPierre Ossman struct mmc_host *mmc; 9991c6a0718SPierre Ossman int ret; 10001c6a0718SPierre Ossman 10011c6a0718SPierre Ossman /* must have platform data */ 10021c6a0718SPierre Ossman if (!plat) { 10031c6a0718SPierre Ossman ret = -EINVAL; 10041c6a0718SPierre Ossman goto out; 10051c6a0718SPierre Ossman } 10061c6a0718SPierre Ossman 10071c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 10081c6a0718SPierre Ossman if (ret) 10091c6a0718SPierre Ossman goto out; 10101c6a0718SPierre Ossman 10111c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 10121c6a0718SPierre Ossman if (!mmc) { 10131c6a0718SPierre Ossman ret = -ENOMEM; 10141c6a0718SPierre Ossman goto rel_regions; 10151c6a0718SPierre Ossman } 10161c6a0718SPierre Ossman 10171c6a0718SPierre Ossman host = mmc_priv(mmc); 10184ea580f1SRabin Vincent host->mmc = mmc; 1019012b7d33SRussell King 102089001446SRussell King host->gpio_wp = -ENOSYS; 102189001446SRussell King host->gpio_cd = -ENOSYS; 1022148b8b39SRabin Vincent host->gpio_cd_irq = -1; 102389001446SRussell King 1024012b7d33SRussell King host->hw_designer = amba_manf(dev); 1025012b7d33SRussell King host->hw_revision = amba_rev(dev); 102664de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 102764de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1028012b7d33SRussell King 1029ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 10301c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 10311c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 10321c6a0718SPierre Ossman host->clk = NULL; 10331c6a0718SPierre Ossman goto host_free; 10341c6a0718SPierre Ossman } 10351c6a0718SPierre Ossman 10361c6a0718SPierre Ossman ret = clk_enable(host->clk); 10371c6a0718SPierre Ossman if (ret) 10381c6a0718SPierre Ossman goto clk_free; 10391c6a0718SPierre Ossman 10401c6a0718SPierre Ossman host->plat = plat; 10414956e109SRabin Vincent host->variant = variant; 10421c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1043c8df9a53SLinus Walleij /* 1044c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1045c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1046c8df9a53SLinus Walleij * (if possible). 1047c8df9a53SLinus Walleij */ 1048c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1049c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1050c8df9a53SLinus Walleij if (ret < 0) 1051c8df9a53SLinus Walleij goto clk_disable; 1052c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 105364de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 105464de0289SLinus Walleij host->mclk); 1055c8df9a53SLinus Walleij } 1056c8ebae37SRussell King host->phybase = dev->res.start; 1057dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 10581c6a0718SPierre Ossman if (!host->base) { 10591c6a0718SPierre Ossman ret = -ENOMEM; 10601c6a0718SPierre Ossman goto clk_disable; 10611c6a0718SPierre Ossman } 10621c6a0718SPierre Ossman 10631c6a0718SPierre Ossman mmc->ops = &mmci_ops; 10641c6a0718SPierre Ossman mmc->f_min = (host->mclk + 511) / 512; 1065808d97ccSLinus Walleij /* 1066808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1067808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1068808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1069808d97ccSLinus Walleij * default value in case it is not specified. Either 1070808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1071808d97ccSLinus Walleij * of course. 1072808d97ccSLinus Walleij */ 1073808d97ccSLinus Walleij if (plat->f_max) 1074808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1075808d97ccSLinus Walleij else 10761c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 107764de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 107864de0289SLinus Walleij 107934e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 108034e84f39SLinus Walleij /* If we're using the regulator framework, try to fetch a regulator */ 108134e84f39SLinus Walleij host->vcc = regulator_get(&dev->dev, "vmmc"); 108234e84f39SLinus Walleij if (IS_ERR(host->vcc)) 108334e84f39SLinus Walleij host->vcc = NULL; 108434e84f39SLinus Walleij else { 108534e84f39SLinus Walleij int mask = mmc_regulator_get_ocrmask(host->vcc); 108634e84f39SLinus Walleij 108734e84f39SLinus Walleij if (mask < 0) 108834e84f39SLinus Walleij dev_err(&dev->dev, "error getting OCR mask (%d)\n", 108934e84f39SLinus Walleij mask); 109034e84f39SLinus Walleij else { 109134e84f39SLinus Walleij host->mmc->ocr_avail = (u32) mask; 109234e84f39SLinus Walleij if (plat->ocr_mask) 109334e84f39SLinus Walleij dev_warn(&dev->dev, 109434e84f39SLinus Walleij "Provided ocr_mask/setpower will not be used " 109534e84f39SLinus Walleij "(using regulator instead)\n"); 109634e84f39SLinus Walleij } 109734e84f39SLinus Walleij } 109834e84f39SLinus Walleij #endif 109934e84f39SLinus Walleij /* Fall back to platform data if no regulator is found */ 110034e84f39SLinus Walleij if (host->vcc == NULL) 11011c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 11029e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 11031c6a0718SPierre Ossman 11041c6a0718SPierre Ossman /* 11051c6a0718SPierre Ossman * We can do SGIO 11061c6a0718SPierre Ossman */ 1107a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 11081c6a0718SPierre Ossman 11091c6a0718SPierre Ossman /* 111008458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 111108458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 111208458ef6SRabin Vincent * single request. 11131c6a0718SPierre Ossman */ 111408458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 11151c6a0718SPierre Ossman 11161c6a0718SPierre Ossman /* 11171c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 11181c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 11191c6a0718SPierre Ossman */ 11201c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 11211c6a0718SPierre Ossman 11221c6a0718SPierre Ossman /* 11231c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 11241c6a0718SPierre Ossman */ 11251c6a0718SPierre Ossman mmc->max_blk_size = 2048; 11261c6a0718SPierre Ossman 11271c6a0718SPierre Ossman /* 11281c6a0718SPierre Ossman * No limit on the number of blocks transferred. 11291c6a0718SPierre Ossman */ 11301c6a0718SPierre Ossman mmc->max_blk_count = mmc->max_req_size; 11311c6a0718SPierre Ossman 11321c6a0718SPierre Ossman spin_lock_init(&host->lock); 11331c6a0718SPierre Ossman 11341c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 11351c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 11361c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 11371c6a0718SPierre Ossman 113889001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 113989001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 114089001446SRussell King if (ret == 0) 114189001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 114289001446SRussell King if (ret == 0) 114389001446SRussell King host->gpio_cd = plat->gpio_cd; 114489001446SRussell King else if (ret != -ENOSYS) 114589001446SRussell King goto err_gpio_cd; 1146148b8b39SRabin Vincent 1147148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1148148b8b39SRabin Vincent mmci_cd_irq, 0, 1149148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1150148b8b39SRabin Vincent if (ret >= 0) 1151148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 115289001446SRussell King } 115389001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 115489001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 115589001446SRussell King if (ret == 0) 115689001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 115789001446SRussell King if (ret == 0) 115889001446SRussell King host->gpio_wp = plat->gpio_wp; 115989001446SRussell King else if (ret != -ENOSYS) 116089001446SRussell King goto err_gpio_wp; 116189001446SRussell King } 116289001446SRussell King 11634b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 11644b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1165148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1166148b8b39SRabin Vincent 11671c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 11681c6a0718SPierre Ossman if (ret) 11691c6a0718SPierre Ossman goto unmap; 11701c6a0718SPierre Ossman 11712686b4b4SLinus Walleij if (dev->irq[1] == NO_IRQ) 11722686b4b4SLinus Walleij host->singleirq = true; 11732686b4b4SLinus Walleij else { 11742686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 11752686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 11761c6a0718SPierre Ossman if (ret) 11771c6a0718SPierre Ossman goto irq0_free; 11782686b4b4SLinus Walleij } 11791c6a0718SPierre Ossman 11808cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 11811c6a0718SPierre Ossman 11821c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 11831c6a0718SPierre Ossman 1184c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1185c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1186c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1187c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1188c8ebae37SRussell King 1189c8ebae37SRussell King mmci_dma_setup(host); 11901c6a0718SPierre Ossman 11918c11a94dSRussell King mmc_add_host(mmc); 11928c11a94dSRussell King 11931c6a0718SPierre Ossman return 0; 11941c6a0718SPierre Ossman 11951c6a0718SPierre Ossman irq0_free: 11961c6a0718SPierre Ossman free_irq(dev->irq[0], host); 11971c6a0718SPierre Ossman unmap: 119889001446SRussell King if (host->gpio_wp != -ENOSYS) 119989001446SRussell King gpio_free(host->gpio_wp); 120089001446SRussell King err_gpio_wp: 1201148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1202148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 120389001446SRussell King if (host->gpio_cd != -ENOSYS) 120489001446SRussell King gpio_free(host->gpio_cd); 120589001446SRussell King err_gpio_cd: 12061c6a0718SPierre Ossman iounmap(host->base); 12071c6a0718SPierre Ossman clk_disable: 12081c6a0718SPierre Ossman clk_disable(host->clk); 12091c6a0718SPierre Ossman clk_free: 12101c6a0718SPierre Ossman clk_put(host->clk); 12111c6a0718SPierre Ossman host_free: 12121c6a0718SPierre Ossman mmc_free_host(mmc); 12131c6a0718SPierre Ossman rel_regions: 12141c6a0718SPierre Ossman amba_release_regions(dev); 12151c6a0718SPierre Ossman out: 12161c6a0718SPierre Ossman return ret; 12171c6a0718SPierre Ossman } 12181c6a0718SPierre Ossman 12196dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 12201c6a0718SPierre Ossman { 12211c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 12221c6a0718SPierre Ossman 12231c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 12241c6a0718SPierre Ossman 12251c6a0718SPierre Ossman if (mmc) { 12261c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 12271c6a0718SPierre Ossman 12281c6a0718SPierre Ossman mmc_remove_host(mmc); 12291c6a0718SPierre Ossman 12301c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 12311c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 12321c6a0718SPierre Ossman 12331c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 12341c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 12351c6a0718SPierre Ossman 1236c8ebae37SRussell King mmci_dma_release(host); 12371c6a0718SPierre Ossman free_irq(dev->irq[0], host); 12382686b4b4SLinus Walleij if (!host->singleirq) 12391c6a0718SPierre Ossman free_irq(dev->irq[1], host); 12401c6a0718SPierre Ossman 124189001446SRussell King if (host->gpio_wp != -ENOSYS) 124289001446SRussell King gpio_free(host->gpio_wp); 1243148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1244148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 124589001446SRussell King if (host->gpio_cd != -ENOSYS) 124689001446SRussell King gpio_free(host->gpio_cd); 124789001446SRussell King 12481c6a0718SPierre Ossman iounmap(host->base); 12491c6a0718SPierre Ossman clk_disable(host->clk); 12501c6a0718SPierre Ossman clk_put(host->clk); 12511c6a0718SPierre Ossman 125299fc5131SLinus Walleij if (host->vcc) 125399fc5131SLinus Walleij mmc_regulator_set_ocr(mmc, host->vcc, 0); 125434e84f39SLinus Walleij regulator_put(host->vcc); 125534e84f39SLinus Walleij 12561c6a0718SPierre Ossman mmc_free_host(mmc); 12571c6a0718SPierre Ossman 12581c6a0718SPierre Ossman amba_release_regions(dev); 12591c6a0718SPierre Ossman } 12601c6a0718SPierre Ossman 12611c6a0718SPierre Ossman return 0; 12621c6a0718SPierre Ossman } 12631c6a0718SPierre Ossman 12641c6a0718SPierre Ossman #ifdef CONFIG_PM 12651c6a0718SPierre Ossman static int mmci_suspend(struct amba_device *dev, pm_message_t state) 12661c6a0718SPierre Ossman { 12671c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 12681c6a0718SPierre Ossman int ret = 0; 12691c6a0718SPierre Ossman 12701c6a0718SPierre Ossman if (mmc) { 12711c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 12721c6a0718SPierre Ossman 12731a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 12741c6a0718SPierre Ossman if (ret == 0) 12751c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 12761c6a0718SPierre Ossman } 12771c6a0718SPierre Ossman 12781c6a0718SPierre Ossman return ret; 12791c6a0718SPierre Ossman } 12801c6a0718SPierre Ossman 12811c6a0718SPierre Ossman static int mmci_resume(struct amba_device *dev) 12821c6a0718SPierre Ossman { 12831c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 12841c6a0718SPierre Ossman int ret = 0; 12851c6a0718SPierre Ossman 12861c6a0718SPierre Ossman if (mmc) { 12871c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 12881c6a0718SPierre Ossman 12891c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 12901c6a0718SPierre Ossman 12911c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 12921c6a0718SPierre Ossman } 12931c6a0718SPierre Ossman 12941c6a0718SPierre Ossman return ret; 12951c6a0718SPierre Ossman } 12961c6a0718SPierre Ossman #else 12971c6a0718SPierre Ossman #define mmci_suspend NULL 12981c6a0718SPierre Ossman #define mmci_resume NULL 12991c6a0718SPierre Ossman #endif 13001c6a0718SPierre Ossman 13011c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 13021c6a0718SPierre Ossman { 13031c6a0718SPierre Ossman .id = 0x00041180, 1304768fbc18SPawel Moll .mask = 0xff0fffff, 13054956e109SRabin Vincent .data = &variant_arm, 13061c6a0718SPierre Ossman }, 13071c6a0718SPierre Ossman { 1308768fbc18SPawel Moll .id = 0x01041180, 1309768fbc18SPawel Moll .mask = 0xff0fffff, 1310768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1311768fbc18SPawel Moll }, 1312768fbc18SPawel Moll { 13131c6a0718SPierre Ossman .id = 0x00041181, 13141c6a0718SPierre Ossman .mask = 0x000fffff, 13154956e109SRabin Vincent .data = &variant_arm, 13161c6a0718SPierre Ossman }, 1317cc30d60eSLinus Walleij /* ST Micro variants */ 1318cc30d60eSLinus Walleij { 1319cc30d60eSLinus Walleij .id = 0x00180180, 1320cc30d60eSLinus Walleij .mask = 0x00ffffff, 13214956e109SRabin Vincent .data = &variant_u300, 1322cc30d60eSLinus Walleij }, 1323cc30d60eSLinus Walleij { 1324cc30d60eSLinus Walleij .id = 0x00280180, 1325cc30d60eSLinus Walleij .mask = 0x00ffffff, 13264956e109SRabin Vincent .data = &variant_u300, 13274956e109SRabin Vincent }, 13284956e109SRabin Vincent { 13294956e109SRabin Vincent .id = 0x00480180, 13301784b157SPhilippe Langlais .mask = 0xf0ffffff, 13314956e109SRabin Vincent .data = &variant_ux500, 1332cc30d60eSLinus Walleij }, 13331784b157SPhilippe Langlais { 13341784b157SPhilippe Langlais .id = 0x10480180, 13351784b157SPhilippe Langlais .mask = 0xf0ffffff, 13361784b157SPhilippe Langlais .data = &variant_ux500v2, 13371784b157SPhilippe Langlais }, 13381c6a0718SPierre Ossman { 0, 0 }, 13391c6a0718SPierre Ossman }; 13401c6a0718SPierre Ossman 13411c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 13421c6a0718SPierre Ossman .drv = { 13431c6a0718SPierre Ossman .name = DRIVER_NAME, 13441c6a0718SPierre Ossman }, 13451c6a0718SPierre Ossman .probe = mmci_probe, 13466dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 13471c6a0718SPierre Ossman .suspend = mmci_suspend, 13481c6a0718SPierre Ossman .resume = mmci_resume, 13491c6a0718SPierre Ossman .id_table = mmci_ids, 13501c6a0718SPierre Ossman }; 13511c6a0718SPierre Ossman 13521c6a0718SPierre Ossman static int __init mmci_init(void) 13531c6a0718SPierre Ossman { 13541c6a0718SPierre Ossman return amba_driver_register(&mmci_driver); 13551c6a0718SPierre Ossman } 13561c6a0718SPierre Ossman 13571c6a0718SPierre Ossman static void __exit mmci_exit(void) 13581c6a0718SPierre Ossman { 13591c6a0718SPierre Ossman amba_driver_unregister(&mmci_driver); 13601c6a0718SPierre Ossman } 13611c6a0718SPierre Ossman 13621c6a0718SPierre Ossman module_init(mmci_init); 13631c6a0718SPierre Ossman module_exit(mmci_exit); 13641c6a0718SPierre Ossman module_param(fmax, uint, 0444); 13651c6a0718SPierre Ossman 13661c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 13671c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1368