11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 16ef289982SUlf Hansson #include <linux/io.h> 171c6a0718SPierre Ossman #include <linux/interrupt.h> 18613b152cSRussell King #include <linux/kernel.h> 19000bc9d5SLee Jones #include <linux/slab.h> 201c6a0718SPierre Ossman #include <linux/delay.h> 211c6a0718SPierre Ossman #include <linux/err.h> 221c6a0718SPierre Ossman #include <linux/highmem.h> 23019a5f56SNicolas Pitre #include <linux/log2.h> 2470be208fSUlf Hansson #include <linux/mmc/pm.h> 251c6a0718SPierre Ossman #include <linux/mmc/host.h> 2634177802SLinus Walleij #include <linux/mmc/card.h> 27d2762090SUlf Hansson #include <linux/mmc/slot-gpio.h> 281c6a0718SPierre Ossman #include <linux/amba/bus.h> 291c6a0718SPierre Ossman #include <linux/clk.h> 30bd6dee6fSJens Axboe #include <linux/scatterlist.h> 319ef986a6SLinus Walleij #include <linux/of.h> 3234e84f39SLinus Walleij #include <linux/regulator/consumer.h> 33c8ebae37SRussell King #include <linux/dmaengine.h> 34c8ebae37SRussell King #include <linux/dma-mapping.h> 35c8ebae37SRussell King #include <linux/amba/mmci.h> 361c3be369SRussell King #include <linux/pm_runtime.h> 37258aea76SViresh Kumar #include <linux/types.h> 38a9a83785SLinus Walleij #include <linux/pinctrl/consumer.h> 3915878e58SLudovic Barre #include <linux/reset.h> 401c6a0718SPierre Ossman 411c6a0718SPierre Ossman #include <asm/div64.h> 421c6a0718SPierre Ossman #include <asm/io.h> 431c6a0718SPierre Ossman 441c6a0718SPierre Ossman #include "mmci.h" 459cb15142SSrinivas Kandagatla #include "mmci_qcom_dml.h" 461c6a0718SPierre Ossman 471c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 481c6a0718SPierre Ossman 49c3647fdcSLudovic Barre #ifdef CONFIG_DMA_ENGINE 50c3647fdcSLudovic Barre void mmci_variant_init(struct mmci_host *host); 51c3647fdcSLudovic Barre #else 52c3647fdcSLudovic Barre static inline void mmci_variant_init(struct mmci_host *host) {} 53c3647fdcSLudovic Barre #endif 54c3647fdcSLudovic Barre 5546b723ddSLudovic Barre #ifdef CONFIG_MMC_STM32_SDMMC 5646b723ddSLudovic Barre void sdmmc_variant_init(struct mmci_host *host); 5746b723ddSLudovic Barre #else 5846b723ddSLudovic Barre static inline void sdmmc_variant_init(struct mmci_host *host) {} 5946b723ddSLudovic Barre #endif 6046b723ddSLudovic Barre 611c6a0718SPierre Ossman static unsigned int fmax = 515633; 621c6a0718SPierre Ossman 634956e109SRabin Vincent static struct variant_data variant_arm = { 648301bb68SRabin Vincent .fifosize = 16 * 4, 658301bb68SRabin Vincent .fifohalfsize = 8 * 4, 660f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 670f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 680f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 690f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 7008458ef6SRabin Vincent .datalength_bits = 16, 71c931d495SLudovic Barre .datactrl_blocksz = 11, 729b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 737d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 74dc6500bfSSrinivas Kandagatla .f_max = 100000000, 757878289bSUlf Hansson .reversed_irq_handling = true, 766ea9cdf3SPatrice Chotard .mmcimask1 = true, 7759db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 787f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 7911dfb970SPatrice Chotard .opendrain = MCI_ROD, 80c3647fdcSLudovic Barre .init = mmci_variant_init, 814956e109SRabin Vincent }; 824956e109SRabin Vincent 83768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 84768fbc18SPawel Moll .fifosize = 128 * 4, 85768fbc18SPawel Moll .fifohalfsize = 64 * 4, 860f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 870f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 880f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 890f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 90768fbc18SPawel Moll .datalength_bits = 16, 91c931d495SLudovic Barre .datactrl_blocksz = 11, 929b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 937d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 94dc6500bfSSrinivas Kandagatla .f_max = 100000000, 956ea9cdf3SPatrice Chotard .mmcimask1 = true, 9659db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 977f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 9811dfb970SPatrice Chotard .opendrain = MCI_ROD, 99c3647fdcSLudovic Barre .init = mmci_variant_init, 100768fbc18SPawel Moll }; 101768fbc18SPawel Moll 1023a37298aSPawel Moll static struct variant_data variant_arm_extended_fifo_hwfc = { 1033a37298aSPawel Moll .fifosize = 128 * 4, 1043a37298aSPawel Moll .fifohalfsize = 64 * 4, 1053a37298aSPawel Moll .clkreg_enable = MCI_ARM_HWFCEN, 1060f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 1070f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 1080f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 1090f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 1103a37298aSPawel Moll .datalength_bits = 16, 111c931d495SLudovic Barre .datactrl_blocksz = 11, 1129b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 1133a37298aSPawel Moll .pwrreg_powerup = MCI_PWR_UP, 114dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1156ea9cdf3SPatrice Chotard .mmcimask1 = true, 11659db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 1177f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 11811dfb970SPatrice Chotard .opendrain = MCI_ROD, 119c3647fdcSLudovic Barre .init = mmci_variant_init, 1203a37298aSPawel Moll }; 1213a37298aSPawel Moll 1224956e109SRabin Vincent static struct variant_data variant_u300 = { 1238301bb68SRabin Vincent .fifosize = 16 * 4, 1248301bb68SRabin Vincent .fifohalfsize = 8 * 4, 12549ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 126e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 1270f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 1280f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 1290f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 1300f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 13108458ef6SRabin Vincent .datalength_bits = 16, 132c931d495SLudovic Barre .datactrl_blocksz = 11, 1339b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 1345db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 135c7354133SSrinivas Kandagatla .st_sdio = true, 1367d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 137dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1384d1a3a0dSUlf Hansson .signal_direction = true, 139f4670daeSUlf Hansson .pwrreg_clkgate = true, 1401ff44433SUlf Hansson .pwrreg_nopower = true, 1416ea9cdf3SPatrice Chotard .mmcimask1 = true, 14259db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 1437f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 14411dfb970SPatrice Chotard .opendrain = MCI_OD, 145c3647fdcSLudovic Barre .init = mmci_variant_init, 1464956e109SRabin Vincent }; 1474956e109SRabin Vincent 14834fd4213SLinus Walleij static struct variant_data variant_nomadik = { 14934fd4213SLinus Walleij .fifosize = 16 * 4, 15034fd4213SLinus Walleij .fifohalfsize = 8 * 4, 15134fd4213SLinus Walleij .clkreg = MCI_CLK_ENABLE, 152f5abc767SLinus Walleij .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 1530f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 1540f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 1550f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 1560f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 15734fd4213SLinus Walleij .datalength_bits = 24, 158c931d495SLudovic Barre .datactrl_blocksz = 11, 1599b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 1605db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 161c7354133SSrinivas Kandagatla .st_sdio = true, 16234fd4213SLinus Walleij .st_clkdiv = true, 16334fd4213SLinus Walleij .pwrreg_powerup = MCI_PWR_ON, 164dc6500bfSSrinivas Kandagatla .f_max = 100000000, 16534fd4213SLinus Walleij .signal_direction = true, 166f4670daeSUlf Hansson .pwrreg_clkgate = true, 1671ff44433SUlf Hansson .pwrreg_nopower = true, 1686ea9cdf3SPatrice Chotard .mmcimask1 = true, 16959db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 1707f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 17111dfb970SPatrice Chotard .opendrain = MCI_OD, 172c3647fdcSLudovic Barre .init = mmci_variant_init, 17334fd4213SLinus Walleij }; 17434fd4213SLinus Walleij 1754956e109SRabin Vincent static struct variant_data variant_ux500 = { 1768301bb68SRabin Vincent .fifosize = 30 * 4, 1778301bb68SRabin Vincent .fifohalfsize = 8 * 4, 1784956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 17949ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 180e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 181e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 1820f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 1830f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 1840f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 1850f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 18608458ef6SRabin Vincent .datalength_bits = 24, 187c931d495SLudovic Barre .datactrl_blocksz = 11, 1889b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 1895db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 190c7354133SSrinivas Kandagatla .st_sdio = true, 191b70a67f9SLinus Walleij .st_clkdiv = true, 1927d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 193dc6500bfSSrinivas Kandagatla .f_max = 100000000, 1944d1a3a0dSUlf Hansson .signal_direction = true, 195f4670daeSUlf Hansson .pwrreg_clkgate = true, 19601259620SUlf Hansson .busy_detect = true, 19749adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 19849adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 19949adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 2001ff44433SUlf Hansson .pwrreg_nopower = true, 2016ea9cdf3SPatrice Chotard .mmcimask1 = true, 20259db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 2037f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 20411dfb970SPatrice Chotard .opendrain = MCI_OD, 205c3647fdcSLudovic Barre .init = mmci_variant_init, 2064956e109SRabin Vincent }; 207b70a67f9SLinus Walleij 2081784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 2091784b157SPhilippe Langlais .fifosize = 30 * 4, 2101784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 2111784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 2121784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 213e1412d85SSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 214e8740644SSrinivas Kandagatla .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 2150f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 2160f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 2170f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 2180f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 2195db3eee7SLinus Walleij .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 2201784b157SPhilippe Langlais .datalength_bits = 24, 221c931d495SLudovic Barre .datactrl_blocksz = 11, 2229b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 2235db3eee7SLinus Walleij .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 224c7354133SSrinivas Kandagatla .st_sdio = true, 2251784b157SPhilippe Langlais .st_clkdiv = true, 2261784b157SPhilippe Langlais .blksz_datactrl16 = true, 2277d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 228dc6500bfSSrinivas Kandagatla .f_max = 100000000, 2294d1a3a0dSUlf Hansson .signal_direction = true, 230f4670daeSUlf Hansson .pwrreg_clkgate = true, 23101259620SUlf Hansson .busy_detect = true, 23249adc0caSLinus Walleij .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 23349adc0caSLinus Walleij .busy_detect_flag = MCI_ST_CARDBUSY, 23449adc0caSLinus Walleij .busy_detect_mask = MCI_ST_BUSYENDMASK, 2351ff44433SUlf Hansson .pwrreg_nopower = true, 2366ea9cdf3SPatrice Chotard .mmcimask1 = true, 23759db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 2387f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 23911dfb970SPatrice Chotard .opendrain = MCI_OD, 240c3647fdcSLudovic Barre .init = mmci_variant_init, 2411784b157SPhilippe Langlais }; 2421784b157SPhilippe Langlais 2432a9d6c80SPatrice Chotard static struct variant_data variant_stm32 = { 2442a9d6c80SPatrice Chotard .fifosize = 32 * 4, 2452a9d6c80SPatrice Chotard .fifohalfsize = 8 * 4, 2462a9d6c80SPatrice Chotard .clkreg = MCI_CLK_ENABLE, 2472a9d6c80SPatrice Chotard .clkreg_enable = MCI_ST_UX500_HWFCEN, 2482a9d6c80SPatrice Chotard .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 2492a9d6c80SPatrice Chotard .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 2500f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 2510f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 2520f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 2530f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 25459db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 2552a9d6c80SPatrice Chotard .datalength_bits = 24, 256c931d495SLudovic Barre .datactrl_blocksz = 11, 2579b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 2582a9d6c80SPatrice Chotard .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 2592a9d6c80SPatrice Chotard .st_sdio = true, 2602a9d6c80SPatrice Chotard .st_clkdiv = true, 2612a9d6c80SPatrice Chotard .pwrreg_powerup = MCI_PWR_ON, 2622a9d6c80SPatrice Chotard .f_max = 48000000, 2632a9d6c80SPatrice Chotard .pwrreg_clkgate = true, 2642a9d6c80SPatrice Chotard .pwrreg_nopower = true, 265c3647fdcSLudovic Barre .init = mmci_variant_init, 2662a9d6c80SPatrice Chotard }; 2672a9d6c80SPatrice Chotard 26846b723ddSLudovic Barre static struct variant_data variant_stm32_sdmmc = { 26946b723ddSLudovic Barre .fifosize = 16 * 4, 27046b723ddSLudovic Barre .fifohalfsize = 8 * 4, 27146b723ddSLudovic Barre .f_max = 208000000, 27246b723ddSLudovic Barre .stm32_clkdiv = true, 27346b723ddSLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 27446b723ddSLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 27546b723ddSLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 27646b723ddSLudovic Barre .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 27746b723ddSLudovic Barre .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 27846b723ddSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 27946b723ddSLudovic Barre .datactrl_first = true, 28046b723ddSLudovic Barre .datacnt_useless = true, 28146b723ddSLudovic Barre .datalength_bits = 25, 28246b723ddSLudovic Barre .datactrl_blocksz = 14, 28346b723ddSLudovic Barre .stm32_idmabsize_mask = GENMASK(12, 5), 28446b723ddSLudovic Barre .init = sdmmc_variant_init, 28546b723ddSLudovic Barre }; 28646b723ddSLudovic Barre 28755b604aeSSrinivas Kandagatla static struct variant_data variant_qcom = { 28855b604aeSSrinivas Kandagatla .fifosize = 16 * 4, 28955b604aeSSrinivas Kandagatla .fifohalfsize = 8 * 4, 29055b604aeSSrinivas Kandagatla .clkreg = MCI_CLK_ENABLE, 29155b604aeSSrinivas Kandagatla .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 29255b604aeSSrinivas Kandagatla MCI_QCOM_CLK_SELECT_IN_FBCLK, 29355b604aeSSrinivas Kandagatla .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 29455b604aeSSrinivas Kandagatla .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 2950f244804SLudovic Barre .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 2960f244804SLudovic Barre .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 2970f244804SLudovic Barre .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 2980f244804SLudovic Barre .cmdreg_srsp = MCI_CPSM_RESPONSE, 2995db3eee7SLinus Walleij .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 30055b604aeSSrinivas Kandagatla .blksz_datactrl4 = true, 30155b604aeSSrinivas Kandagatla .datalength_bits = 24, 302c931d495SLudovic Barre .datactrl_blocksz = 11, 3039b279941SLudovic Barre .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 30455b604aeSSrinivas Kandagatla .pwrreg_powerup = MCI_PWR_UP, 30555b604aeSSrinivas Kandagatla .f_max = 208000000, 30655b604aeSSrinivas Kandagatla .explicit_mclk_control = true, 30755b604aeSSrinivas Kandagatla .qcom_fifo = true, 3089cb15142SSrinivas Kandagatla .qcom_dml = true, 3096ea9cdf3SPatrice Chotard .mmcimask1 = true, 31059db5e2dSLudovic Barre .irq_pio_mask = MCI_IRQ_PIO_MASK, 3117f7b5503SPatrice Chotard .start_err = MCI_STARTBITERR, 31211dfb970SPatrice Chotard .opendrain = MCI_ROD, 31329aba07aSUlf Hansson .init = qcom_variant_init, 31455b604aeSSrinivas Kandagatla }; 31555b604aeSSrinivas Kandagatla 31649adc0caSLinus Walleij /* Busy detection for the ST Micro variant */ 31701259620SUlf Hansson static int mmci_card_busy(struct mmc_host *mmc) 31801259620SUlf Hansson { 31901259620SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 32001259620SUlf Hansson unsigned long flags; 32101259620SUlf Hansson int busy = 0; 32201259620SUlf Hansson 32301259620SUlf Hansson spin_lock_irqsave(&host->lock, flags); 32449adc0caSLinus Walleij if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 32501259620SUlf Hansson busy = 1; 32601259620SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 32701259620SUlf Hansson 32801259620SUlf Hansson return busy; 32901259620SUlf Hansson } 33001259620SUlf Hansson 331f829c042SUlf Hansson static void mmci_reg_delay(struct mmci_host *host) 332f829c042SUlf Hansson { 333f829c042SUlf Hansson /* 334f829c042SUlf Hansson * According to the spec, at least three feedback clock cycles 335f829c042SUlf Hansson * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 336f829c042SUlf Hansson * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 337f829c042SUlf Hansson * Worst delay time during card init is at 100 kHz => 30 us. 338f829c042SUlf Hansson * Worst delay time when up and running is at 25 MHz => 120 ns. 339f829c042SUlf Hansson */ 340f829c042SUlf Hansson if (host->cclk < 25000000) 341f829c042SUlf Hansson udelay(30); 342f829c042SUlf Hansson else 343f829c042SUlf Hansson ndelay(120); 344f829c042SUlf Hansson } 345f829c042SUlf Hansson 346653a761eSUlf Hansson /* 347a6a6464aSLinus Walleij * This must be called with host->lock held 348a6a6464aSLinus Walleij */ 349cd3ee8c5SLudovic Barre void mmci_write_clkreg(struct mmci_host *host, u32 clk) 3507437cfa5SUlf Hansson { 3517437cfa5SUlf Hansson if (host->clk_reg != clk) { 3527437cfa5SUlf Hansson host->clk_reg = clk; 3537437cfa5SUlf Hansson writel(clk, host->base + MMCICLOCK); 3547437cfa5SUlf Hansson } 3557437cfa5SUlf Hansson } 3567437cfa5SUlf Hansson 3577437cfa5SUlf Hansson /* 3587437cfa5SUlf Hansson * This must be called with host->lock held 3597437cfa5SUlf Hansson */ 360cd3ee8c5SLudovic Barre void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 3617437cfa5SUlf Hansson { 3627437cfa5SUlf Hansson if (host->pwr_reg != pwr) { 3637437cfa5SUlf Hansson host->pwr_reg = pwr; 3647437cfa5SUlf Hansson writel(pwr, host->base + MMCIPOWER); 3657437cfa5SUlf Hansson } 3667437cfa5SUlf Hansson } 3677437cfa5SUlf Hansson 3687437cfa5SUlf Hansson /* 3697437cfa5SUlf Hansson * This must be called with host->lock held 3707437cfa5SUlf Hansson */ 3719cc639a2SUlf Hansson static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 3729cc639a2SUlf Hansson { 37349adc0caSLinus Walleij /* Keep busy mode in DPSM if enabled */ 37449adc0caSLinus Walleij datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 37501259620SUlf Hansson 3769cc639a2SUlf Hansson if (host->datactrl_reg != datactrl) { 3779cc639a2SUlf Hansson host->datactrl_reg = datactrl; 3789cc639a2SUlf Hansson writel(datactrl, host->base + MMCIDATACTRL); 3799cc639a2SUlf Hansson } 3809cc639a2SUlf Hansson } 3819cc639a2SUlf Hansson 3829cc639a2SUlf Hansson /* 3839cc639a2SUlf Hansson * This must be called with host->lock held 3849cc639a2SUlf Hansson */ 385a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 386a6a6464aSLinus Walleij { 3874956e109SRabin Vincent struct variant_data *variant = host->variant; 3884956e109SRabin Vincent u32 clk = variant->clkreg; 389a6a6464aSLinus Walleij 390c58a8509SUlf Hansson /* Make sure cclk reflects the current calculated clock */ 391c58a8509SUlf Hansson host->cclk = 0; 392c58a8509SUlf Hansson 393a6a6464aSLinus Walleij if (desired) { 3943f4e6f7bSSrinivas Kandagatla if (variant->explicit_mclk_control) { 3953f4e6f7bSSrinivas Kandagatla host->cclk = host->mclk; 3963f4e6f7bSSrinivas Kandagatla } else if (desired >= host->mclk) { 397a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 398399bc486SLinus Walleij if (variant->st_clkdiv) 399399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 400a6a6464aSLinus Walleij host->cclk = host->mclk; 401b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 402b70a67f9SLinus Walleij /* 403b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 404b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 405b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 406b70a67f9SLinus Walleij * frequency 407b70a67f9SLinus Walleij */ 408b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 409b70a67f9SLinus Walleij if (clk >= 256) 410b70a67f9SLinus Walleij clk = 255; 411b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 412a6a6464aSLinus Walleij } else { 413b70a67f9SLinus Walleij /* 414b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 415b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 416b70a67f9SLinus Walleij */ 417a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 418a6a6464aSLinus Walleij if (clk >= 256) 419a6a6464aSLinus Walleij clk = 255; 420a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 421a6a6464aSLinus Walleij } 4224380c14fSRabin Vincent 4234380c14fSRabin Vincent clk |= variant->clkreg_enable; 424a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 425a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 426a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 427a6a6464aSLinus Walleij } 428a6a6464aSLinus Walleij 429c58a8509SUlf Hansson /* Set actual clock for debug */ 430c58a8509SUlf Hansson host->mmc->actual_clock = host->cclk; 431c58a8509SUlf Hansson 4329e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 433771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 434771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 435e1412d85SSrinivas Kandagatla clk |= variant->clkreg_8bit_bus_enable; 4369e6c82cdSLinus Walleij 4376dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 4386dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 439e8740644SSrinivas Kandagatla clk |= variant->clkreg_neg_edge_enable; 4406dbb6ee0SUlf Hansson 4417437cfa5SUlf Hansson mmci_write_clkreg(host, clk); 442a6a6464aSLinus Walleij } 443a6a6464aSLinus Walleij 444c3647fdcSLudovic Barre void mmci_dma_release(struct mmci_host *host) 445c3647fdcSLudovic Barre { 446c3647fdcSLudovic Barre if (host->ops && host->ops->dma_release) 447c3647fdcSLudovic Barre host->ops->dma_release(host); 448c3647fdcSLudovic Barre 449c3647fdcSLudovic Barre host->use_dma = false; 450c3647fdcSLudovic Barre } 451c3647fdcSLudovic Barre 452c3647fdcSLudovic Barre void mmci_dma_setup(struct mmci_host *host) 453c3647fdcSLudovic Barre { 454c3647fdcSLudovic Barre if (!host->ops || !host->ops->dma_setup) 455c3647fdcSLudovic Barre return; 456c3647fdcSLudovic Barre 457c3647fdcSLudovic Barre if (host->ops->dma_setup(host)) 458c3647fdcSLudovic Barre return; 459c3647fdcSLudovic Barre 460a813f2a2SLudovic Barre /* initialize pre request cookie */ 461a813f2a2SLudovic Barre host->next_cookie = 1; 462a813f2a2SLudovic Barre 463c3647fdcSLudovic Barre host->use_dma = true; 464c3647fdcSLudovic Barre } 465c3647fdcSLudovic Barre 466e0da1721SLudovic Barre /* 467e0da1721SLudovic Barre * Validate mmc prerequisites 468e0da1721SLudovic Barre */ 469e0da1721SLudovic Barre static int mmci_validate_data(struct mmci_host *host, 470e0da1721SLudovic Barre struct mmc_data *data) 471e0da1721SLudovic Barre { 472e0da1721SLudovic Barre if (!data) 473e0da1721SLudovic Barre return 0; 474e0da1721SLudovic Barre 475e0da1721SLudovic Barre if (!is_power_of_2(data->blksz)) { 476e0da1721SLudovic Barre dev_err(mmc_dev(host->mmc), 477e0da1721SLudovic Barre "unsupported block size (%d bytes)\n", data->blksz); 478e0da1721SLudovic Barre return -EINVAL; 479e0da1721SLudovic Barre } 480e0da1721SLudovic Barre 481e0da1721SLudovic Barre if (host->ops && host->ops->validate_data) 482e0da1721SLudovic Barre return host->ops->validate_data(host, data); 483e0da1721SLudovic Barre 484e0da1721SLudovic Barre return 0; 485e0da1721SLudovic Barre } 486e0da1721SLudovic Barre 48747983510SLudovic Barre int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 48847983510SLudovic Barre { 48947983510SLudovic Barre int err; 49047983510SLudovic Barre 49147983510SLudovic Barre if (!host->ops || !host->ops->prep_data) 49247983510SLudovic Barre return 0; 49347983510SLudovic Barre 49447983510SLudovic Barre err = host->ops->prep_data(host, data, next); 49547983510SLudovic Barre 49647983510SLudovic Barre if (next && !err) 49747983510SLudovic Barre data->host_cookie = ++host->next_cookie < 0 ? 49847983510SLudovic Barre 1 : host->next_cookie; 49947983510SLudovic Barre 50047983510SLudovic Barre return err; 50147983510SLudovic Barre } 50247983510SLudovic Barre 50347983510SLudovic Barre void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 50447983510SLudovic Barre int err) 50547983510SLudovic Barre { 50647983510SLudovic Barre if (host->ops && host->ops->unprep_data) 50747983510SLudovic Barre host->ops->unprep_data(host, data, err); 50847983510SLudovic Barre 50947983510SLudovic Barre data->host_cookie = 0; 51047983510SLudovic Barre } 51147983510SLudovic Barre 51202769968SLudovic Barre void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 51302769968SLudovic Barre { 51402769968SLudovic Barre WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 51502769968SLudovic Barre 51602769968SLudovic Barre if (host->ops && host->ops->get_next_data) 51702769968SLudovic Barre host->ops->get_next_data(host, data); 51802769968SLudovic Barre } 51902769968SLudovic Barre 520135ea30eSLudovic Barre int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 521135ea30eSLudovic Barre { 522135ea30eSLudovic Barre struct mmc_data *data = host->data; 523135ea30eSLudovic Barre int ret; 524135ea30eSLudovic Barre 525135ea30eSLudovic Barre if (!host->use_dma) 526135ea30eSLudovic Barre return -EINVAL; 527135ea30eSLudovic Barre 528135ea30eSLudovic Barre ret = mmci_prep_data(host, data, false); 529135ea30eSLudovic Barre if (ret) 530135ea30eSLudovic Barre return ret; 531135ea30eSLudovic Barre 532135ea30eSLudovic Barre if (!host->ops || !host->ops->dma_start) 533135ea30eSLudovic Barre return -EINVAL; 534135ea30eSLudovic Barre 535135ea30eSLudovic Barre /* Okay, go for it. */ 536135ea30eSLudovic Barre dev_vdbg(mmc_dev(host->mmc), 537135ea30eSLudovic Barre "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 538135ea30eSLudovic Barre data->sg_len, data->blksz, data->blocks, data->flags); 539135ea30eSLudovic Barre 540135ea30eSLudovic Barre host->ops->dma_start(host, &datactrl); 541135ea30eSLudovic Barre 542135ea30eSLudovic Barre /* Trigger the DMA transfer */ 543135ea30eSLudovic Barre mmci_write_datactrlreg(host, datactrl); 544135ea30eSLudovic Barre 545135ea30eSLudovic Barre /* 546135ea30eSLudovic Barre * Let the MMCI say when the data is ended and it's time 547135ea30eSLudovic Barre * to fire next DMA request. When that happens, MMCI will 548135ea30eSLudovic Barre * call mmci_data_end() 549135ea30eSLudovic Barre */ 550135ea30eSLudovic Barre writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 551135ea30eSLudovic Barre host->base + MMCIMASK0); 552135ea30eSLudovic Barre return 0; 553135ea30eSLudovic Barre } 554135ea30eSLudovic Barre 5555a9f10c3SLudovic Barre void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 5565a9f10c3SLudovic Barre { 5575a9f10c3SLudovic Barre if (!host->use_dma) 5585a9f10c3SLudovic Barre return; 5595a9f10c3SLudovic Barre 5605a9f10c3SLudovic Barre if (host->ops && host->ops->dma_finalize) 5615a9f10c3SLudovic Barre host->ops->dma_finalize(host, data); 5625a9f10c3SLudovic Barre } 5635a9f10c3SLudovic Barre 564cfccc6acSLudovic Barre void mmci_dma_error(struct mmci_host *host) 565cfccc6acSLudovic Barre { 566cfccc6acSLudovic Barre if (!host->use_dma) 567cfccc6acSLudovic Barre return; 568cfccc6acSLudovic Barre 569cfccc6acSLudovic Barre if (host->ops && host->ops->dma_error) 570cfccc6acSLudovic Barre host->ops->dma_error(host); 571cfccc6acSLudovic Barre } 572cfccc6acSLudovic Barre 5731c6a0718SPierre Ossman static void 5741c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 5751c6a0718SPierre Ossman { 5761c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 5771c6a0718SPierre Ossman 5781c6a0718SPierre Ossman BUG_ON(host->data); 5791c6a0718SPierre Ossman 5801c6a0718SPierre Ossman host->mrq = NULL; 5811c6a0718SPierre Ossman host->cmd = NULL; 5821c6a0718SPierre Ossman 5831c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 5841c6a0718SPierre Ossman } 5851c6a0718SPierre Ossman 5862686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 5872686b4b4SLinus Walleij { 5882686b4b4SLinus Walleij void __iomem *base = host->base; 5896ea9cdf3SPatrice Chotard struct variant_data *variant = host->variant; 5902686b4b4SLinus Walleij 5912686b4b4SLinus Walleij if (host->singleirq) { 5922686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 5932686b4b4SLinus Walleij 59459db5e2dSLudovic Barre mask0 &= ~variant->irq_pio_mask; 5952686b4b4SLinus Walleij mask0 |= mask; 5962686b4b4SLinus Walleij 5972686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 5982686b4b4SLinus Walleij } 5992686b4b4SLinus Walleij 6006ea9cdf3SPatrice Chotard if (variant->mmcimask1) 6012686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 6026ea9cdf3SPatrice Chotard 6036ea9cdf3SPatrice Chotard host->mask1_reg = mask; 6042686b4b4SLinus Walleij } 6052686b4b4SLinus Walleij 6061c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 6071c6a0718SPierre Ossman { 6089cc639a2SUlf Hansson mmci_write_datactrlreg(host, 0); 6092686b4b4SLinus Walleij mmci_set_mask1(host, 0); 6101c6a0718SPierre Ossman host->data = NULL; 6111c6a0718SPierre Ossman } 6121c6a0718SPierre Ossman 6134ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 6144ce1d6cbSRabin Vincent { 6154ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 6164ce1d6cbSRabin Vincent 6174ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 6184ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 6194ce1d6cbSRabin Vincent else 6204ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 6214ce1d6cbSRabin Vincent 6224ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 6234ce1d6cbSRabin Vincent } 6244ce1d6cbSRabin Vincent 625c8ebae37SRussell King /* 626c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 627c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 628c8ebae37SRussell King * no custom DMA interfaces are supported. 629c8ebae37SRussell King */ 630c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 631a813f2a2SLudovic Barre struct mmci_dmae_next { 632a813f2a2SLudovic Barre struct dma_async_tx_descriptor *desc; 633a813f2a2SLudovic Barre struct dma_chan *chan; 634a813f2a2SLudovic Barre }; 635a813f2a2SLudovic Barre 636a813f2a2SLudovic Barre struct mmci_dmae_priv { 637a813f2a2SLudovic Barre struct dma_chan *cur; 638a813f2a2SLudovic Barre struct dma_chan *rx_channel; 639a813f2a2SLudovic Barre struct dma_chan *tx_channel; 640a813f2a2SLudovic Barre struct dma_async_tx_descriptor *desc_current; 641a813f2a2SLudovic Barre struct mmci_dmae_next next_data; 642a813f2a2SLudovic Barre }; 643a813f2a2SLudovic Barre 644c3647fdcSLudovic Barre int mmci_dmae_setup(struct mmci_host *host) 645c8ebae37SRussell King { 646c8ebae37SRussell King const char *rxname, *txname; 647a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae; 648c8ebae37SRussell King 649a813f2a2SLudovic Barre dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 650a813f2a2SLudovic Barre if (!dmae) 651a813f2a2SLudovic Barre return -ENOMEM; 652c8ebae37SRussell King 653a813f2a2SLudovic Barre host->dma_priv = dmae; 654a813f2a2SLudovic Barre 655a813f2a2SLudovic Barre dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 656a813f2a2SLudovic Barre "rx"); 657a813f2a2SLudovic Barre dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 658a813f2a2SLudovic Barre "tx"); 65958c7ccbfSPer Forlin 6601fd83f0eSLee Jones /* 6611fd83f0eSLee Jones * If only an RX channel is specified, the driver will 6621fd83f0eSLee Jones * attempt to use it bidirectionally, however if it is 6631fd83f0eSLee Jones * is specified but cannot be located, DMA will be disabled. 6641fd83f0eSLee Jones */ 665a813f2a2SLudovic Barre if (dmae->rx_channel && !dmae->tx_channel) 666a813f2a2SLudovic Barre dmae->tx_channel = dmae->rx_channel; 667c8ebae37SRussell King 668a813f2a2SLudovic Barre if (dmae->rx_channel) 669a813f2a2SLudovic Barre rxname = dma_chan_name(dmae->rx_channel); 670c8ebae37SRussell King else 671c8ebae37SRussell King rxname = "none"; 672c8ebae37SRussell King 673a813f2a2SLudovic Barre if (dmae->tx_channel) 674a813f2a2SLudovic Barre txname = dma_chan_name(dmae->tx_channel); 675c8ebae37SRussell King else 676c8ebae37SRussell King txname = "none"; 677c8ebae37SRussell King 678c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 679c8ebae37SRussell King rxname, txname); 680c8ebae37SRussell King 681c8ebae37SRussell King /* 682c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 683c8ebae37SRussell King * the parameters of the DMA engine device. 684c8ebae37SRussell King */ 685a813f2a2SLudovic Barre if (dmae->tx_channel) { 686a813f2a2SLudovic Barre struct device *dev = dmae->tx_channel->device->dev; 687c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 688c8ebae37SRussell King 689c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 690c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 691c8ebae37SRussell King } 692a813f2a2SLudovic Barre if (dmae->rx_channel) { 693a813f2a2SLudovic Barre struct device *dev = dmae->rx_channel->device->dev; 694c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 695c8ebae37SRussell King 696c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 697c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 698c8ebae37SRussell King } 6999cb15142SSrinivas Kandagatla 700a813f2a2SLudovic Barre if (!dmae->tx_channel || !dmae->rx_channel) { 701c3647fdcSLudovic Barre mmci_dmae_release(host); 702c3647fdcSLudovic Barre return -EINVAL; 703c3647fdcSLudovic Barre } 704c3647fdcSLudovic Barre 705c3647fdcSLudovic Barre return 0; 706c8ebae37SRussell King } 707c8ebae37SRussell King 708c8ebae37SRussell King /* 7096e0ee714SBill Pemberton * This is used in or so inline it 710c8ebae37SRussell King * so it can be discarded. 711c8ebae37SRussell King */ 712c3647fdcSLudovic Barre void mmci_dmae_release(struct mmci_host *host) 713c8ebae37SRussell King { 714a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 715a813f2a2SLudovic Barre 716a813f2a2SLudovic Barre if (dmae->rx_channel) 717a813f2a2SLudovic Barre dma_release_channel(dmae->rx_channel); 718a813f2a2SLudovic Barre if (dmae->tx_channel) 719a813f2a2SLudovic Barre dma_release_channel(dmae->tx_channel); 720a813f2a2SLudovic Barre dmae->rx_channel = dmae->tx_channel = NULL; 721c8ebae37SRussell King } 722c8ebae37SRussell King 723c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 724c8ebae37SRussell King { 725a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 726653a761eSUlf Hansson struct dma_chan *chan; 727653a761eSUlf Hansson 728feeef096SHeiner Kallweit if (data->flags & MMC_DATA_READ) 729a813f2a2SLudovic Barre chan = dmae->rx_channel; 730feeef096SHeiner Kallweit else 731a813f2a2SLudovic Barre chan = dmae->tx_channel; 732653a761eSUlf Hansson 733feeef096SHeiner Kallweit dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 734feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 735653a761eSUlf Hansson } 736653a761eSUlf Hansson 737cfccc6acSLudovic Barre void mmci_dmae_error(struct mmci_host *host) 7387b2a6d51SLudovic Barre { 739a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 740a813f2a2SLudovic Barre 741cfccc6acSLudovic Barre if (!dma_inprogress(host)) 742cdea1947SLudovic Barre return; 743cdea1947SLudovic Barre 7447b2a6d51SLudovic Barre dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 745a813f2a2SLudovic Barre dmaengine_terminate_all(dmae->cur); 7467b2a6d51SLudovic Barre host->dma_in_progress = false; 747a813f2a2SLudovic Barre dmae->cur = NULL; 748a813f2a2SLudovic Barre dmae->desc_current = NULL; 7497b2a6d51SLudovic Barre host->data->host_cookie = 0; 7507b2a6d51SLudovic Barre 7517b2a6d51SLudovic Barre mmci_dma_unmap(host, host->data); 7527b2a6d51SLudovic Barre } 7537b2a6d51SLudovic Barre 7545a9f10c3SLudovic Barre void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 755653a761eSUlf Hansson { 756a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 757c8ebae37SRussell King u32 status; 758c8ebae37SRussell King int i; 759c8ebae37SRussell King 7605a9f10c3SLudovic Barre if (!dma_inprogress(host)) 761cdea1947SLudovic Barre return; 762cdea1947SLudovic Barre 763c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 764c8ebae37SRussell King for (i = 0; ; i++) { 765c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 766c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 767c8ebae37SRussell King break; 768c8ebae37SRussell King udelay(10); 769c8ebae37SRussell King } 770c8ebae37SRussell King 771c8ebae37SRussell King /* 772c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 773c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 774c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 775c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 776c8ebae37SRussell King */ 777c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 778cfccc6acSLudovic Barre mmci_dma_error(host); 779c8ebae37SRussell King if (!data->error) 780c8ebae37SRussell King data->error = -EIO; 7817b2a6d51SLudovic Barre } else if (!data->host_cookie) { 782653a761eSUlf Hansson mmci_dma_unmap(host, data); 7837b2a6d51SLudovic Barre } 784c8ebae37SRussell King 785c8ebae37SRussell King /* 786c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 787c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 788c8ebae37SRussell King */ 789c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 790c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 791c8ebae37SRussell King mmci_dma_release(host); 792c8ebae37SRussell King } 793653a761eSUlf Hansson 794e13934bdSLinus Walleij host->dma_in_progress = false; 795a813f2a2SLudovic Barre dmae->cur = NULL; 796a813f2a2SLudovic Barre dmae->desc_current = NULL; 797c8ebae37SRussell King } 798c8ebae37SRussell King 799653a761eSUlf Hansson /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 80047983510SLudovic Barre static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 801653a761eSUlf Hansson struct dma_chan **dma_chan, 802653a761eSUlf Hansson struct dma_async_tx_descriptor **dma_desc) 803c8ebae37SRussell King { 804a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 805c8ebae37SRussell King struct variant_data *variant = host->variant; 806c8ebae37SRussell King struct dma_slave_config conf = { 807c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 808c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 809c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 810c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 811c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 812c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 813258aea76SViresh Kumar .device_fc = false, 814c8ebae37SRussell King }; 815c8ebae37SRussell King struct dma_chan *chan; 816c8ebae37SRussell King struct dma_device *device; 817c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 818c8ebae37SRussell King int nr_sg; 8199cb15142SSrinivas Kandagatla unsigned long flags = DMA_CTRL_ACK; 820c8ebae37SRussell King 821c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 82205f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 823a813f2a2SLudovic Barre chan = dmae->rx_channel; 824c8ebae37SRussell King } else { 82505f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 826a813f2a2SLudovic Barre chan = dmae->tx_channel; 827c8ebae37SRussell King } 828c8ebae37SRussell King 829c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 830c8ebae37SRussell King if (!chan) 831c8ebae37SRussell King return -EINVAL; 832c8ebae37SRussell King 833c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 83458c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 835c8ebae37SRussell King return -EINVAL; 836c8ebae37SRussell King 837c8ebae37SRussell King device = chan->device; 838feeef096SHeiner Kallweit nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 839feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 840c8ebae37SRussell King if (nr_sg == 0) 841c8ebae37SRussell King return -EINVAL; 842c8ebae37SRussell King 8439cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 8449cb15142SSrinivas Kandagatla flags |= DMA_PREP_INTERRUPT; 8459cb15142SSrinivas Kandagatla 846c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 84716052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 8489cb15142SSrinivas Kandagatla conf.direction, flags); 849c8ebae37SRussell King if (!desc) 850c8ebae37SRussell King goto unmap_exit; 851c8ebae37SRussell King 852653a761eSUlf Hansson *dma_chan = chan; 853653a761eSUlf Hansson *dma_desc = desc; 854c8ebae37SRussell King 85558c7ccbfSPer Forlin return 0; 85658c7ccbfSPer Forlin 85758c7ccbfSPer Forlin unmap_exit: 858feeef096SHeiner Kallweit dma_unmap_sg(device->dev, data->sg, data->sg_len, 859feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 86058c7ccbfSPer Forlin return -ENOMEM; 86158c7ccbfSPer Forlin } 86258c7ccbfSPer Forlin 86347983510SLudovic Barre int mmci_dmae_prep_data(struct mmci_host *host, 864ad7b8918SLudovic Barre struct mmc_data *data, 865ad7b8918SLudovic Barre bool next) 866653a761eSUlf Hansson { 867a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 868ad7b8918SLudovic Barre struct mmci_dmae_next *nd = &dmae->next_data; 869a813f2a2SLudovic Barre 87047983510SLudovic Barre if (!host->use_dma) 87147983510SLudovic Barre return -EINVAL; 87247983510SLudovic Barre 873ad7b8918SLudovic Barre if (next) 87447983510SLudovic Barre return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 875653a761eSUlf Hansson /* Check if next job is already prepared. */ 876a813f2a2SLudovic Barre if (dmae->cur && dmae->desc_current) 877653a761eSUlf Hansson return 0; 878653a761eSUlf Hansson 879653a761eSUlf Hansson /* No job were prepared thus do it now. */ 88047983510SLudovic Barre return _mmci_dmae_prep_data(host, data, &dmae->cur, 881a813f2a2SLudovic Barre &dmae->desc_current); 882653a761eSUlf Hansson } 883653a761eSUlf Hansson 884135ea30eSLudovic Barre int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 88558c7ccbfSPer Forlin { 886a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 88758c7ccbfSPer Forlin struct mmc_data *data = host->data; 88858c7ccbfSPer Forlin 889e13934bdSLinus Walleij host->dma_in_progress = true; 890a813f2a2SLudovic Barre dmaengine_submit(dmae->desc_current); 891a813f2a2SLudovic Barre dma_async_issue_pending(dmae->cur); 892c8ebae37SRussell King 8939cb15142SSrinivas Kandagatla if (host->variant->qcom_dml) 8949cb15142SSrinivas Kandagatla dml_start_xfer(host, data); 8959cb15142SSrinivas Kandagatla 896135ea30eSLudovic Barre *datactrl |= MCI_DPSM_DMAENABLE; 897c8ebae37SRussell King 898c8ebae37SRussell King return 0; 899c8ebae37SRussell King } 90058c7ccbfSPer Forlin 90102769968SLudovic Barre void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 90258c7ccbfSPer Forlin { 903a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 904a813f2a2SLudovic Barre struct mmci_dmae_next *next = &dmae->next_data; 90558c7ccbfSPer Forlin 906c3647fdcSLudovic Barre if (!host->use_dma) 907c3647fdcSLudovic Barre return; 908c3647fdcSLudovic Barre 909a813f2a2SLudovic Barre WARN_ON(!data->host_cookie && (next->desc || next->chan)); 91058c7ccbfSPer Forlin 911a813f2a2SLudovic Barre dmae->desc_current = next->desc; 912a813f2a2SLudovic Barre dmae->cur = next->chan; 913a813f2a2SLudovic Barre next->desc = NULL; 914a813f2a2SLudovic Barre next->chan = NULL; 91558c7ccbfSPer Forlin } 91658c7ccbfSPer Forlin 91747983510SLudovic Barre void mmci_dmae_unprep_data(struct mmci_host *host, 91847983510SLudovic Barre struct mmc_data *data, int err) 91947983510SLudovic Barre 92058c7ccbfSPer Forlin { 921a813f2a2SLudovic Barre struct mmci_dmae_priv *dmae = host->dma_priv; 92258c7ccbfSPer Forlin 92347983510SLudovic Barre if (!host->use_dma) 92458c7ccbfSPer Forlin return; 92558c7ccbfSPer Forlin 926653a761eSUlf Hansson mmci_dma_unmap(host, data); 927653a761eSUlf Hansson 928653a761eSUlf Hansson if (err) { 929a813f2a2SLudovic Barre struct mmci_dmae_next *next = &dmae->next_data; 930653a761eSUlf Hansson struct dma_chan *chan; 931653a761eSUlf Hansson if (data->flags & MMC_DATA_READ) 932a813f2a2SLudovic Barre chan = dmae->rx_channel; 933653a761eSUlf Hansson else 934a813f2a2SLudovic Barre chan = dmae->tx_channel; 93558c7ccbfSPer Forlin dmaengine_terminate_all(chan); 936653a761eSUlf Hansson 937a813f2a2SLudovic Barre if (dmae->desc_current == next->desc) 938a813f2a2SLudovic Barre dmae->desc_current = NULL; 939b5c16a60SSrinivas Kandagatla 940a813f2a2SLudovic Barre if (dmae->cur == next->chan) { 941e13934bdSLinus Walleij host->dma_in_progress = false; 942a813f2a2SLudovic Barre dmae->cur = NULL; 943e13934bdSLinus Walleij } 944b5c16a60SSrinivas Kandagatla 945a813f2a2SLudovic Barre next->desc = NULL; 946a813f2a2SLudovic Barre next->chan = NULL; 94758c7ccbfSPer Forlin } 94858c7ccbfSPer Forlin } 94958c7ccbfSPer Forlin 950c3647fdcSLudovic Barre static struct mmci_host_ops mmci_variant_ops = { 95147983510SLudovic Barre .prep_data = mmci_dmae_prep_data, 95247983510SLudovic Barre .unprep_data = mmci_dmae_unprep_data, 95302769968SLudovic Barre .get_next_data = mmci_dmae_get_next_data, 954c3647fdcSLudovic Barre .dma_setup = mmci_dmae_setup, 955c3647fdcSLudovic Barre .dma_release = mmci_dmae_release, 956135ea30eSLudovic Barre .dma_start = mmci_dmae_start, 9575a9f10c3SLudovic Barre .dma_finalize = mmci_dmae_finalize, 958cfccc6acSLudovic Barre .dma_error = mmci_dmae_error, 959c3647fdcSLudovic Barre }; 960c3647fdcSLudovic Barre 961c3647fdcSLudovic Barre void mmci_variant_init(struct mmci_host *host) 962c3647fdcSLudovic Barre { 963c3647fdcSLudovic Barre host->ops = &mmci_variant_ops; 964c3647fdcSLudovic Barre } 965c8ebae37SRussell King #endif 966c8ebae37SRussell King 96747983510SLudovic Barre static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 96847983510SLudovic Barre { 96947983510SLudovic Barre struct mmci_host *host = mmc_priv(mmc); 97047983510SLudovic Barre struct mmc_data *data = mrq->data; 97147983510SLudovic Barre 97247983510SLudovic Barre if (!data) 97347983510SLudovic Barre return; 97447983510SLudovic Barre 97547983510SLudovic Barre WARN_ON(data->host_cookie); 97647983510SLudovic Barre 97747983510SLudovic Barre if (mmci_validate_data(host, data)) 97847983510SLudovic Barre return; 97947983510SLudovic Barre 98047983510SLudovic Barre mmci_prep_data(host, data, true); 98147983510SLudovic Barre } 98247983510SLudovic Barre 98347983510SLudovic Barre static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 98447983510SLudovic Barre int err) 98547983510SLudovic Barre { 98647983510SLudovic Barre struct mmci_host *host = mmc_priv(mmc); 98747983510SLudovic Barre struct mmc_data *data = mrq->data; 98847983510SLudovic Barre 98947983510SLudovic Barre if (!data || !data->host_cookie) 99047983510SLudovic Barre return; 99147983510SLudovic Barre 99247983510SLudovic Barre mmci_unprep_data(host, data, err); 99347983510SLudovic Barre } 99447983510SLudovic Barre 9951c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 9961c6a0718SPierre Ossman { 9978301bb68SRabin Vincent struct variant_data *variant = host->variant; 9981c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 9991c6a0718SPierre Ossman unsigned long long clks; 10001c6a0718SPierre Ossman void __iomem *base; 10011c6a0718SPierre Ossman int blksz_bits; 10021c6a0718SPierre Ossman 100364de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 10041c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 10051c6a0718SPierre Ossman 10061c6a0718SPierre Ossman host->data = data; 1007528320dbSRabin Vincent host->size = data->blksz * data->blocks; 100851d4375dSRussell King data->bytes_xfered = 0; 10091c6a0718SPierre Ossman 10101c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 1011c4a35769SSrinivas Kandagatla do_div(clks, NSEC_PER_SEC); 10121c6a0718SPierre Ossman 10131c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 10141c6a0718SPierre Ossman 10151c6a0718SPierre Ossman base = host->base; 10161c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 10171c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 10181c6a0718SPierre Ossman 10191c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 10201c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 10211c6a0718SPierre Ossman 10221784b157SPhilippe Langlais if (variant->blksz_datactrl16) 10239b279941SLudovic Barre datactrl = variant->datactrl_dpsm_enable | (data->blksz << 16); 1024ff783233SSrinivas Kandagatla else if (variant->blksz_datactrl4) 10259b279941SLudovic Barre datactrl = variant->datactrl_dpsm_enable | (data->blksz << 4); 10261784b157SPhilippe Langlais else 10279b279941SLudovic Barre datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; 1028c8ebae37SRussell King 1029c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 10301c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 1031c8ebae37SRussell King 1032c7354133SSrinivas Kandagatla if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 103306c1a121SUlf Hansson u32 clk; 1034c7354133SSrinivas Kandagatla 10355df014dfSSrinivas Kandagatla datactrl |= variant->datactrl_mask_sdio; 10367258db7eSUlf Hansson 1037c8ebae37SRussell King /* 103870ac0935SUlf Hansson * The ST Micro variant for SDIO small write transfers 103970ac0935SUlf Hansson * needs to have clock H/W flow control disabled, 104070ac0935SUlf Hansson * otherwise the transfer will not start. The threshold 104170ac0935SUlf Hansson * depends on the rate of MCLK. 104206c1a121SUlf Hansson */ 1043c7354133SSrinivas Kandagatla if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 104470ac0935SUlf Hansson (host->size < 8 || 104570ac0935SUlf Hansson (host->size <= 8 && host->mclk > 50000000))) 104606c1a121SUlf Hansson clk = host->clk_reg & ~variant->clkreg_enable; 104706c1a121SUlf Hansson else 104806c1a121SUlf Hansson clk = host->clk_reg | variant->clkreg_enable; 104906c1a121SUlf Hansson 105006c1a121SUlf Hansson mmci_write_clkreg(host, clk); 105106c1a121SUlf Hansson } 105206c1a121SUlf Hansson 10536dad6c95SSeungwon Jeon if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 10546dad6c95SSeungwon Jeon host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1055e17dca2bSSrinivas Kandagatla datactrl |= variant->datactrl_mask_ddrmode; 10566dbb6ee0SUlf Hansson 105706c1a121SUlf Hansson /* 1058c8ebae37SRussell King * Attempt to use DMA operation mode, if this 1059c8ebae37SRussell King * should fail, fall back to PIO mode 1060c8ebae37SRussell King */ 1061135ea30eSLudovic Barre if (!mmci_dma_start(host, datactrl)) 1062c8ebae37SRussell King return; 1063c8ebae37SRussell King 1064c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 1065c8ebae37SRussell King mmci_init_sg(host, data); 1066c8ebae37SRussell King 1067c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 10681c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 10691c6a0718SPierre Ossman 10701c6a0718SPierre Ossman /* 1071c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 1072c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 1073c4d877c1SRussell King * is available. 10741c6a0718SPierre Ossman */ 1075c4d877c1SRussell King if (host->size < variant->fifohalfsize) 10761c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 10771c6a0718SPierre Ossman } else { 10781c6a0718SPierre Ossman /* 10791c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 10801c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 10811c6a0718SPierre Ossman */ 10821c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 10831c6a0718SPierre Ossman } 10841c6a0718SPierre Ossman 10859cc639a2SUlf Hansson mmci_write_datactrlreg(host, datactrl); 10861c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 10872686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 10881c6a0718SPierre Ossman } 10891c6a0718SPierre Ossman 10901c6a0718SPierre Ossman static void 10911c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 10921c6a0718SPierre Ossman { 10931c6a0718SPierre Ossman void __iomem *base = host->base; 10941c6a0718SPierre Ossman 109564de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 10961c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 10971c6a0718SPierre Ossman 10980f244804SLudovic Barre if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 10991c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 11006adb2a80SSrinivas Kandagatla mmci_reg_delay(host); 11011c6a0718SPierre Ossman } 11021c6a0718SPierre Ossman 11030f244804SLudovic Barre c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 11041c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 11051c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 11060f244804SLudovic Barre c |= host->variant->cmdreg_lrsp_crc; 11070f244804SLudovic Barre else if (cmd->flags & MMC_RSP_CRC) 11080f244804SLudovic Barre c |= host->variant->cmdreg_srsp_crc; 11090f244804SLudovic Barre else 11100f244804SLudovic Barre c |= host->variant->cmdreg_srsp; 11111c6a0718SPierre Ossman } 11121c6a0718SPierre Ossman if (/*interrupt*/0) 11131c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 11141c6a0718SPierre Ossman 1115ae7b0061SSrinivas Kandagatla if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1116ae7b0061SSrinivas Kandagatla c |= host->variant->data_cmd_enable; 1117ae7b0061SSrinivas Kandagatla 11181c6a0718SPierre Ossman host->cmd = cmd; 11191c6a0718SPierre Ossman 11201c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 11211c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 11221c6a0718SPierre Ossman } 11231c6a0718SPierre Ossman 11241c6a0718SPierre Ossman static void 11251c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 11261c6a0718SPierre Ossman unsigned int status) 11271c6a0718SPierre Ossman { 1128daf9713cSLudovic Barre unsigned int status_err; 1129daf9713cSLudovic Barre 11301cb9da50SUlf Hansson /* Make sure we have data to handle */ 11311cb9da50SUlf Hansson if (!data) 11321cb9da50SUlf Hansson return; 11331cb9da50SUlf Hansson 1134f20f8f21SLinus Walleij /* First check for errors */ 1135daf9713cSLudovic Barre status_err = status & (host->variant->start_err | 1136daf9713cSLudovic Barre MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1137daf9713cSLudovic Barre MCI_TXUNDERRUN | MCI_RXOVERRUN); 1138daf9713cSLudovic Barre 1139daf9713cSLudovic Barre if (status_err) { 11408cb28155SLinus Walleij u32 remain, success; 1141f20f8f21SLinus Walleij 1142c8ebae37SRussell King /* Terminate the DMA transfer */ 1143cfccc6acSLudovic Barre mmci_dma_error(host); 1144c8ebae37SRussell King 1145c8afc9d5SRussell King /* 1146c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 1147c8afc9d5SRussell King * the data counter gives the number of bytes transferred 1148c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 1149c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 1150c8afc9d5SRussell King * matters for FIFO overruns only. 1151c8afc9d5SRussell King */ 1152b79220b3SLudovic Barre if (!host->variant->datacnt_useless) { 1153f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 11548cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 1155b79220b3SLudovic Barre } else { 1156b79220b3SLudovic Barre success = 0; 1157b79220b3SLudovic Barre } 11588cb28155SLinus Walleij 1159c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1160daf9713cSLudovic Barre status_err, success); 1161daf9713cSLudovic Barre if (status_err & MCI_DATACRCFAIL) { 11628cb28155SLinus Walleij /* Last block was not successful */ 1163c8afc9d5SRussell King success -= 1; 116417b0429dSPierre Ossman data->error = -EILSEQ; 1165daf9713cSLudovic Barre } else if (status_err & MCI_DATATIMEOUT) { 116617b0429dSPierre Ossman data->error = -ETIMEDOUT; 1167daf9713cSLudovic Barre } else if (status_err & MCI_STARTBITERR) { 1168757df746SLinus Walleij data->error = -ECOMM; 1169daf9713cSLudovic Barre } else if (status_err & MCI_TXUNDERRUN) { 117017b0429dSPierre Ossman data->error = -EIO; 1171daf9713cSLudovic Barre } else if (status_err & MCI_RXOVERRUN) { 1172c8afc9d5SRussell King if (success > host->variant->fifosize) 1173c8afc9d5SRussell King success -= host->variant->fifosize; 1174c8afc9d5SRussell King else 1175c8afc9d5SRussell King success = 0; 11768cb28155SLinus Walleij data->error = -EIO; 11774ce1d6cbSRabin Vincent } 117851d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 11791c6a0718SPierre Ossman } 1180f20f8f21SLinus Walleij 11818cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 11828cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1183f20f8f21SLinus Walleij 1184ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 1185653a761eSUlf Hansson mmci_dma_finalize(host, data); 1186cdea1947SLudovic Barre 11871c6a0718SPierre Ossman mmci_stop_data(host); 11881c6a0718SPierre Ossman 11898cb28155SLinus Walleij if (!data->error) 11908cb28155SLinus Walleij /* The error clause is handled above, success! */ 119151d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 1192f20f8f21SLinus Walleij 119309b4f706SLudovic Barre if (!data->stop || (host->mrq->sbc && !data->error)) 11941c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 119509b4f706SLudovic Barre else 11961c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 11971c6a0718SPierre Ossman } 11981c6a0718SPierre Ossman } 11991c6a0718SPierre Ossman 12001c6a0718SPierre Ossman static void 12011c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 12021c6a0718SPierre Ossman unsigned int status) 12031c6a0718SPierre Ossman { 12041c6a0718SPierre Ossman void __iomem *base = host->base; 120549adc0caSLinus Walleij bool sbc; 1206ad82bfeaSUlf Hansson 1207ad82bfeaSUlf Hansson if (!cmd) 1208ad82bfeaSUlf Hansson return; 1209ad82bfeaSUlf Hansson 1210ad82bfeaSUlf Hansson sbc = (cmd == host->mrq->sbc); 1211ad82bfeaSUlf Hansson 121249adc0caSLinus Walleij /* 121349adc0caSLinus Walleij * We need to be one of these interrupts to be considered worth 121449adc0caSLinus Walleij * handling. Note that we tag on any latent IRQs postponed 121549adc0caSLinus Walleij * due to waiting for busy status. 121649adc0caSLinus Walleij */ 121749adc0caSLinus Walleij if (!((status|host->busy_status) & 121849adc0caSLinus Walleij (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1219ad82bfeaSUlf Hansson return; 12208d94b54dSUlf Hansson 122149adc0caSLinus Walleij /* 122249adc0caSLinus Walleij * ST Micro variant: handle busy detection. 122349adc0caSLinus Walleij */ 122449adc0caSLinus Walleij if (host->variant->busy_detect) { 122549adc0caSLinus Walleij bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 122649adc0caSLinus Walleij 122749adc0caSLinus Walleij /* We are busy with a command, return */ 122849adc0caSLinus Walleij if (host->busy_status && 122949adc0caSLinus Walleij (status & host->variant->busy_detect_flag)) 12308d94b54dSUlf Hansson return; 12318d94b54dSUlf Hansson 123249adc0caSLinus Walleij /* 123349adc0caSLinus Walleij * We were not busy, but we now got a busy response on 123449adc0caSLinus Walleij * something that was not an error, and we double-check 123549adc0caSLinus Walleij * that the special busy status bit is still set before 123649adc0caSLinus Walleij * proceeding. 123749adc0caSLinus Walleij */ 12388d94b54dSUlf Hansson if (!host->busy_status && busy_resp && 12398d94b54dSUlf Hansson !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 124049adc0caSLinus Walleij (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 12415cad24d8SJean-Nicolas Graux 12425cad24d8SJean-Nicolas Graux /* Clear the busy start IRQ */ 12435cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 12445cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 12455cad24d8SJean-Nicolas Graux 12465cad24d8SJean-Nicolas Graux /* Unmask the busy end IRQ */ 124749adc0caSLinus Walleij writel(readl(base + MMCIMASK0) | 124849adc0caSLinus Walleij host->variant->busy_detect_mask, 12498d94b54dSUlf Hansson base + MMCIMASK0); 125049adc0caSLinus Walleij /* 125149adc0caSLinus Walleij * Now cache the last response status code (until 125249adc0caSLinus Walleij * the busy bit goes low), and return. 125349adc0caSLinus Walleij */ 125449adc0caSLinus Walleij host->busy_status = 125549adc0caSLinus Walleij status & (MCI_CMDSENT|MCI_CMDRESPEND); 12568d94b54dSUlf Hansson return; 12578d94b54dSUlf Hansson } 12588d94b54dSUlf Hansson 125949adc0caSLinus Walleij /* 126049adc0caSLinus Walleij * At this point we are not busy with a command, we have 12615cad24d8SJean-Nicolas Graux * not received a new busy request, clear and mask the busy 12625cad24d8SJean-Nicolas Graux * end IRQ and fall through to process the IRQ. 126349adc0caSLinus Walleij */ 12648d94b54dSUlf Hansson if (host->busy_status) { 12655cad24d8SJean-Nicolas Graux 12665cad24d8SJean-Nicolas Graux writel(host->variant->busy_detect_mask, 12675cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 12685cad24d8SJean-Nicolas Graux 126949adc0caSLinus Walleij writel(readl(base + MMCIMASK0) & 127049adc0caSLinus Walleij ~host->variant->busy_detect_mask, 12718d94b54dSUlf Hansson base + MMCIMASK0); 12728d94b54dSUlf Hansson host->busy_status = 0; 12738d94b54dSUlf Hansson } 127449adc0caSLinus Walleij } 12751c6a0718SPierre Ossman 12761c6a0718SPierre Ossman host->cmd = NULL; 12771c6a0718SPierre Ossman 12781c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 127917b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 12801c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 128117b0429dSPierre Ossman cmd->error = -EILSEQ; 12829047b435SRussell King - ARM Linux } else { 12839047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 12849047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 12859047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 12869047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 12871c6a0718SPierre Ossman } 12881c6a0718SPierre Ossman 1289024629c6SUlf Hansson if ((!sbc && !cmd->data) || cmd->error) { 12903b6e3c73SUlf Hansson if (host->data) { 12913b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 1292cfccc6acSLudovic Barre mmci_dma_error(host); 12937b2a6d51SLudovic Barre 12941c6a0718SPierre Ossman mmci_stop_data(host); 12953b6e3c73SUlf Hansson } 1296024629c6SUlf Hansson mmci_request_end(host, host->mrq); 1297024629c6SUlf Hansson } else if (sbc) { 1298024629c6SUlf Hansson mmci_start_command(host, host->mrq->cmd, 0); 1299d2141547SLudovic Barre } else if (!host->variant->datactrl_first && 1300d2141547SLudovic Barre !(cmd->data->flags & MMC_DATA_READ)) { 13011c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 13021c6a0718SPierre Ossman } 13031c6a0718SPierre Ossman } 13041c6a0718SPierre Ossman 13059c34b73dSSrinivas Kandagatla static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 13069c34b73dSSrinivas Kandagatla { 13079c34b73dSSrinivas Kandagatla return remain - (readl(host->base + MMCIFIFOCNT) << 2); 13089c34b73dSSrinivas Kandagatla } 13099c34b73dSSrinivas Kandagatla 13109c34b73dSSrinivas Kandagatla static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 13119c34b73dSSrinivas Kandagatla { 13129c34b73dSSrinivas Kandagatla /* 13139c34b73dSSrinivas Kandagatla * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 13149c34b73dSSrinivas Kandagatla * from the fifo range should be used 13159c34b73dSSrinivas Kandagatla */ 13169c34b73dSSrinivas Kandagatla if (status & MCI_RXFIFOHALFFULL) 13179c34b73dSSrinivas Kandagatla return host->variant->fifohalfsize; 13189c34b73dSSrinivas Kandagatla else if (status & MCI_RXDATAAVLBL) 13199c34b73dSSrinivas Kandagatla return 4; 13209c34b73dSSrinivas Kandagatla 13219c34b73dSSrinivas Kandagatla return 0; 13229c34b73dSSrinivas Kandagatla } 13239c34b73dSSrinivas Kandagatla 13241c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 13251c6a0718SPierre Ossman { 13261c6a0718SPierre Ossman void __iomem *base = host->base; 13271c6a0718SPierre Ossman char *ptr = buffer; 13289c34b73dSSrinivas Kandagatla u32 status = readl(host->base + MMCISTATUS); 132926eed9a5SLinus Walleij int host_remain = host->size; 13301c6a0718SPierre Ossman 13311c6a0718SPierre Ossman do { 13329c34b73dSSrinivas Kandagatla int count = host->get_rx_fifocnt(host, status, host_remain); 13331c6a0718SPierre Ossman 13341c6a0718SPierre Ossman if (count > remain) 13351c6a0718SPierre Ossman count = remain; 13361c6a0718SPierre Ossman 13371c6a0718SPierre Ossman if (count <= 0) 13381c6a0718SPierre Ossman break; 13391c6a0718SPierre Ossman 1340393e5e24SUlf Hansson /* 1341393e5e24SUlf Hansson * SDIO especially may want to send something that is 1342393e5e24SUlf Hansson * not divisible by 4 (as opposed to card sectors 1343393e5e24SUlf Hansson * etc). Therefore make sure to always read the last bytes 1344393e5e24SUlf Hansson * while only doing full 32-bit reads towards the FIFO. 1345393e5e24SUlf Hansson */ 1346393e5e24SUlf Hansson if (unlikely(count & 0x3)) { 1347393e5e24SUlf Hansson if (count < 4) { 1348393e5e24SUlf Hansson unsigned char buf[4]; 13494b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, buf, 1); 1350393e5e24SUlf Hansson memcpy(ptr, buf, count); 1351393e5e24SUlf Hansson } else { 13524b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1353393e5e24SUlf Hansson count &= ~0x3; 1354393e5e24SUlf Hansson } 1355393e5e24SUlf Hansson } else { 13564b85da08SDavide Ciminaghi ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1357393e5e24SUlf Hansson } 13581c6a0718SPierre Ossman 13591c6a0718SPierre Ossman ptr += count; 13601c6a0718SPierre Ossman remain -= count; 136126eed9a5SLinus Walleij host_remain -= count; 13621c6a0718SPierre Ossman 13631c6a0718SPierre Ossman if (remain == 0) 13641c6a0718SPierre Ossman break; 13651c6a0718SPierre Ossman 13661c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 13671c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 13681c6a0718SPierre Ossman 13691c6a0718SPierre Ossman return ptr - buffer; 13701c6a0718SPierre Ossman } 13711c6a0718SPierre Ossman 13721c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 13731c6a0718SPierre Ossman { 13748301bb68SRabin Vincent struct variant_data *variant = host->variant; 13751c6a0718SPierre Ossman void __iomem *base = host->base; 13761c6a0718SPierre Ossman char *ptr = buffer; 13771c6a0718SPierre Ossman 13781c6a0718SPierre Ossman do { 13791c6a0718SPierre Ossman unsigned int count, maxcnt; 13801c6a0718SPierre Ossman 13818301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 13828301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 13831c6a0718SPierre Ossman count = min(remain, maxcnt); 13841c6a0718SPierre Ossman 138534177802SLinus Walleij /* 138634177802SLinus Walleij * SDIO especially may want to send something that is 138734177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 138834177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 138934177802SLinus Walleij * So compensate by adding +3 on the count, a single 139034177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 139134177802SLinus Walleij * 32bit writes etc. 139234177802SLinus Walleij */ 13934b85da08SDavide Ciminaghi iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 13941c6a0718SPierre Ossman 13951c6a0718SPierre Ossman ptr += count; 13961c6a0718SPierre Ossman remain -= count; 13971c6a0718SPierre Ossman 13981c6a0718SPierre Ossman if (remain == 0) 13991c6a0718SPierre Ossman break; 14001c6a0718SPierre Ossman 14011c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 14021c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 14031c6a0718SPierre Ossman 14041c6a0718SPierre Ossman return ptr - buffer; 14051c6a0718SPierre Ossman } 14061c6a0718SPierre Ossman 14071c6a0718SPierre Ossman /* 14081c6a0718SPierre Ossman * PIO data transfer IRQ handler. 14091c6a0718SPierre Ossman */ 14101c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 14111c6a0718SPierre Ossman { 14121c6a0718SPierre Ossman struct mmci_host *host = dev_id; 14134ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 14148301bb68SRabin Vincent struct variant_data *variant = host->variant; 14151c6a0718SPierre Ossman void __iomem *base = host->base; 14161c6a0718SPierre Ossman u32 status; 14171c6a0718SPierre Ossman 14181c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 14191c6a0718SPierre Ossman 142064de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 14211c6a0718SPierre Ossman 14221c6a0718SPierre Ossman do { 14231c6a0718SPierre Ossman unsigned int remain, len; 14241c6a0718SPierre Ossman char *buffer; 14251c6a0718SPierre Ossman 14261c6a0718SPierre Ossman /* 14271c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 14281c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 14291c6a0718SPierre Ossman * definition it is more than half empty. 14301c6a0718SPierre Ossman * 14311c6a0718SPierre Ossman * For read, check for data available. 14321c6a0718SPierre Ossman */ 14331c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 14341c6a0718SPierre Ossman break; 14351c6a0718SPierre Ossman 14364ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 14374ce1d6cbSRabin Vincent break; 14384ce1d6cbSRabin Vincent 14394ce1d6cbSRabin Vincent buffer = sg_miter->addr; 14404ce1d6cbSRabin Vincent remain = sg_miter->length; 14411c6a0718SPierre Ossman 14421c6a0718SPierre Ossman len = 0; 14431c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 14441c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 14451c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 14461c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 14471c6a0718SPierre Ossman 14484ce1d6cbSRabin Vincent sg_miter->consumed = len; 14491c6a0718SPierre Ossman 14501c6a0718SPierre Ossman host->size -= len; 14511c6a0718SPierre Ossman remain -= len; 14521c6a0718SPierre Ossman 14531c6a0718SPierre Ossman if (remain) 14541c6a0718SPierre Ossman break; 14551c6a0718SPierre Ossman 14561c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 14571c6a0718SPierre Ossman } while (1); 14581c6a0718SPierre Ossman 14594ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 14604ce1d6cbSRabin Vincent 14611c6a0718SPierre Ossman /* 1462c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 1463c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 14641c6a0718SPierre Ossman */ 1465c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 14662686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 14671c6a0718SPierre Ossman 14681c6a0718SPierre Ossman /* 14691c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 14701c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 14711c6a0718SPierre Ossman * the chip itself has disabled the data path, and 14721c6a0718SPierre Ossman * stops us racing with our data end IRQ. 14731c6a0718SPierre Ossman */ 14741c6a0718SPierre Ossman if (host->size == 0) { 14752686b4b4SLinus Walleij mmci_set_mask1(host, 0); 14761c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 14771c6a0718SPierre Ossman } 14781c6a0718SPierre Ossman 14791c6a0718SPierre Ossman return IRQ_HANDLED; 14801c6a0718SPierre Ossman } 14811c6a0718SPierre Ossman 14821c6a0718SPierre Ossman /* 14831c6a0718SPierre Ossman * Handle completion of command and data transfers. 14841c6a0718SPierre Ossman */ 14851c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 14861c6a0718SPierre Ossman { 14871c6a0718SPierre Ossman struct mmci_host *host = dev_id; 14881c6a0718SPierre Ossman u32 status; 14891c6a0718SPierre Ossman int ret = 0; 14901c6a0718SPierre Ossman 14911c6a0718SPierre Ossman spin_lock(&host->lock); 14921c6a0718SPierre Ossman 14931c6a0718SPierre Ossman do { 14941c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 14952686b4b4SLinus Walleij 14962686b4b4SLinus Walleij if (host->singleirq) { 14976ea9cdf3SPatrice Chotard if (status & host->mask1_reg) 14982686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 14992686b4b4SLinus Walleij 150059db5e2dSLudovic Barre status &= ~host->variant->irq_pio_mask; 15012686b4b4SLinus Walleij } 15022686b4b4SLinus Walleij 15038d94b54dSUlf Hansson /* 15045cad24d8SJean-Nicolas Graux * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 15055cad24d8SJean-Nicolas Graux * enabled) in mmci_cmd_irq() function where ST Micro busy 15065cad24d8SJean-Nicolas Graux * detection variant is handled. Considering the HW seems to be 15075cad24d8SJean-Nicolas Graux * triggering the IRQ on both edges while monitoring DAT0 for 15085cad24d8SJean-Nicolas Graux * busy completion and that same status bit is used to monitor 15095cad24d8SJean-Nicolas Graux * start and end of busy detection, special care must be taken 15105cad24d8SJean-Nicolas Graux * to make sure that both start and end interrupts are always 15115cad24d8SJean-Nicolas Graux * cleared one after the other. 15128d94b54dSUlf Hansson */ 15131c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 15145cad24d8SJean-Nicolas Graux if (host->variant->busy_detect) 15155cad24d8SJean-Nicolas Graux writel(status & ~host->variant->busy_detect_mask, 15165cad24d8SJean-Nicolas Graux host->base + MMCICLEAR); 15175cad24d8SJean-Nicolas Graux else 15181c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 15191c6a0718SPierre Ossman 152064de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 15211c6a0718SPierre Ossman 15227878289bSUlf Hansson if (host->variant->reversed_irq_handling) { 15237878289bSUlf Hansson mmci_data_irq(host, host->data, status); 15247878289bSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 15257878289bSUlf Hansson } else { 1526ad82bfeaSUlf Hansson mmci_cmd_irq(host, host->cmd, status); 15271cb9da50SUlf Hansson mmci_data_irq(host, host->data, status); 15287878289bSUlf Hansson } 15291c6a0718SPierre Ossman 153049adc0caSLinus Walleij /* 153149adc0caSLinus Walleij * Don't poll for busy completion in irq context. 153249adc0caSLinus Walleij */ 153349adc0caSLinus Walleij if (host->variant->busy_detect && host->busy_status) 153449adc0caSLinus Walleij status &= ~host->variant->busy_detect_flag; 15358d94b54dSUlf Hansson 15361c6a0718SPierre Ossman ret = 1; 15371c6a0718SPierre Ossman } while (status); 15381c6a0718SPierre Ossman 15391c6a0718SPierre Ossman spin_unlock(&host->lock); 15401c6a0718SPierre Ossman 15411c6a0718SPierre Ossman return IRQ_RETVAL(ret); 15421c6a0718SPierre Ossman } 15431c6a0718SPierre Ossman 15441c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 15451c6a0718SPierre Ossman { 15461c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15479e943021SLinus Walleij unsigned long flags; 15481c6a0718SPierre Ossman 15491c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 15501c6a0718SPierre Ossman 1551653a761eSUlf Hansson mrq->cmd->error = mmci_validate_data(host, mrq->data); 1552653a761eSUlf Hansson if (mrq->cmd->error) { 1553255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1554255d01afSPierre Ossman return; 1555255d01afSPierre Ossman } 1556255d01afSPierre Ossman 15579e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 15581c6a0718SPierre Ossman 15591c6a0718SPierre Ossman host->mrq = mrq; 15601c6a0718SPierre Ossman 156158c7ccbfSPer Forlin if (mrq->data) 156258c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 156358c7ccbfSPer Forlin 1564d2141547SLudovic Barre if (mrq->data && 1565d2141547SLudovic Barre (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 15661c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 15671c6a0718SPierre Ossman 1568024629c6SUlf Hansson if (mrq->sbc) 1569024629c6SUlf Hansson mmci_start_command(host, mrq->sbc, 0); 1570024629c6SUlf Hansson else 15711c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 15721c6a0718SPierre Ossman 15739e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 15741c6a0718SPierre Ossman } 15751c6a0718SPierre Ossman 15761c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 15771c6a0718SPierre Ossman { 15781c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 15797d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1580a6a6464aSLinus Walleij u32 pwr = 0; 1581a6a6464aSLinus Walleij unsigned long flags; 1582db90f91fSLee Jones int ret; 15831c6a0718SPierre Ossman 1584bc521818SUlf Hansson if (host->plat->ios_handler && 1585bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1586bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1587bc521818SUlf Hansson 15881c6a0718SPierre Ossman switch (ios->power_mode) { 15891c6a0718SPierre Ossman case MMC_POWER_OFF: 1590599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1591599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1592237fb5e6SLee Jones 15937c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1594237fb5e6SLee Jones regulator_disable(mmc->supply.vqmmc); 15957c0136efSUlf Hansson host->vqmmc_enabled = false; 15967c0136efSUlf Hansson } 1597237fb5e6SLee Jones 15981c6a0718SPierre Ossman break; 15991c6a0718SPierre Ossman case MMC_POWER_UP: 1600599c1d5cSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 1601599c1d5cSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1602599c1d5cSUlf Hansson 16037d72a1d4SUlf Hansson /* 16047d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 16057d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 16067d72a1d4SUlf Hansson * configured in the variant data. 16077d72a1d4SUlf Hansson */ 16087d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 16097d72a1d4SUlf Hansson 16101c6a0718SPierre Ossman break; 16111c6a0718SPierre Ossman case MMC_POWER_ON: 16127c0136efSUlf Hansson if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1613db90f91fSLee Jones ret = regulator_enable(mmc->supply.vqmmc); 1614db90f91fSLee Jones if (ret < 0) 1615db90f91fSLee Jones dev_err(mmc_dev(mmc), 1616db90f91fSLee Jones "failed to enable vqmmc regulator\n"); 16177c0136efSUlf Hansson else 16187c0136efSUlf Hansson host->vqmmc_enabled = true; 1619db90f91fSLee Jones } 1620237fb5e6SLee Jones 16211c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 16221c6a0718SPierre Ossman break; 16231c6a0718SPierre Ossman } 16241c6a0718SPierre Ossman 16254d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 16264d1a3a0dSUlf Hansson /* 16274d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 16284d1a3a0dSUlf Hansson * indicating signal direction for the signals in 16294d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 16304d1a3a0dSUlf Hansson */ 16314593df29SUlf Hansson pwr |= host->pwr_reg_add; 16324d1a3a0dSUlf Hansson 16334d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 16344d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 16354d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 16364d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 16374d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 16384d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 16394d1a3a0dSUlf Hansson } 16404d1a3a0dSUlf Hansson 1641f9bb304cSPatrice Chotard if (variant->opendrain) { 1642f9bb304cSPatrice Chotard if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 164311dfb970SPatrice Chotard pwr |= variant->opendrain; 1644f9bb304cSPatrice Chotard } else { 1645f9bb304cSPatrice Chotard /* 1646f9bb304cSPatrice Chotard * If the variant cannot configure the pads by its own, then we 1647f9bb304cSPatrice Chotard * expect the pinctrl to be able to do that for us 1648f9bb304cSPatrice Chotard */ 1649f9bb304cSPatrice Chotard if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1650f9bb304cSPatrice Chotard pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1651f9bb304cSPatrice Chotard else 1652f9bb304cSPatrice Chotard pinctrl_select_state(host->pinctrl, host->pins_default); 1653f9bb304cSPatrice Chotard } 16541c6a0718SPierre Ossman 1655f4670daeSUlf Hansson /* 1656f4670daeSUlf Hansson * If clock = 0 and the variant requires the MMCIPOWER to be used for 1657f4670daeSUlf Hansson * gating the clock, the MCI_PWR_ON bit is cleared. 1658f4670daeSUlf Hansson */ 1659f4670daeSUlf Hansson if (!ios->clock && variant->pwrreg_clkgate) 1660f4670daeSUlf Hansson pwr &= ~MCI_PWR_ON; 1661f4670daeSUlf Hansson 16623f4e6f7bSSrinivas Kandagatla if (host->variant->explicit_mclk_control && 16633f4e6f7bSSrinivas Kandagatla ios->clock != host->clock_cache) { 16643f4e6f7bSSrinivas Kandagatla ret = clk_set_rate(host->clk, ios->clock); 16653f4e6f7bSSrinivas Kandagatla if (ret < 0) 16663f4e6f7bSSrinivas Kandagatla dev_err(mmc_dev(host->mmc), 16673f4e6f7bSSrinivas Kandagatla "Error setting clock rate (%d)\n", ret); 16683f4e6f7bSSrinivas Kandagatla else 16693f4e6f7bSSrinivas Kandagatla host->mclk = clk_get_rate(host->clk); 16703f4e6f7bSSrinivas Kandagatla } 16713f4e6f7bSSrinivas Kandagatla host->clock_cache = ios->clock; 16723f4e6f7bSSrinivas Kandagatla 1673a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1674a6a6464aSLinus Walleij 1675cd3ee8c5SLudovic Barre if (host->ops && host->ops->set_clkreg) 1676cd3ee8c5SLudovic Barre host->ops->set_clkreg(host, ios->clock); 1677cd3ee8c5SLudovic Barre else 1678a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 1679cd3ee8c5SLudovic Barre 1680cd3ee8c5SLudovic Barre if (host->ops && host->ops->set_pwrreg) 1681cd3ee8c5SLudovic Barre host->ops->set_pwrreg(host, pwr); 1682cd3ee8c5SLudovic Barre else 16837437cfa5SUlf Hansson mmci_write_pwrreg(host, pwr); 1684cd3ee8c5SLudovic Barre 1685f829c042SUlf Hansson mmci_reg_delay(host); 1686a6a6464aSLinus Walleij 1687a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 16881c6a0718SPierre Ossman } 16891c6a0718SPierre Ossman 169089001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 169189001446SRussell King { 169289001446SRussell King struct mmci_host *host = mmc_priv(mmc); 169329719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 1694d2762090SUlf Hansson unsigned int status = mmc_gpio_get_cd(mmc); 169589001446SRussell King 1696d2762090SUlf Hansson if (status == -ENOSYS) { 16974b8caec0SRabin Vincent if (!plat->status) 16984b8caec0SRabin Vincent return 1; /* Assume always present */ 16994b8caec0SRabin Vincent 170029719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 1701d2762090SUlf Hansson } 170274bc8093SRussell King return status; 170389001446SRussell King } 170489001446SRussell King 17050f3ed7f7SUlf Hansson static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 17060f3ed7f7SUlf Hansson { 17070f3ed7f7SUlf Hansson int ret = 0; 17080f3ed7f7SUlf Hansson 17090f3ed7f7SUlf Hansson if (!IS_ERR(mmc->supply.vqmmc)) { 17100f3ed7f7SUlf Hansson 17110f3ed7f7SUlf Hansson switch (ios->signal_voltage) { 17120f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_330: 17130f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 17140f3ed7f7SUlf Hansson 2700000, 3600000); 17150f3ed7f7SUlf Hansson break; 17160f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_180: 17170f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 17180f3ed7f7SUlf Hansson 1700000, 1950000); 17190f3ed7f7SUlf Hansson break; 17200f3ed7f7SUlf Hansson case MMC_SIGNAL_VOLTAGE_120: 17210f3ed7f7SUlf Hansson ret = regulator_set_voltage(mmc->supply.vqmmc, 17220f3ed7f7SUlf Hansson 1100000, 1300000); 17230f3ed7f7SUlf Hansson break; 17240f3ed7f7SUlf Hansson } 17250f3ed7f7SUlf Hansson 17260f3ed7f7SUlf Hansson if (ret) 17270f3ed7f7SUlf Hansson dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 17280f3ed7f7SUlf Hansson } 17290f3ed7f7SUlf Hansson 17300f3ed7f7SUlf Hansson return ret; 17310f3ed7f7SUlf Hansson } 17320f3ed7f7SUlf Hansson 173301259620SUlf Hansson static struct mmc_host_ops mmci_ops = { 17341c6a0718SPierre Ossman .request = mmci_request, 173558c7ccbfSPer Forlin .pre_req = mmci_pre_request, 173658c7ccbfSPer Forlin .post_req = mmci_post_request, 17371c6a0718SPierre Ossman .set_ios = mmci_set_ios, 1738d2762090SUlf Hansson .get_ro = mmc_gpio_get_ro, 173989001446SRussell King .get_cd = mmci_get_cd, 17400f3ed7f7SUlf Hansson .start_signal_voltage_switch = mmci_sig_volt_switch, 17411c6a0718SPierre Ossman }; 17421c6a0718SPierre Ossman 174378f87df2SUlf Hansson static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 174478f87df2SUlf Hansson { 17454593df29SUlf Hansson struct mmci_host *host = mmc_priv(mmc); 174678f87df2SUlf Hansson int ret = mmc_of_parse(mmc); 1747000bc9d5SLee Jones 174878f87df2SUlf Hansson if (ret) 174978f87df2SUlf Hansson return ret; 1750000bc9d5SLee Jones 17514593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat0", NULL)) 17524593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA0DIREN; 17534593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat2", NULL)) 17544593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA2DIREN; 17554593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat31", NULL)) 17564593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA31DIREN; 17574593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-dat74", NULL)) 17584593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_DATA74DIREN; 17594593df29SUlf Hansson if (of_get_property(np, "st,sig-dir-cmd", NULL)) 17604593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_CMDDIREN; 17614593df29SUlf Hansson if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 17624593df29SUlf Hansson host->pwr_reg_add |= MCI_ST_FBCLKEN; 176346b723ddSLudovic Barre if (of_get_property(np, "st,sig-dir", NULL)) 176446b723ddSLudovic Barre host->pwr_reg_add |= MCI_STM32_DIRPOL; 176546b723ddSLudovic Barre if (of_get_property(np, "st,neg-edge", NULL)) 176646b723ddSLudovic Barre host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 176746b723ddSLudovic Barre if (of_get_property(np, "st,use-ckin", NULL)) 176846b723ddSLudovic Barre host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 17694593df29SUlf Hansson 1770000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 177178f87df2SUlf Hansson mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1772000bc9d5SLee Jones if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 177378f87df2SUlf Hansson mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1774000bc9d5SLee Jones 177578f87df2SUlf Hansson return 0; 1776000bc9d5SLee Jones } 1777000bc9d5SLee Jones 1778c3be1efdSBill Pemberton static int mmci_probe(struct amba_device *dev, 1779aa25afadSRussell King const struct amba_id *id) 17801c6a0718SPierre Ossman { 17816ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 1782000bc9d5SLee Jones struct device_node *np = dev->dev.of_node; 17834956e109SRabin Vincent struct variant_data *variant = id->data; 17841c6a0718SPierre Ossman struct mmci_host *host; 17851c6a0718SPierre Ossman struct mmc_host *mmc; 17861c6a0718SPierre Ossman int ret; 17871c6a0718SPierre Ossman 1788000bc9d5SLee Jones /* Must have platform data or Device Tree. */ 1789000bc9d5SLee Jones if (!plat && !np) { 1790000bc9d5SLee Jones dev_err(&dev->dev, "No plat data or DT found\n"); 1791000bc9d5SLee Jones return -EINVAL; 17921c6a0718SPierre Ossman } 17931c6a0718SPierre Ossman 1794b9b52918SLee Jones if (!plat) { 1795b9b52918SLee Jones plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1796b9b52918SLee Jones if (!plat) 1797b9b52918SLee Jones return -ENOMEM; 1798b9b52918SLee Jones } 1799b9b52918SLee Jones 18001c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1801ef289982SUlf Hansson if (!mmc) 1802ef289982SUlf Hansson return -ENOMEM; 18031c6a0718SPierre Ossman 180478f87df2SUlf Hansson ret = mmci_of_parse(np, mmc); 180578f87df2SUlf Hansson if (ret) 180678f87df2SUlf Hansson goto host_free; 180778f87df2SUlf Hansson 18081c6a0718SPierre Ossman host = mmc_priv(mmc); 18094ea580f1SRabin Vincent host->mmc = mmc; 1810012b7d33SRussell King 1811f9bb304cSPatrice Chotard /* 1812f9bb304cSPatrice Chotard * Some variant (STM32) doesn't have opendrain bit, nevertheless 1813f9bb304cSPatrice Chotard * pins can be set accordingly using pinctrl 1814f9bb304cSPatrice Chotard */ 1815f9bb304cSPatrice Chotard if (!variant->opendrain) { 1816f9bb304cSPatrice Chotard host->pinctrl = devm_pinctrl_get(&dev->dev); 1817f9bb304cSPatrice Chotard if (IS_ERR(host->pinctrl)) { 1818f9bb304cSPatrice Chotard dev_err(&dev->dev, "failed to get pinctrl"); 1819310eb252SWei Yongjun ret = PTR_ERR(host->pinctrl); 1820f9bb304cSPatrice Chotard goto host_free; 1821f9bb304cSPatrice Chotard } 1822f9bb304cSPatrice Chotard 1823f9bb304cSPatrice Chotard host->pins_default = pinctrl_lookup_state(host->pinctrl, 1824f9bb304cSPatrice Chotard PINCTRL_STATE_DEFAULT); 1825f9bb304cSPatrice Chotard if (IS_ERR(host->pins_default)) { 1826f9bb304cSPatrice Chotard dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1827310eb252SWei Yongjun ret = PTR_ERR(host->pins_default); 1828f9bb304cSPatrice Chotard goto host_free; 1829f9bb304cSPatrice Chotard } 1830f9bb304cSPatrice Chotard 1831f9bb304cSPatrice Chotard host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1832f9bb304cSPatrice Chotard MMCI_PINCTRL_STATE_OPENDRAIN); 1833f9bb304cSPatrice Chotard if (IS_ERR(host->pins_opendrain)) { 1834f9bb304cSPatrice Chotard dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1835310eb252SWei Yongjun ret = PTR_ERR(host->pins_opendrain); 1836f9bb304cSPatrice Chotard goto host_free; 1837f9bb304cSPatrice Chotard } 1838f9bb304cSPatrice Chotard } 1839f9bb304cSPatrice Chotard 1840012b7d33SRussell King host->hw_designer = amba_manf(dev); 1841012b7d33SRussell King host->hw_revision = amba_rev(dev); 184264de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 184364de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1844012b7d33SRussell King 1845665ba56fSUlf Hansson host->clk = devm_clk_get(&dev->dev, NULL); 18461c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 18471c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 18481c6a0718SPierre Ossman goto host_free; 18491c6a0718SPierre Ossman } 18501c6a0718SPierre Ossman 1851ac940938SJulia Lawall ret = clk_prepare_enable(host->clk); 18521c6a0718SPierre Ossman if (ret) 1853665ba56fSUlf Hansson goto host_free; 18541c6a0718SPierre Ossman 18559c34b73dSSrinivas Kandagatla if (variant->qcom_fifo) 18569c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 18579c34b73dSSrinivas Kandagatla else 18589c34b73dSSrinivas Kandagatla host->get_rx_fifocnt = mmci_get_rx_fifocnt; 18599c34b73dSSrinivas Kandagatla 18601c6a0718SPierre Ossman host->plat = plat; 18614956e109SRabin Vincent host->variant = variant; 18621c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1863c8df9a53SLinus Walleij /* 1864c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1865c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1866c8df9a53SLinus Walleij * (if possible). 1867c8df9a53SLinus Walleij */ 1868dc6500bfSSrinivas Kandagatla if (host->mclk > variant->f_max) { 1869dc6500bfSSrinivas Kandagatla ret = clk_set_rate(host->clk, variant->f_max); 1870c8df9a53SLinus Walleij if (ret < 0) 1871c8df9a53SLinus Walleij goto clk_disable; 1872c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 187364de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 187464de0289SLinus Walleij host->mclk); 1875c8df9a53SLinus Walleij } 1876ef289982SUlf Hansson 1877c8ebae37SRussell King host->phybase = dev->res.start; 1878ef289982SUlf Hansson host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1879ef289982SUlf Hansson if (IS_ERR(host->base)) { 1880ef289982SUlf Hansson ret = PTR_ERR(host->base); 18811c6a0718SPierre Ossman goto clk_disable; 18821c6a0718SPierre Ossman } 18831c6a0718SPierre Ossman 1884ed9067fdSUlf Hansson if (variant->init) 1885ed9067fdSUlf Hansson variant->init(host); 1886ed9067fdSUlf Hansson 18877f294e49SLinus Walleij /* 18887f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 18897f294e49SLinus Walleij * clock divider equations which means that the minimum divider 18907f294e49SLinus Walleij * differs too. 18913f4e6f7bSSrinivas Kandagatla * on Qualcomm like controllers get the nearest minimum clock to 100Khz 18927f294e49SLinus Walleij */ 18937f294e49SLinus Walleij if (variant->st_clkdiv) 18947f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 189500e930d8SLudovic Barre else if (variant->stm32_clkdiv) 189600e930d8SLudovic Barre mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 18973f4e6f7bSSrinivas Kandagatla else if (variant->explicit_mclk_control) 18983f4e6f7bSSrinivas Kandagatla mmc->f_min = clk_round_rate(host->clk, 100000); 18997f294e49SLinus Walleij else 19007f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1901808d97ccSLinus Walleij /* 190278f87df2SUlf Hansson * If no maximum operating frequency is supplied, fall back to use 190378f87df2SUlf Hansson * the module parameter, which has a (low) default value in case it 190478f87df2SUlf Hansson * is not specified. Either value must not exceed the clock rate into 19055080a08dSUlf Hansson * the block, of course. 1906808d97ccSLinus Walleij */ 190778f87df2SUlf Hansson if (mmc->f_max) 19083f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 19093f4e6f7bSSrinivas Kandagatla min(variant->f_max, mmc->f_max) : 19103f4e6f7bSSrinivas Kandagatla min(host->mclk, mmc->f_max); 1911808d97ccSLinus Walleij else 19123f4e6f7bSSrinivas Kandagatla mmc->f_max = variant->explicit_mclk_control ? 19133f4e6f7bSSrinivas Kandagatla fmax : min(host->mclk, fmax); 19143f4e6f7bSSrinivas Kandagatla 19153f4e6f7bSSrinivas Kandagatla 191664de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 191764de0289SLinus Walleij 191815878e58SLudovic Barre host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 191915878e58SLudovic Barre if (IS_ERR(host->rst)) { 192015878e58SLudovic Barre ret = PTR_ERR(host->rst); 192115878e58SLudovic Barre goto clk_disable; 192215878e58SLudovic Barre } 192315878e58SLudovic Barre 1924599c1d5cSUlf Hansson /* Get regulators and the supported OCR mask */ 19259369c97cSBjorn Andersson ret = mmc_regulator_get_supply(mmc); 192651006952SWolfram Sang if (ret) 19279369c97cSBjorn Andersson goto clk_disable; 19289369c97cSBjorn Andersson 1929599c1d5cSUlf Hansson if (!mmc->ocr_avail) 19301c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 1931599c1d5cSUlf Hansson else if (plat->ocr_mask) 1932599c1d5cSUlf Hansson dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1933599c1d5cSUlf Hansson 19349dd8a8b8SUlf Hansson /* We support these capabilities. */ 19359dd8a8b8SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 19369dd8a8b8SUlf Hansson 193749adc0caSLinus Walleij /* 193849adc0caSLinus Walleij * Enable busy detection. 193949adc0caSLinus Walleij */ 19408d94b54dSUlf Hansson if (variant->busy_detect) { 19418d94b54dSUlf Hansson mmci_ops.card_busy = mmci_card_busy; 194249adc0caSLinus Walleij /* 194349adc0caSLinus Walleij * Not all variants have a flag to enable busy detection 194449adc0caSLinus Walleij * in the DPSM, but if they do, set it here. 194549adc0caSLinus Walleij */ 194649adc0caSLinus Walleij if (variant->busy_dpsm_flag) 194749adc0caSLinus Walleij mmci_write_datactrlreg(host, 194849adc0caSLinus Walleij host->variant->busy_dpsm_flag); 19498d94b54dSUlf Hansson mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 19508d94b54dSUlf Hansson mmc->max_busy_timeout = 0; 19518d94b54dSUlf Hansson } 19528d94b54dSUlf Hansson 19538d94b54dSUlf Hansson mmc->ops = &mmci_ops; 19548d94b54dSUlf Hansson 195570be208fSUlf Hansson /* We support these PM capabilities. */ 195678f87df2SUlf Hansson mmc->pm_caps |= MMC_PM_KEEP_POWER; 195770be208fSUlf Hansson 19581c6a0718SPierre Ossman /* 19591c6a0718SPierre Ossman * We can do SGIO 19601c6a0718SPierre Ossman */ 1961a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 19621c6a0718SPierre Ossman 19631c6a0718SPierre Ossman /* 196408458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 196508458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 196608458ef6SRabin Vincent * single request. 19671c6a0718SPierre Ossman */ 196808458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 19691c6a0718SPierre Ossman 19701c6a0718SPierre Ossman /* 19711c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 19721c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 19731c6a0718SPierre Ossman */ 19741c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 19751c6a0718SPierre Ossman 19761c6a0718SPierre Ossman /* 19771c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 19781c6a0718SPierre Ossman */ 1979c931d495SLudovic Barre mmc->max_blk_size = 1 << variant->datactrl_blocksz; 19801c6a0718SPierre Ossman 19811c6a0718SPierre Ossman /* 19828f7f6b7eSWill Deacon * Limit the number of blocks transferred so that we don't overflow 19838f7f6b7eSWill Deacon * the maximum request size. 19841c6a0718SPierre Ossman */ 1985c931d495SLudovic Barre mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 19861c6a0718SPierre Ossman 19871c6a0718SPierre Ossman spin_lock_init(&host->lock); 19881c6a0718SPierre Ossman 19891c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 19906ea9cdf3SPatrice Chotard 19916ea9cdf3SPatrice Chotard if (variant->mmcimask1) 19921c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 19936ea9cdf3SPatrice Chotard 19941c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 19951c6a0718SPierre Ossman 1996ce437aa4SLinus Walleij /* 1997ce437aa4SLinus Walleij * If: 1998ce437aa4SLinus Walleij * - not using DT but using a descriptor table, or 1999ce437aa4SLinus Walleij * - using a table of descriptors ALONGSIDE DT, or 2000ce437aa4SLinus Walleij * look up these descriptors named "cd" and "wp" right here, fail 20019ef986a6SLinus Walleij * silently of these do not exist 2002ce437aa4SLinus Walleij */ 2003ce437aa4SLinus Walleij if (!np) { 200489168b48SLinus Walleij ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 2005ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 2006ce437aa4SLinus Walleij goto clk_disable; 2007ce437aa4SLinus Walleij 200889168b48SLinus Walleij ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 2009ce437aa4SLinus Walleij if (ret == -EPROBE_DEFER) 2010ce437aa4SLinus Walleij goto clk_disable; 2011ce437aa4SLinus Walleij } 201289001446SRussell King 2013ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 2014ef289982SUlf Hansson DRIVER_NAME " (cmd)", host); 20151c6a0718SPierre Ossman if (ret) 2016ef289982SUlf Hansson goto clk_disable; 20171c6a0718SPierre Ossman 2018dfb85185SRussell King if (!dev->irq[1]) 20192686b4b4SLinus Walleij host->singleirq = true; 20202686b4b4SLinus Walleij else { 2021ef289982SUlf Hansson ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2022ef289982SUlf Hansson IRQF_SHARED, DRIVER_NAME " (pio)", host); 20231c6a0718SPierre Ossman if (ret) 2024ef289982SUlf Hansson goto clk_disable; 20252686b4b4SLinus Walleij } 20261c6a0718SPierre Ossman 2027daf9713cSLudovic Barre writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 20281c6a0718SPierre Ossman 20291c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 20301c6a0718SPierre Ossman 2031c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2032c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2033c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 2034c8ebae37SRussell King dev->irq[0], dev->irq[1]); 2035c8ebae37SRussell King 2036c8ebae37SRussell King mmci_dma_setup(host); 20371c6a0718SPierre Ossman 20382cd976c4SUlf Hansson pm_runtime_set_autosuspend_delay(&dev->dev, 50); 20392cd976c4SUlf Hansson pm_runtime_use_autosuspend(&dev->dev); 20401c3be369SRussell King 20418c11a94dSRussell King mmc_add_host(mmc); 20428c11a94dSRussell King 20436f2d3c89SUlf Hansson pm_runtime_put(&dev->dev); 20441c6a0718SPierre Ossman return 0; 20451c6a0718SPierre Ossman 20461c6a0718SPierre Ossman clk_disable: 2047ac940938SJulia Lawall clk_disable_unprepare(host->clk); 20481c6a0718SPierre Ossman host_free: 20491c6a0718SPierre Ossman mmc_free_host(mmc); 20501c6a0718SPierre Ossman return ret; 20511c6a0718SPierre Ossman } 20521c6a0718SPierre Ossman 20536e0ee714SBill Pemberton static int mmci_remove(struct amba_device *dev) 20541c6a0718SPierre Ossman { 20551c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 20561c6a0718SPierre Ossman 20571c6a0718SPierre Ossman if (mmc) { 20581c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 20596ea9cdf3SPatrice Chotard struct variant_data *variant = host->variant; 20601c6a0718SPierre Ossman 20611c3be369SRussell King /* 20621c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 20631c3be369SRussell King * version here so that we can access the primecell. 20641c3be369SRussell King */ 20651c3be369SRussell King pm_runtime_get_sync(&dev->dev); 20661c3be369SRussell King 20671c6a0718SPierre Ossman mmc_remove_host(mmc); 20681c6a0718SPierre Ossman 20691c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 20706ea9cdf3SPatrice Chotard 20716ea9cdf3SPatrice Chotard if (variant->mmcimask1) 20721c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 20731c6a0718SPierre Ossman 20741c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 20751c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 20761c6a0718SPierre Ossman 2077c8ebae37SRussell King mmci_dma_release(host); 2078ac940938SJulia Lawall clk_disable_unprepare(host->clk); 20791c6a0718SPierre Ossman mmc_free_host(mmc); 20801c6a0718SPierre Ossman } 20811c6a0718SPierre Ossman 20821c6a0718SPierre Ossman return 0; 20831c6a0718SPierre Ossman } 20841c6a0718SPierre Ossman 2085571dce4fSUlf Hansson #ifdef CONFIG_PM 20861ff44433SUlf Hansson static void mmci_save(struct mmci_host *host) 20871ff44433SUlf Hansson { 20881ff44433SUlf Hansson unsigned long flags; 20891ff44433SUlf Hansson 20901ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 20911ff44433SUlf Hansson 20921ff44433SUlf Hansson writel(0, host->base + MMCIMASK0); 209342dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 20941ff44433SUlf Hansson writel(0, host->base + MMCIDATACTRL); 20951ff44433SUlf Hansson writel(0, host->base + MMCIPOWER); 20961ff44433SUlf Hansson writel(0, host->base + MMCICLOCK); 209742dcc89aSUlf Hansson } 20981ff44433SUlf Hansson mmci_reg_delay(host); 20991ff44433SUlf Hansson 21001ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 21011ff44433SUlf Hansson } 21021ff44433SUlf Hansson 21031ff44433SUlf Hansson static void mmci_restore(struct mmci_host *host) 21041ff44433SUlf Hansson { 21051ff44433SUlf Hansson unsigned long flags; 21061ff44433SUlf Hansson 21071ff44433SUlf Hansson spin_lock_irqsave(&host->lock, flags); 21081ff44433SUlf Hansson 210942dcc89aSUlf Hansson if (host->variant->pwrreg_nopower) { 21101ff44433SUlf Hansson writel(host->clk_reg, host->base + MMCICLOCK); 21111ff44433SUlf Hansson writel(host->datactrl_reg, host->base + MMCIDATACTRL); 21121ff44433SUlf Hansson writel(host->pwr_reg, host->base + MMCIPOWER); 211342dcc89aSUlf Hansson } 2114daf9713cSLudovic Barre writel(MCI_IRQENABLE | host->variant->start_err, 2115daf9713cSLudovic Barre host->base + MMCIMASK0); 21161ff44433SUlf Hansson mmci_reg_delay(host); 21171ff44433SUlf Hansson 21181ff44433SUlf Hansson spin_unlock_irqrestore(&host->lock, flags); 21191ff44433SUlf Hansson } 21201ff44433SUlf Hansson 21218259293aSUlf Hansson static int mmci_runtime_suspend(struct device *dev) 21228259293aSUlf Hansson { 21238259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 21248259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 21258259293aSUlf Hansson 21268259293aSUlf Hansson if (mmc) { 21278259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 2128e36bd9c6SUlf Hansson pinctrl_pm_select_sleep_state(dev); 21291ff44433SUlf Hansson mmci_save(host); 21308259293aSUlf Hansson clk_disable_unprepare(host->clk); 21318259293aSUlf Hansson } 21328259293aSUlf Hansson 21338259293aSUlf Hansson return 0; 21348259293aSUlf Hansson } 21358259293aSUlf Hansson 21368259293aSUlf Hansson static int mmci_runtime_resume(struct device *dev) 21378259293aSUlf Hansson { 21388259293aSUlf Hansson struct amba_device *adev = to_amba_device(dev); 21398259293aSUlf Hansson struct mmc_host *mmc = amba_get_drvdata(adev); 21408259293aSUlf Hansson 21418259293aSUlf Hansson if (mmc) { 21428259293aSUlf Hansson struct mmci_host *host = mmc_priv(mmc); 21438259293aSUlf Hansson clk_prepare_enable(host->clk); 21441ff44433SUlf Hansson mmci_restore(host); 2145e36bd9c6SUlf Hansson pinctrl_pm_select_default_state(dev); 21468259293aSUlf Hansson } 21478259293aSUlf Hansson 21488259293aSUlf Hansson return 0; 21498259293aSUlf Hansson } 21508259293aSUlf Hansson #endif 21518259293aSUlf Hansson 215248fa7003SUlf Hansson static const struct dev_pm_ops mmci_dev_pm_ops = { 2153f3737fa3SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2154f3737fa3SUlf Hansson pm_runtime_force_resume) 21556ed23b80SRafael J. Wysocki SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 215648fa7003SUlf Hansson }; 215748fa7003SUlf Hansson 215888411deaSArvind Yadav static const struct amba_id mmci_ids[] = { 21591c6a0718SPierre Ossman { 21601c6a0718SPierre Ossman .id = 0x00041180, 2161768fbc18SPawel Moll .mask = 0xff0fffff, 21624956e109SRabin Vincent .data = &variant_arm, 21631c6a0718SPierre Ossman }, 21641c6a0718SPierre Ossman { 2165768fbc18SPawel Moll .id = 0x01041180, 2166768fbc18SPawel Moll .mask = 0xff0fffff, 2167768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 2168768fbc18SPawel Moll }, 2169768fbc18SPawel Moll { 21703a37298aSPawel Moll .id = 0x02041180, 21713a37298aSPawel Moll .mask = 0xff0fffff, 21723a37298aSPawel Moll .data = &variant_arm_extended_fifo_hwfc, 21733a37298aSPawel Moll }, 21743a37298aSPawel Moll { 21751c6a0718SPierre Ossman .id = 0x00041181, 21761c6a0718SPierre Ossman .mask = 0x000fffff, 21774956e109SRabin Vincent .data = &variant_arm, 21781c6a0718SPierre Ossman }, 2179cc30d60eSLinus Walleij /* ST Micro variants */ 2180cc30d60eSLinus Walleij { 2181cc30d60eSLinus Walleij .id = 0x00180180, 2182cc30d60eSLinus Walleij .mask = 0x00ffffff, 21834956e109SRabin Vincent .data = &variant_u300, 2184cc30d60eSLinus Walleij }, 2185cc30d60eSLinus Walleij { 218634fd4213SLinus Walleij .id = 0x10180180, 218734fd4213SLinus Walleij .mask = 0xf0ffffff, 218834fd4213SLinus Walleij .data = &variant_nomadik, 218934fd4213SLinus Walleij }, 219034fd4213SLinus Walleij { 2191cc30d60eSLinus Walleij .id = 0x00280180, 2192cc30d60eSLinus Walleij .mask = 0x00ffffff, 21930bcb7efdSLinus Walleij .data = &variant_nomadik, 21944956e109SRabin Vincent }, 21954956e109SRabin Vincent { 21964956e109SRabin Vincent .id = 0x00480180, 21971784b157SPhilippe Langlais .mask = 0xf0ffffff, 21984956e109SRabin Vincent .data = &variant_ux500, 2199cc30d60eSLinus Walleij }, 22001784b157SPhilippe Langlais { 22011784b157SPhilippe Langlais .id = 0x10480180, 22021784b157SPhilippe Langlais .mask = 0xf0ffffff, 22031784b157SPhilippe Langlais .data = &variant_ux500v2, 22041784b157SPhilippe Langlais }, 22052a9d6c80SPatrice Chotard { 22062a9d6c80SPatrice Chotard .id = 0x00880180, 22072a9d6c80SPatrice Chotard .mask = 0x00ffffff, 22082a9d6c80SPatrice Chotard .data = &variant_stm32, 22092a9d6c80SPatrice Chotard }, 221046b723ddSLudovic Barre { 221146b723ddSLudovic Barre .id = 0x10153180, 221246b723ddSLudovic Barre .mask = 0xf0ffffff, 221346b723ddSLudovic Barre .data = &variant_stm32_sdmmc, 221446b723ddSLudovic Barre }, 221555b604aeSSrinivas Kandagatla /* Qualcomm variants */ 221655b604aeSSrinivas Kandagatla { 221755b604aeSSrinivas Kandagatla .id = 0x00051180, 221855b604aeSSrinivas Kandagatla .mask = 0x000fffff, 221955b604aeSSrinivas Kandagatla .data = &variant_qcom, 222055b604aeSSrinivas Kandagatla }, 22211c6a0718SPierre Ossman { 0, 0 }, 22221c6a0718SPierre Ossman }; 22231c6a0718SPierre Ossman 22249f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 22259f99835fSDave Martin 22261c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 22271c6a0718SPierre Ossman .drv = { 22281c6a0718SPierre Ossman .name = DRIVER_NAME, 222948fa7003SUlf Hansson .pm = &mmci_dev_pm_ops, 22301c6a0718SPierre Ossman }, 22311c6a0718SPierre Ossman .probe = mmci_probe, 22320433c143SBill Pemberton .remove = mmci_remove, 22331c6a0718SPierre Ossman .id_table = mmci_ids, 22341c6a0718SPierre Ossman }; 22351c6a0718SPierre Ossman 22369e5ed094Sviresh kumar module_amba_driver(mmci_driver); 22371c6a0718SPierre Ossman 22381c6a0718SPierre Ossman module_param(fmax, uint, 0444); 22391c6a0718SPierre Ossman 22401c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 22411c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 2242