xref: /openbmc/linux/drivers/mmc/host/mmc_spi.c (revision d2999e1b)
1 /*
2  * mmc_spi.c - Access SD/MMC cards through SPI master controllers
3  *
4  * (C) Copyright 2005, Intec Automation,
5  *		Mike Lavender (mike@steroidmicros)
6  * (C) Copyright 2006-2007, David Brownell
7  * (C) Copyright 2007, Axis Communications,
8  *		Hans-Peter Nilsson (hp@axis.com)
9  * (C) Copyright 2007, ATRON electronic GmbH,
10  *		Jan Nikitenko <jan.nikitenko@gmail.com>
11  *
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26  */
27 #include <linux/sched.h>
28 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/module.h>
31 #include <linux/bio.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/crc7.h>
34 #include <linux/crc-itu-t.h>
35 #include <linux/scatterlist.h>
36 
37 #include <linux/mmc/host.h>
38 #include <linux/mmc/mmc.h>		/* for R1_SPI_* bit values */
39 #include <linux/mmc/slot-gpio.h>
40 
41 #include <linux/spi/spi.h>
42 #include <linux/spi/mmc_spi.h>
43 
44 #include <asm/unaligned.h>
45 
46 
47 /* NOTES:
48  *
49  * - For now, we won't try to interoperate with a real mmc/sd/sdio
50  *   controller, although some of them do have hardware support for
51  *   SPI protocol.  The main reason for such configs would be mmc-ish
52  *   cards like DataFlash, which don't support that "native" protocol.
53  *
54  *   We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
55  *   switch between driver stacks, and in any case if "native" mode
56  *   is available, it will be faster and hence preferable.
57  *
58  * - MMC depends on a different chipselect management policy than the
59  *   SPI interface currently supports for shared bus segments:  it needs
60  *   to issue multiple spi_message requests with the chipselect active,
61  *   using the results of one message to decide the next one to issue.
62  *
63  *   Pending updates to the programming interface, this driver expects
64  *   that it not share the bus with other drivers (precluding conflicts).
65  *
66  * - We tell the controller to keep the chipselect active from the
67  *   beginning of an mmc_host_ops.request until the end.  So beware
68  *   of SPI controller drivers that mis-handle the cs_change flag!
69  *
70  *   However, many cards seem OK with chipselect flapping up/down
71  *   during that time ... at least on unshared bus segments.
72  */
73 
74 
75 /*
76  * Local protocol constants, internal to data block protocols.
77  */
78 
79 /* Response tokens used to ack each block written: */
80 #define SPI_MMC_RESPONSE_CODE(x)	((x) & 0x1f)
81 #define SPI_RESPONSE_ACCEPTED		((2 << 1)|1)
82 #define SPI_RESPONSE_CRC_ERR		((5 << 1)|1)
83 #define SPI_RESPONSE_WRITE_ERR		((6 << 1)|1)
84 
85 /* Read and write blocks start with these tokens and end with crc;
86  * on error, read tokens act like a subset of R2_SPI_* values.
87  */
88 #define SPI_TOKEN_SINGLE	0xfe	/* single block r/w, multiblock read */
89 #define SPI_TOKEN_MULTI_WRITE	0xfc	/* multiblock write */
90 #define SPI_TOKEN_STOP_TRAN	0xfd	/* terminate multiblock write */
91 
92 #define MMC_SPI_BLOCKSIZE	512
93 
94 
95 /* These fixed timeouts come from the latest SD specs, which say to ignore
96  * the CSD values.  The R1B value is for card erase (e.g. the "I forgot the
97  * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after
98  * reads which takes nowhere near that long.  Older cards may be able to use
99  * shorter timeouts ... but why bother?
100  */
101 #define r1b_timeout		(HZ * 3)
102 
103 /* One of the critical speed parameters is the amount of data which may
104  * be transferred in one command. If this value is too low, the SD card
105  * controller has to do multiple partial block writes (argggh!). With
106  * today (2008) SD cards there is little speed gain if we transfer more
107  * than 64 KBytes at a time. So use this value until there is any indication
108  * that we should do more here.
109  */
110 #define MMC_SPI_BLOCKSATONCE	128
111 
112 /****************************************************************************/
113 
114 /*
115  * Local Data Structures
116  */
117 
118 /* "scratch" is per-{command,block} data exchanged with the card */
119 struct scratch {
120 	u8			status[29];
121 	u8			data_token;
122 	__be16			crc_val;
123 };
124 
125 struct mmc_spi_host {
126 	struct mmc_host		*mmc;
127 	struct spi_device	*spi;
128 
129 	unsigned char		power_mode;
130 	u16			powerup_msecs;
131 
132 	struct mmc_spi_platform_data	*pdata;
133 
134 	/* for bulk data transfers */
135 	struct spi_transfer	token, t, crc, early_status;
136 	struct spi_message	m;
137 
138 	/* for status readback */
139 	struct spi_transfer	status;
140 	struct spi_message	readback;
141 
142 	/* underlying DMA-aware controller, or null */
143 	struct device		*dma_dev;
144 
145 	/* buffer used for commands and for message "overhead" */
146 	struct scratch		*data;
147 	dma_addr_t		data_dma;
148 
149 	/* Specs say to write ones most of the time, even when the card
150 	 * has no need to read its input data; and many cards won't care.
151 	 * This is our source of those ones.
152 	 */
153 	void			*ones;
154 	dma_addr_t		ones_dma;
155 };
156 
157 
158 /****************************************************************************/
159 
160 /*
161  * MMC-over-SPI protocol glue, used by the MMC stack interface
162  */
163 
164 static inline int mmc_cs_off(struct mmc_spi_host *host)
165 {
166 	/* chipselect will always be inactive after setup() */
167 	return spi_setup(host->spi);
168 }
169 
170 static int
171 mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
172 {
173 	int status;
174 
175 	if (len > sizeof(*host->data)) {
176 		WARN_ON(1);
177 		return -EIO;
178 	}
179 
180 	host->status.len = len;
181 
182 	if (host->dma_dev)
183 		dma_sync_single_for_device(host->dma_dev,
184 				host->data_dma, sizeof(*host->data),
185 				DMA_FROM_DEVICE);
186 
187 	status = spi_sync_locked(host->spi, &host->readback);
188 
189 	if (host->dma_dev)
190 		dma_sync_single_for_cpu(host->dma_dev,
191 				host->data_dma, sizeof(*host->data),
192 				DMA_FROM_DEVICE);
193 
194 	return status;
195 }
196 
197 static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
198 			unsigned n, u8 byte)
199 {
200 	u8		*cp = host->data->status;
201 	unsigned long start = jiffies;
202 
203 	while (1) {
204 		int		status;
205 		unsigned	i;
206 
207 		status = mmc_spi_readbytes(host, n);
208 		if (status < 0)
209 			return status;
210 
211 		for (i = 0; i < n; i++) {
212 			if (cp[i] != byte)
213 				return cp[i];
214 		}
215 
216 		if (time_is_before_jiffies(start + timeout))
217 			break;
218 
219 		/* If we need long timeouts, we may release the CPU.
220 		 * We use jiffies here because we want to have a relation
221 		 * between elapsed time and the blocking of the scheduler.
222 		 */
223 		if (time_is_before_jiffies(start+1))
224 			schedule();
225 	}
226 	return -ETIMEDOUT;
227 }
228 
229 static inline int
230 mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
231 {
232 	return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
233 }
234 
235 static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
236 {
237 	return mmc_spi_skip(host, timeout, 1, 0xff);
238 }
239 
240 
241 /*
242  * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
243  * hosts return!  The low byte holds R1_SPI bits.  The next byte may hold
244  * R2_SPI bits ... for SEND_STATUS, or after data read errors.
245  *
246  * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
247  * newer cards R7 (IF_COND).
248  */
249 
250 static char *maptype(struct mmc_command *cmd)
251 {
252 	switch (mmc_spi_resp_type(cmd)) {
253 	case MMC_RSP_SPI_R1:	return "R1";
254 	case MMC_RSP_SPI_R1B:	return "R1B";
255 	case MMC_RSP_SPI_R2:	return "R2/R5";
256 	case MMC_RSP_SPI_R3:	return "R3/R4/R7";
257 	default:		return "?";
258 	}
259 }
260 
261 /* return zero, else negative errno after setting cmd->error */
262 static int mmc_spi_response_get(struct mmc_spi_host *host,
263 		struct mmc_command *cmd, int cs_on)
264 {
265 	u8	*cp = host->data->status;
266 	u8	*end = cp + host->t.len;
267 	int	value = 0;
268 	int	bitshift;
269 	u8 	leftover = 0;
270 	unsigned short rotator;
271 	int 	i;
272 	char	tag[32];
273 
274 	snprintf(tag, sizeof(tag), "  ... CMD%d response SPI_%s",
275 		cmd->opcode, maptype(cmd));
276 
277 	/* Except for data block reads, the whole response will already
278 	 * be stored in the scratch buffer.  It's somewhere after the
279 	 * command and the first byte we read after it.  We ignore that
280 	 * first byte.  After STOP_TRANSMISSION command it may include
281 	 * two data bits, but otherwise it's all ones.
282 	 */
283 	cp += 8;
284 	while (cp < end && *cp == 0xff)
285 		cp++;
286 
287 	/* Data block reads (R1 response types) may need more data... */
288 	if (cp == end) {
289 		cp = host->data->status;
290 		end = cp+1;
291 
292 		/* Card sends N(CR) (== 1..8) bytes of all-ones then one
293 		 * status byte ... and we already scanned 2 bytes.
294 		 *
295 		 * REVISIT block read paths use nasty byte-at-a-time I/O
296 		 * so it can always DMA directly into the target buffer.
297 		 * It'd probably be better to memcpy() the first chunk and
298 		 * avoid extra i/o calls...
299 		 *
300 		 * Note we check for more than 8 bytes, because in practice,
301 		 * some SD cards are slow...
302 		 */
303 		for (i = 2; i < 16; i++) {
304 			value = mmc_spi_readbytes(host, 1);
305 			if (value < 0)
306 				goto done;
307 			if (*cp != 0xff)
308 				goto checkstatus;
309 		}
310 		value = -ETIMEDOUT;
311 		goto done;
312 	}
313 
314 checkstatus:
315 	bitshift = 0;
316 	if (*cp & 0x80)	{
317 		/* Houston, we have an ugly card with a bit-shifted response */
318 		rotator = *cp++ << 8;
319 		/* read the next byte */
320 		if (cp == end) {
321 			value = mmc_spi_readbytes(host, 1);
322 			if (value < 0)
323 				goto done;
324 			cp = host->data->status;
325 			end = cp+1;
326 		}
327 		rotator |= *cp++;
328 		while (rotator & 0x8000) {
329 			bitshift++;
330 			rotator <<= 1;
331 		}
332 		cmd->resp[0] = rotator >> 8;
333 		leftover = rotator;
334 	} else {
335 		cmd->resp[0] = *cp++;
336 	}
337 	cmd->error = 0;
338 
339 	/* Status byte: the entire seven-bit R1 response.  */
340 	if (cmd->resp[0] != 0) {
341 		if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
342 				& cmd->resp[0])
343 			value = -EFAULT; /* Bad address */
344 		else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
345 			value = -ENOSYS; /* Function not implemented */
346 		else if (R1_SPI_COM_CRC & cmd->resp[0])
347 			value = -EILSEQ; /* Illegal byte sequence */
348 		else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
349 				& cmd->resp[0])
350 			value = -EIO;    /* I/O error */
351 		/* else R1_SPI_IDLE, "it's resetting" */
352 	}
353 
354 	switch (mmc_spi_resp_type(cmd)) {
355 
356 	/* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
357 	 * and less-common stuff like various erase operations.
358 	 */
359 	case MMC_RSP_SPI_R1B:
360 		/* maybe we read all the busy tokens already */
361 		while (cp < end && *cp == 0)
362 			cp++;
363 		if (cp == end)
364 			mmc_spi_wait_unbusy(host, r1b_timeout);
365 		break;
366 
367 	/* SPI R2 == R1 + second status byte; SEND_STATUS
368 	 * SPI R5 == R1 + data byte; IO_RW_DIRECT
369 	 */
370 	case MMC_RSP_SPI_R2:
371 		/* read the next byte */
372 		if (cp == end) {
373 			value = mmc_spi_readbytes(host, 1);
374 			if (value < 0)
375 				goto done;
376 			cp = host->data->status;
377 			end = cp+1;
378 		}
379 		if (bitshift) {
380 			rotator = leftover << 8;
381 			rotator |= *cp << bitshift;
382 			cmd->resp[0] |= (rotator & 0xFF00);
383 		} else {
384 			cmd->resp[0] |= *cp << 8;
385 		}
386 		break;
387 
388 	/* SPI R3, R4, or R7 == R1 + 4 bytes */
389 	case MMC_RSP_SPI_R3:
390 		rotator = leftover << 8;
391 		cmd->resp[1] = 0;
392 		for (i = 0; i < 4; i++) {
393 			cmd->resp[1] <<= 8;
394 			/* read the next byte */
395 			if (cp == end) {
396 				value = mmc_spi_readbytes(host, 1);
397 				if (value < 0)
398 					goto done;
399 				cp = host->data->status;
400 				end = cp+1;
401 			}
402 			if (bitshift) {
403 				rotator |= *cp++ << bitshift;
404 				cmd->resp[1] |= (rotator >> 8);
405 				rotator <<= 8;
406 			} else {
407 				cmd->resp[1] |= *cp++;
408 			}
409 		}
410 		break;
411 
412 	/* SPI R1 == just one status byte */
413 	case MMC_RSP_SPI_R1:
414 		break;
415 
416 	default:
417 		dev_dbg(&host->spi->dev, "bad response type %04x\n",
418 				mmc_spi_resp_type(cmd));
419 		if (value >= 0)
420 			value = -EINVAL;
421 		goto done;
422 	}
423 
424 	if (value < 0)
425 		dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
426 			tag, cmd->resp[0], cmd->resp[1]);
427 
428 	/* disable chipselect on errors and some success cases */
429 	if (value >= 0 && cs_on)
430 		return value;
431 done:
432 	if (value < 0)
433 		cmd->error = value;
434 	mmc_cs_off(host);
435 	return value;
436 }
437 
438 /* Issue command and read its response.
439  * Returns zero on success, negative for error.
440  *
441  * On error, caller must cope with mmc core retry mechanism.  That
442  * means immediate low-level resubmit, which affects the bus lock...
443  */
444 static int
445 mmc_spi_command_send(struct mmc_spi_host *host,
446 		struct mmc_request *mrq,
447 		struct mmc_command *cmd, int cs_on)
448 {
449 	struct scratch		*data = host->data;
450 	u8			*cp = data->status;
451 	int			status;
452 	struct spi_transfer	*t;
453 
454 	/* We can handle most commands (except block reads) in one full
455 	 * duplex I/O operation before either starting the next transfer
456 	 * (data block or command) or else deselecting the card.
457 	 *
458 	 * First, write 7 bytes:
459 	 *  - an all-ones byte to ensure the card is ready
460 	 *  - opcode byte (plus start and transmission bits)
461 	 *  - four bytes of big-endian argument
462 	 *  - crc7 (plus end bit) ... always computed, it's cheap
463 	 *
464 	 * We init the whole buffer to all-ones, which is what we need
465 	 * to write while we're reading (later) response data.
466 	 */
467 	memset(cp, 0xff, sizeof(data->status));
468 
469 	cp[1] = 0x40 | cmd->opcode;
470 	put_unaligned_be32(cmd->arg, cp+2);
471 	cp[6] = crc7_be(0, cp+1, 5) | 0x01;
472 	cp += 7;
473 
474 	/* Then, read up to 13 bytes (while writing all-ones):
475 	 *  - N(CR) (== 1..8) bytes of all-ones
476 	 *  - status byte (for all response types)
477 	 *  - the rest of the response, either:
478 	 *      + nothing, for R1 or R1B responses
479 	 *	+ second status byte, for R2 responses
480 	 *	+ four data bytes, for R3 and R7 responses
481 	 *
482 	 * Finally, read some more bytes ... in the nice cases we know in
483 	 * advance how many, and reading 1 more is always OK:
484 	 *  - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
485 	 *  - N(RC) (== 1..N) bytes of all-ones, before next command
486 	 *  - N(WR) (== 1..N) bytes of all-ones, before data write
487 	 *
488 	 * So in those cases one full duplex I/O of at most 21 bytes will
489 	 * handle the whole command, leaving the card ready to receive a
490 	 * data block or new command.  We do that whenever we can, shaving
491 	 * CPU and IRQ costs (especially when using DMA or FIFOs).
492 	 *
493 	 * There are two other cases, where it's not generally practical
494 	 * to rely on a single I/O:
495 	 *
496 	 *  - R1B responses need at least N(EC) bytes of all-zeroes.
497 	 *
498 	 *    In this case we can *try* to fit it into one I/O, then
499 	 *    maybe read more data later.
500 	 *
501 	 *  - Data block reads are more troublesome, since a variable
502 	 *    number of padding bytes precede the token and data.
503 	 *      + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
504 	 *      + N(AC) (== 1..many) bytes of all-ones
505 	 *
506 	 *    In this case we currently only have minimal speedups here:
507 	 *    when N(CR) == 1 we can avoid I/O in response_get().
508 	 */
509 	if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
510 		cp += 2;	/* min(N(CR)) + status */
511 		/* R1 */
512 	} else {
513 		cp += 10;	/* max(N(CR)) + status + min(N(RC),N(WR)) */
514 		if (cmd->flags & MMC_RSP_SPI_S2)	/* R2/R5 */
515 			cp++;
516 		else if (cmd->flags & MMC_RSP_SPI_B4)	/* R3/R4/R7 */
517 			cp += 4;
518 		else if (cmd->flags & MMC_RSP_BUSY)	/* R1B */
519 			cp = data->status + sizeof(data->status);
520 		/* else:  R1 (most commands) */
521 	}
522 
523 	dev_dbg(&host->spi->dev, "  mmc_spi: CMD%d, resp %s\n",
524 		cmd->opcode, maptype(cmd));
525 
526 	/* send command, leaving chipselect active */
527 	spi_message_init(&host->m);
528 
529 	t = &host->t;
530 	memset(t, 0, sizeof(*t));
531 	t->tx_buf = t->rx_buf = data->status;
532 	t->tx_dma = t->rx_dma = host->data_dma;
533 	t->len = cp - data->status;
534 	t->cs_change = 1;
535 	spi_message_add_tail(t, &host->m);
536 
537 	if (host->dma_dev) {
538 		host->m.is_dma_mapped = 1;
539 		dma_sync_single_for_device(host->dma_dev,
540 				host->data_dma, sizeof(*host->data),
541 				DMA_BIDIRECTIONAL);
542 	}
543 	status = spi_sync_locked(host->spi, &host->m);
544 
545 	if (host->dma_dev)
546 		dma_sync_single_for_cpu(host->dma_dev,
547 				host->data_dma, sizeof(*host->data),
548 				DMA_BIDIRECTIONAL);
549 	if (status < 0) {
550 		dev_dbg(&host->spi->dev, "  ... write returned %d\n", status);
551 		cmd->error = status;
552 		return status;
553 	}
554 
555 	/* after no-data commands and STOP_TRANSMISSION, chipselect off */
556 	return mmc_spi_response_get(host, cmd, cs_on);
557 }
558 
559 /* Build data message with up to four separate transfers.  For TX, we
560  * start by writing the data token.  And in most cases, we finish with
561  * a status transfer.
562  *
563  * We always provide TX data for data and CRC.  The MMC/SD protocol
564  * requires us to write ones; but Linux defaults to writing zeroes;
565  * so we explicitly initialize it to all ones on RX paths.
566  *
567  * We also handle DMA mapping, so the underlying SPI controller does
568  * not need to (re)do it for each message.
569  */
570 static void
571 mmc_spi_setup_data_message(
572 	struct mmc_spi_host	*host,
573 	int			multiple,
574 	enum dma_data_direction	direction)
575 {
576 	struct spi_transfer	*t;
577 	struct scratch		*scratch = host->data;
578 	dma_addr_t		dma = host->data_dma;
579 
580 	spi_message_init(&host->m);
581 	if (dma)
582 		host->m.is_dma_mapped = 1;
583 
584 	/* for reads, readblock() skips 0xff bytes before finding
585 	 * the token; for writes, this transfer issues that token.
586 	 */
587 	if (direction == DMA_TO_DEVICE) {
588 		t = &host->token;
589 		memset(t, 0, sizeof(*t));
590 		t->len = 1;
591 		if (multiple)
592 			scratch->data_token = SPI_TOKEN_MULTI_WRITE;
593 		else
594 			scratch->data_token = SPI_TOKEN_SINGLE;
595 		t->tx_buf = &scratch->data_token;
596 		if (dma)
597 			t->tx_dma = dma + offsetof(struct scratch, data_token);
598 		spi_message_add_tail(t, &host->m);
599 	}
600 
601 	/* Body of transfer is buffer, then CRC ...
602 	 * either TX-only, or RX with TX-ones.
603 	 */
604 	t = &host->t;
605 	memset(t, 0, sizeof(*t));
606 	t->tx_buf = host->ones;
607 	t->tx_dma = host->ones_dma;
608 	/* length and actual buffer info are written later */
609 	spi_message_add_tail(t, &host->m);
610 
611 	t = &host->crc;
612 	memset(t, 0, sizeof(*t));
613 	t->len = 2;
614 	if (direction == DMA_TO_DEVICE) {
615 		/* the actual CRC may get written later */
616 		t->tx_buf = &scratch->crc_val;
617 		if (dma)
618 			t->tx_dma = dma + offsetof(struct scratch, crc_val);
619 	} else {
620 		t->tx_buf = host->ones;
621 		t->tx_dma = host->ones_dma;
622 		t->rx_buf = &scratch->crc_val;
623 		if (dma)
624 			t->rx_dma = dma + offsetof(struct scratch, crc_val);
625 	}
626 	spi_message_add_tail(t, &host->m);
627 
628 	/*
629 	 * A single block read is followed by N(EC) [0+] all-ones bytes
630 	 * before deselect ... don't bother.
631 	 *
632 	 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
633 	 * the next block is read, or a STOP_TRANSMISSION is issued.  We'll
634 	 * collect that single byte, so readblock() doesn't need to.
635 	 *
636 	 * For a write, the one-byte data response follows immediately, then
637 	 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
638 	 * Then single block reads may deselect, and multiblock ones issue
639 	 * the next token (next data block, or STOP_TRAN).  We can try to
640 	 * minimize I/O ops by using a single read to collect end-of-busy.
641 	 */
642 	if (multiple || direction == DMA_TO_DEVICE) {
643 		t = &host->early_status;
644 		memset(t, 0, sizeof(*t));
645 		t->len = (direction == DMA_TO_DEVICE)
646 				? sizeof(scratch->status)
647 				: 1;
648 		t->tx_buf = host->ones;
649 		t->tx_dma = host->ones_dma;
650 		t->rx_buf = scratch->status;
651 		if (dma)
652 			t->rx_dma = dma + offsetof(struct scratch, status);
653 		t->cs_change = 1;
654 		spi_message_add_tail(t, &host->m);
655 	}
656 }
657 
658 /*
659  * Write one block:
660  *  - caller handled preceding N(WR) [1+] all-ones bytes
661  *  - data block
662  *	+ token
663  *	+ data bytes
664  *	+ crc16
665  *  - an all-ones byte ... card writes a data-response byte
666  *  - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
667  *
668  * Return negative errno, else success.
669  */
670 static int
671 mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
672 	unsigned long timeout)
673 {
674 	struct spi_device	*spi = host->spi;
675 	int			status, i;
676 	struct scratch		*scratch = host->data;
677 	u32			pattern;
678 
679 	if (host->mmc->use_spi_crc)
680 		scratch->crc_val = cpu_to_be16(
681 				crc_itu_t(0, t->tx_buf, t->len));
682 	if (host->dma_dev)
683 		dma_sync_single_for_device(host->dma_dev,
684 				host->data_dma, sizeof(*scratch),
685 				DMA_BIDIRECTIONAL);
686 
687 	status = spi_sync_locked(spi, &host->m);
688 
689 	if (status != 0) {
690 		dev_dbg(&spi->dev, "write error (%d)\n", status);
691 		return status;
692 	}
693 
694 	if (host->dma_dev)
695 		dma_sync_single_for_cpu(host->dma_dev,
696 				host->data_dma, sizeof(*scratch),
697 				DMA_BIDIRECTIONAL);
698 
699 	/*
700 	 * Get the transmission data-response reply.  It must follow
701 	 * immediately after the data block we transferred.  This reply
702 	 * doesn't necessarily tell whether the write operation succeeded;
703 	 * it just says if the transmission was ok and whether *earlier*
704 	 * writes succeeded; see the standard.
705 	 *
706 	 * In practice, there are (even modern SDHC-)cards which are late
707 	 * in sending the response, and miss the time frame by a few bits,
708 	 * so we have to cope with this situation and check the response
709 	 * bit-by-bit. Arggh!!!
710 	 */
711 	pattern = get_unaligned_be32(scratch->status);
712 
713 	/* First 3 bit of pattern are undefined */
714 	pattern |= 0xE0000000;
715 
716 	/* left-adjust to leading 0 bit */
717 	while (pattern & 0x80000000)
718 		pattern <<= 1;
719 	/* right-adjust for pattern matching. Code is in bit 4..0 now. */
720 	pattern >>= 27;
721 
722 	switch (pattern) {
723 	case SPI_RESPONSE_ACCEPTED:
724 		status = 0;
725 		break;
726 	case SPI_RESPONSE_CRC_ERR:
727 		/* host shall then issue MMC_STOP_TRANSMISSION */
728 		status = -EILSEQ;
729 		break;
730 	case SPI_RESPONSE_WRITE_ERR:
731 		/* host shall then issue MMC_STOP_TRANSMISSION,
732 		 * and should MMC_SEND_STATUS to sort it out
733 		 */
734 		status = -EIO;
735 		break;
736 	default:
737 		status = -EPROTO;
738 		break;
739 	}
740 	if (status != 0) {
741 		dev_dbg(&spi->dev, "write error %02x (%d)\n",
742 			scratch->status[0], status);
743 		return status;
744 	}
745 
746 	t->tx_buf += t->len;
747 	if (host->dma_dev)
748 		t->tx_dma += t->len;
749 
750 	/* Return when not busy.  If we didn't collect that status yet,
751 	 * we'll need some more I/O.
752 	 */
753 	for (i = 4; i < sizeof(scratch->status); i++) {
754 		/* card is non-busy if the most recent bit is 1 */
755 		if (scratch->status[i] & 0x01)
756 			return 0;
757 	}
758 	return mmc_spi_wait_unbusy(host, timeout);
759 }
760 
761 /*
762  * Read one block:
763  *  - skip leading all-ones bytes ... either
764  *      + N(AC) [1..f(clock,CSD)] usually, else
765  *      + N(CX) [0..8] when reading CSD or CID
766  *  - data block
767  *	+ token ... if error token, no data or crc
768  *	+ data bytes
769  *	+ crc16
770  *
771  * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
772  * before dropping chipselect.
773  *
774  * For multiblock reads, caller either reads the next block or issues a
775  * STOP_TRANSMISSION command.
776  */
777 static int
778 mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
779 	unsigned long timeout)
780 {
781 	struct spi_device	*spi = host->spi;
782 	int			status;
783 	struct scratch		*scratch = host->data;
784 	unsigned int 		bitshift;
785 	u8			leftover;
786 
787 	/* At least one SD card sends an all-zeroes byte when N(CX)
788 	 * applies, before the all-ones bytes ... just cope with that.
789 	 */
790 	status = mmc_spi_readbytes(host, 1);
791 	if (status < 0)
792 		return status;
793 	status = scratch->status[0];
794 	if (status == 0xff || status == 0)
795 		status = mmc_spi_readtoken(host, timeout);
796 
797 	if (status < 0) {
798 		dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
799 		return status;
800 	}
801 
802 	/* The token may be bit-shifted...
803 	 * the first 0-bit precedes the data stream.
804 	 */
805 	bitshift = 7;
806 	while (status & 0x80) {
807 		status <<= 1;
808 		bitshift--;
809 	}
810 	leftover = status << 1;
811 
812 	if (host->dma_dev) {
813 		dma_sync_single_for_device(host->dma_dev,
814 				host->data_dma, sizeof(*scratch),
815 				DMA_BIDIRECTIONAL);
816 		dma_sync_single_for_device(host->dma_dev,
817 				t->rx_dma, t->len,
818 				DMA_FROM_DEVICE);
819 	}
820 
821 	status = spi_sync_locked(spi, &host->m);
822 
823 	if (host->dma_dev) {
824 		dma_sync_single_for_cpu(host->dma_dev,
825 				host->data_dma, sizeof(*scratch),
826 				DMA_BIDIRECTIONAL);
827 		dma_sync_single_for_cpu(host->dma_dev,
828 				t->rx_dma, t->len,
829 				DMA_FROM_DEVICE);
830 	}
831 
832 	if (bitshift) {
833 		/* Walk through the data and the crc and do
834 		 * all the magic to get byte-aligned data.
835 		 */
836 		u8 *cp = t->rx_buf;
837 		unsigned int len;
838 		unsigned int bitright = 8 - bitshift;
839 		u8 temp;
840 		for (len = t->len; len; len--) {
841 			temp = *cp;
842 			*cp++ = leftover | (temp >> bitshift);
843 			leftover = temp << bitright;
844 		}
845 		cp = (u8 *) &scratch->crc_val;
846 		temp = *cp;
847 		*cp++ = leftover | (temp >> bitshift);
848 		leftover = temp << bitright;
849 		temp = *cp;
850 		*cp = leftover | (temp >> bitshift);
851 	}
852 
853 	if (host->mmc->use_spi_crc) {
854 		u16 crc = crc_itu_t(0, t->rx_buf, t->len);
855 
856 		be16_to_cpus(&scratch->crc_val);
857 		if (scratch->crc_val != crc) {
858 			dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, "
859 					"computed=0x%04x len=%d\n",
860 					scratch->crc_val, crc, t->len);
861 			return -EILSEQ;
862 		}
863 	}
864 
865 	t->rx_buf += t->len;
866 	if (host->dma_dev)
867 		t->rx_dma += t->len;
868 
869 	return 0;
870 }
871 
872 /*
873  * An MMC/SD data stage includes one or more blocks, optional CRCs,
874  * and inline handshaking.  That handhaking makes it unlike most
875  * other SPI protocol stacks.
876  */
877 static void
878 mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
879 		struct mmc_data *data, u32 blk_size)
880 {
881 	struct spi_device	*spi = host->spi;
882 	struct device		*dma_dev = host->dma_dev;
883 	struct spi_transfer	*t;
884 	enum dma_data_direction	direction;
885 	struct scatterlist	*sg;
886 	unsigned		n_sg;
887 	int			multiple = (data->blocks > 1);
888 	u32			clock_rate;
889 	unsigned long		timeout;
890 
891 	if (data->flags & MMC_DATA_READ)
892 		direction = DMA_FROM_DEVICE;
893 	else
894 		direction = DMA_TO_DEVICE;
895 	mmc_spi_setup_data_message(host, multiple, direction);
896 	t = &host->t;
897 
898 	if (t->speed_hz)
899 		clock_rate = t->speed_hz;
900 	else
901 		clock_rate = spi->max_speed_hz;
902 
903 	timeout = data->timeout_ns +
904 		  data->timeout_clks * 1000000 / clock_rate;
905 	timeout = usecs_to_jiffies((unsigned int)(timeout / 1000)) + 1;
906 
907 	/* Handle scatterlist segments one at a time, with synch for
908 	 * each 512-byte block
909 	 */
910 	for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) {
911 		int			status = 0;
912 		dma_addr_t		dma_addr = 0;
913 		void			*kmap_addr;
914 		unsigned		length = sg->length;
915 		enum dma_data_direction	dir = direction;
916 
917 		/* set up dma mapping for controller drivers that might
918 		 * use DMA ... though they may fall back to PIO
919 		 */
920 		if (dma_dev) {
921 			/* never invalidate whole *shared* pages ... */
922 			if ((sg->offset != 0 || length != PAGE_SIZE)
923 					&& dir == DMA_FROM_DEVICE)
924 				dir = DMA_BIDIRECTIONAL;
925 
926 			dma_addr = dma_map_page(dma_dev, sg_page(sg), 0,
927 						PAGE_SIZE, dir);
928 			if (direction == DMA_TO_DEVICE)
929 				t->tx_dma = dma_addr + sg->offset;
930 			else
931 				t->rx_dma = dma_addr + sg->offset;
932 		}
933 
934 		/* allow pio too; we don't allow highmem */
935 		kmap_addr = kmap(sg_page(sg));
936 		if (direction == DMA_TO_DEVICE)
937 			t->tx_buf = kmap_addr + sg->offset;
938 		else
939 			t->rx_buf = kmap_addr + sg->offset;
940 
941 		/* transfer each block, and update request status */
942 		while (length) {
943 			t->len = min(length, blk_size);
944 
945 			dev_dbg(&host->spi->dev,
946 				"    mmc_spi: %s block, %d bytes\n",
947 				(direction == DMA_TO_DEVICE)
948 				? "write"
949 				: "read",
950 				t->len);
951 
952 			if (direction == DMA_TO_DEVICE)
953 				status = mmc_spi_writeblock(host, t, timeout);
954 			else
955 				status = mmc_spi_readblock(host, t, timeout);
956 			if (status < 0)
957 				break;
958 
959 			data->bytes_xfered += t->len;
960 			length -= t->len;
961 
962 			if (!multiple)
963 				break;
964 		}
965 
966 		/* discard mappings */
967 		if (direction == DMA_FROM_DEVICE)
968 			flush_kernel_dcache_page(sg_page(sg));
969 		kunmap(sg_page(sg));
970 		if (dma_dev)
971 			dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);
972 
973 		if (status < 0) {
974 			data->error = status;
975 			dev_dbg(&spi->dev, "%s status %d\n",
976 				(direction == DMA_TO_DEVICE)
977 					? "write" : "read",
978 				status);
979 			break;
980 		}
981 	}
982 
983 	/* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
984 	 * can be issued before multiblock writes.  Unlike its more widely
985 	 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
986 	 * that can affect the STOP_TRAN logic.   Complete (and current)
987 	 * MMC specs should sort that out before Linux starts using CMD23.
988 	 */
989 	if (direction == DMA_TO_DEVICE && multiple) {
990 		struct scratch	*scratch = host->data;
991 		int		tmp;
992 		const unsigned	statlen = sizeof(scratch->status);
993 
994 		dev_dbg(&spi->dev, "    mmc_spi: STOP_TRAN\n");
995 
996 		/* Tweak the per-block message we set up earlier by morphing
997 		 * it to hold single buffer with the token followed by some
998 		 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
999 		 * "not busy any longer" status, and leave chip selected.
1000 		 */
1001 		INIT_LIST_HEAD(&host->m.transfers);
1002 		list_add(&host->early_status.transfer_list,
1003 				&host->m.transfers);
1004 
1005 		memset(scratch->status, 0xff, statlen);
1006 		scratch->status[0] = SPI_TOKEN_STOP_TRAN;
1007 
1008 		host->early_status.tx_buf = host->early_status.rx_buf;
1009 		host->early_status.tx_dma = host->early_status.rx_dma;
1010 		host->early_status.len = statlen;
1011 
1012 		if (host->dma_dev)
1013 			dma_sync_single_for_device(host->dma_dev,
1014 					host->data_dma, sizeof(*scratch),
1015 					DMA_BIDIRECTIONAL);
1016 
1017 		tmp = spi_sync_locked(spi, &host->m);
1018 
1019 		if (host->dma_dev)
1020 			dma_sync_single_for_cpu(host->dma_dev,
1021 					host->data_dma, sizeof(*scratch),
1022 					DMA_BIDIRECTIONAL);
1023 
1024 		if (tmp < 0) {
1025 			if (!data->error)
1026 				data->error = tmp;
1027 			return;
1028 		}
1029 
1030 		/* Ideally we collected "not busy" status with one I/O,
1031 		 * avoiding wasteful byte-at-a-time scanning... but more
1032 		 * I/O is often needed.
1033 		 */
1034 		for (tmp = 2; tmp < statlen; tmp++) {
1035 			if (scratch->status[tmp] != 0)
1036 				return;
1037 		}
1038 		tmp = mmc_spi_wait_unbusy(host, timeout);
1039 		if (tmp < 0 && !data->error)
1040 			data->error = tmp;
1041 	}
1042 }
1043 
1044 /****************************************************************************/
1045 
1046 /*
1047  * MMC driver implementation -- the interface to the MMC stack
1048  */
1049 
1050 static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
1051 {
1052 	struct mmc_spi_host	*host = mmc_priv(mmc);
1053 	int			status = -EINVAL;
1054 	int			crc_retry = 5;
1055 	struct mmc_command	stop;
1056 
1057 #ifdef DEBUG
1058 	/* MMC core and layered drivers *MUST* issue SPI-aware commands */
1059 	{
1060 		struct mmc_command	*cmd;
1061 		int			invalid = 0;
1062 
1063 		cmd = mrq->cmd;
1064 		if (!mmc_spi_resp_type(cmd)) {
1065 			dev_dbg(&host->spi->dev, "bogus command\n");
1066 			cmd->error = -EINVAL;
1067 			invalid = 1;
1068 		}
1069 
1070 		cmd = mrq->stop;
1071 		if (cmd && !mmc_spi_resp_type(cmd)) {
1072 			dev_dbg(&host->spi->dev, "bogus STOP command\n");
1073 			cmd->error = -EINVAL;
1074 			invalid = 1;
1075 		}
1076 
1077 		if (invalid) {
1078 			dump_stack();
1079 			mmc_request_done(host->mmc, mrq);
1080 			return;
1081 		}
1082 	}
1083 #endif
1084 
1085 	/* request exclusive bus access */
1086 	spi_bus_lock(host->spi->master);
1087 
1088 crc_recover:
1089 	/* issue command; then optionally data and stop */
1090 	status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
1091 	if (status == 0 && mrq->data) {
1092 		mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
1093 
1094 		/*
1095 		 * The SPI bus is not always reliable for large data transfers.
1096 		 * If an occasional crc error is reported by the SD device with
1097 		 * data read/write over SPI, it may be recovered by repeating
1098 		 * the last SD command again. The retry count is set to 5 to
1099 		 * ensure the driver passes stress tests.
1100 		 */
1101 		if (mrq->data->error == -EILSEQ && crc_retry) {
1102 			stop.opcode = MMC_STOP_TRANSMISSION;
1103 			stop.arg = 0;
1104 			stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
1105 			status = mmc_spi_command_send(host, mrq, &stop, 0);
1106 			crc_retry--;
1107 			mrq->data->error = 0;
1108 			goto crc_recover;
1109 		}
1110 
1111 		if (mrq->stop)
1112 			status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
1113 		else
1114 			mmc_cs_off(host);
1115 	}
1116 
1117 	/* release the bus */
1118 	spi_bus_unlock(host->spi->master);
1119 
1120 	mmc_request_done(host->mmc, mrq);
1121 }
1122 
1123 /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
1124  *
1125  * NOTE that here we can't know that the card has just been powered up;
1126  * not all MMC/SD sockets support power switching.
1127  *
1128  * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
1129  * this doesn't seem to do the right thing at all...
1130  */
1131 static void mmc_spi_initsequence(struct mmc_spi_host *host)
1132 {
1133 	/* Try to be very sure any previous command has completed;
1134 	 * wait till not-busy, skip debris from any old commands.
1135 	 */
1136 	mmc_spi_wait_unbusy(host, r1b_timeout);
1137 	mmc_spi_readbytes(host, 10);
1138 
1139 	/*
1140 	 * Do a burst with chipselect active-high.  We need to do this to
1141 	 * meet the requirement of 74 clock cycles with both chipselect
1142 	 * and CMD (MOSI) high before CMD0 ... after the card has been
1143 	 * powered up to Vdd(min), and so is ready to take commands.
1144 	 *
1145 	 * Some cards are particularly needy of this (e.g. Viking "SD256")
1146 	 * while most others don't seem to care.
1147 	 *
1148 	 * Note that this is one of the places MMC/SD plays games with the
1149 	 * SPI protocol.  Another is that when chipselect is released while
1150 	 * the card returns BUSY status, the clock must issue several cycles
1151 	 * with chipselect high before the card will stop driving its output.
1152 	 */
1153 	host->spi->mode |= SPI_CS_HIGH;
1154 	if (spi_setup(host->spi) != 0) {
1155 		/* Just warn; most cards work without it. */
1156 		dev_warn(&host->spi->dev,
1157 				"can't change chip-select polarity\n");
1158 		host->spi->mode &= ~SPI_CS_HIGH;
1159 	} else {
1160 		mmc_spi_readbytes(host, 18);
1161 
1162 		host->spi->mode &= ~SPI_CS_HIGH;
1163 		if (spi_setup(host->spi) != 0) {
1164 			/* Wot, we can't get the same setup we had before? */
1165 			dev_err(&host->spi->dev,
1166 					"can't restore chip-select polarity\n");
1167 		}
1168 	}
1169 }
1170 
1171 static char *mmc_powerstring(u8 power_mode)
1172 {
1173 	switch (power_mode) {
1174 	case MMC_POWER_OFF: return "off";
1175 	case MMC_POWER_UP:  return "up";
1176 	case MMC_POWER_ON:  return "on";
1177 	}
1178 	return "?";
1179 }
1180 
1181 static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1182 {
1183 	struct mmc_spi_host *host = mmc_priv(mmc);
1184 
1185 	if (host->power_mode != ios->power_mode) {
1186 		int		canpower;
1187 
1188 		canpower = host->pdata && host->pdata->setpower;
1189 
1190 		dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n",
1191 				mmc_powerstring(ios->power_mode),
1192 				ios->vdd,
1193 				canpower ? ", can switch" : "");
1194 
1195 		/* switch power on/off if possible, accounting for
1196 		 * max 250msec powerup time if needed.
1197 		 */
1198 		if (canpower) {
1199 			switch (ios->power_mode) {
1200 			case MMC_POWER_OFF:
1201 			case MMC_POWER_UP:
1202 				host->pdata->setpower(&host->spi->dev,
1203 						ios->vdd);
1204 				if (ios->power_mode == MMC_POWER_UP)
1205 					msleep(host->powerup_msecs);
1206 			}
1207 		}
1208 
1209 		/* See 6.4.1 in the simplified SD card physical spec 2.0 */
1210 		if (ios->power_mode == MMC_POWER_ON)
1211 			mmc_spi_initsequence(host);
1212 
1213 		/* If powering down, ground all card inputs to avoid power
1214 		 * delivery from data lines!  On a shared SPI bus, this
1215 		 * will probably be temporary; 6.4.2 of the simplified SD
1216 		 * spec says this must last at least 1msec.
1217 		 *
1218 		 *   - Clock low means CPOL 0, e.g. mode 0
1219 		 *   - MOSI low comes from writing zero
1220 		 *   - Chipselect is usually active low...
1221 		 */
1222 		if (canpower && ios->power_mode == MMC_POWER_OFF) {
1223 			int mres;
1224 			u8 nullbyte = 0;
1225 
1226 			host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1227 			mres = spi_setup(host->spi);
1228 			if (mres < 0)
1229 				dev_dbg(&host->spi->dev,
1230 					"switch to SPI mode 0 failed\n");
1231 
1232 			if (spi_write(host->spi, &nullbyte, 1) < 0)
1233 				dev_dbg(&host->spi->dev,
1234 					"put spi signals to low failed\n");
1235 
1236 			/*
1237 			 * Now clock should be low due to spi mode 0;
1238 			 * MOSI should be low because of written 0x00;
1239 			 * chipselect should be low (it is active low)
1240 			 * power supply is off, so now MMC is off too!
1241 			 *
1242 			 * FIXME no, chipselect can be high since the
1243 			 * device is inactive and SPI_CS_HIGH is clear...
1244 			 */
1245 			msleep(10);
1246 			if (mres == 0) {
1247 				host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1248 				mres = spi_setup(host->spi);
1249 				if (mres < 0)
1250 					dev_dbg(&host->spi->dev,
1251 						"switch back to SPI mode 3"
1252 						" failed\n");
1253 			}
1254 		}
1255 
1256 		host->power_mode = ios->power_mode;
1257 	}
1258 
1259 	if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1260 		int		status;
1261 
1262 		host->spi->max_speed_hz = ios->clock;
1263 		status = spi_setup(host->spi);
1264 		dev_dbg(&host->spi->dev,
1265 			"mmc_spi:  clock to %d Hz, %d\n",
1266 			host->spi->max_speed_hz, status);
1267 	}
1268 }
1269 
1270 static const struct mmc_host_ops mmc_spi_ops = {
1271 	.request	= mmc_spi_request,
1272 	.set_ios	= mmc_spi_set_ios,
1273 	.get_ro		= mmc_gpio_get_ro,
1274 	.get_cd		= mmc_gpio_get_cd,
1275 };
1276 
1277 
1278 /****************************************************************************/
1279 
1280 /*
1281  * SPI driver implementation
1282  */
1283 
1284 static irqreturn_t
1285 mmc_spi_detect_irq(int irq, void *mmc)
1286 {
1287 	struct mmc_spi_host *host = mmc_priv(mmc);
1288 	u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1289 
1290 	mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1291 	return IRQ_HANDLED;
1292 }
1293 
1294 static int mmc_spi_probe(struct spi_device *spi)
1295 {
1296 	void			*ones;
1297 	struct mmc_host		*mmc;
1298 	struct mmc_spi_host	*host;
1299 	int			status;
1300 	bool			has_ro = false;
1301 
1302 	/* We rely on full duplex transfers, mostly to reduce
1303 	 * per-transfer overheads (by making fewer transfers).
1304 	 */
1305 	if (spi->master->flags & SPI_MASTER_HALF_DUPLEX)
1306 		return -EINVAL;
1307 
1308 	/* MMC and SD specs only seem to care that sampling is on the
1309 	 * rising edge ... meaning SPI modes 0 or 3.  So either SPI mode
1310 	 * should be legit.  We'll use mode 0 since the steady state is 0,
1311 	 * which is appropriate for hotplugging, unless the platform data
1312 	 * specify mode 3 (if hardware is not compatible to mode 0).
1313 	 */
1314 	if (spi->mode != SPI_MODE_3)
1315 		spi->mode = SPI_MODE_0;
1316 	spi->bits_per_word = 8;
1317 
1318 	status = spi_setup(spi);
1319 	if (status < 0) {
1320 		dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1321 				spi->mode, spi->max_speed_hz / 1000,
1322 				status);
1323 		return status;
1324 	}
1325 
1326 	/* We need a supply of ones to transmit.  This is the only time
1327 	 * the CPU touches these, so cache coherency isn't a concern.
1328 	 *
1329 	 * NOTE if many systems use more than one MMC-over-SPI connector
1330 	 * it'd save some memory to share this.  That's evidently rare.
1331 	 */
1332 	status = -ENOMEM;
1333 	ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1334 	if (!ones)
1335 		goto nomem;
1336 	memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1337 
1338 	mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1339 	if (!mmc)
1340 		goto nomem;
1341 
1342 	mmc->ops = &mmc_spi_ops;
1343 	mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1344 	mmc->max_segs = MMC_SPI_BLOCKSATONCE;
1345 	mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1346 	mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1347 
1348 	mmc->caps = MMC_CAP_SPI;
1349 
1350 	/* SPI doesn't need the lowspeed device identification thing for
1351 	 * MMC or SD cards, since it never comes up in open drain mode.
1352 	 * That's good; some SPI masters can't handle very low speeds!
1353 	 *
1354 	 * However, low speed SDIO cards need not handle over 400 KHz;
1355 	 * that's the only reason not to use a few MHz for f_min (until
1356 	 * the upper layer reads the target frequency from the CSD).
1357 	 */
1358 	mmc->f_min = 400000;
1359 	mmc->f_max = spi->max_speed_hz;
1360 
1361 	host = mmc_priv(mmc);
1362 	host->mmc = mmc;
1363 	host->spi = spi;
1364 
1365 	host->ones = ones;
1366 
1367 	/* Platform data is used to hook up things like card sensing
1368 	 * and power switching gpios.
1369 	 */
1370 	host->pdata = mmc_spi_get_pdata(spi);
1371 	if (host->pdata)
1372 		mmc->ocr_avail = host->pdata->ocr_mask;
1373 	if (!mmc->ocr_avail) {
1374 		dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1375 		mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1376 	}
1377 	if (host->pdata && host->pdata->setpower) {
1378 		host->powerup_msecs = host->pdata->powerup_msecs;
1379 		if (!host->powerup_msecs || host->powerup_msecs > 250)
1380 			host->powerup_msecs = 250;
1381 	}
1382 
1383 	dev_set_drvdata(&spi->dev, mmc);
1384 
1385 	/* preallocate dma buffers */
1386 	host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1387 	if (!host->data)
1388 		goto fail_nobuf1;
1389 
1390 	if (spi->master->dev.parent->dma_mask) {
1391 		struct device	*dev = spi->master->dev.parent;
1392 
1393 		host->dma_dev = dev;
1394 		host->ones_dma = dma_map_single(dev, ones,
1395 				MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1396 		host->data_dma = dma_map_single(dev, host->data,
1397 				sizeof(*host->data), DMA_BIDIRECTIONAL);
1398 
1399 		/* REVISIT in theory those map operations can fail... */
1400 
1401 		dma_sync_single_for_cpu(host->dma_dev,
1402 				host->data_dma, sizeof(*host->data),
1403 				DMA_BIDIRECTIONAL);
1404 	}
1405 
1406 	/* setup message for status/busy readback */
1407 	spi_message_init(&host->readback);
1408 	host->readback.is_dma_mapped = (host->dma_dev != NULL);
1409 
1410 	spi_message_add_tail(&host->status, &host->readback);
1411 	host->status.tx_buf = host->ones;
1412 	host->status.tx_dma = host->ones_dma;
1413 	host->status.rx_buf = &host->data->status;
1414 	host->status.rx_dma = host->data_dma + offsetof(struct scratch, status);
1415 	host->status.cs_change = 1;
1416 
1417 	/* register card detect irq */
1418 	if (host->pdata && host->pdata->init) {
1419 		status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1420 		if (status != 0)
1421 			goto fail_glue_init;
1422 	}
1423 
1424 	/* pass platform capabilities, if any */
1425 	if (host->pdata) {
1426 		mmc->caps |= host->pdata->caps;
1427 		mmc->caps2 |= host->pdata->caps2;
1428 	}
1429 
1430 	status = mmc_add_host(mmc);
1431 	if (status != 0)
1432 		goto fail_add_host;
1433 
1434 	if (host->pdata && host->pdata->flags & MMC_SPI_USE_CD_GPIO) {
1435 		status = mmc_gpio_request_cd(mmc, host->pdata->cd_gpio,
1436 					     host->pdata->cd_debounce);
1437 		if (status != 0)
1438 			goto fail_add_host;
1439 	}
1440 
1441 	if (host->pdata && host->pdata->flags & MMC_SPI_USE_RO_GPIO) {
1442 		has_ro = true;
1443 		status = mmc_gpio_request_ro(mmc, host->pdata->ro_gpio);
1444 		if (status != 0)
1445 			goto fail_add_host;
1446 	}
1447 
1448 	dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n",
1449 			dev_name(&mmc->class_dev),
1450 			host->dma_dev ? "" : ", no DMA",
1451 			has_ro ? "" : ", no WP",
1452 			(host->pdata && host->pdata->setpower)
1453 				? "" : ", no poweroff",
1454 			(mmc->caps & MMC_CAP_NEEDS_POLL)
1455 				? ", cd polling" : "");
1456 	return 0;
1457 
1458 fail_add_host:
1459 	mmc_remove_host (mmc);
1460 fail_glue_init:
1461 	if (host->dma_dev)
1462 		dma_unmap_single(host->dma_dev, host->data_dma,
1463 				sizeof(*host->data), DMA_BIDIRECTIONAL);
1464 	kfree(host->data);
1465 
1466 fail_nobuf1:
1467 	mmc_free_host(mmc);
1468 	mmc_spi_put_pdata(spi);
1469 	dev_set_drvdata(&spi->dev, NULL);
1470 
1471 nomem:
1472 	kfree(ones);
1473 	return status;
1474 }
1475 
1476 
1477 static int mmc_spi_remove(struct spi_device *spi)
1478 {
1479 	struct mmc_host		*mmc = dev_get_drvdata(&spi->dev);
1480 	struct mmc_spi_host	*host;
1481 
1482 	if (mmc) {
1483 		host = mmc_priv(mmc);
1484 
1485 		/* prevent new mmc_detect_change() calls */
1486 		if (host->pdata && host->pdata->exit)
1487 			host->pdata->exit(&spi->dev, mmc);
1488 
1489 		mmc_remove_host(mmc);
1490 
1491 		if (host->dma_dev) {
1492 			dma_unmap_single(host->dma_dev, host->ones_dma,
1493 				MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1494 			dma_unmap_single(host->dma_dev, host->data_dma,
1495 				sizeof(*host->data), DMA_BIDIRECTIONAL);
1496 		}
1497 
1498 		kfree(host->data);
1499 		kfree(host->ones);
1500 
1501 		spi->max_speed_hz = mmc->f_max;
1502 		mmc_free_host(mmc);
1503 		mmc_spi_put_pdata(spi);
1504 		dev_set_drvdata(&spi->dev, NULL);
1505 	}
1506 	return 0;
1507 }
1508 
1509 static struct of_device_id mmc_spi_of_match_table[] = {
1510 	{ .compatible = "mmc-spi-slot", },
1511 	{},
1512 };
1513 
1514 static struct spi_driver mmc_spi_driver = {
1515 	.driver = {
1516 		.name =		"mmc_spi",
1517 		.owner =	THIS_MODULE,
1518 		.of_match_table = mmc_spi_of_match_table,
1519 	},
1520 	.probe =	mmc_spi_probe,
1521 	.remove =	mmc_spi_remove,
1522 };
1523 
1524 module_spi_driver(mmc_spi_driver);
1525 
1526 MODULE_AUTHOR("Mike Lavender, David Brownell, "
1527 		"Hans-Peter Nilsson, Jan Nikitenko");
1528 MODULE_DESCRIPTION("SPI SD/MMC host driver");
1529 MODULE_LICENSE("GPL");
1530 MODULE_ALIAS("spi:mmc_spi");
1531