1 /* 2 * mmc_spi.c - Access SD/MMC cards through SPI master controllers 3 * 4 * (C) Copyright 2005, Intec Automation, 5 * Mike Lavender (mike@steroidmicros) 6 * (C) Copyright 2006-2007, David Brownell 7 * (C) Copyright 2007, Axis Communications, 8 * Hans-Peter Nilsson (hp@axis.com) 9 * (C) Copyright 2007, ATRON electronic GmbH, 10 * Jan Nikitenko <jan.nikitenko@gmail.com> 11 * 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 #include <linux/hrtimer.h> 28 #include <linux/delay.h> 29 #include <linux/bio.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/crc7.h> 32 #include <linux/crc-itu-t.h> 33 #include <linux/scatterlist.h> 34 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */ 37 38 #include <linux/spi/spi.h> 39 #include <linux/spi/mmc_spi.h> 40 41 #include <asm/unaligned.h> 42 43 44 /* NOTES: 45 * 46 * - For now, we won't try to interoperate with a real mmc/sd/sdio 47 * controller, although some of them do have hardware support for 48 * SPI protocol. The main reason for such configs would be mmc-ish 49 * cards like DataFlash, which don't support that "native" protocol. 50 * 51 * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to 52 * switch between driver stacks, and in any case if "native" mode 53 * is available, it will be faster and hence preferable. 54 * 55 * - MMC depends on a different chipselect management policy than the 56 * SPI interface currently supports for shared bus segments: it needs 57 * to issue multiple spi_message requests with the chipselect active, 58 * using the results of one message to decide the next one to issue. 59 * 60 * Pending updates to the programming interface, this driver expects 61 * that it not share the bus with other drivers (precluding conflicts). 62 * 63 * - We tell the controller to keep the chipselect active from the 64 * beginning of an mmc_host_ops.request until the end. So beware 65 * of SPI controller drivers that mis-handle the cs_change flag! 66 * 67 * However, many cards seem OK with chipselect flapping up/down 68 * during that time ... at least on unshared bus segments. 69 */ 70 71 72 /* 73 * Local protocol constants, internal to data block protocols. 74 */ 75 76 /* Response tokens used to ack each block written: */ 77 #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f) 78 #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1) 79 #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1) 80 #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1) 81 82 /* Read and write blocks start with these tokens and end with crc; 83 * on error, read tokens act like a subset of R2_SPI_* values. 84 */ 85 #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */ 86 #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */ 87 #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */ 88 89 #define MMC_SPI_BLOCKSIZE 512 90 91 92 /* These fixed timeouts come from the latest SD specs, which say to ignore 93 * the CSD values. The R1B value is for card erase (e.g. the "I forgot the 94 * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after 95 * reads which takes nowhere near that long. Older cards may be able to use 96 * shorter timeouts ... but why bother? 97 */ 98 #define readblock_timeout ktime_set(0, 100 * 1000 * 1000) 99 #define writeblock_timeout ktime_set(0, 250 * 1000 * 1000) 100 #define r1b_timeout ktime_set(3, 0) 101 102 103 /****************************************************************************/ 104 105 /* 106 * Local Data Structures 107 */ 108 109 /* "scratch" is per-{command,block} data exchanged with the card */ 110 struct scratch { 111 u8 status[29]; 112 u8 data_token; 113 __be16 crc_val; 114 }; 115 116 struct mmc_spi_host { 117 struct mmc_host *mmc; 118 struct spi_device *spi; 119 120 unsigned char power_mode; 121 u16 powerup_msecs; 122 123 struct mmc_spi_platform_data *pdata; 124 125 /* for bulk data transfers */ 126 struct spi_transfer token, t, crc, early_status; 127 struct spi_message m; 128 129 /* for status readback */ 130 struct spi_transfer status; 131 struct spi_message readback; 132 133 /* underlying DMA-aware controller, or null */ 134 struct device *dma_dev; 135 136 /* buffer used for commands and for message "overhead" */ 137 struct scratch *data; 138 dma_addr_t data_dma; 139 140 /* Specs say to write ones most of the time, even when the card 141 * has no need to read its input data; and many cards won't care. 142 * This is our source of those ones. 143 */ 144 void *ones; 145 dma_addr_t ones_dma; 146 }; 147 148 149 /****************************************************************************/ 150 151 /* 152 * MMC-over-SPI protocol glue, used by the MMC stack interface 153 */ 154 155 static inline int mmc_cs_off(struct mmc_spi_host *host) 156 { 157 /* chipselect will always be inactive after setup() */ 158 return spi_setup(host->spi); 159 } 160 161 static int 162 mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len) 163 { 164 int status; 165 166 if (len > sizeof(*host->data)) { 167 WARN_ON(1); 168 return -EIO; 169 } 170 171 host->status.len = len; 172 173 if (host->dma_dev) 174 dma_sync_single_for_device(host->dma_dev, 175 host->data_dma, sizeof(*host->data), 176 DMA_FROM_DEVICE); 177 178 status = spi_sync(host->spi, &host->readback); 179 180 if (host->dma_dev) 181 dma_sync_single_for_cpu(host->dma_dev, 182 host->data_dma, sizeof(*host->data), 183 DMA_FROM_DEVICE); 184 185 return status; 186 } 187 188 static int 189 mmc_spi_skip(struct mmc_spi_host *host, ktime_t timeout, unsigned n, u8 byte) 190 { 191 u8 *cp = host->data->status; 192 193 timeout = ktime_add(timeout, ktime_get()); 194 195 while (1) { 196 int status; 197 unsigned i; 198 199 status = mmc_spi_readbytes(host, n); 200 if (status < 0) 201 return status; 202 203 for (i = 0; i < n; i++) { 204 if (cp[i] != byte) 205 return cp[i]; 206 } 207 208 /* REVISIT investigate msleep() to avoid busy-wait I/O 209 * in at least some cases. 210 */ 211 if (ktime_to_ns(ktime_sub(ktime_get(), timeout)) > 0) 212 break; 213 } 214 return -ETIMEDOUT; 215 } 216 217 static inline int 218 mmc_spi_wait_unbusy(struct mmc_spi_host *host, ktime_t timeout) 219 { 220 return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0); 221 } 222 223 static int mmc_spi_readtoken(struct mmc_spi_host *host) 224 { 225 return mmc_spi_skip(host, readblock_timeout, 1, 0xff); 226 } 227 228 229 /* 230 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol 231 * hosts return! The low byte holds R1_SPI bits. The next byte may hold 232 * R2_SPI bits ... for SEND_STATUS, or after data read errors. 233 * 234 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on 235 * newer cards R7 (IF_COND). 236 */ 237 238 static char *maptype(struct mmc_command *cmd) 239 { 240 switch (mmc_spi_resp_type(cmd)) { 241 case MMC_RSP_SPI_R1: return "R1"; 242 case MMC_RSP_SPI_R1B: return "R1B"; 243 case MMC_RSP_SPI_R2: return "R2/R5"; 244 case MMC_RSP_SPI_R3: return "R3/R4/R7"; 245 default: return "?"; 246 } 247 } 248 249 /* return zero, else negative errno after setting cmd->error */ 250 static int mmc_spi_response_get(struct mmc_spi_host *host, 251 struct mmc_command *cmd, int cs_on) 252 { 253 u8 *cp = host->data->status; 254 u8 *end = cp + host->t.len; 255 int value = 0; 256 char tag[32]; 257 258 snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s", 259 cmd->opcode, maptype(cmd)); 260 261 /* Except for data block reads, the whole response will already 262 * be stored in the scratch buffer. It's somewhere after the 263 * command and the first byte we read after it. We ignore that 264 * first byte. After STOP_TRANSMISSION command it may include 265 * two data bits, but otherwise it's all ones. 266 */ 267 cp += 8; 268 while (cp < end && *cp == 0xff) 269 cp++; 270 271 /* Data block reads (R1 response types) may need more data... */ 272 if (cp == end) { 273 unsigned i; 274 275 cp = host->data->status; 276 277 /* Card sends N(CR) (== 1..8) bytes of all-ones then one 278 * status byte ... and we already scanned 2 bytes. 279 * 280 * REVISIT block read paths use nasty byte-at-a-time I/O 281 * so it can always DMA directly into the target buffer. 282 * It'd probably be better to memcpy() the first chunk and 283 * avoid extra i/o calls... 284 */ 285 for (i = 2; i < 9; i++) { 286 value = mmc_spi_readbytes(host, 1); 287 if (value < 0) 288 goto done; 289 if (*cp != 0xff) 290 goto checkstatus; 291 } 292 value = -ETIMEDOUT; 293 goto done; 294 } 295 296 checkstatus: 297 if (*cp & 0x80) { 298 dev_dbg(&host->spi->dev, "%s: INVALID RESPONSE, %02x\n", 299 tag, *cp); 300 value = -EBADR; 301 goto done; 302 } 303 304 cmd->resp[0] = *cp++; 305 cmd->error = 0; 306 307 /* Status byte: the entire seven-bit R1 response. */ 308 if (cmd->resp[0] != 0) { 309 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS 310 | R1_SPI_ILLEGAL_COMMAND) 311 & cmd->resp[0]) 312 value = -EINVAL; 313 else if (R1_SPI_COM_CRC & cmd->resp[0]) 314 value = -EILSEQ; 315 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET) 316 & cmd->resp[0]) 317 value = -EIO; 318 /* else R1_SPI_IDLE, "it's resetting" */ 319 } 320 321 switch (mmc_spi_resp_type(cmd)) { 322 323 /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads) 324 * and less-common stuff like various erase operations. 325 */ 326 case MMC_RSP_SPI_R1B: 327 /* maybe we read all the busy tokens already */ 328 while (cp < end && *cp == 0) 329 cp++; 330 if (cp == end) 331 mmc_spi_wait_unbusy(host, r1b_timeout); 332 break; 333 334 /* SPI R2 == R1 + second status byte; SEND_STATUS 335 * SPI R5 == R1 + data byte; IO_RW_DIRECT 336 */ 337 case MMC_RSP_SPI_R2: 338 cmd->resp[0] |= *cp << 8; 339 break; 340 341 /* SPI R3, R4, or R7 == R1 + 4 bytes */ 342 case MMC_RSP_SPI_R3: 343 cmd->resp[1] = get_unaligned_be32(cp); 344 break; 345 346 /* SPI R1 == just one status byte */ 347 case MMC_RSP_SPI_R1: 348 break; 349 350 default: 351 dev_dbg(&host->spi->dev, "bad response type %04x\n", 352 mmc_spi_resp_type(cmd)); 353 if (value >= 0) 354 value = -EINVAL; 355 goto done; 356 } 357 358 if (value < 0) 359 dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n", 360 tag, cmd->resp[0], cmd->resp[1]); 361 362 /* disable chipselect on errors and some success cases */ 363 if (value >= 0 && cs_on) 364 return value; 365 done: 366 if (value < 0) 367 cmd->error = value; 368 mmc_cs_off(host); 369 return value; 370 } 371 372 /* Issue command and read its response. 373 * Returns zero on success, negative for error. 374 * 375 * On error, caller must cope with mmc core retry mechanism. That 376 * means immediate low-level resubmit, which affects the bus lock... 377 */ 378 static int 379 mmc_spi_command_send(struct mmc_spi_host *host, 380 struct mmc_request *mrq, 381 struct mmc_command *cmd, int cs_on) 382 { 383 struct scratch *data = host->data; 384 u8 *cp = data->status; 385 u32 arg = cmd->arg; 386 int status; 387 struct spi_transfer *t; 388 389 /* We can handle most commands (except block reads) in one full 390 * duplex I/O operation before either starting the next transfer 391 * (data block or command) or else deselecting the card. 392 * 393 * First, write 7 bytes: 394 * - an all-ones byte to ensure the card is ready 395 * - opcode byte (plus start and transmission bits) 396 * - four bytes of big-endian argument 397 * - crc7 (plus end bit) ... always computed, it's cheap 398 * 399 * We init the whole buffer to all-ones, which is what we need 400 * to write while we're reading (later) response data. 401 */ 402 memset(cp++, 0xff, sizeof(data->status)); 403 404 *cp++ = 0x40 | cmd->opcode; 405 *cp++ = (u8)(arg >> 24); 406 *cp++ = (u8)(arg >> 16); 407 *cp++ = (u8)(arg >> 8); 408 *cp++ = (u8)arg; 409 *cp++ = (crc7(0, &data->status[1], 5) << 1) | 0x01; 410 411 /* Then, read up to 13 bytes (while writing all-ones): 412 * - N(CR) (== 1..8) bytes of all-ones 413 * - status byte (for all response types) 414 * - the rest of the response, either: 415 * + nothing, for R1 or R1B responses 416 * + second status byte, for R2 responses 417 * + four data bytes, for R3 and R7 responses 418 * 419 * Finally, read some more bytes ... in the nice cases we know in 420 * advance how many, and reading 1 more is always OK: 421 * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish 422 * - N(RC) (== 1..N) bytes of all-ones, before next command 423 * - N(WR) (== 1..N) bytes of all-ones, before data write 424 * 425 * So in those cases one full duplex I/O of at most 21 bytes will 426 * handle the whole command, leaving the card ready to receive a 427 * data block or new command. We do that whenever we can, shaving 428 * CPU and IRQ costs (especially when using DMA or FIFOs). 429 * 430 * There are two other cases, where it's not generally practical 431 * to rely on a single I/O: 432 * 433 * - R1B responses need at least N(EC) bytes of all-zeroes. 434 * 435 * In this case we can *try* to fit it into one I/O, then 436 * maybe read more data later. 437 * 438 * - Data block reads are more troublesome, since a variable 439 * number of padding bytes precede the token and data. 440 * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID 441 * + N(AC) (== 1..many) bytes of all-ones 442 * 443 * In this case we currently only have minimal speedups here: 444 * when N(CR) == 1 we can avoid I/O in response_get(). 445 */ 446 if (cs_on && (mrq->data->flags & MMC_DATA_READ)) { 447 cp += 2; /* min(N(CR)) + status */ 448 /* R1 */ 449 } else { 450 cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */ 451 if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */ 452 cp++; 453 else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */ 454 cp += 4; 455 else if (cmd->flags & MMC_RSP_BUSY) /* R1B */ 456 cp = data->status + sizeof(data->status); 457 /* else: R1 (most commands) */ 458 } 459 460 dev_dbg(&host->spi->dev, " mmc_spi: CMD%d, resp %s\n", 461 cmd->opcode, maptype(cmd)); 462 463 /* send command, leaving chipselect active */ 464 spi_message_init(&host->m); 465 466 t = &host->t; 467 memset(t, 0, sizeof(*t)); 468 t->tx_buf = t->rx_buf = data->status; 469 t->tx_dma = t->rx_dma = host->data_dma; 470 t->len = cp - data->status; 471 t->cs_change = 1; 472 spi_message_add_tail(t, &host->m); 473 474 if (host->dma_dev) { 475 host->m.is_dma_mapped = 1; 476 dma_sync_single_for_device(host->dma_dev, 477 host->data_dma, sizeof(*host->data), 478 DMA_BIDIRECTIONAL); 479 } 480 status = spi_sync(host->spi, &host->m); 481 482 if (host->dma_dev) 483 dma_sync_single_for_cpu(host->dma_dev, 484 host->data_dma, sizeof(*host->data), 485 DMA_BIDIRECTIONAL); 486 if (status < 0) { 487 dev_dbg(&host->spi->dev, " ... write returned %d\n", status); 488 cmd->error = status; 489 return status; 490 } 491 492 /* after no-data commands and STOP_TRANSMISSION, chipselect off */ 493 return mmc_spi_response_get(host, cmd, cs_on); 494 } 495 496 /* Build data message with up to four separate transfers. For TX, we 497 * start by writing the data token. And in most cases, we finish with 498 * a status transfer. 499 * 500 * We always provide TX data for data and CRC. The MMC/SD protocol 501 * requires us to write ones; but Linux defaults to writing zeroes; 502 * so we explicitly initialize it to all ones on RX paths. 503 * 504 * We also handle DMA mapping, so the underlying SPI controller does 505 * not need to (re)do it for each message. 506 */ 507 static void 508 mmc_spi_setup_data_message( 509 struct mmc_spi_host *host, 510 int multiple, 511 enum dma_data_direction direction) 512 { 513 struct spi_transfer *t; 514 struct scratch *scratch = host->data; 515 dma_addr_t dma = host->data_dma; 516 517 spi_message_init(&host->m); 518 if (dma) 519 host->m.is_dma_mapped = 1; 520 521 /* for reads, readblock() skips 0xff bytes before finding 522 * the token; for writes, this transfer issues that token. 523 */ 524 if (direction == DMA_TO_DEVICE) { 525 t = &host->token; 526 memset(t, 0, sizeof(*t)); 527 t->len = 1; 528 if (multiple) 529 scratch->data_token = SPI_TOKEN_MULTI_WRITE; 530 else 531 scratch->data_token = SPI_TOKEN_SINGLE; 532 t->tx_buf = &scratch->data_token; 533 if (dma) 534 t->tx_dma = dma + offsetof(struct scratch, data_token); 535 spi_message_add_tail(t, &host->m); 536 } 537 538 /* Body of transfer is buffer, then CRC ... 539 * either TX-only, or RX with TX-ones. 540 */ 541 t = &host->t; 542 memset(t, 0, sizeof(*t)); 543 t->tx_buf = host->ones; 544 t->tx_dma = host->ones_dma; 545 /* length and actual buffer info are written later */ 546 spi_message_add_tail(t, &host->m); 547 548 t = &host->crc; 549 memset(t, 0, sizeof(*t)); 550 t->len = 2; 551 if (direction == DMA_TO_DEVICE) { 552 /* the actual CRC may get written later */ 553 t->tx_buf = &scratch->crc_val; 554 if (dma) 555 t->tx_dma = dma + offsetof(struct scratch, crc_val); 556 } else { 557 t->tx_buf = host->ones; 558 t->tx_dma = host->ones_dma; 559 t->rx_buf = &scratch->crc_val; 560 if (dma) 561 t->rx_dma = dma + offsetof(struct scratch, crc_val); 562 } 563 spi_message_add_tail(t, &host->m); 564 565 /* 566 * A single block read is followed by N(EC) [0+] all-ones bytes 567 * before deselect ... don't bother. 568 * 569 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before 570 * the next block is read, or a STOP_TRANSMISSION is issued. We'll 571 * collect that single byte, so readblock() doesn't need to. 572 * 573 * For a write, the one-byte data response follows immediately, then 574 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes. 575 * Then single block reads may deselect, and multiblock ones issue 576 * the next token (next data block, or STOP_TRAN). We can try to 577 * minimize I/O ops by using a single read to collect end-of-busy. 578 */ 579 if (multiple || direction == DMA_TO_DEVICE) { 580 t = &host->early_status; 581 memset(t, 0, sizeof(*t)); 582 t->len = (direction == DMA_TO_DEVICE) 583 ? sizeof(scratch->status) 584 : 1; 585 t->tx_buf = host->ones; 586 t->tx_dma = host->ones_dma; 587 t->rx_buf = scratch->status; 588 if (dma) 589 t->rx_dma = dma + offsetof(struct scratch, status); 590 t->cs_change = 1; 591 spi_message_add_tail(t, &host->m); 592 } 593 } 594 595 /* 596 * Write one block: 597 * - caller handled preceding N(WR) [1+] all-ones bytes 598 * - data block 599 * + token 600 * + data bytes 601 * + crc16 602 * - an all-ones byte ... card writes a data-response byte 603 * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy' 604 * 605 * Return negative errno, else success. 606 */ 607 static int 608 mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t) 609 { 610 struct spi_device *spi = host->spi; 611 int status, i; 612 struct scratch *scratch = host->data; 613 614 if (host->mmc->use_spi_crc) 615 scratch->crc_val = cpu_to_be16( 616 crc_itu_t(0, t->tx_buf, t->len)); 617 if (host->dma_dev) 618 dma_sync_single_for_device(host->dma_dev, 619 host->data_dma, sizeof(*scratch), 620 DMA_BIDIRECTIONAL); 621 622 status = spi_sync(spi, &host->m); 623 624 if (status != 0) { 625 dev_dbg(&spi->dev, "write error (%d)\n", status); 626 return status; 627 } 628 629 if (host->dma_dev) 630 dma_sync_single_for_cpu(host->dma_dev, 631 host->data_dma, sizeof(*scratch), 632 DMA_BIDIRECTIONAL); 633 634 /* 635 * Get the transmission data-response reply. It must follow 636 * immediately after the data block we transferred. This reply 637 * doesn't necessarily tell whether the write operation succeeded; 638 * it just says if the transmission was ok and whether *earlier* 639 * writes succeeded; see the standard. 640 */ 641 switch (SPI_MMC_RESPONSE_CODE(scratch->status[0])) { 642 case SPI_RESPONSE_ACCEPTED: 643 status = 0; 644 break; 645 case SPI_RESPONSE_CRC_ERR: 646 /* host shall then issue MMC_STOP_TRANSMISSION */ 647 status = -EILSEQ; 648 break; 649 case SPI_RESPONSE_WRITE_ERR: 650 /* host shall then issue MMC_STOP_TRANSMISSION, 651 * and should MMC_SEND_STATUS to sort it out 652 */ 653 status = -EIO; 654 break; 655 default: 656 status = -EPROTO; 657 break; 658 } 659 if (status != 0) { 660 dev_dbg(&spi->dev, "write error %02x (%d)\n", 661 scratch->status[0], status); 662 return status; 663 } 664 665 t->tx_buf += t->len; 666 if (host->dma_dev) 667 t->tx_dma += t->len; 668 669 /* Return when not busy. If we didn't collect that status yet, 670 * we'll need some more I/O. 671 */ 672 for (i = 1; i < sizeof(scratch->status); i++) { 673 if (scratch->status[i] != 0) 674 return 0; 675 } 676 return mmc_spi_wait_unbusy(host, writeblock_timeout); 677 } 678 679 /* 680 * Read one block: 681 * - skip leading all-ones bytes ... either 682 * + N(AC) [1..f(clock,CSD)] usually, else 683 * + N(CX) [0..8] when reading CSD or CID 684 * - data block 685 * + token ... if error token, no data or crc 686 * + data bytes 687 * + crc16 688 * 689 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow 690 * before dropping chipselect. 691 * 692 * For multiblock reads, caller either reads the next block or issues a 693 * STOP_TRANSMISSION command. 694 */ 695 static int 696 mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t) 697 { 698 struct spi_device *spi = host->spi; 699 int status; 700 struct scratch *scratch = host->data; 701 702 /* At least one SD card sends an all-zeroes byte when N(CX) 703 * applies, before the all-ones bytes ... just cope with that. 704 */ 705 status = mmc_spi_readbytes(host, 1); 706 if (status < 0) 707 return status; 708 status = scratch->status[0]; 709 if (status == 0xff || status == 0) 710 status = mmc_spi_readtoken(host); 711 712 if (status == SPI_TOKEN_SINGLE) { 713 if (host->dma_dev) { 714 dma_sync_single_for_device(host->dma_dev, 715 host->data_dma, sizeof(*scratch), 716 DMA_BIDIRECTIONAL); 717 dma_sync_single_for_device(host->dma_dev, 718 t->rx_dma, t->len, 719 DMA_FROM_DEVICE); 720 } 721 722 status = spi_sync(spi, &host->m); 723 724 if (host->dma_dev) { 725 dma_sync_single_for_cpu(host->dma_dev, 726 host->data_dma, sizeof(*scratch), 727 DMA_BIDIRECTIONAL); 728 dma_sync_single_for_cpu(host->dma_dev, 729 t->rx_dma, t->len, 730 DMA_FROM_DEVICE); 731 } 732 733 } else { 734 dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status); 735 736 /* we've read extra garbage, timed out, etc */ 737 if (status < 0) 738 return status; 739 740 /* low four bits are an R2 subset, fifth seems to be 741 * vendor specific ... map them all to generic error.. 742 */ 743 return -EIO; 744 } 745 746 if (host->mmc->use_spi_crc) { 747 u16 crc = crc_itu_t(0, t->rx_buf, t->len); 748 749 be16_to_cpus(&scratch->crc_val); 750 if (scratch->crc_val != crc) { 751 dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, " 752 "computed=0x%04x len=%d\n", 753 scratch->crc_val, crc, t->len); 754 return -EILSEQ; 755 } 756 } 757 758 t->rx_buf += t->len; 759 if (host->dma_dev) 760 t->rx_dma += t->len; 761 762 return 0; 763 } 764 765 /* 766 * An MMC/SD data stage includes one or more blocks, optional CRCs, 767 * and inline handshaking. That handhaking makes it unlike most 768 * other SPI protocol stacks. 769 */ 770 static void 771 mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, 772 struct mmc_data *data, u32 blk_size) 773 { 774 struct spi_device *spi = host->spi; 775 struct device *dma_dev = host->dma_dev; 776 struct spi_transfer *t; 777 enum dma_data_direction direction; 778 struct scatterlist *sg; 779 unsigned n_sg; 780 int multiple = (data->blocks > 1); 781 782 if (data->flags & MMC_DATA_READ) 783 direction = DMA_FROM_DEVICE; 784 else 785 direction = DMA_TO_DEVICE; 786 mmc_spi_setup_data_message(host, multiple, direction); 787 t = &host->t; 788 789 /* Handle scatterlist segments one at a time, with synch for 790 * each 512-byte block 791 */ 792 for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) { 793 int status = 0; 794 dma_addr_t dma_addr = 0; 795 void *kmap_addr; 796 unsigned length = sg->length; 797 enum dma_data_direction dir = direction; 798 799 /* set up dma mapping for controller drivers that might 800 * use DMA ... though they may fall back to PIO 801 */ 802 if (dma_dev) { 803 /* never invalidate whole *shared* pages ... */ 804 if ((sg->offset != 0 || length != PAGE_SIZE) 805 && dir == DMA_FROM_DEVICE) 806 dir = DMA_BIDIRECTIONAL; 807 808 dma_addr = dma_map_page(dma_dev, sg_page(sg), 0, 809 PAGE_SIZE, dir); 810 if (direction == DMA_TO_DEVICE) 811 t->tx_dma = dma_addr + sg->offset; 812 else 813 t->rx_dma = dma_addr + sg->offset; 814 } 815 816 /* allow pio too; we don't allow highmem */ 817 kmap_addr = kmap(sg_page(sg)); 818 if (direction == DMA_TO_DEVICE) 819 t->tx_buf = kmap_addr + sg->offset; 820 else 821 t->rx_buf = kmap_addr + sg->offset; 822 823 /* transfer each block, and update request status */ 824 while (length) { 825 t->len = min(length, blk_size); 826 827 dev_dbg(&host->spi->dev, 828 " mmc_spi: %s block, %d bytes\n", 829 (direction == DMA_TO_DEVICE) 830 ? "write" 831 : "read", 832 t->len); 833 834 if (direction == DMA_TO_DEVICE) 835 status = mmc_spi_writeblock(host, t); 836 else 837 status = mmc_spi_readblock(host, t); 838 if (status < 0) 839 break; 840 841 data->bytes_xfered += t->len; 842 length -= t->len; 843 844 if (!multiple) 845 break; 846 } 847 848 /* discard mappings */ 849 if (direction == DMA_FROM_DEVICE) 850 flush_kernel_dcache_page(sg_page(sg)); 851 kunmap(sg_page(sg)); 852 if (dma_dev) 853 dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir); 854 855 if (status < 0) { 856 data->error = status; 857 dev_dbg(&spi->dev, "%s status %d\n", 858 (direction == DMA_TO_DEVICE) 859 ? "write" : "read", 860 status); 861 break; 862 } 863 } 864 865 /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that 866 * can be issued before multiblock writes. Unlike its more widely 867 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23), 868 * that can affect the STOP_TRAN logic. Complete (and current) 869 * MMC specs should sort that out before Linux starts using CMD23. 870 */ 871 if (direction == DMA_TO_DEVICE && multiple) { 872 struct scratch *scratch = host->data; 873 int tmp; 874 const unsigned statlen = sizeof(scratch->status); 875 876 dev_dbg(&spi->dev, " mmc_spi: STOP_TRAN\n"); 877 878 /* Tweak the per-block message we set up earlier by morphing 879 * it to hold single buffer with the token followed by some 880 * all-ones bytes ... skip N(BR) (0..1), scan the rest for 881 * "not busy any longer" status, and leave chip selected. 882 */ 883 INIT_LIST_HEAD(&host->m.transfers); 884 list_add(&host->early_status.transfer_list, 885 &host->m.transfers); 886 887 memset(scratch->status, 0xff, statlen); 888 scratch->status[0] = SPI_TOKEN_STOP_TRAN; 889 890 host->early_status.tx_buf = host->early_status.rx_buf; 891 host->early_status.tx_dma = host->early_status.rx_dma; 892 host->early_status.len = statlen; 893 894 if (host->dma_dev) 895 dma_sync_single_for_device(host->dma_dev, 896 host->data_dma, sizeof(*scratch), 897 DMA_BIDIRECTIONAL); 898 899 tmp = spi_sync(spi, &host->m); 900 901 if (host->dma_dev) 902 dma_sync_single_for_cpu(host->dma_dev, 903 host->data_dma, sizeof(*scratch), 904 DMA_BIDIRECTIONAL); 905 906 if (tmp < 0) { 907 if (!data->error) 908 data->error = tmp; 909 return; 910 } 911 912 /* Ideally we collected "not busy" status with one I/O, 913 * avoiding wasteful byte-at-a-time scanning... but more 914 * I/O is often needed. 915 */ 916 for (tmp = 2; tmp < statlen; tmp++) { 917 if (scratch->status[tmp] != 0) 918 return; 919 } 920 tmp = mmc_spi_wait_unbusy(host, writeblock_timeout); 921 if (tmp < 0 && !data->error) 922 data->error = tmp; 923 } 924 } 925 926 /****************************************************************************/ 927 928 /* 929 * MMC driver implementation -- the interface to the MMC stack 930 */ 931 932 static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) 933 { 934 struct mmc_spi_host *host = mmc_priv(mmc); 935 int status = -EINVAL; 936 937 #ifdef DEBUG 938 /* MMC core and layered drivers *MUST* issue SPI-aware commands */ 939 { 940 struct mmc_command *cmd; 941 int invalid = 0; 942 943 cmd = mrq->cmd; 944 if (!mmc_spi_resp_type(cmd)) { 945 dev_dbg(&host->spi->dev, "bogus command\n"); 946 cmd->error = -EINVAL; 947 invalid = 1; 948 } 949 950 cmd = mrq->stop; 951 if (cmd && !mmc_spi_resp_type(cmd)) { 952 dev_dbg(&host->spi->dev, "bogus STOP command\n"); 953 cmd->error = -EINVAL; 954 invalid = 1; 955 } 956 957 if (invalid) { 958 dump_stack(); 959 mmc_request_done(host->mmc, mrq); 960 return; 961 } 962 } 963 #endif 964 965 /* issue command; then optionally data and stop */ 966 status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); 967 if (status == 0 && mrq->data) { 968 mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz); 969 if (mrq->stop) 970 status = mmc_spi_command_send(host, mrq, mrq->stop, 0); 971 else 972 mmc_cs_off(host); 973 } 974 975 mmc_request_done(host->mmc, mrq); 976 } 977 978 /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0" 979 * 980 * NOTE that here we can't know that the card has just been powered up; 981 * not all MMC/SD sockets support power switching. 982 * 983 * FIXME when the card is still in SPI mode, e.g. from a previous kernel, 984 * this doesn't seem to do the right thing at all... 985 */ 986 static void mmc_spi_initsequence(struct mmc_spi_host *host) 987 { 988 /* Try to be very sure any previous command has completed; 989 * wait till not-busy, skip debris from any old commands. 990 */ 991 mmc_spi_wait_unbusy(host, r1b_timeout); 992 mmc_spi_readbytes(host, 10); 993 994 /* 995 * Do a burst with chipselect active-high. We need to do this to 996 * meet the requirement of 74 clock cycles with both chipselect 997 * and CMD (MOSI) high before CMD0 ... after the card has been 998 * powered up to Vdd(min), and so is ready to take commands. 999 * 1000 * Some cards are particularly needy of this (e.g. Viking "SD256") 1001 * while most others don't seem to care. 1002 * 1003 * Note that this is one of the places MMC/SD plays games with the 1004 * SPI protocol. Another is that when chipselect is released while 1005 * the card returns BUSY status, the clock must issue several cycles 1006 * with chipselect high before the card will stop driving its output. 1007 */ 1008 host->spi->mode |= SPI_CS_HIGH; 1009 if (spi_setup(host->spi) != 0) { 1010 /* Just warn; most cards work without it. */ 1011 dev_warn(&host->spi->dev, 1012 "can't change chip-select polarity\n"); 1013 host->spi->mode &= ~SPI_CS_HIGH; 1014 } else { 1015 mmc_spi_readbytes(host, 18); 1016 1017 host->spi->mode &= ~SPI_CS_HIGH; 1018 if (spi_setup(host->spi) != 0) { 1019 /* Wot, we can't get the same setup we had before? */ 1020 dev_err(&host->spi->dev, 1021 "can't restore chip-select polarity\n"); 1022 } 1023 } 1024 } 1025 1026 static char *mmc_powerstring(u8 power_mode) 1027 { 1028 switch (power_mode) { 1029 case MMC_POWER_OFF: return "off"; 1030 case MMC_POWER_UP: return "up"; 1031 case MMC_POWER_ON: return "on"; 1032 } 1033 return "?"; 1034 } 1035 1036 static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1037 { 1038 struct mmc_spi_host *host = mmc_priv(mmc); 1039 1040 if (host->power_mode != ios->power_mode) { 1041 int canpower; 1042 1043 canpower = host->pdata && host->pdata->setpower; 1044 1045 dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n", 1046 mmc_powerstring(ios->power_mode), 1047 ios->vdd, 1048 canpower ? ", can switch" : ""); 1049 1050 /* switch power on/off if possible, accounting for 1051 * max 250msec powerup time if needed. 1052 */ 1053 if (canpower) { 1054 switch (ios->power_mode) { 1055 case MMC_POWER_OFF: 1056 case MMC_POWER_UP: 1057 host->pdata->setpower(&host->spi->dev, 1058 ios->vdd); 1059 if (ios->power_mode == MMC_POWER_UP) 1060 msleep(host->powerup_msecs); 1061 } 1062 } 1063 1064 /* See 6.4.1 in the simplified SD card physical spec 2.0 */ 1065 if (ios->power_mode == MMC_POWER_ON) 1066 mmc_spi_initsequence(host); 1067 1068 /* If powering down, ground all card inputs to avoid power 1069 * delivery from data lines! On a shared SPI bus, this 1070 * will probably be temporary; 6.4.2 of the simplified SD 1071 * spec says this must last at least 1msec. 1072 * 1073 * - Clock low means CPOL 0, e.g. mode 0 1074 * - MOSI low comes from writing zero 1075 * - Chipselect is usually active low... 1076 */ 1077 if (canpower && ios->power_mode == MMC_POWER_OFF) { 1078 int mres; 1079 1080 host->spi->mode &= ~(SPI_CPOL|SPI_CPHA); 1081 mres = spi_setup(host->spi); 1082 if (mres < 0) 1083 dev_dbg(&host->spi->dev, 1084 "switch to SPI mode 0 failed\n"); 1085 1086 if (spi_w8r8(host->spi, 0x00) < 0) 1087 dev_dbg(&host->spi->dev, 1088 "put spi signals to low failed\n"); 1089 1090 /* 1091 * Now clock should be low due to spi mode 0; 1092 * MOSI should be low because of written 0x00; 1093 * chipselect should be low (it is active low) 1094 * power supply is off, so now MMC is off too! 1095 * 1096 * FIXME no, chipselect can be high since the 1097 * device is inactive and SPI_CS_HIGH is clear... 1098 */ 1099 msleep(10); 1100 if (mres == 0) { 1101 host->spi->mode |= (SPI_CPOL|SPI_CPHA); 1102 mres = spi_setup(host->spi); 1103 if (mres < 0) 1104 dev_dbg(&host->spi->dev, 1105 "switch back to SPI mode 3" 1106 " failed\n"); 1107 } 1108 } 1109 1110 host->power_mode = ios->power_mode; 1111 } 1112 1113 if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) { 1114 int status; 1115 1116 host->spi->max_speed_hz = ios->clock; 1117 status = spi_setup(host->spi); 1118 dev_dbg(&host->spi->dev, 1119 "mmc_spi: clock to %d Hz, %d\n", 1120 host->spi->max_speed_hz, status); 1121 } 1122 } 1123 1124 static int mmc_spi_get_ro(struct mmc_host *mmc) 1125 { 1126 struct mmc_spi_host *host = mmc_priv(mmc); 1127 1128 if (host->pdata && host->pdata->get_ro) 1129 return host->pdata->get_ro(mmc->parent); 1130 /* board doesn't support read only detection; assume writeable */ 1131 return 0; 1132 } 1133 1134 1135 static const struct mmc_host_ops mmc_spi_ops = { 1136 .request = mmc_spi_request, 1137 .set_ios = mmc_spi_set_ios, 1138 .get_ro = mmc_spi_get_ro, 1139 }; 1140 1141 1142 /****************************************************************************/ 1143 1144 /* 1145 * SPI driver implementation 1146 */ 1147 1148 static irqreturn_t 1149 mmc_spi_detect_irq(int irq, void *mmc) 1150 { 1151 struct mmc_spi_host *host = mmc_priv(mmc); 1152 u16 delay_msec = max(host->pdata->detect_delay, (u16)100); 1153 1154 mmc_detect_change(mmc, msecs_to_jiffies(delay_msec)); 1155 return IRQ_HANDLED; 1156 } 1157 1158 struct count_children { 1159 unsigned n; 1160 struct bus_type *bus; 1161 }; 1162 1163 static int maybe_count_child(struct device *dev, void *c) 1164 { 1165 struct count_children *ccp = c; 1166 1167 if (dev->bus == ccp->bus) { 1168 if (ccp->n) 1169 return -EBUSY; 1170 ccp->n++; 1171 } 1172 return 0; 1173 } 1174 1175 static int mmc_spi_probe(struct spi_device *spi) 1176 { 1177 void *ones; 1178 struct mmc_host *mmc; 1179 struct mmc_spi_host *host; 1180 int status; 1181 1182 /* MMC and SD specs only seem to care that sampling is on the 1183 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode 1184 * should be legit. We'll use mode 0 since it seems to be a 1185 * bit less troublesome on some hardware ... unclear why. 1186 */ 1187 spi->mode = SPI_MODE_0; 1188 spi->bits_per_word = 8; 1189 1190 status = spi_setup(spi); 1191 if (status < 0) { 1192 dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n", 1193 spi->mode, spi->max_speed_hz / 1000, 1194 status); 1195 return status; 1196 } 1197 1198 /* We can use the bus safely iff nobody else will interfere with us. 1199 * Most commands consist of one SPI message to issue a command, then 1200 * several more to collect its response, then possibly more for data 1201 * transfer. Clocking access to other devices during that period will 1202 * corrupt the command execution. 1203 * 1204 * Until we have software primitives which guarantee non-interference, 1205 * we'll aim for a hardware-level guarantee. 1206 * 1207 * REVISIT we can't guarantee another device won't be added later... 1208 */ 1209 if (spi->master->num_chipselect > 1) { 1210 struct count_children cc; 1211 1212 cc.n = 0; 1213 cc.bus = spi->dev.bus; 1214 status = device_for_each_child(spi->dev.parent, &cc, 1215 maybe_count_child); 1216 if (status < 0) { 1217 dev_err(&spi->dev, "can't share SPI bus\n"); 1218 return status; 1219 } 1220 1221 dev_warn(&spi->dev, "ASSUMING SPI bus stays unshared!\n"); 1222 } 1223 1224 /* We need a supply of ones to transmit. This is the only time 1225 * the CPU touches these, so cache coherency isn't a concern. 1226 * 1227 * NOTE if many systems use more than one MMC-over-SPI connector 1228 * it'd save some memory to share this. That's evidently rare. 1229 */ 1230 status = -ENOMEM; 1231 ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL); 1232 if (!ones) 1233 goto nomem; 1234 memset(ones, 0xff, MMC_SPI_BLOCKSIZE); 1235 1236 mmc = mmc_alloc_host(sizeof(*host), &spi->dev); 1237 if (!mmc) 1238 goto nomem; 1239 1240 mmc->ops = &mmc_spi_ops; 1241 mmc->max_blk_size = MMC_SPI_BLOCKSIZE; 1242 1243 /* As long as we keep track of the number of successfully 1244 * transmitted blocks, we're good for multiwrite. 1245 */ 1246 mmc->caps = MMC_CAP_SPI | MMC_CAP_MULTIWRITE; 1247 1248 /* SPI doesn't need the lowspeed device identification thing for 1249 * MMC or SD cards, since it never comes up in open drain mode. 1250 * That's good; some SPI masters can't handle very low speeds! 1251 * 1252 * However, low speed SDIO cards need not handle over 400 KHz; 1253 * that's the only reason not to use a few MHz for f_min (until 1254 * the upper layer reads the target frequency from the CSD). 1255 */ 1256 mmc->f_min = 400000; 1257 mmc->f_max = spi->max_speed_hz; 1258 1259 host = mmc_priv(mmc); 1260 host->mmc = mmc; 1261 host->spi = spi; 1262 1263 host->ones = ones; 1264 1265 /* Platform data is used to hook up things like card sensing 1266 * and power switching gpios. 1267 */ 1268 host->pdata = spi->dev.platform_data; 1269 if (host->pdata) 1270 mmc->ocr_avail = host->pdata->ocr_mask; 1271 if (!mmc->ocr_avail) { 1272 dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n"); 1273 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; 1274 } 1275 if (host->pdata && host->pdata->setpower) { 1276 host->powerup_msecs = host->pdata->powerup_msecs; 1277 if (!host->powerup_msecs || host->powerup_msecs > 250) 1278 host->powerup_msecs = 250; 1279 } 1280 1281 dev_set_drvdata(&spi->dev, mmc); 1282 1283 /* preallocate dma buffers */ 1284 host->data = kmalloc(sizeof(*host->data), GFP_KERNEL); 1285 if (!host->data) 1286 goto fail_nobuf1; 1287 1288 if (spi->master->dev.parent->dma_mask) { 1289 struct device *dev = spi->master->dev.parent; 1290 1291 host->dma_dev = dev; 1292 host->ones_dma = dma_map_single(dev, ones, 1293 MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); 1294 host->data_dma = dma_map_single(dev, host->data, 1295 sizeof(*host->data), DMA_BIDIRECTIONAL); 1296 1297 /* REVISIT in theory those map operations can fail... */ 1298 1299 dma_sync_single_for_cpu(host->dma_dev, 1300 host->data_dma, sizeof(*host->data), 1301 DMA_BIDIRECTIONAL); 1302 } 1303 1304 /* setup message for status/busy readback */ 1305 spi_message_init(&host->readback); 1306 host->readback.is_dma_mapped = (host->dma_dev != NULL); 1307 1308 spi_message_add_tail(&host->status, &host->readback); 1309 host->status.tx_buf = host->ones; 1310 host->status.tx_dma = host->ones_dma; 1311 host->status.rx_buf = &host->data->status; 1312 host->status.rx_dma = host->data_dma + offsetof(struct scratch, status); 1313 host->status.cs_change = 1; 1314 1315 /* register card detect irq */ 1316 if (host->pdata && host->pdata->init) { 1317 status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc); 1318 if (status != 0) 1319 goto fail_glue_init; 1320 } 1321 1322 status = mmc_add_host(mmc); 1323 if (status != 0) 1324 goto fail_add_host; 1325 1326 dev_info(&spi->dev, "SD/MMC host %s%s%s%s\n", 1327 mmc->class_dev.bus_id, 1328 host->dma_dev ? "" : ", no DMA", 1329 (host->pdata && host->pdata->get_ro) 1330 ? "" : ", no WP", 1331 (host->pdata && host->pdata->setpower) 1332 ? "" : ", no poweroff"); 1333 return 0; 1334 1335 fail_add_host: 1336 mmc_remove_host (mmc); 1337 fail_glue_init: 1338 if (host->dma_dev) 1339 dma_unmap_single(host->dma_dev, host->data_dma, 1340 sizeof(*host->data), DMA_BIDIRECTIONAL); 1341 kfree(host->data); 1342 1343 fail_nobuf1: 1344 mmc_free_host(mmc); 1345 dev_set_drvdata(&spi->dev, NULL); 1346 1347 nomem: 1348 kfree(ones); 1349 return status; 1350 } 1351 1352 1353 static int __devexit mmc_spi_remove(struct spi_device *spi) 1354 { 1355 struct mmc_host *mmc = dev_get_drvdata(&spi->dev); 1356 struct mmc_spi_host *host; 1357 1358 if (mmc) { 1359 host = mmc_priv(mmc); 1360 1361 /* prevent new mmc_detect_change() calls */ 1362 if (host->pdata && host->pdata->exit) 1363 host->pdata->exit(&spi->dev, mmc); 1364 1365 mmc_remove_host(mmc); 1366 1367 if (host->dma_dev) { 1368 dma_unmap_single(host->dma_dev, host->ones_dma, 1369 MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); 1370 dma_unmap_single(host->dma_dev, host->data_dma, 1371 sizeof(*host->data), DMA_BIDIRECTIONAL); 1372 } 1373 1374 kfree(host->data); 1375 kfree(host->ones); 1376 1377 spi->max_speed_hz = mmc->f_max; 1378 mmc_free_host(mmc); 1379 dev_set_drvdata(&spi->dev, NULL); 1380 } 1381 return 0; 1382 } 1383 1384 1385 static struct spi_driver mmc_spi_driver = { 1386 .driver = { 1387 .name = "mmc_spi", 1388 .bus = &spi_bus_type, 1389 .owner = THIS_MODULE, 1390 }, 1391 .probe = mmc_spi_probe, 1392 .remove = __devexit_p(mmc_spi_remove), 1393 }; 1394 1395 1396 static int __init mmc_spi_init(void) 1397 { 1398 return spi_register_driver(&mmc_spi_driver); 1399 } 1400 module_init(mmc_spi_init); 1401 1402 1403 static void __exit mmc_spi_exit(void) 1404 { 1405 spi_unregister_driver(&mmc_spi_driver); 1406 } 1407 module_exit(mmc_spi_exit); 1408 1409 1410 MODULE_AUTHOR("Mike Lavender, David Brownell, " 1411 "Hans-Peter Nilsson, Jan Nikitenko"); 1412 MODULE_DESCRIPTION("SPI SD/MMC host driver"); 1413 MODULE_LICENSE("GPL"); 1414