1 /* 2 * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller 3 * 4 * Copyright (C) 2015 Endless Mobile, Inc. 5 * Author: Carlo Caione <carlo@endlessm.com> 6 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/ioport.h> 24 #include <linux/platform_device.h> 25 #include <linux/of_platform.h> 26 #include <linux/timer.h> 27 #include <linux/types.h> 28 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #define MESON_MX_SDIO_ARGU 0x00 35 36 #define MESON_MX_SDIO_SEND 0x04 37 #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0) 38 #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8) 39 #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16) 40 #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17) 41 #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18) 42 #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19) 43 #define MESON_MX_SDIO_SEND_DATA BIT(20) 44 #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21) 45 #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24) 46 47 #define MESON_MX_SDIO_CONF 0x08 48 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0 49 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10 50 #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10) 51 #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11) 52 #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12) 53 #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18) 54 #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19) 55 #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20) 56 #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21) 57 #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23) 58 #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29) 59 60 #define MESON_MX_SDIO_IRQS 0x0c 61 #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0) 62 #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4) 63 #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5) 64 #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6) 65 #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7) 66 #define MESON_MX_SDIO_IRQS_IF_INT BIT(8) 67 #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9) 68 #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12) 69 #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16) 70 #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17) 71 #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18) 72 #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19) 73 74 #define MESON_MX_SDIO_IRQC 0x10 75 #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3) 76 #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4) 77 #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6) 78 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8) 79 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9) 80 #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(10, 13) 81 #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15) 82 #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30) 83 #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31) 84 85 #define MESON_MX_SDIO_MULT 0x14 86 #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0) 87 #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2) 88 #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3) 89 #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4) 90 #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5) 91 #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8) 92 #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10) 93 #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11) 94 #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12) 95 96 #define MESON_MX_SDIO_ADDR 0x18 97 98 #define MESON_MX_SDIO_EXT 0x1c 99 #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16) 100 101 #define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024) 102 #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1) 103 #define MESON_MX_SDIO_MAX_SLOTS 3 104 105 struct meson_mx_mmc_host { 106 struct device *controller_dev; 107 108 struct clk *parent_clk; 109 struct clk *core_clk; 110 struct clk_divider cfg_div; 111 struct clk *cfg_div_clk; 112 struct clk_fixed_factor fixed_factor; 113 struct clk *fixed_factor_clk; 114 115 void __iomem *base; 116 int irq; 117 spinlock_t irq_lock; 118 119 struct timer_list cmd_timeout; 120 121 unsigned int slot_id; 122 struct mmc_host *mmc; 123 124 struct mmc_request *mrq; 125 struct mmc_command *cmd; 126 int error; 127 }; 128 129 static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask, 130 u32 val) 131 { 132 struct meson_mx_mmc_host *host = mmc_priv(mmc); 133 u32 regval; 134 135 regval = readl(host->base + reg); 136 regval &= ~mask; 137 regval |= (val & mask); 138 139 writel(regval, host->base + reg); 140 } 141 142 static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host) 143 { 144 writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC); 145 udelay(2); 146 } 147 148 static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd) 149 { 150 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 151 return cmd->mrq->cmd; 152 else if (mmc_op_multi(cmd->opcode) && 153 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 154 return cmd->mrq->stop; 155 else 156 return NULL; 157 } 158 159 static void meson_mx_mmc_start_cmd(struct mmc_host *mmc, 160 struct mmc_command *cmd) 161 { 162 struct meson_mx_mmc_host *host = mmc_priv(mmc); 163 unsigned int pack_size; 164 unsigned long irqflags, timeout; 165 u32 mult, send = 0, ext = 0; 166 167 host->cmd = cmd; 168 169 if (cmd->busy_timeout) 170 timeout = msecs_to_jiffies(cmd->busy_timeout); 171 else 172 timeout = msecs_to_jiffies(1000); 173 174 switch (mmc_resp_type(cmd)) { 175 case MMC_RSP_R1: 176 case MMC_RSP_R1B: 177 case MMC_RSP_R3: 178 /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */ 179 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45); 180 break; 181 case MMC_RSP_R2: 182 /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */ 183 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133); 184 send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8; 185 break; 186 default: 187 break; 188 } 189 190 if (!(cmd->flags & MMC_RSP_CRC)) 191 send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7; 192 193 if (cmd->flags & MMC_RSP_BUSY) 194 send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY; 195 196 if (cmd->data) { 197 send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, 198 (cmd->data->blocks - 1)); 199 200 pack_size = cmd->data->blksz * BITS_PER_BYTE; 201 if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 202 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4; 203 else 204 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1; 205 206 ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, 207 pack_size); 208 209 if (cmd->data->flags & MMC_DATA_WRITE) 210 send |= MESON_MX_SDIO_SEND_DATA; 211 else 212 send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA; 213 214 cmd->data->bytes_xfered = 0; 215 } 216 217 send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK, 218 (0x40 | cmd->opcode)); 219 220 spin_lock_irqsave(&host->irq_lock, irqflags); 221 222 mult = readl(host->base + MESON_MX_SDIO_MULT); 223 mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK; 224 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id); 225 mult |= BIT(31); 226 writel(mult, host->base + MESON_MX_SDIO_MULT); 227 228 /* enable the CMD done interrupt */ 229 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC, 230 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN, 231 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN); 232 233 /* clear pending interrupts */ 234 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS, 235 MESON_MX_SDIO_IRQS_CMD_INT, 236 MESON_MX_SDIO_IRQS_CMD_INT); 237 238 writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU); 239 writel(ext, host->base + MESON_MX_SDIO_EXT); 240 writel(send, host->base + MESON_MX_SDIO_SEND); 241 242 spin_unlock_irqrestore(&host->irq_lock, irqflags); 243 244 mod_timer(&host->cmd_timeout, jiffies + timeout); 245 } 246 247 static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host) 248 { 249 struct mmc_request *mrq; 250 251 mrq = host->mrq; 252 253 host->mrq = NULL; 254 host->cmd = NULL; 255 256 mmc_request_done(host->mmc, mrq); 257 } 258 259 static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 260 { 261 struct meson_mx_mmc_host *host = mmc_priv(mmc); 262 unsigned short vdd = ios->vdd; 263 unsigned long clk_rate = ios->clock; 264 265 switch (ios->bus_width) { 266 case MMC_BUS_WIDTH_1: 267 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, 268 MESON_MX_SDIO_CONF_BUS_WIDTH, 0); 269 break; 270 271 case MMC_BUS_WIDTH_4: 272 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, 273 MESON_MX_SDIO_CONF_BUS_WIDTH, 274 MESON_MX_SDIO_CONF_BUS_WIDTH); 275 break; 276 277 case MMC_BUS_WIDTH_8: 278 default: 279 dev_err(mmc_dev(mmc), "unsupported bus width: %d\n", 280 ios->bus_width); 281 host->error = -EINVAL; 282 return; 283 } 284 285 host->error = clk_set_rate(host->cfg_div_clk, ios->clock); 286 if (host->error) { 287 dev_warn(mmc_dev(mmc), 288 "failed to set MMC clock to %lu: %d\n", 289 clk_rate, host->error); 290 return; 291 } 292 293 mmc->actual_clock = clk_get_rate(host->cfg_div_clk); 294 295 switch (ios->power_mode) { 296 case MMC_POWER_OFF: 297 vdd = 0; 298 /* fall through */ 299 case MMC_POWER_UP: 300 if (!IS_ERR(mmc->supply.vmmc)) { 301 host->error = mmc_regulator_set_ocr(mmc, 302 mmc->supply.vmmc, 303 vdd); 304 if (host->error) 305 return; 306 } 307 break; 308 } 309 } 310 311 static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq) 312 { 313 struct mmc_data *data = mrq->data; 314 int dma_len; 315 struct scatterlist *sg; 316 317 if (!data) 318 return 0; 319 320 sg = data->sg; 321 if (sg->offset & 3 || sg->length & 3) { 322 dev_err(mmc_dev(mmc), 323 "unaligned scatterlist: offset %x length %d\n", 324 sg->offset, sg->length); 325 return -EINVAL; 326 } 327 328 dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 329 mmc_get_dma_dir(data)); 330 if (dma_len <= 0) { 331 dev_err(mmc_dev(mmc), "dma_map_sg failed\n"); 332 return -ENOMEM; 333 } 334 335 return 0; 336 } 337 338 static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 339 { 340 struct meson_mx_mmc_host *host = mmc_priv(mmc); 341 struct mmc_command *cmd = mrq->cmd; 342 343 if (!host->error) 344 host->error = meson_mx_mmc_map_dma(mmc, mrq); 345 346 if (host->error) { 347 cmd->error = host->error; 348 mmc_request_done(mmc, mrq); 349 return; 350 } 351 352 host->mrq = mrq; 353 354 if (mrq->data) 355 writel(sg_dma_address(mrq->data->sg), 356 host->base + MESON_MX_SDIO_ADDR); 357 358 if (mrq->sbc) 359 meson_mx_mmc_start_cmd(mmc, mrq->sbc); 360 else 361 meson_mx_mmc_start_cmd(mmc, mrq->cmd); 362 } 363 364 static int meson_mx_mmc_card_busy(struct mmc_host *mmc) 365 { 366 struct meson_mx_mmc_host *host = mmc_priv(mmc); 367 u32 irqc = readl(host->base + MESON_MX_SDIO_IRQC); 368 369 return !!(irqc & MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK); 370 } 371 372 static void meson_mx_mmc_read_response(struct mmc_host *mmc, 373 struct mmc_command *cmd) 374 { 375 struct meson_mx_mmc_host *host = mmc_priv(mmc); 376 u32 mult; 377 int i, resp[4]; 378 379 mult = readl(host->base + MESON_MX_SDIO_MULT); 380 mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX; 381 mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK; 382 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0); 383 writel(mult, host->base + MESON_MX_SDIO_MULT); 384 385 if (cmd->flags & MMC_RSP_136) { 386 for (i = 0; i <= 3; i++) 387 resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU); 388 cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff); 389 cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff); 390 cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff); 391 cmd->resp[3] = (resp[3] << 8); 392 } else if (cmd->flags & MMC_RSP_PRESENT) { 393 cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU); 394 } 395 } 396 397 static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host, 398 u32 irqs, u32 send) 399 { 400 struct mmc_command *cmd = host->cmd; 401 402 /* 403 * NOTE: even though it shouldn't happen we sometimes get command 404 * interrupts twice (at least this is what it looks like). Ideally 405 * we find out why this happens and warn here as soon as it occurs. 406 */ 407 if (!cmd) 408 return IRQ_HANDLED; 409 410 cmd->error = 0; 411 meson_mx_mmc_read_response(host->mmc, cmd); 412 413 if (cmd->data) { 414 if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) || 415 (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK))) 416 cmd->error = -EILSEQ; 417 } else { 418 if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) || 419 (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7))) 420 cmd->error = -EILSEQ; 421 } 422 423 return IRQ_WAKE_THREAD; 424 } 425 426 static irqreturn_t meson_mx_mmc_irq(int irq, void *data) 427 { 428 struct meson_mx_mmc_host *host = (void *) data; 429 u32 irqs, send; 430 unsigned long irqflags; 431 irqreturn_t ret; 432 433 spin_lock_irqsave(&host->irq_lock, irqflags); 434 435 irqs = readl(host->base + MESON_MX_SDIO_IRQS); 436 send = readl(host->base + MESON_MX_SDIO_SEND); 437 438 if (irqs & MESON_MX_SDIO_IRQS_CMD_INT) 439 ret = meson_mx_mmc_process_cmd_irq(host, irqs, send); 440 else 441 ret = IRQ_HANDLED; 442 443 /* finally ACK all pending interrupts */ 444 writel(irqs, host->base + MESON_MX_SDIO_IRQS); 445 446 spin_unlock_irqrestore(&host->irq_lock, irqflags); 447 448 return ret; 449 } 450 451 static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data) 452 { 453 struct meson_mx_mmc_host *host = (void *) irq_data; 454 struct mmc_command *cmd = host->cmd, *next_cmd; 455 456 if (WARN_ON(!cmd)) 457 return IRQ_HANDLED; 458 459 del_timer_sync(&host->cmd_timeout); 460 461 if (cmd->data) { 462 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg, 463 cmd->data->sg_len, 464 mmc_get_dma_dir(cmd->data)); 465 466 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks; 467 } 468 469 next_cmd = meson_mx_mmc_get_next_cmd(cmd); 470 if (next_cmd) 471 meson_mx_mmc_start_cmd(host->mmc, next_cmd); 472 else 473 meson_mx_mmc_request_done(host); 474 475 return IRQ_HANDLED; 476 } 477 478 static void meson_mx_mmc_timeout(struct timer_list *t) 479 { 480 struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout); 481 unsigned long irqflags; 482 u32 irqc; 483 484 spin_lock_irqsave(&host->irq_lock, irqflags); 485 486 /* disable the CMD interrupt */ 487 irqc = readl(host->base + MESON_MX_SDIO_IRQC); 488 irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN; 489 writel(irqc, host->base + MESON_MX_SDIO_IRQC); 490 491 spin_unlock_irqrestore(&host->irq_lock, irqflags); 492 493 /* 494 * skip the timeout handling if the interrupt handler already processed 495 * the command. 496 */ 497 if (!host->cmd) 498 return; 499 500 dev_dbg(mmc_dev(host->mmc), 501 "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n", 502 host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS), 503 readl(host->base + MESON_MX_SDIO_ARGU)); 504 505 host->cmd->error = -ETIMEDOUT; 506 507 meson_mx_mmc_request_done(host); 508 } 509 510 static struct mmc_host_ops meson_mx_mmc_ops = { 511 .request = meson_mx_mmc_request, 512 .set_ios = meson_mx_mmc_set_ios, 513 .card_busy = meson_mx_mmc_card_busy, 514 .get_cd = mmc_gpio_get_cd, 515 .get_ro = mmc_gpio_get_ro, 516 }; 517 518 static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent) 519 { 520 struct device_node *slot_node; 521 struct platform_device *pdev; 522 523 /* 524 * TODO: the MMC core framework currently does not support 525 * controllers with multiple slots properly. So we only register 526 * the first slot for now 527 */ 528 slot_node = of_get_compatible_child(parent->of_node, "mmc-slot"); 529 if (!slot_node) { 530 dev_warn(parent, "no 'mmc-slot' sub-node found\n"); 531 return ERR_PTR(-ENOENT); 532 } 533 534 pdev = of_platform_device_create(slot_node, NULL, parent); 535 of_node_put(slot_node); 536 537 return pdev; 538 } 539 540 static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host) 541 { 542 struct mmc_host *mmc = host->mmc; 543 struct device *slot_dev = mmc_dev(mmc); 544 int ret; 545 546 if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) { 547 dev_err(slot_dev, "missing 'reg' property\n"); 548 return -EINVAL; 549 } 550 551 if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) { 552 dev_err(slot_dev, "invalid 'reg' property value %d\n", 553 host->slot_id); 554 return -EINVAL; 555 } 556 557 /* Get regulators and the supported OCR mask */ 558 ret = mmc_regulator_get_supply(mmc); 559 if (ret) 560 return ret; 561 562 mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE; 563 mmc->max_seg_size = mmc->max_req_size; 564 mmc->max_blk_count = 565 FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, 566 0xffffffff); 567 mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, 568 0xffffffff); 569 mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS); 570 mmc->max_blk_size /= BITS_PER_BYTE; 571 572 /* Get the min and max supported clock rates */ 573 mmc->f_min = clk_round_rate(host->cfg_div_clk, 1); 574 mmc->f_max = clk_round_rate(host->cfg_div_clk, 575 clk_get_rate(host->parent_clk)); 576 577 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 578 mmc->ops = &meson_mx_mmc_ops; 579 580 ret = mmc_of_parse(mmc); 581 if (ret) 582 return ret; 583 584 ret = mmc_add_host(mmc); 585 if (ret) 586 return ret; 587 588 return 0; 589 } 590 591 static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host) 592 { 593 struct clk_init_data init; 594 const char *clk_div_parent, *clk_fixed_factor_parent; 595 596 clk_fixed_factor_parent = __clk_get_name(host->parent_clk); 597 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, 598 "%s#fixed_factor", 599 dev_name(host->controller_dev)); 600 if (!init.name) 601 return -ENOMEM; 602 603 init.ops = &clk_fixed_factor_ops; 604 init.flags = 0; 605 init.parent_names = &clk_fixed_factor_parent; 606 init.num_parents = 1; 607 host->fixed_factor.div = 2; 608 host->fixed_factor.mult = 1; 609 host->fixed_factor.hw.init = &init; 610 611 host->fixed_factor_clk = devm_clk_register(host->controller_dev, 612 &host->fixed_factor.hw); 613 if (WARN_ON(IS_ERR(host->fixed_factor_clk))) 614 return PTR_ERR(host->fixed_factor_clk); 615 616 clk_div_parent = __clk_get_name(host->fixed_factor_clk); 617 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, 618 "%s#div", dev_name(host->controller_dev)); 619 if (!init.name) 620 return -ENOMEM; 621 622 init.ops = &clk_divider_ops; 623 init.flags = CLK_SET_RATE_PARENT; 624 init.parent_names = &clk_div_parent; 625 init.num_parents = 1; 626 host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF; 627 host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; 628 host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; 629 host->cfg_div.hw.init = &init; 630 host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO; 631 632 host->cfg_div_clk = devm_clk_register(host->controller_dev, 633 &host->cfg_div.hw); 634 if (WARN_ON(IS_ERR(host->cfg_div_clk))) 635 return PTR_ERR(host->cfg_div_clk); 636 637 return 0; 638 } 639 640 static int meson_mx_mmc_probe(struct platform_device *pdev) 641 { 642 struct platform_device *slot_pdev; 643 struct mmc_host *mmc; 644 struct meson_mx_mmc_host *host; 645 struct resource *res; 646 int ret, irq; 647 u32 conf; 648 649 slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev); 650 if (!slot_pdev) 651 return -ENODEV; 652 else if (IS_ERR(slot_pdev)) 653 return PTR_ERR(slot_pdev); 654 655 mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev); 656 if (!mmc) { 657 ret = -ENOMEM; 658 goto error_unregister_slot_pdev; 659 } 660 661 host = mmc_priv(mmc); 662 host->mmc = mmc; 663 host->controller_dev = &pdev->dev; 664 665 spin_lock_init(&host->irq_lock); 666 timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0); 667 668 platform_set_drvdata(pdev, host); 669 670 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 671 host->base = devm_ioremap_resource(host->controller_dev, res); 672 if (IS_ERR(host->base)) { 673 ret = PTR_ERR(host->base); 674 goto error_free_mmc; 675 } 676 677 irq = platform_get_irq(pdev, 0); 678 ret = devm_request_threaded_irq(host->controller_dev, irq, 679 meson_mx_mmc_irq, 680 meson_mx_mmc_irq_thread, IRQF_ONESHOT, 681 NULL, host); 682 if (ret) 683 goto error_free_mmc; 684 685 host->core_clk = devm_clk_get(host->controller_dev, "core"); 686 if (IS_ERR(host->core_clk)) { 687 ret = PTR_ERR(host->core_clk); 688 goto error_free_mmc; 689 } 690 691 host->parent_clk = devm_clk_get(host->controller_dev, "clkin"); 692 if (IS_ERR(host->parent_clk)) { 693 ret = PTR_ERR(host->parent_clk); 694 goto error_free_mmc; 695 } 696 697 ret = meson_mx_mmc_register_clks(host); 698 if (ret) 699 goto error_free_mmc; 700 701 ret = clk_prepare_enable(host->core_clk); 702 if (ret) { 703 dev_err(host->controller_dev, "Failed to enable core clock\n"); 704 goto error_free_mmc; 705 } 706 707 ret = clk_prepare_enable(host->cfg_div_clk); 708 if (ret) { 709 dev_err(host->controller_dev, "Failed to enable MMC clock\n"); 710 goto error_disable_core_clk; 711 } 712 713 conf = 0; 714 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39); 715 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3); 716 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2); 717 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2); 718 writel(conf, host->base + MESON_MX_SDIO_CONF); 719 720 meson_mx_mmc_soft_reset(host); 721 722 ret = meson_mx_mmc_add_host(host); 723 if (ret) 724 goto error_disable_clks; 725 726 return 0; 727 728 error_disable_clks: 729 clk_disable_unprepare(host->cfg_div_clk); 730 error_disable_core_clk: 731 clk_disable_unprepare(host->core_clk); 732 error_free_mmc: 733 mmc_free_host(mmc); 734 error_unregister_slot_pdev: 735 of_platform_device_destroy(&slot_pdev->dev, NULL); 736 return ret; 737 } 738 739 static int meson_mx_mmc_remove(struct platform_device *pdev) 740 { 741 struct meson_mx_mmc_host *host = platform_get_drvdata(pdev); 742 struct device *slot_dev = mmc_dev(host->mmc); 743 744 del_timer_sync(&host->cmd_timeout); 745 746 mmc_remove_host(host->mmc); 747 748 of_platform_device_destroy(slot_dev, NULL); 749 750 clk_disable_unprepare(host->cfg_div_clk); 751 clk_disable_unprepare(host->core_clk); 752 753 mmc_free_host(host->mmc); 754 755 return 0; 756 } 757 758 static const struct of_device_id meson_mx_mmc_of_match[] = { 759 { .compatible = "amlogic,meson8-sdio", }, 760 { .compatible = "amlogic,meson8b-sdio", }, 761 { /* sentinel */ } 762 }; 763 MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match); 764 765 static struct platform_driver meson_mx_mmc_driver = { 766 .probe = meson_mx_mmc_probe, 767 .remove = meson_mx_mmc_remove, 768 .driver = { 769 .name = "meson-mx-sdio", 770 .of_match_table = of_match_ptr(meson_mx_mmc_of_match), 771 }, 772 }; 773 774 module_platform_driver(meson_mx_mmc_driver); 775 776 MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver"); 777 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>"); 778 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 779 MODULE_LICENSE("GPL v2"); 780