1 /* 2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Kevin Hilman <khilman@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * The full GNU General Public License is included in this distribution 19 * in the file called COPYING. 20 */ 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/device.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/ioport.h> 28 #include <linux/spinlock.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 #include <linux/io.h> 35 #include <linux/clk.h> 36 #include <linux/clk-provider.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/interrupt.h> 39 40 #define DRIVER_NAME "meson-gx-mmc" 41 42 #define SD_EMMC_CLOCK 0x0 43 #define CLK_DIV_SHIFT 0 44 #define CLK_DIV_WIDTH 6 45 #define CLK_DIV_MASK 0x3f 46 #define CLK_DIV_MAX 63 47 #define CLK_SRC_SHIFT 6 48 #define CLK_SRC_WIDTH 2 49 #define CLK_SRC_MASK 0x3 50 #define CLK_SRC_XTAL 0 /* external crystal */ 51 #define CLK_SRC_XTAL_RATE 24000000 52 #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ 53 #define CLK_SRC_PLL_RATE 1000000000 54 #define CLK_PHASE_SHIFT 8 55 #define CLK_PHASE_MASK 0x3 56 #define CLK_PHASE_0 0 57 #define CLK_PHASE_90 1 58 #define CLK_PHASE_180 2 59 #define CLK_PHASE_270 3 60 #define CLK_ALWAYS_ON BIT(24) 61 62 #define SD_EMMC_DElAY 0x4 63 #define SD_EMMC_ADJUST 0x8 64 #define SD_EMMC_CALOUT 0x10 65 #define SD_EMMC_START 0x40 66 #define START_DESC_INIT BIT(0) 67 #define START_DESC_BUSY BIT(1) 68 #define START_DESC_ADDR_SHIFT 2 69 #define START_DESC_ADDR_MASK (~0x3) 70 71 #define SD_EMMC_CFG 0x44 72 #define CFG_BUS_WIDTH_SHIFT 0 73 #define CFG_BUS_WIDTH_MASK 0x3 74 #define CFG_BUS_WIDTH_1 0x0 75 #define CFG_BUS_WIDTH_4 0x1 76 #define CFG_BUS_WIDTH_8 0x2 77 #define CFG_DDR BIT(2) 78 #define CFG_BLK_LEN_SHIFT 4 79 #define CFG_BLK_LEN_MASK 0xf 80 #define CFG_RESP_TIMEOUT_SHIFT 8 81 #define CFG_RESP_TIMEOUT_MASK 0xf 82 #define CFG_RC_CC_SHIFT 12 83 #define CFG_RC_CC_MASK 0xf 84 #define CFG_STOP_CLOCK BIT(22) 85 #define CFG_CLK_ALWAYS_ON BIT(18) 86 #define CFG_CHK_DS BIT(20) 87 #define CFG_AUTO_CLK BIT(23) 88 89 #define SD_EMMC_STATUS 0x48 90 #define STATUS_BUSY BIT(31) 91 92 #define SD_EMMC_IRQ_EN 0x4c 93 #define IRQ_EN_MASK 0x3fff 94 #define IRQ_RXD_ERR_SHIFT 0 95 #define IRQ_RXD_ERR_MASK 0xff 96 #define IRQ_TXD_ERR BIT(8) 97 #define IRQ_DESC_ERR BIT(9) 98 #define IRQ_RESP_ERR BIT(10) 99 #define IRQ_RESP_TIMEOUT BIT(11) 100 #define IRQ_DESC_TIMEOUT BIT(12) 101 #define IRQ_END_OF_CHAIN BIT(13) 102 #define IRQ_RESP_STATUS BIT(14) 103 #define IRQ_SDIO BIT(15) 104 105 #define SD_EMMC_CMD_CFG 0x50 106 #define SD_EMMC_CMD_ARG 0x54 107 #define SD_EMMC_CMD_DAT 0x58 108 #define SD_EMMC_CMD_RSP 0x5c 109 #define SD_EMMC_CMD_RSP1 0x60 110 #define SD_EMMC_CMD_RSP2 0x64 111 #define SD_EMMC_CMD_RSP3 0x68 112 113 #define SD_EMMC_RXD 0x94 114 #define SD_EMMC_TXD 0x94 115 #define SD_EMMC_LAST_REG SD_EMMC_TXD 116 117 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 118 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 119 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 120 #define MUX_CLK_NUM_PARENTS 2 121 122 struct meson_host { 123 struct device *dev; 124 struct mmc_host *mmc; 125 struct mmc_request *mrq; 126 struct mmc_command *cmd; 127 128 spinlock_t lock; 129 void __iomem *regs; 130 int irq; 131 u32 ocr_mask; 132 struct clk *core_clk; 133 struct clk_mux mux; 134 struct clk *mux_clk; 135 struct clk *mux_parent[MUX_CLK_NUM_PARENTS]; 136 unsigned long current_clock; 137 138 struct clk_divider cfg_div; 139 struct clk *cfg_div_clk; 140 141 unsigned int bounce_buf_size; 142 void *bounce_buf; 143 dma_addr_t bounce_dma_addr; 144 145 bool vqmmc_enabled; 146 }; 147 148 struct sd_emmc_desc { 149 u32 cmd_cfg; 150 u32 cmd_arg; 151 u32 cmd_data; 152 u32 cmd_resp; 153 }; 154 #define CMD_CFG_LENGTH_SHIFT 0 155 #define CMD_CFG_LENGTH_MASK 0x1ff 156 #define CMD_CFG_BLOCK_MODE BIT(9) 157 #define CMD_CFG_R1B BIT(10) 158 #define CMD_CFG_END_OF_CHAIN BIT(11) 159 #define CMD_CFG_TIMEOUT_SHIFT 12 160 #define CMD_CFG_TIMEOUT_MASK 0xf 161 #define CMD_CFG_NO_RESP BIT(16) 162 #define CMD_CFG_NO_CMD BIT(17) 163 #define CMD_CFG_DATA_IO BIT(18) 164 #define CMD_CFG_DATA_WR BIT(19) 165 #define CMD_CFG_RESP_NOCRC BIT(20) 166 #define CMD_CFG_RESP_128 BIT(21) 167 #define CMD_CFG_RESP_NUM BIT(22) 168 #define CMD_CFG_DATA_NUM BIT(23) 169 #define CMD_CFG_CMD_INDEX_SHIFT 24 170 #define CMD_CFG_CMD_INDEX_MASK 0x3f 171 #define CMD_CFG_ERROR BIT(30) 172 #define CMD_CFG_OWNER BIT(31) 173 174 #define CMD_DATA_MASK (~0x3) 175 #define CMD_DATA_BIG_ENDIAN BIT(1) 176 #define CMD_DATA_SRAM BIT(0) 177 #define CMD_RESP_MASK (~0x1) 178 #define CMD_RESP_SRAM BIT(0) 179 180 static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) 181 { 182 struct mmc_host *mmc = host->mmc; 183 int ret; 184 u32 cfg; 185 186 if (clk_rate) { 187 if (WARN_ON(clk_rate > mmc->f_max)) 188 clk_rate = mmc->f_max; 189 else if (WARN_ON(clk_rate < mmc->f_min)) 190 clk_rate = mmc->f_min; 191 } 192 193 if (clk_rate == host->current_clock) 194 return 0; 195 196 /* stop clock */ 197 cfg = readl(host->regs + SD_EMMC_CFG); 198 if (!(cfg & CFG_STOP_CLOCK)) { 199 cfg |= CFG_STOP_CLOCK; 200 writel(cfg, host->regs + SD_EMMC_CFG); 201 } 202 203 dev_dbg(host->dev, "change clock rate %u -> %lu\n", 204 mmc->actual_clock, clk_rate); 205 206 if (!clk_rate) { 207 mmc->actual_clock = 0; 208 host->current_clock = 0; 209 /* return with clock being stopped */ 210 return 0; 211 } 212 213 ret = clk_set_rate(host->cfg_div_clk, clk_rate); 214 if (ret) { 215 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 216 clk_rate, ret); 217 return ret; 218 } 219 220 mmc->actual_clock = clk_get_rate(host->cfg_div_clk); 221 host->current_clock = clk_rate; 222 223 if (clk_rate != mmc->actual_clock) 224 dev_dbg(host->dev, 225 "divider requested rate %lu != actual rate %u\n", 226 clk_rate, mmc->actual_clock); 227 228 /* (re)start clock */ 229 cfg = readl(host->regs + SD_EMMC_CFG); 230 cfg &= ~CFG_STOP_CLOCK; 231 writel(cfg, host->regs + SD_EMMC_CFG); 232 233 return 0; 234 } 235 236 /* 237 * The SD/eMMC IP block has an internal mux and divider used for 238 * generating the MMC clock. Use the clock framework to create and 239 * manage these clocks. 240 */ 241 static int meson_mmc_clk_init(struct meson_host *host) 242 { 243 struct clk_init_data init; 244 char clk_name[32]; 245 int i, ret = 0; 246 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 247 unsigned int mux_parent_count = 0; 248 const char *clk_div_parents[1]; 249 u32 clk_reg, cfg; 250 251 /* get the mux parents */ 252 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 253 char name[16]; 254 255 snprintf(name, sizeof(name), "clkin%d", i); 256 host->mux_parent[i] = devm_clk_get(host->dev, name); 257 if (IS_ERR(host->mux_parent[i])) { 258 ret = PTR_ERR(host->mux_parent[i]); 259 if (PTR_ERR(host->mux_parent[i]) != -EPROBE_DEFER) 260 dev_err(host->dev, "Missing clock %s\n", name); 261 host->mux_parent[i] = NULL; 262 return ret; 263 } 264 265 mux_parent_names[i] = __clk_get_name(host->mux_parent[i]); 266 mux_parent_count++; 267 } 268 269 /* create the mux */ 270 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 271 init.name = clk_name; 272 init.ops = &clk_mux_ops; 273 init.flags = 0; 274 init.parent_names = mux_parent_names; 275 init.num_parents = mux_parent_count; 276 277 host->mux.reg = host->regs + SD_EMMC_CLOCK; 278 host->mux.shift = CLK_SRC_SHIFT; 279 host->mux.mask = CLK_SRC_MASK; 280 host->mux.flags = 0; 281 host->mux.table = NULL; 282 host->mux.hw.init = &init; 283 284 host->mux_clk = devm_clk_register(host->dev, &host->mux.hw); 285 if (WARN_ON(IS_ERR(host->mux_clk))) 286 return PTR_ERR(host->mux_clk); 287 288 /* create the divider */ 289 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 290 init.name = devm_kstrdup(host->dev, clk_name, GFP_KERNEL); 291 init.ops = &clk_divider_ops; 292 init.flags = CLK_SET_RATE_PARENT; 293 clk_div_parents[0] = __clk_get_name(host->mux_clk); 294 init.parent_names = clk_div_parents; 295 init.num_parents = ARRAY_SIZE(clk_div_parents); 296 297 host->cfg_div.reg = host->regs + SD_EMMC_CLOCK; 298 host->cfg_div.shift = CLK_DIV_SHIFT; 299 host->cfg_div.width = CLK_DIV_WIDTH; 300 host->cfg_div.hw.init = &init; 301 host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | 302 CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO; 303 304 host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); 305 if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) 306 return PTR_ERR(host->cfg_div_clk); 307 308 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 309 clk_reg = 0; 310 clk_reg |= CLK_PHASE_180 << CLK_PHASE_SHIFT; 311 clk_reg |= CLK_SRC_XTAL << CLK_SRC_SHIFT; 312 clk_reg |= CLK_DIV_MAX << CLK_DIV_SHIFT; 313 clk_reg &= ~CLK_ALWAYS_ON; 314 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 315 316 /* Ensure clock starts in "auto" mode, not "always on" */ 317 cfg = readl(host->regs + SD_EMMC_CFG); 318 cfg &= ~CFG_CLK_ALWAYS_ON; 319 cfg |= CFG_AUTO_CLK; 320 writel(cfg, host->regs + SD_EMMC_CFG); 321 322 ret = clk_prepare_enable(host->cfg_div_clk); 323 if (ret) 324 return ret; 325 326 /* Get the nearest minimum clock to 400KHz */ 327 host->mmc->f_min = clk_round_rate(host->cfg_div_clk, 400000); 328 329 ret = meson_mmc_clk_set(host, host->mmc->f_min); 330 if (!ret) 331 clk_disable_unprepare(host->cfg_div_clk); 332 333 return ret; 334 } 335 336 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 337 { 338 struct meson_host *host = mmc_priv(mmc); 339 u32 bus_width; 340 u32 val, orig; 341 342 /* 343 * GPIO regulator, only controls switching between 1v8 and 344 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 345 */ 346 switch (ios->power_mode) { 347 case MMC_POWER_OFF: 348 if (!IS_ERR(mmc->supply.vmmc)) 349 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 350 351 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 352 regulator_disable(mmc->supply.vqmmc); 353 host->vqmmc_enabled = false; 354 } 355 356 break; 357 358 case MMC_POWER_UP: 359 if (!IS_ERR(mmc->supply.vmmc)) 360 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 361 break; 362 363 case MMC_POWER_ON: 364 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 365 int ret = regulator_enable(mmc->supply.vqmmc); 366 367 if (ret < 0) 368 dev_err(mmc_dev(mmc), 369 "failed to enable vqmmc regulator\n"); 370 else 371 host->vqmmc_enabled = true; 372 } 373 374 break; 375 } 376 377 378 meson_mmc_clk_set(host, ios->clock); 379 380 /* Bus width */ 381 switch (ios->bus_width) { 382 case MMC_BUS_WIDTH_1: 383 bus_width = CFG_BUS_WIDTH_1; 384 break; 385 case MMC_BUS_WIDTH_4: 386 bus_width = CFG_BUS_WIDTH_4; 387 break; 388 case MMC_BUS_WIDTH_8: 389 bus_width = CFG_BUS_WIDTH_8; 390 break; 391 default: 392 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 393 ios->bus_width); 394 bus_width = CFG_BUS_WIDTH_4; 395 } 396 397 val = readl(host->regs + SD_EMMC_CFG); 398 orig = val; 399 400 val &= ~(CFG_BUS_WIDTH_MASK << CFG_BUS_WIDTH_SHIFT); 401 val |= bus_width << CFG_BUS_WIDTH_SHIFT; 402 403 val &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 404 val |= ilog2(SD_EMMC_CFG_BLK_SIZE) << CFG_BLK_LEN_SHIFT; 405 406 val &= ~(CFG_RESP_TIMEOUT_MASK << CFG_RESP_TIMEOUT_SHIFT); 407 val |= ilog2(SD_EMMC_CFG_RESP_TIMEOUT) << CFG_RESP_TIMEOUT_SHIFT; 408 409 val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT); 410 val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT; 411 412 val &= ~CFG_DDR; 413 if (ios->timing == MMC_TIMING_UHS_DDR50 || 414 ios->timing == MMC_TIMING_MMC_DDR52 || 415 ios->timing == MMC_TIMING_MMC_HS400) 416 val |= CFG_DDR; 417 418 val &= ~CFG_CHK_DS; 419 if (ios->timing == MMC_TIMING_MMC_HS400) 420 val |= CFG_CHK_DS; 421 422 writel(val, host->regs + SD_EMMC_CFG); 423 424 if (val != orig) 425 dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n", 426 __func__, orig, val); 427 } 428 429 static int meson_mmc_request_done(struct mmc_host *mmc, struct mmc_request *mrq) 430 { 431 struct meson_host *host = mmc_priv(mmc); 432 433 WARN_ON(host->mrq != mrq); 434 435 host->mrq = NULL; 436 host->cmd = NULL; 437 mmc_request_done(host->mmc, mrq); 438 439 return 0; 440 } 441 442 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 443 { 444 struct meson_host *host = mmc_priv(mmc); 445 struct sd_emmc_desc *desc, desc_tmp; 446 u32 cfg; 447 u8 blk_len, cmd_cfg_timeout; 448 unsigned int xfer_bytes = 0; 449 450 /* Setup descriptors */ 451 dma_rmb(); 452 desc = &desc_tmp; 453 memset(desc, 0, sizeof(struct sd_emmc_desc)); 454 455 desc->cmd_cfg |= (cmd->opcode & CMD_CFG_CMD_INDEX_MASK) << 456 CMD_CFG_CMD_INDEX_SHIFT; 457 desc->cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 458 desc->cmd_arg = cmd->arg; 459 460 /* Response */ 461 if (cmd->flags & MMC_RSP_PRESENT) { 462 desc->cmd_cfg &= ~CMD_CFG_NO_RESP; 463 if (cmd->flags & MMC_RSP_136) 464 desc->cmd_cfg |= CMD_CFG_RESP_128; 465 desc->cmd_cfg |= CMD_CFG_RESP_NUM; 466 desc->cmd_resp = 0; 467 468 if (!(cmd->flags & MMC_RSP_CRC)) 469 desc->cmd_cfg |= CMD_CFG_RESP_NOCRC; 470 471 if (cmd->flags & MMC_RSP_BUSY) 472 desc->cmd_cfg |= CMD_CFG_R1B; 473 } else { 474 desc->cmd_cfg |= CMD_CFG_NO_RESP; 475 } 476 477 /* data? */ 478 if (cmd->data) { 479 desc->cmd_cfg |= CMD_CFG_DATA_IO; 480 if (cmd->data->blocks > 1) { 481 desc->cmd_cfg |= CMD_CFG_BLOCK_MODE; 482 desc->cmd_cfg |= 483 (cmd->data->blocks & CMD_CFG_LENGTH_MASK) << 484 CMD_CFG_LENGTH_SHIFT; 485 486 /* check if block-size matches, if not update */ 487 cfg = readl(host->regs + SD_EMMC_CFG); 488 blk_len = cfg & (CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 489 blk_len >>= CFG_BLK_LEN_SHIFT; 490 if (blk_len != ilog2(cmd->data->blksz)) { 491 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", 492 __func__, blk_len, 493 ilog2(cmd->data->blksz)); 494 blk_len = ilog2(cmd->data->blksz); 495 cfg &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 496 cfg |= blk_len << CFG_BLK_LEN_SHIFT; 497 writel(cfg, host->regs + SD_EMMC_CFG); 498 } 499 } else { 500 desc->cmd_cfg &= ~CMD_CFG_BLOCK_MODE; 501 desc->cmd_cfg |= 502 (cmd->data->blksz & CMD_CFG_LENGTH_MASK) << 503 CMD_CFG_LENGTH_SHIFT; 504 } 505 506 cmd->data->bytes_xfered = 0; 507 xfer_bytes = cmd->data->blksz * cmd->data->blocks; 508 if (cmd->data->flags & MMC_DATA_WRITE) { 509 desc->cmd_cfg |= CMD_CFG_DATA_WR; 510 WARN_ON(xfer_bytes > host->bounce_buf_size); 511 sg_copy_to_buffer(cmd->data->sg, cmd->data->sg_len, 512 host->bounce_buf, xfer_bytes); 513 cmd->data->bytes_xfered = xfer_bytes; 514 dma_wmb(); 515 } else { 516 desc->cmd_cfg &= ~CMD_CFG_DATA_WR; 517 } 518 519 if (xfer_bytes > 0) { 520 desc->cmd_cfg &= ~CMD_CFG_DATA_NUM; 521 desc->cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 522 } else { 523 /* write data to data_addr */ 524 desc->cmd_cfg |= CMD_CFG_DATA_NUM; 525 desc->cmd_data = 0; 526 } 527 528 cmd_cfg_timeout = 12; 529 } else { 530 desc->cmd_cfg &= ~CMD_CFG_DATA_IO; 531 cmd_cfg_timeout = 10; 532 } 533 desc->cmd_cfg |= (cmd_cfg_timeout & CMD_CFG_TIMEOUT_MASK) << 534 CMD_CFG_TIMEOUT_SHIFT; 535 536 host->cmd = cmd; 537 538 /* Last descriptor */ 539 desc->cmd_cfg |= CMD_CFG_END_OF_CHAIN; 540 writel(desc->cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 541 writel(desc->cmd_data, host->regs + SD_EMMC_CMD_DAT); 542 writel(desc->cmd_resp, host->regs + SD_EMMC_CMD_RSP); 543 wmb(); /* ensure descriptor is written before kicked */ 544 writel(desc->cmd_arg, host->regs + SD_EMMC_CMD_ARG); 545 } 546 547 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 548 { 549 struct meson_host *host = mmc_priv(mmc); 550 551 WARN_ON(host->mrq != NULL); 552 553 /* Stop execution */ 554 writel(0, host->regs + SD_EMMC_START); 555 556 host->mrq = mrq; 557 558 if (mrq->sbc) 559 meson_mmc_start_cmd(mmc, mrq->sbc); 560 else 561 meson_mmc_start_cmd(mmc, mrq->cmd); 562 } 563 564 static int meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 565 { 566 struct meson_host *host = mmc_priv(mmc); 567 568 if (cmd->flags & MMC_RSP_136) { 569 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 570 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 571 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 572 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 573 } else if (cmd->flags & MMC_RSP_PRESENT) { 574 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 575 } 576 577 return 0; 578 } 579 580 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 581 { 582 struct meson_host *host = dev_id; 583 struct mmc_request *mrq; 584 struct mmc_command *cmd; 585 u32 irq_en, status, raw_status; 586 irqreturn_t ret = IRQ_HANDLED; 587 588 if (WARN_ON(!host)) 589 return IRQ_NONE; 590 591 cmd = host->cmd; 592 593 mrq = host->mrq; 594 595 if (WARN_ON(!mrq)) 596 return IRQ_NONE; 597 598 if (WARN_ON(!cmd)) 599 return IRQ_NONE; 600 601 spin_lock(&host->lock); 602 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 603 raw_status = readl(host->regs + SD_EMMC_STATUS); 604 status = raw_status & irq_en; 605 606 if (!status) { 607 dev_warn(host->dev, "Spurious IRQ! status=0x%08x, irq_en=0x%08x\n", 608 raw_status, irq_en); 609 ret = IRQ_NONE; 610 goto out; 611 } 612 613 cmd->error = 0; 614 if (status & IRQ_RXD_ERR_MASK) { 615 dev_dbg(host->dev, "Unhandled IRQ: RXD error\n"); 616 cmd->error = -EILSEQ; 617 } 618 if (status & IRQ_TXD_ERR) { 619 dev_dbg(host->dev, "Unhandled IRQ: TXD error\n"); 620 cmd->error = -EILSEQ; 621 } 622 if (status & IRQ_DESC_ERR) 623 dev_dbg(host->dev, "Unhandled IRQ: Descriptor error\n"); 624 if (status & IRQ_RESP_ERR) { 625 dev_dbg(host->dev, "Unhandled IRQ: Response error\n"); 626 cmd->error = -EILSEQ; 627 } 628 if (status & IRQ_RESP_TIMEOUT) { 629 dev_dbg(host->dev, "Unhandled IRQ: Response timeout\n"); 630 cmd->error = -ETIMEDOUT; 631 } 632 if (status & IRQ_DESC_TIMEOUT) { 633 dev_dbg(host->dev, "Unhandled IRQ: Descriptor timeout\n"); 634 cmd->error = -ETIMEDOUT; 635 } 636 if (status & IRQ_SDIO) 637 dev_dbg(host->dev, "Unhandled IRQ: SDIO.\n"); 638 639 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) 640 ret = IRQ_WAKE_THREAD; 641 else { 642 dev_warn(host->dev, "Unknown IRQ! status=0x%04x: MMC CMD%u arg=0x%08x flags=0x%08x stop=%d\n", 643 status, cmd->opcode, cmd->arg, 644 cmd->flags, mrq->stop ? 1 : 0); 645 if (cmd->data) { 646 struct mmc_data *data = cmd->data; 647 648 dev_warn(host->dev, "\tblksz %u blocks %u flags 0x%08x (%s%s)", 649 data->blksz, data->blocks, data->flags, 650 data->flags & MMC_DATA_WRITE ? "write" : "", 651 data->flags & MMC_DATA_READ ? "read" : ""); 652 } 653 } 654 655 out: 656 /* ack all (enabled) interrupts */ 657 writel(status, host->regs + SD_EMMC_STATUS); 658 659 if (ret == IRQ_HANDLED) { 660 meson_mmc_read_resp(host->mmc, cmd); 661 meson_mmc_request_done(host->mmc, cmd->mrq); 662 } 663 664 spin_unlock(&host->lock); 665 return ret; 666 } 667 668 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 669 { 670 struct meson_host *host = dev_id; 671 struct mmc_request *mrq = host->mrq; 672 struct mmc_command *cmd = host->cmd; 673 struct mmc_data *data; 674 unsigned int xfer_bytes; 675 676 if (WARN_ON(!mrq)) 677 return IRQ_NONE; 678 679 if (WARN_ON(!cmd)) 680 return IRQ_NONE; 681 682 data = cmd->data; 683 if (data && data->flags & MMC_DATA_READ) { 684 xfer_bytes = data->blksz * data->blocks; 685 WARN_ON(xfer_bytes > host->bounce_buf_size); 686 sg_copy_from_buffer(data->sg, data->sg_len, 687 host->bounce_buf, xfer_bytes); 688 data->bytes_xfered = xfer_bytes; 689 } 690 691 meson_mmc_read_resp(host->mmc, cmd); 692 if (!data || !data->stop || mrq->sbc) 693 meson_mmc_request_done(host->mmc, mrq); 694 else 695 meson_mmc_start_cmd(host->mmc, data->stop); 696 697 return IRQ_HANDLED; 698 } 699 700 /* 701 * NOTE: we only need this until the GPIO/pinctrl driver can handle 702 * interrupts. For now, the MMC core will use this for polling. 703 */ 704 static int meson_mmc_get_cd(struct mmc_host *mmc) 705 { 706 int status = mmc_gpio_get_cd(mmc); 707 708 if (status == -ENOSYS) 709 return 1; /* assume present */ 710 711 return status; 712 } 713 714 static const struct mmc_host_ops meson_mmc_ops = { 715 .request = meson_mmc_request, 716 .set_ios = meson_mmc_set_ios, 717 .get_cd = meson_mmc_get_cd, 718 }; 719 720 static int meson_mmc_probe(struct platform_device *pdev) 721 { 722 struct resource *res; 723 struct meson_host *host; 724 struct mmc_host *mmc; 725 int ret; 726 727 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 728 if (!mmc) 729 return -ENOMEM; 730 host = mmc_priv(mmc); 731 host->mmc = mmc; 732 host->dev = &pdev->dev; 733 dev_set_drvdata(&pdev->dev, host); 734 735 spin_lock_init(&host->lock); 736 737 /* Get regulators and the supported OCR mask */ 738 host->vqmmc_enabled = false; 739 ret = mmc_regulator_get_supply(mmc); 740 if (ret == -EPROBE_DEFER) 741 goto free_host; 742 743 ret = mmc_of_parse(mmc); 744 if (ret) { 745 if (ret != -EPROBE_DEFER) 746 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 747 goto free_host; 748 } 749 750 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 751 host->regs = devm_ioremap_resource(&pdev->dev, res); 752 if (IS_ERR(host->regs)) { 753 ret = PTR_ERR(host->regs); 754 goto free_host; 755 } 756 757 host->irq = platform_get_irq(pdev, 0); 758 if (host->irq == 0) { 759 dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 760 ret = -EINVAL; 761 goto free_host; 762 } 763 764 host->core_clk = devm_clk_get(&pdev->dev, "core"); 765 if (IS_ERR(host->core_clk)) { 766 ret = PTR_ERR(host->core_clk); 767 goto free_host; 768 } 769 770 ret = clk_prepare_enable(host->core_clk); 771 if (ret) 772 goto free_host; 773 774 ret = meson_mmc_clk_init(host); 775 if (ret) 776 goto free_host; 777 778 /* Stop execution */ 779 writel(0, host->regs + SD_EMMC_START); 780 781 /* clear, ack, enable all interrupts */ 782 writel(0, host->regs + SD_EMMC_IRQ_EN); 783 writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); 784 writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); 785 786 ret = devm_request_threaded_irq(&pdev->dev, host->irq, 787 meson_mmc_irq, meson_mmc_irq_thread, 788 IRQF_SHARED, DRIVER_NAME, host); 789 if (ret) 790 goto free_host; 791 792 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 793 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 794 795 /* data bounce buffer */ 796 host->bounce_buf_size = mmc->max_req_size; 797 host->bounce_buf = 798 dma_alloc_coherent(host->dev, host->bounce_buf_size, 799 &host->bounce_dma_addr, GFP_KERNEL); 800 if (host->bounce_buf == NULL) { 801 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 802 ret = -ENOMEM; 803 goto free_host; 804 } 805 806 mmc->ops = &meson_mmc_ops; 807 mmc_add_host(mmc); 808 809 return 0; 810 811 free_host: 812 clk_disable_unprepare(host->cfg_div_clk); 813 clk_disable_unprepare(host->core_clk); 814 mmc_free_host(mmc); 815 return ret; 816 } 817 818 static int meson_mmc_remove(struct platform_device *pdev) 819 { 820 struct meson_host *host = dev_get_drvdata(&pdev->dev); 821 822 /* disable interrupts */ 823 writel(0, host->regs + SD_EMMC_IRQ_EN); 824 825 dma_free_coherent(host->dev, host->bounce_buf_size, 826 host->bounce_buf, host->bounce_dma_addr); 827 828 clk_disable_unprepare(host->cfg_div_clk); 829 clk_disable_unprepare(host->core_clk); 830 831 mmc_free_host(host->mmc); 832 return 0; 833 } 834 835 static const struct of_device_id meson_mmc_of_match[] = { 836 { .compatible = "amlogic,meson-gx-mmc", }, 837 { .compatible = "amlogic,meson-gxbb-mmc", }, 838 { .compatible = "amlogic,meson-gxl-mmc", }, 839 { .compatible = "amlogic,meson-gxm-mmc", }, 840 {} 841 }; 842 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 843 844 static struct platform_driver meson_mmc_driver = { 845 .probe = meson_mmc_probe, 846 .remove = meson_mmc_remove, 847 .driver = { 848 .name = DRIVER_NAME, 849 .of_match_table = of_match_ptr(meson_mmc_of_match), 850 }, 851 }; 852 853 module_platform_driver(meson_mmc_driver); 854 855 MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver"); 856 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 857 MODULE_LICENSE("GPL v2"); 858