1 /* 2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Kevin Hilman <khilman@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * The full GNU General Public License is included in this distribution 19 * in the file called COPYING. 20 */ 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/ioport.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 #include <linux/io.h> 35 #include <linux/clk.h> 36 #include <linux/clk-provider.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/interrupt.h> 40 #include <linux/bitfield.h> 41 #include <linux/pinctrl/consumer.h> 42 43 #define DRIVER_NAME "meson-gx-mmc" 44 45 #define SD_EMMC_CLOCK 0x0 46 #define CLK_DIV_MASK GENMASK(5, 0) 47 #define CLK_SRC_MASK GENMASK(7, 6) 48 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 49 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 50 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 51 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 52 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 53 #define CLK_V2_ALWAYS_ON BIT(24) 54 55 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 56 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 57 #define CLK_V3_ALWAYS_ON BIT(28) 58 59 #define CLK_DELAY_STEP_PS 200 60 #define CLK_PHASE_STEP 30 61 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) 62 63 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 64 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 65 #define CLK_ALWAYS_ON(h) (h->data->always_on) 66 67 #define SD_EMMC_DELAY 0x4 68 #define SD_EMMC_ADJUST 0x8 69 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 70 #define ADJUST_DS_EN BIT(15) 71 #define ADJUST_ADJ_EN BIT(13) 72 73 #define SD_EMMC_DELAY1 0x4 74 #define SD_EMMC_DELAY2 0x8 75 #define SD_EMMC_V3_ADJUST 0xc 76 77 #define SD_EMMC_CALOUT 0x10 78 #define SD_EMMC_START 0x40 79 #define START_DESC_INIT BIT(0) 80 #define START_DESC_BUSY BIT(1) 81 #define START_DESC_ADDR_MASK GENMASK(31, 2) 82 83 #define SD_EMMC_CFG 0x44 84 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 85 #define CFG_BUS_WIDTH_1 0x0 86 #define CFG_BUS_WIDTH_4 0x1 87 #define CFG_BUS_WIDTH_8 0x2 88 #define CFG_DDR BIT(2) 89 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 90 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 91 #define CFG_RC_CC_MASK GENMASK(15, 12) 92 #define CFG_STOP_CLOCK BIT(22) 93 #define CFG_CLK_ALWAYS_ON BIT(18) 94 #define CFG_CHK_DS BIT(20) 95 #define CFG_AUTO_CLK BIT(23) 96 #define CFG_ERR_ABORT BIT(27) 97 98 #define SD_EMMC_STATUS 0x48 99 #define STATUS_BUSY BIT(31) 100 #define STATUS_DESC_BUSY BIT(30) 101 #define STATUS_DATI GENMASK(23, 16) 102 103 #define SD_EMMC_IRQ_EN 0x4c 104 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 105 #define IRQ_TXD_ERR BIT(8) 106 #define IRQ_DESC_ERR BIT(9) 107 #define IRQ_RESP_ERR BIT(10) 108 #define IRQ_CRC_ERR \ 109 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 110 #define IRQ_RESP_TIMEOUT BIT(11) 111 #define IRQ_DESC_TIMEOUT BIT(12) 112 #define IRQ_TIMEOUTS \ 113 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 114 #define IRQ_END_OF_CHAIN BIT(13) 115 #define IRQ_RESP_STATUS BIT(14) 116 #define IRQ_SDIO BIT(15) 117 #define IRQ_EN_MASK \ 118 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 119 IRQ_SDIO) 120 121 #define SD_EMMC_CMD_CFG 0x50 122 #define SD_EMMC_CMD_ARG 0x54 123 #define SD_EMMC_CMD_DAT 0x58 124 #define SD_EMMC_CMD_RSP 0x5c 125 #define SD_EMMC_CMD_RSP1 0x60 126 #define SD_EMMC_CMD_RSP2 0x64 127 #define SD_EMMC_CMD_RSP3 0x68 128 129 #define SD_EMMC_RXD 0x94 130 #define SD_EMMC_TXD 0x94 131 #define SD_EMMC_LAST_REG SD_EMMC_TXD 132 133 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 134 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 135 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 136 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 137 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 138 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 139 140 #define SD_EMMC_PRE_REQ_DONE BIT(0) 141 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 142 143 #define MUX_CLK_NUM_PARENTS 2 144 145 struct meson_mmc_data { 146 unsigned int tx_delay_mask; 147 unsigned int rx_delay_mask; 148 unsigned int always_on; 149 unsigned int adjust; 150 }; 151 152 struct sd_emmc_desc { 153 u32 cmd_cfg; 154 u32 cmd_arg; 155 u32 cmd_data; 156 u32 cmd_resp; 157 }; 158 159 struct meson_host { 160 struct device *dev; 161 struct meson_mmc_data *data; 162 struct mmc_host *mmc; 163 struct mmc_command *cmd; 164 165 void __iomem *regs; 166 struct clk *core_clk; 167 struct clk *mmc_clk; 168 struct clk *rx_clk; 169 struct clk *tx_clk; 170 unsigned long req_rate; 171 172 struct pinctrl *pinctrl; 173 struct pinctrl_state *pins_default; 174 struct pinctrl_state *pins_clk_gate; 175 176 unsigned int bounce_buf_size; 177 void *bounce_buf; 178 dma_addr_t bounce_dma_addr; 179 struct sd_emmc_desc *descs; 180 dma_addr_t descs_dma_addr; 181 182 bool vqmmc_enabled; 183 }; 184 185 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 186 #define CMD_CFG_BLOCK_MODE BIT(9) 187 #define CMD_CFG_R1B BIT(10) 188 #define CMD_CFG_END_OF_CHAIN BIT(11) 189 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 190 #define CMD_CFG_NO_RESP BIT(16) 191 #define CMD_CFG_NO_CMD BIT(17) 192 #define CMD_CFG_DATA_IO BIT(18) 193 #define CMD_CFG_DATA_WR BIT(19) 194 #define CMD_CFG_RESP_NOCRC BIT(20) 195 #define CMD_CFG_RESP_128 BIT(21) 196 #define CMD_CFG_RESP_NUM BIT(22) 197 #define CMD_CFG_DATA_NUM BIT(23) 198 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 199 #define CMD_CFG_ERROR BIT(30) 200 #define CMD_CFG_OWNER BIT(31) 201 202 #define CMD_DATA_MASK GENMASK(31, 2) 203 #define CMD_DATA_BIG_ENDIAN BIT(1) 204 #define CMD_DATA_SRAM BIT(0) 205 #define CMD_RESP_MASK GENMASK(31, 1) 206 #define CMD_RESP_SRAM BIT(0) 207 208 struct meson_mmc_phase { 209 struct clk_hw hw; 210 void __iomem *reg; 211 unsigned long phase_mask; 212 unsigned long delay_mask; 213 unsigned int delay_step_ps; 214 }; 215 216 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw) 217 218 static int meson_mmc_clk_get_phase(struct clk_hw *hw) 219 { 220 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); 221 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); 222 unsigned long period_ps, p, d; 223 int degrees; 224 u32 val; 225 226 val = readl(mmc->reg); 227 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask); 228 degrees = p * 360 / phase_num; 229 230 if (mmc->delay_mask) { 231 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, 232 clk_get_rate(hw->clk)); 233 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask); 234 degrees += d * mmc->delay_step_ps * 360 / period_ps; 235 degrees %= 360; 236 } 237 238 return degrees; 239 } 240 241 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc, 242 unsigned int phase, 243 unsigned int delay) 244 { 245 u32 val; 246 247 val = readl(mmc->reg); 248 val &= ~mmc->phase_mask; 249 val |= phase << __ffs(mmc->phase_mask); 250 251 if (mmc->delay_mask) { 252 val &= ~mmc->delay_mask; 253 val |= delay << __ffs(mmc->delay_mask); 254 } 255 256 writel(val, mmc->reg); 257 } 258 259 static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees) 260 { 261 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); 262 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); 263 unsigned long period_ps, d = 0, r; 264 uint64_t p; 265 266 p = degrees % 360; 267 268 if (!mmc->delay_mask) { 269 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); 270 } else { 271 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, 272 clk_get_rate(hw->clk)); 273 274 /* First compute the phase index (p), the remainder (r) is the 275 * part we'll try to acheive using the delays (d). 276 */ 277 r = do_div(p, 360 / phase_num); 278 d = DIV_ROUND_CLOSEST(r * period_ps, 279 360 * mmc->delay_step_ps); 280 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask)); 281 } 282 283 meson_mmc_apply_phase_delay(mmc, p, d); 284 return 0; 285 } 286 287 static const struct clk_ops meson_mmc_clk_phase_ops = { 288 .get_phase = meson_mmc_clk_get_phase, 289 .set_phase = meson_mmc_clk_set_phase, 290 }; 291 292 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 293 { 294 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 295 296 if (!timeout) 297 return SD_EMMC_CMD_TIMEOUT_DATA; 298 299 timeout = roundup_pow_of_two(timeout); 300 301 return min(timeout, 32768U); /* max. 2^15 ms */ 302 } 303 304 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 305 { 306 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 307 return cmd->mrq->cmd; 308 else if (mmc_op_multi(cmd->opcode) && 309 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 310 return cmd->mrq->stop; 311 else 312 return NULL; 313 } 314 315 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 316 struct mmc_request *mrq) 317 { 318 struct mmc_data *data = mrq->data; 319 struct scatterlist *sg; 320 int i; 321 bool use_desc_chain_mode = true; 322 323 /* 324 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 325 * reported. For some strange reason this occurs in descriptor 326 * chain mode only. So let's fall back to bounce buffer mode 327 * for command SD_IO_RW_EXTENDED. 328 */ 329 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 330 return; 331 332 for_each_sg(data->sg, sg, data->sg_len, i) 333 /* check for 8 byte alignment */ 334 if (sg->offset & 7) { 335 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 336 use_desc_chain_mode = false; 337 break; 338 } 339 340 if (use_desc_chain_mode) 341 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 342 } 343 344 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 345 { 346 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 347 } 348 349 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 350 { 351 return data && data->flags & MMC_DATA_READ && 352 !meson_mmc_desc_chain_mode(data); 353 } 354 355 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 356 { 357 struct mmc_data *data = mrq->data; 358 359 if (!data) 360 return; 361 362 meson_mmc_get_transfer_mode(mmc, mrq); 363 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 364 365 if (!meson_mmc_desc_chain_mode(data)) 366 return; 367 368 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 369 mmc_get_dma_dir(data)); 370 if (!data->sg_count) 371 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 372 } 373 374 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 375 int err) 376 { 377 struct mmc_data *data = mrq->data; 378 379 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 380 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 381 mmc_get_dma_dir(data)); 382 } 383 384 static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) 385 { 386 if (ios->timing == MMC_TIMING_MMC_DDR52 || 387 ios->timing == MMC_TIMING_UHS_DDR50 || 388 ios->timing == MMC_TIMING_MMC_HS400) 389 return true; 390 391 return false; 392 } 393 394 /* 395 * Gating the clock on this controller is tricky. It seems the mmc clock 396 * is also used by the controller. It may crash during some operation if the 397 * clock is stopped. The safest thing to do, whenever possible, is to keep 398 * clock running at stop it at the pad using the pinmux. 399 */ 400 static void meson_mmc_clk_gate(struct meson_host *host) 401 { 402 u32 cfg; 403 404 if (host->pins_clk_gate) { 405 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 406 } else { 407 /* 408 * If the pinmux is not provided - default to the classic and 409 * unsafe method 410 */ 411 cfg = readl(host->regs + SD_EMMC_CFG); 412 cfg |= CFG_STOP_CLOCK; 413 writel(cfg, host->regs + SD_EMMC_CFG); 414 } 415 } 416 417 static void meson_mmc_clk_ungate(struct meson_host *host) 418 { 419 u32 cfg; 420 421 if (host->pins_clk_gate) 422 pinctrl_select_state(host->pinctrl, host->pins_default); 423 424 /* Make sure the clock is not stopped in the controller */ 425 cfg = readl(host->regs + SD_EMMC_CFG); 426 cfg &= ~CFG_STOP_CLOCK; 427 writel(cfg, host->regs + SD_EMMC_CFG); 428 } 429 430 static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) 431 { 432 struct mmc_host *mmc = host->mmc; 433 unsigned long rate = ios->clock; 434 int ret; 435 u32 cfg; 436 437 /* DDR modes require higher module clock */ 438 if (meson_mmc_timing_is_ddr(ios)) 439 rate <<= 1; 440 441 /* Same request - bail-out */ 442 if (host->req_rate == rate) 443 return 0; 444 445 /* stop clock */ 446 meson_mmc_clk_gate(host); 447 host->req_rate = 0; 448 449 if (!rate) { 450 mmc->actual_clock = 0; 451 /* return with clock being stopped */ 452 return 0; 453 } 454 455 /* Stop the clock during rate change to avoid glitches */ 456 cfg = readl(host->regs + SD_EMMC_CFG); 457 cfg |= CFG_STOP_CLOCK; 458 writel(cfg, host->regs + SD_EMMC_CFG); 459 460 ret = clk_set_rate(host->mmc_clk, rate); 461 if (ret) { 462 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 463 rate, ret); 464 return ret; 465 } 466 467 host->req_rate = rate; 468 mmc->actual_clock = clk_get_rate(host->mmc_clk); 469 470 /* We should report the real output frequency of the controller */ 471 if (meson_mmc_timing_is_ddr(ios)) 472 mmc->actual_clock >>= 1; 473 474 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 475 if (ios->clock != mmc->actual_clock) 476 dev_dbg(host->dev, "requested rate was %u\n", ios->clock); 477 478 /* (re)start clock */ 479 meson_mmc_clk_ungate(host); 480 481 return 0; 482 } 483 484 /* 485 * The SD/eMMC IP block has an internal mux and divider used for 486 * generating the MMC clock. Use the clock framework to create and 487 * manage these clocks. 488 */ 489 static int meson_mmc_clk_init(struct meson_host *host) 490 { 491 struct clk_init_data init; 492 struct clk_mux *mux; 493 struct clk_divider *div; 494 struct meson_mmc_phase *core, *tx, *rx; 495 struct clk *clk; 496 char clk_name[32]; 497 int i, ret = 0; 498 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 499 const char *clk_parent[1]; 500 u32 clk_reg; 501 502 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 503 clk_reg = 0; 504 clk_reg |= CLK_ALWAYS_ON(host); 505 clk_reg |= CLK_DIV_MASK; 506 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 507 508 /* get the mux parents */ 509 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 510 struct clk *clk; 511 char name[16]; 512 513 snprintf(name, sizeof(name), "clkin%d", i); 514 clk = devm_clk_get(host->dev, name); 515 if (IS_ERR(clk)) { 516 if (clk != ERR_PTR(-EPROBE_DEFER)) 517 dev_err(host->dev, "Missing clock %s\n", name); 518 return PTR_ERR(clk); 519 } 520 521 mux_parent_names[i] = __clk_get_name(clk); 522 } 523 524 /* create the mux */ 525 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 526 if (!mux) 527 return -ENOMEM; 528 529 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 530 init.name = clk_name; 531 init.ops = &clk_mux_ops; 532 init.flags = 0; 533 init.parent_names = mux_parent_names; 534 init.num_parents = MUX_CLK_NUM_PARENTS; 535 536 mux->reg = host->regs + SD_EMMC_CLOCK; 537 mux->shift = __ffs(CLK_SRC_MASK); 538 mux->mask = CLK_SRC_MASK >> mux->shift; 539 mux->hw.init = &init; 540 541 clk = devm_clk_register(host->dev, &mux->hw); 542 if (WARN_ON(IS_ERR(clk))) 543 return PTR_ERR(clk); 544 545 /* create the divider */ 546 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 547 if (!div) 548 return -ENOMEM; 549 550 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 551 init.name = clk_name; 552 init.ops = &clk_divider_ops; 553 init.flags = CLK_SET_RATE_PARENT; 554 clk_parent[0] = __clk_get_name(clk); 555 init.parent_names = clk_parent; 556 init.num_parents = 1; 557 558 div->reg = host->regs + SD_EMMC_CLOCK; 559 div->shift = __ffs(CLK_DIV_MASK); 560 div->width = __builtin_popcountl(CLK_DIV_MASK); 561 div->hw.init = &init; 562 div->flags = CLK_DIVIDER_ONE_BASED; 563 564 clk = devm_clk_register(host->dev, &div->hw); 565 if (WARN_ON(IS_ERR(clk))) 566 return PTR_ERR(clk); 567 568 /* create the mmc core clock */ 569 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL); 570 if (!core) 571 return -ENOMEM; 572 573 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev)); 574 init.name = clk_name; 575 init.ops = &meson_mmc_clk_phase_ops; 576 init.flags = CLK_SET_RATE_PARENT; 577 clk_parent[0] = __clk_get_name(clk); 578 init.parent_names = clk_parent; 579 init.num_parents = 1; 580 581 core->reg = host->regs + SD_EMMC_CLOCK; 582 core->phase_mask = CLK_CORE_PHASE_MASK; 583 core->hw.init = &init; 584 585 host->mmc_clk = devm_clk_register(host->dev, &core->hw); 586 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) 587 return PTR_ERR(host->mmc_clk); 588 589 /* create the mmc tx clock */ 590 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL); 591 if (!tx) 592 return -ENOMEM; 593 594 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev)); 595 init.name = clk_name; 596 init.ops = &meson_mmc_clk_phase_ops; 597 init.flags = 0; 598 clk_parent[0] = __clk_get_name(host->mmc_clk); 599 init.parent_names = clk_parent; 600 init.num_parents = 1; 601 602 tx->reg = host->regs + SD_EMMC_CLOCK; 603 tx->phase_mask = CLK_TX_PHASE_MASK; 604 tx->delay_mask = CLK_TX_DELAY_MASK(host); 605 tx->delay_step_ps = CLK_DELAY_STEP_PS; 606 tx->hw.init = &init; 607 608 host->tx_clk = devm_clk_register(host->dev, &tx->hw); 609 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk))) 610 return PTR_ERR(host->tx_clk); 611 612 /* create the mmc rx clock */ 613 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL); 614 if (!rx) 615 return -ENOMEM; 616 617 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev)); 618 init.name = clk_name; 619 init.ops = &meson_mmc_clk_phase_ops; 620 init.flags = 0; 621 clk_parent[0] = __clk_get_name(host->mmc_clk); 622 init.parent_names = clk_parent; 623 init.num_parents = 1; 624 625 rx->reg = host->regs + SD_EMMC_CLOCK; 626 rx->phase_mask = CLK_RX_PHASE_MASK; 627 rx->delay_mask = CLK_RX_DELAY_MASK(host); 628 rx->delay_step_ps = CLK_DELAY_STEP_PS; 629 rx->hw.init = &init; 630 631 host->rx_clk = devm_clk_register(host->dev, &rx->hw); 632 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) 633 return PTR_ERR(host->rx_clk); 634 635 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 636 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 637 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 638 if (ret) 639 return ret; 640 641 clk_set_phase(host->mmc_clk, 180); 642 clk_set_phase(host->tx_clk, 0); 643 clk_set_phase(host->rx_clk, 0); 644 645 return clk_prepare_enable(host->mmc_clk); 646 } 647 648 static void meson_mmc_shift_map(unsigned long *map, unsigned long shift) 649 { 650 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM); 651 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM); 652 653 /* 654 * shift the bitmap right and reintroduce the dropped bits on the left 655 * of the bitmap 656 */ 657 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM); 658 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift, 659 CLK_PHASE_POINT_NUM); 660 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM); 661 } 662 663 static void meson_mmc_find_next_region(unsigned long *map, 664 unsigned long *start, 665 unsigned long *stop) 666 { 667 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start); 668 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start); 669 } 670 671 static int meson_mmc_find_tuning_point(unsigned long *test) 672 { 673 unsigned long shift, stop, offset = 0, start = 0, size = 0; 674 675 /* Get the all good/all bad situation out the way */ 676 if (bitmap_full(test, CLK_PHASE_POINT_NUM)) 677 return 0; /* All points are good so point 0 will do */ 678 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM)) 679 return -EIO; /* No successful tuning point */ 680 681 /* 682 * Now we know there is a least one region find. Make sure it does 683 * not wrap by the shifting the bitmap if necessary 684 */ 685 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM); 686 if (shift != 0) 687 meson_mmc_shift_map(test, shift); 688 689 while (start < CLK_PHASE_POINT_NUM) { 690 meson_mmc_find_next_region(test, &start, &stop); 691 692 if ((stop - start) > size) { 693 offset = start; 694 size = stop - start; 695 } 696 697 start = stop; 698 } 699 700 /* Get the center point of the region */ 701 offset += (size / 2); 702 703 /* Shift the result back */ 704 offset = (offset + shift) % CLK_PHASE_POINT_NUM; 705 706 return offset; 707 } 708 709 static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, 710 struct clk *clk) 711 { 712 int point, ret; 713 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM); 714 715 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n", 716 __clk_get_name(clk)); 717 bitmap_zero(test, CLK_PHASE_POINT_NUM); 718 719 /* Explore tuning points */ 720 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) { 721 clk_set_phase(clk, point * CLK_PHASE_STEP); 722 ret = mmc_send_tuning(mmc, opcode, NULL); 723 if (!ret) 724 set_bit(point, test); 725 } 726 727 /* Find the optimal tuning point and apply it */ 728 point = meson_mmc_find_tuning_point(test); 729 if (point < 0) 730 return point; /* tuning failed */ 731 732 clk_set_phase(clk, point * CLK_PHASE_STEP); 733 dev_dbg(mmc_dev(mmc), "success with phase: %d\n", 734 clk_get_phase(clk)); 735 return 0; 736 } 737 738 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 739 { 740 struct meson_host *host = mmc_priv(mmc); 741 742 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); 743 } 744 745 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 746 { 747 struct meson_host *host = mmc_priv(mmc); 748 u32 bus_width, val; 749 int err; 750 751 /* 752 * GPIO regulator, only controls switching between 1v8 and 753 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 754 */ 755 switch (ios->power_mode) { 756 case MMC_POWER_OFF: 757 if (!IS_ERR(mmc->supply.vmmc)) 758 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 759 760 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 761 regulator_disable(mmc->supply.vqmmc); 762 host->vqmmc_enabled = false; 763 } 764 765 break; 766 767 case MMC_POWER_UP: 768 if (!IS_ERR(mmc->supply.vmmc)) 769 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 770 771 /* Reset rx phase */ 772 clk_set_phase(host->rx_clk, 0); 773 774 break; 775 776 case MMC_POWER_ON: 777 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 778 int ret = regulator_enable(mmc->supply.vqmmc); 779 780 if (ret < 0) 781 dev_err(host->dev, 782 "failed to enable vqmmc regulator\n"); 783 else 784 host->vqmmc_enabled = true; 785 } 786 787 break; 788 } 789 790 /* Bus width */ 791 switch (ios->bus_width) { 792 case MMC_BUS_WIDTH_1: 793 bus_width = CFG_BUS_WIDTH_1; 794 break; 795 case MMC_BUS_WIDTH_4: 796 bus_width = CFG_BUS_WIDTH_4; 797 break; 798 case MMC_BUS_WIDTH_8: 799 bus_width = CFG_BUS_WIDTH_8; 800 break; 801 default: 802 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 803 ios->bus_width); 804 bus_width = CFG_BUS_WIDTH_4; 805 } 806 807 val = readl(host->regs + SD_EMMC_CFG); 808 val &= ~CFG_BUS_WIDTH_MASK; 809 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 810 811 val &= ~CFG_DDR; 812 if (meson_mmc_timing_is_ddr(ios)) 813 val |= CFG_DDR; 814 815 val &= ~CFG_CHK_DS; 816 if (ios->timing == MMC_TIMING_MMC_HS400) 817 val |= CFG_CHK_DS; 818 819 err = meson_mmc_clk_set(host, ios); 820 if (err) 821 dev_err(host->dev, "Failed to set clock: %d\n,", err); 822 823 writel(val, host->regs + SD_EMMC_CFG); 824 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 825 } 826 827 static void meson_mmc_request_done(struct mmc_host *mmc, 828 struct mmc_request *mrq) 829 { 830 struct meson_host *host = mmc_priv(mmc); 831 832 host->cmd = NULL; 833 mmc_request_done(host->mmc, mrq); 834 } 835 836 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 837 { 838 struct meson_host *host = mmc_priv(mmc); 839 u32 cfg, blksz_old; 840 841 cfg = readl(host->regs + SD_EMMC_CFG); 842 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 843 844 if (!is_power_of_2(blksz)) 845 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 846 847 blksz = ilog2(blksz); 848 849 /* check if block-size matches, if not update */ 850 if (blksz == blksz_old) 851 return; 852 853 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 854 blksz_old, blksz); 855 856 cfg &= ~CFG_BLK_LEN_MASK; 857 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 858 writel(cfg, host->regs + SD_EMMC_CFG); 859 } 860 861 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 862 { 863 if (cmd->flags & MMC_RSP_PRESENT) { 864 if (cmd->flags & MMC_RSP_136) 865 *cmd_cfg |= CMD_CFG_RESP_128; 866 *cmd_cfg |= CMD_CFG_RESP_NUM; 867 868 if (!(cmd->flags & MMC_RSP_CRC)) 869 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 870 871 if (cmd->flags & MMC_RSP_BUSY) 872 *cmd_cfg |= CMD_CFG_R1B; 873 } else { 874 *cmd_cfg |= CMD_CFG_NO_RESP; 875 } 876 } 877 878 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 879 { 880 struct meson_host *host = mmc_priv(mmc); 881 struct sd_emmc_desc *desc = host->descs; 882 struct mmc_data *data = host->cmd->data; 883 struct scatterlist *sg; 884 u32 start; 885 int i; 886 887 if (data->flags & MMC_DATA_WRITE) 888 cmd_cfg |= CMD_CFG_DATA_WR; 889 890 if (data->blocks > 1) { 891 cmd_cfg |= CMD_CFG_BLOCK_MODE; 892 meson_mmc_set_blksz(mmc, data->blksz); 893 } 894 895 for_each_sg(data->sg, sg, data->sg_count, i) { 896 unsigned int len = sg_dma_len(sg); 897 898 if (data->blocks > 1) 899 len /= data->blksz; 900 901 desc[i].cmd_cfg = cmd_cfg; 902 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 903 if (i > 0) 904 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 905 desc[i].cmd_arg = host->cmd->arg; 906 desc[i].cmd_resp = 0; 907 desc[i].cmd_data = sg_dma_address(sg); 908 } 909 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 910 911 dma_wmb(); /* ensure descriptor is written before kicked */ 912 start = host->descs_dma_addr | START_DESC_BUSY; 913 writel(start, host->regs + SD_EMMC_START); 914 } 915 916 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 917 { 918 struct meson_host *host = mmc_priv(mmc); 919 struct mmc_data *data = cmd->data; 920 u32 cmd_cfg = 0, cmd_data = 0; 921 unsigned int xfer_bytes = 0; 922 923 /* Setup descriptors */ 924 dma_rmb(); 925 926 host->cmd = cmd; 927 928 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 929 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 930 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 931 932 meson_mmc_set_response_bits(cmd, &cmd_cfg); 933 934 /* data? */ 935 if (data) { 936 data->bytes_xfered = 0; 937 cmd_cfg |= CMD_CFG_DATA_IO; 938 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 939 ilog2(meson_mmc_get_timeout_msecs(data))); 940 941 if (meson_mmc_desc_chain_mode(data)) { 942 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 943 return; 944 } 945 946 if (data->blocks > 1) { 947 cmd_cfg |= CMD_CFG_BLOCK_MODE; 948 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 949 data->blocks); 950 meson_mmc_set_blksz(mmc, data->blksz); 951 } else { 952 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 953 } 954 955 xfer_bytes = data->blksz * data->blocks; 956 if (data->flags & MMC_DATA_WRITE) { 957 cmd_cfg |= CMD_CFG_DATA_WR; 958 WARN_ON(xfer_bytes > host->bounce_buf_size); 959 sg_copy_to_buffer(data->sg, data->sg_len, 960 host->bounce_buf, xfer_bytes); 961 dma_wmb(); 962 } 963 964 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 965 } else { 966 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 967 ilog2(SD_EMMC_CMD_TIMEOUT)); 968 } 969 970 /* Last descriptor */ 971 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 972 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 973 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 974 writel(0, host->regs + SD_EMMC_CMD_RSP); 975 wmb(); /* ensure descriptor is written before kicked */ 976 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 977 } 978 979 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 980 { 981 struct meson_host *host = mmc_priv(mmc); 982 bool needs_pre_post_req = mrq->data && 983 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 984 985 if (needs_pre_post_req) { 986 meson_mmc_get_transfer_mode(mmc, mrq); 987 if (!meson_mmc_desc_chain_mode(mrq->data)) 988 needs_pre_post_req = false; 989 } 990 991 if (needs_pre_post_req) 992 meson_mmc_pre_req(mmc, mrq); 993 994 /* Stop execution */ 995 writel(0, host->regs + SD_EMMC_START); 996 997 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 998 999 if (needs_pre_post_req) 1000 meson_mmc_post_req(mmc, mrq, 0); 1001 } 1002 1003 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 1004 { 1005 struct meson_host *host = mmc_priv(mmc); 1006 1007 if (cmd->flags & MMC_RSP_136) { 1008 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 1009 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 1010 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 1011 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 1012 } else if (cmd->flags & MMC_RSP_PRESENT) { 1013 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 1014 } 1015 } 1016 1017 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 1018 { 1019 struct meson_host *host = dev_id; 1020 struct mmc_command *cmd; 1021 struct mmc_data *data; 1022 u32 irq_en, status, raw_status; 1023 irqreturn_t ret = IRQ_NONE; 1024 1025 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 1026 raw_status = readl(host->regs + SD_EMMC_STATUS); 1027 status = raw_status & irq_en; 1028 1029 if (!status) { 1030 dev_dbg(host->dev, 1031 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 1032 irq_en, raw_status); 1033 return IRQ_NONE; 1034 } 1035 1036 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 1037 return IRQ_NONE; 1038 1039 cmd = host->cmd; 1040 data = cmd->data; 1041 cmd->error = 0; 1042 if (status & IRQ_CRC_ERR) { 1043 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 1044 cmd->error = -EILSEQ; 1045 ret = IRQ_WAKE_THREAD; 1046 goto out; 1047 } 1048 1049 if (status & IRQ_TIMEOUTS) { 1050 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 1051 cmd->error = -ETIMEDOUT; 1052 ret = IRQ_WAKE_THREAD; 1053 goto out; 1054 } 1055 1056 meson_mmc_read_resp(host->mmc, cmd); 1057 1058 if (status & IRQ_SDIO) { 1059 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 1060 ret = IRQ_HANDLED; 1061 } 1062 1063 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 1064 if (data && !cmd->error) 1065 data->bytes_xfered = data->blksz * data->blocks; 1066 if (meson_mmc_bounce_buf_read(data) || 1067 meson_mmc_get_next_command(cmd)) 1068 ret = IRQ_WAKE_THREAD; 1069 else 1070 ret = IRQ_HANDLED; 1071 } 1072 1073 out: 1074 /* ack all enabled interrupts */ 1075 writel(irq_en, host->regs + SD_EMMC_STATUS); 1076 1077 if (cmd->error) { 1078 /* Stop desc in case of errors */ 1079 u32 start = readl(host->regs + SD_EMMC_START); 1080 1081 start &= ~START_DESC_BUSY; 1082 writel(start, host->regs + SD_EMMC_START); 1083 } 1084 1085 if (ret == IRQ_HANDLED) 1086 meson_mmc_request_done(host->mmc, cmd->mrq); 1087 1088 return ret; 1089 } 1090 1091 static int meson_mmc_wait_desc_stop(struct meson_host *host) 1092 { 1093 int loop; 1094 u32 status; 1095 1096 /* 1097 * It may sometimes take a while for it to actually halt. Here, we 1098 * are giving it 5ms to comply 1099 * 1100 * If we don't confirm the descriptor is stopped, it might raise new 1101 * IRQs after we have called mmc_request_done() which is bad. 1102 */ 1103 for (loop = 50; loop; loop--) { 1104 status = readl(host->regs + SD_EMMC_STATUS); 1105 if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) 1106 udelay(100); 1107 else 1108 break; 1109 } 1110 1111 if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) { 1112 dev_err(host->dev, "Timed out waiting for host to stop\n"); 1113 return -ETIMEDOUT; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 1120 { 1121 struct meson_host *host = dev_id; 1122 struct mmc_command *next_cmd, *cmd = host->cmd; 1123 struct mmc_data *data; 1124 unsigned int xfer_bytes; 1125 1126 if (WARN_ON(!cmd)) 1127 return IRQ_NONE; 1128 1129 if (cmd->error) { 1130 meson_mmc_wait_desc_stop(host); 1131 meson_mmc_request_done(host->mmc, cmd->mrq); 1132 1133 return IRQ_HANDLED; 1134 } 1135 1136 data = cmd->data; 1137 if (meson_mmc_bounce_buf_read(data)) { 1138 xfer_bytes = data->blksz * data->blocks; 1139 WARN_ON(xfer_bytes > host->bounce_buf_size); 1140 sg_copy_from_buffer(data->sg, data->sg_len, 1141 host->bounce_buf, xfer_bytes); 1142 } 1143 1144 next_cmd = meson_mmc_get_next_command(cmd); 1145 if (next_cmd) 1146 meson_mmc_start_cmd(host->mmc, next_cmd); 1147 else 1148 meson_mmc_request_done(host->mmc, cmd->mrq); 1149 1150 return IRQ_HANDLED; 1151 } 1152 1153 /* 1154 * NOTE: we only need this until the GPIO/pinctrl driver can handle 1155 * interrupts. For now, the MMC core will use this for polling. 1156 */ 1157 static int meson_mmc_get_cd(struct mmc_host *mmc) 1158 { 1159 int status = mmc_gpio_get_cd(mmc); 1160 1161 if (status == -ENOSYS) 1162 return 1; /* assume present */ 1163 1164 return status; 1165 } 1166 1167 static void meson_mmc_cfg_init(struct meson_host *host) 1168 { 1169 u32 cfg = 0, adj = 0; 1170 1171 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 1172 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 1173 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 1174 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 1175 1176 /* abort chain on R/W errors */ 1177 cfg |= CFG_ERR_ABORT; 1178 1179 writel(cfg, host->regs + SD_EMMC_CFG); 1180 1181 /* enable signal resampling w/o delay */ 1182 adj = ADJUST_ADJ_EN; 1183 writel(adj, host->regs + host->data->adjust); 1184 } 1185 1186 static int meson_mmc_card_busy(struct mmc_host *mmc) 1187 { 1188 struct meson_host *host = mmc_priv(mmc); 1189 u32 regval; 1190 1191 regval = readl(host->regs + SD_EMMC_STATUS); 1192 1193 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1194 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1195 } 1196 1197 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1198 { 1199 /* vqmmc regulator is available */ 1200 if (!IS_ERR(mmc->supply.vqmmc)) { 1201 /* 1202 * The usual amlogic setup uses a GPIO to switch from one 1203 * regulator to the other. While the voltage ramp up is 1204 * pretty fast, care must be taken when switching from 3.3v 1205 * to 1.8v. Please make sure the regulator framework is aware 1206 * of your own regulator constraints 1207 */ 1208 return mmc_regulator_set_vqmmc(mmc, ios); 1209 } 1210 1211 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1212 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1213 return 0; 1214 1215 return -EINVAL; 1216 } 1217 1218 static const struct mmc_host_ops meson_mmc_ops = { 1219 .request = meson_mmc_request, 1220 .set_ios = meson_mmc_set_ios, 1221 .get_cd = meson_mmc_get_cd, 1222 .pre_req = meson_mmc_pre_req, 1223 .post_req = meson_mmc_post_req, 1224 .execute_tuning = meson_mmc_execute_tuning, 1225 .card_busy = meson_mmc_card_busy, 1226 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1227 }; 1228 1229 static int meson_mmc_probe(struct platform_device *pdev) 1230 { 1231 struct resource *res; 1232 struct meson_host *host; 1233 struct mmc_host *mmc; 1234 int ret, irq; 1235 1236 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1237 if (!mmc) 1238 return -ENOMEM; 1239 host = mmc_priv(mmc); 1240 host->mmc = mmc; 1241 host->dev = &pdev->dev; 1242 dev_set_drvdata(&pdev->dev, host); 1243 1244 /* Get regulators and the supported OCR mask */ 1245 host->vqmmc_enabled = false; 1246 ret = mmc_regulator_get_supply(mmc); 1247 if (ret) 1248 goto free_host; 1249 1250 ret = mmc_of_parse(mmc); 1251 if (ret) { 1252 if (ret != -EPROBE_DEFER) 1253 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1254 goto free_host; 1255 } 1256 1257 host->data = (struct meson_mmc_data *) 1258 of_device_get_match_data(&pdev->dev); 1259 if (!host->data) { 1260 ret = -EINVAL; 1261 goto free_host; 1262 } 1263 1264 ret = device_reset_optional(&pdev->dev); 1265 if (ret) { 1266 if (ret != -EPROBE_DEFER) 1267 dev_err(&pdev->dev, "device reset failed: %d\n", ret); 1268 1269 return ret; 1270 } 1271 1272 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1273 host->regs = devm_ioremap_resource(&pdev->dev, res); 1274 if (IS_ERR(host->regs)) { 1275 ret = PTR_ERR(host->regs); 1276 goto free_host; 1277 } 1278 1279 irq = platform_get_irq(pdev, 0); 1280 if (irq <= 0) { 1281 dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 1282 ret = -EINVAL; 1283 goto free_host; 1284 } 1285 1286 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1287 if (IS_ERR(host->pinctrl)) { 1288 ret = PTR_ERR(host->pinctrl); 1289 goto free_host; 1290 } 1291 1292 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1293 PINCTRL_STATE_DEFAULT); 1294 if (IS_ERR(host->pins_default)) { 1295 ret = PTR_ERR(host->pins_default); 1296 goto free_host; 1297 } 1298 1299 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1300 "clk-gate"); 1301 if (IS_ERR(host->pins_clk_gate)) { 1302 dev_warn(&pdev->dev, 1303 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1304 host->pins_clk_gate = NULL; 1305 } 1306 1307 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1308 if (IS_ERR(host->core_clk)) { 1309 ret = PTR_ERR(host->core_clk); 1310 goto free_host; 1311 } 1312 1313 ret = clk_prepare_enable(host->core_clk); 1314 if (ret) 1315 goto free_host; 1316 1317 ret = meson_mmc_clk_init(host); 1318 if (ret) 1319 goto err_core_clk; 1320 1321 /* set config to sane default */ 1322 meson_mmc_cfg_init(host); 1323 1324 /* Stop execution */ 1325 writel(0, host->regs + SD_EMMC_START); 1326 1327 /* clear, ack and enable interrupts */ 1328 writel(0, host->regs + SD_EMMC_IRQ_EN); 1329 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1330 host->regs + SD_EMMC_STATUS); 1331 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1332 host->regs + SD_EMMC_IRQ_EN); 1333 1334 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq, 1335 meson_mmc_irq_thread, IRQF_SHARED, 1336 NULL, host); 1337 if (ret) 1338 goto err_init_clk; 1339 1340 mmc->caps |= MMC_CAP_CMD23; 1341 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1342 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1343 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); 1344 mmc->max_seg_size = mmc->max_req_size; 1345 1346 /* data bounce buffer */ 1347 host->bounce_buf_size = mmc->max_req_size; 1348 host->bounce_buf = 1349 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1350 &host->bounce_dma_addr, GFP_KERNEL); 1351 if (host->bounce_buf == NULL) { 1352 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1353 ret = -ENOMEM; 1354 goto err_init_clk; 1355 } 1356 1357 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1358 &host->descs_dma_addr, GFP_KERNEL); 1359 if (!host->descs) { 1360 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1361 ret = -ENOMEM; 1362 goto err_bounce_buf; 1363 } 1364 1365 mmc->ops = &meson_mmc_ops; 1366 mmc_add_host(mmc); 1367 1368 return 0; 1369 1370 err_bounce_buf: 1371 dma_free_coherent(host->dev, host->bounce_buf_size, 1372 host->bounce_buf, host->bounce_dma_addr); 1373 err_init_clk: 1374 clk_disable_unprepare(host->mmc_clk); 1375 err_core_clk: 1376 clk_disable_unprepare(host->core_clk); 1377 free_host: 1378 mmc_free_host(mmc); 1379 return ret; 1380 } 1381 1382 static int meson_mmc_remove(struct platform_device *pdev) 1383 { 1384 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1385 1386 mmc_remove_host(host->mmc); 1387 1388 /* disable interrupts */ 1389 writel(0, host->regs + SD_EMMC_IRQ_EN); 1390 1391 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1392 host->descs, host->descs_dma_addr); 1393 dma_free_coherent(host->dev, host->bounce_buf_size, 1394 host->bounce_buf, host->bounce_dma_addr); 1395 1396 clk_disable_unprepare(host->mmc_clk); 1397 clk_disable_unprepare(host->core_clk); 1398 1399 mmc_free_host(host->mmc); 1400 return 0; 1401 } 1402 1403 static const struct meson_mmc_data meson_gx_data = { 1404 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1405 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1406 .always_on = CLK_V2_ALWAYS_ON, 1407 .adjust = SD_EMMC_ADJUST, 1408 }; 1409 1410 static const struct meson_mmc_data meson_axg_data = { 1411 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1412 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1413 .always_on = CLK_V3_ALWAYS_ON, 1414 .adjust = SD_EMMC_V3_ADJUST, 1415 }; 1416 1417 static const struct of_device_id meson_mmc_of_match[] = { 1418 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1419 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1420 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1421 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1422 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1423 {} 1424 }; 1425 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1426 1427 static struct platform_driver meson_mmc_driver = { 1428 .probe = meson_mmc_probe, 1429 .remove = meson_mmc_remove, 1430 .driver = { 1431 .name = DRIVER_NAME, 1432 .of_match_table = of_match_ptr(meson_mmc_of_match), 1433 }, 1434 }; 1435 1436 module_platform_driver(meson_mmc_driver); 1437 1438 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1439 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1440 MODULE_LICENSE("GPL v2"); 1441