1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ioport.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/slot-gpio.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitfield.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "meson-gx-mmc" 32 33 #define SD_EMMC_CLOCK 0x0 34 #define CLK_DIV_MASK GENMASK(5, 0) 35 #define CLK_SRC_MASK GENMASK(7, 6) 36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 39 #define CLK_PHASE_0 0 40 #define CLK_PHASE_180 2 41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43 #define CLK_V2_ALWAYS_ON BIT(24) 44 45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 47 #define CLK_V3_ALWAYS_ON BIT(28) 48 49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 51 #define CLK_ALWAYS_ON(h) (h->data->always_on) 52 53 #define SD_EMMC_DELAY 0x4 54 #define SD_EMMC_ADJUST 0x8 55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 56 #define ADJUST_DS_EN BIT(15) 57 #define ADJUST_ADJ_EN BIT(13) 58 59 #define SD_EMMC_DELAY1 0x4 60 #define SD_EMMC_DELAY2 0x8 61 #define SD_EMMC_V3_ADJUST 0xc 62 63 #define SD_EMMC_CALOUT 0x10 64 #define SD_EMMC_START 0x40 65 #define START_DESC_INIT BIT(0) 66 #define START_DESC_BUSY BIT(1) 67 #define START_DESC_ADDR_MASK GENMASK(31, 2) 68 69 #define SD_EMMC_CFG 0x44 70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 71 #define CFG_BUS_WIDTH_1 0x0 72 #define CFG_BUS_WIDTH_4 0x1 73 #define CFG_BUS_WIDTH_8 0x2 74 #define CFG_DDR BIT(2) 75 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 77 #define CFG_RC_CC_MASK GENMASK(15, 12) 78 #define CFG_STOP_CLOCK BIT(22) 79 #define CFG_CLK_ALWAYS_ON BIT(18) 80 #define CFG_CHK_DS BIT(20) 81 #define CFG_AUTO_CLK BIT(23) 82 #define CFG_ERR_ABORT BIT(27) 83 84 #define SD_EMMC_STATUS 0x48 85 #define STATUS_BUSY BIT(31) 86 #define STATUS_DESC_BUSY BIT(30) 87 #define STATUS_DATI GENMASK(23, 16) 88 89 #define SD_EMMC_IRQ_EN 0x4c 90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 91 #define IRQ_TXD_ERR BIT(8) 92 #define IRQ_DESC_ERR BIT(9) 93 #define IRQ_RESP_ERR BIT(10) 94 #define IRQ_CRC_ERR \ 95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 96 #define IRQ_RESP_TIMEOUT BIT(11) 97 #define IRQ_DESC_TIMEOUT BIT(12) 98 #define IRQ_TIMEOUTS \ 99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 100 #define IRQ_END_OF_CHAIN BIT(13) 101 #define IRQ_RESP_STATUS BIT(14) 102 #define IRQ_SDIO BIT(15) 103 #define IRQ_EN_MASK \ 104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 105 IRQ_SDIO) 106 107 #define SD_EMMC_CMD_CFG 0x50 108 #define SD_EMMC_CMD_ARG 0x54 109 #define SD_EMMC_CMD_DAT 0x58 110 #define SD_EMMC_CMD_RSP 0x5c 111 #define SD_EMMC_CMD_RSP1 0x60 112 #define SD_EMMC_CMD_RSP2 0x64 113 #define SD_EMMC_CMD_RSP3 0x68 114 115 #define SD_EMMC_RXD 0x94 116 #define SD_EMMC_TXD 0x94 117 #define SD_EMMC_LAST_REG SD_EMMC_TXD 118 119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536 120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 121 122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 128 129 #define SD_EMMC_PRE_REQ_DONE BIT(0) 130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 131 132 #define MUX_CLK_NUM_PARENTS 2 133 134 struct meson_mmc_data { 135 unsigned int tx_delay_mask; 136 unsigned int rx_delay_mask; 137 unsigned int always_on; 138 unsigned int adjust; 139 }; 140 141 struct sd_emmc_desc { 142 u32 cmd_cfg; 143 u32 cmd_arg; 144 u32 cmd_data; 145 u32 cmd_resp; 146 }; 147 148 struct meson_host { 149 struct device *dev; 150 struct meson_mmc_data *data; 151 struct mmc_host *mmc; 152 struct mmc_command *cmd; 153 154 void __iomem *regs; 155 struct clk *core_clk; 156 struct clk *mux_clk; 157 struct clk *mmc_clk; 158 unsigned long req_rate; 159 bool ddr; 160 161 bool dram_access_quirk; 162 163 struct pinctrl *pinctrl; 164 struct pinctrl_state *pins_clk_gate; 165 166 unsigned int bounce_buf_size; 167 void *bounce_buf; 168 dma_addr_t bounce_dma_addr; 169 struct sd_emmc_desc *descs; 170 dma_addr_t descs_dma_addr; 171 172 int irq; 173 174 bool vqmmc_enabled; 175 }; 176 177 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 178 #define CMD_CFG_BLOCK_MODE BIT(9) 179 #define CMD_CFG_R1B BIT(10) 180 #define CMD_CFG_END_OF_CHAIN BIT(11) 181 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 182 #define CMD_CFG_NO_RESP BIT(16) 183 #define CMD_CFG_NO_CMD BIT(17) 184 #define CMD_CFG_DATA_IO BIT(18) 185 #define CMD_CFG_DATA_WR BIT(19) 186 #define CMD_CFG_RESP_NOCRC BIT(20) 187 #define CMD_CFG_RESP_128 BIT(21) 188 #define CMD_CFG_RESP_NUM BIT(22) 189 #define CMD_CFG_DATA_NUM BIT(23) 190 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 191 #define CMD_CFG_ERROR BIT(30) 192 #define CMD_CFG_OWNER BIT(31) 193 194 #define CMD_DATA_MASK GENMASK(31, 2) 195 #define CMD_DATA_BIG_ENDIAN BIT(1) 196 #define CMD_DATA_SRAM BIT(0) 197 #define CMD_RESP_MASK GENMASK(31, 1) 198 #define CMD_RESP_SRAM BIT(0) 199 200 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 201 { 202 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 203 204 if (!timeout) 205 return SD_EMMC_CMD_TIMEOUT_DATA; 206 207 timeout = roundup_pow_of_two(timeout); 208 209 return min(timeout, 32768U); /* max. 2^15 ms */ 210 } 211 212 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 213 { 214 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 215 return cmd->mrq->cmd; 216 else if (mmc_op_multi(cmd->opcode) && 217 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 218 return cmd->mrq->stop; 219 else 220 return NULL; 221 } 222 223 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 224 struct mmc_request *mrq) 225 { 226 struct meson_host *host = mmc_priv(mmc); 227 struct mmc_data *data = mrq->data; 228 struct scatterlist *sg; 229 int i; 230 231 /* 232 * When Controller DMA cannot directly access DDR memory, disable 233 * support for Chain Mode to directly use the internal SRAM using 234 * the bounce buffer mode. 235 */ 236 if (host->dram_access_quirk) 237 return; 238 239 /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */ 240 if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) { 241 /* 242 * In block mode DMA descriptor format, "length" field indicates 243 * number of blocks and there is no way to pass DMA size that 244 * is not multiple of SDIO block size, making it impossible to 245 * tie more than one memory buffer with single SDIO block. 246 * Block mode sg buffer size should be aligned with SDIO block 247 * size, otherwise chain mode could not be used. 248 */ 249 for_each_sg(data->sg, sg, data->sg_len, i) { 250 if (sg->length % data->blksz) { 251 dev_warn_once(mmc_dev(mmc), 252 "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n", 253 sg->length, data->blksz); 254 return; 255 } 256 } 257 } 258 259 for_each_sg(data->sg, sg, data->sg_len, i) { 260 /* check for 8 byte alignment */ 261 if (sg->offset % 8) { 262 dev_warn_once(mmc_dev(mmc), 263 "unaligned sg offset %u, disabling descriptor DMA for transfer\n", 264 sg->offset); 265 return; 266 } 267 } 268 269 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 270 } 271 272 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 273 { 274 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 275 } 276 277 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 278 { 279 return data && data->flags & MMC_DATA_READ && 280 !meson_mmc_desc_chain_mode(data); 281 } 282 283 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 284 { 285 struct mmc_data *data = mrq->data; 286 287 if (!data) 288 return; 289 290 meson_mmc_get_transfer_mode(mmc, mrq); 291 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 292 293 if (!meson_mmc_desc_chain_mode(data)) 294 return; 295 296 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 297 mmc_get_dma_dir(data)); 298 if (!data->sg_count) 299 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 300 } 301 302 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 303 int err) 304 { 305 struct mmc_data *data = mrq->data; 306 307 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 308 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 309 mmc_get_dma_dir(data)); 310 } 311 312 /* 313 * Gating the clock on this controller is tricky. It seems the mmc clock 314 * is also used by the controller. It may crash during some operation if the 315 * clock is stopped. The safest thing to do, whenever possible, is to keep 316 * clock running at stop it at the pad using the pinmux. 317 */ 318 static void meson_mmc_clk_gate(struct meson_host *host) 319 { 320 u32 cfg; 321 322 if (host->pins_clk_gate) { 323 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 324 } else { 325 /* 326 * If the pinmux is not provided - default to the classic and 327 * unsafe method 328 */ 329 cfg = readl(host->regs + SD_EMMC_CFG); 330 cfg |= CFG_STOP_CLOCK; 331 writel(cfg, host->regs + SD_EMMC_CFG); 332 } 333 } 334 335 static void meson_mmc_clk_ungate(struct meson_host *host) 336 { 337 u32 cfg; 338 339 if (host->pins_clk_gate) 340 pinctrl_select_default_state(host->dev); 341 342 /* Make sure the clock is not stopped in the controller */ 343 cfg = readl(host->regs + SD_EMMC_CFG); 344 cfg &= ~CFG_STOP_CLOCK; 345 writel(cfg, host->regs + SD_EMMC_CFG); 346 } 347 348 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 349 bool ddr) 350 { 351 struct mmc_host *mmc = host->mmc; 352 int ret; 353 u32 cfg; 354 355 /* Same request - bail-out */ 356 if (host->ddr == ddr && host->req_rate == rate) 357 return 0; 358 359 /* stop clock */ 360 meson_mmc_clk_gate(host); 361 host->req_rate = 0; 362 mmc->actual_clock = 0; 363 364 /* return with clock being stopped */ 365 if (!rate) 366 return 0; 367 368 /* Stop the clock during rate change to avoid glitches */ 369 cfg = readl(host->regs + SD_EMMC_CFG); 370 cfg |= CFG_STOP_CLOCK; 371 writel(cfg, host->regs + SD_EMMC_CFG); 372 373 if (ddr) { 374 /* DDR modes require higher module clock */ 375 rate <<= 1; 376 cfg |= CFG_DDR; 377 } else { 378 cfg &= ~CFG_DDR; 379 } 380 writel(cfg, host->regs + SD_EMMC_CFG); 381 host->ddr = ddr; 382 383 ret = clk_set_rate(host->mmc_clk, rate); 384 if (ret) { 385 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 386 rate, ret); 387 return ret; 388 } 389 390 host->req_rate = rate; 391 mmc->actual_clock = clk_get_rate(host->mmc_clk); 392 393 /* We should report the real output frequency of the controller */ 394 if (ddr) { 395 host->req_rate >>= 1; 396 mmc->actual_clock >>= 1; 397 } 398 399 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 400 if (rate != mmc->actual_clock) 401 dev_dbg(host->dev, "requested rate was %lu\n", rate); 402 403 /* (re)start clock */ 404 meson_mmc_clk_ungate(host); 405 406 return 0; 407 } 408 409 /* 410 * The SD/eMMC IP block has an internal mux and divider used for 411 * generating the MMC clock. Use the clock framework to create and 412 * manage these clocks. 413 */ 414 static int meson_mmc_clk_init(struct meson_host *host) 415 { 416 struct clk_init_data init; 417 struct clk_mux *mux; 418 struct clk_divider *div; 419 char clk_name[32]; 420 int i, ret = 0; 421 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 422 const char *clk_parent[1]; 423 u32 clk_reg; 424 425 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 426 clk_reg = CLK_ALWAYS_ON(host); 427 clk_reg |= CLK_DIV_MASK; 428 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 429 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 430 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 431 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 432 433 /* get the mux parents */ 434 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 435 struct clk *clk; 436 char name[16]; 437 438 snprintf(name, sizeof(name), "clkin%d", i); 439 clk = devm_clk_get(host->dev, name); 440 if (IS_ERR(clk)) 441 return dev_err_probe(host->dev, PTR_ERR(clk), 442 "Missing clock %s\n", name); 443 444 mux_parent_names[i] = __clk_get_name(clk); 445 } 446 447 /* create the mux */ 448 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 449 if (!mux) 450 return -ENOMEM; 451 452 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 453 init.name = clk_name; 454 init.ops = &clk_mux_ops; 455 init.flags = 0; 456 init.parent_names = mux_parent_names; 457 init.num_parents = MUX_CLK_NUM_PARENTS; 458 459 mux->reg = host->regs + SD_EMMC_CLOCK; 460 mux->shift = __ffs(CLK_SRC_MASK); 461 mux->mask = CLK_SRC_MASK >> mux->shift; 462 mux->hw.init = &init; 463 464 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 465 if (WARN_ON(IS_ERR(host->mux_clk))) 466 return PTR_ERR(host->mux_clk); 467 468 /* create the divider */ 469 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 470 if (!div) 471 return -ENOMEM; 472 473 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 474 init.name = clk_name; 475 init.ops = &clk_divider_ops; 476 init.flags = CLK_SET_RATE_PARENT; 477 clk_parent[0] = __clk_get_name(host->mux_clk); 478 init.parent_names = clk_parent; 479 init.num_parents = 1; 480 481 div->reg = host->regs + SD_EMMC_CLOCK; 482 div->shift = __ffs(CLK_DIV_MASK); 483 div->width = __builtin_popcountl(CLK_DIV_MASK); 484 div->hw.init = &init; 485 div->flags = CLK_DIVIDER_ONE_BASED; 486 487 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 488 if (WARN_ON(IS_ERR(host->mmc_clk))) 489 return PTR_ERR(host->mmc_clk); 490 491 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 492 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 493 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 494 if (ret) 495 return ret; 496 497 return clk_prepare_enable(host->mmc_clk); 498 } 499 500 static void meson_mmc_disable_resampling(struct meson_host *host) 501 { 502 unsigned int val = readl(host->regs + host->data->adjust); 503 504 val &= ~ADJUST_ADJ_EN; 505 writel(val, host->regs + host->data->adjust); 506 } 507 508 static void meson_mmc_reset_resampling(struct meson_host *host) 509 { 510 unsigned int val; 511 512 meson_mmc_disable_resampling(host); 513 514 val = readl(host->regs + host->data->adjust); 515 val &= ~ADJUST_ADJ_DELAY_MASK; 516 writel(val, host->regs + host->data->adjust); 517 } 518 519 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 520 { 521 struct meson_host *host = mmc_priv(mmc); 522 unsigned int val, dly, max_dly, i; 523 int ret; 524 525 /* Resampling is done using the source clock */ 526 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 527 clk_get_rate(host->mmc_clk)); 528 529 val = readl(host->regs + host->data->adjust); 530 val |= ADJUST_ADJ_EN; 531 writel(val, host->regs + host->data->adjust); 532 533 if (mmc_doing_retune(mmc)) 534 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 535 else 536 dly = 0; 537 538 for (i = 0; i < max_dly; i++) { 539 val &= ~ADJUST_ADJ_DELAY_MASK; 540 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 541 writel(val, host->regs + host->data->adjust); 542 543 ret = mmc_send_tuning(mmc, opcode, NULL); 544 if (!ret) { 545 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 546 (dly + i) % max_dly); 547 return 0; 548 } 549 } 550 551 meson_mmc_reset_resampling(host); 552 return -EIO; 553 } 554 555 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 556 struct mmc_ios *ios) 557 { 558 bool ddr; 559 560 switch (ios->timing) { 561 case MMC_TIMING_MMC_DDR52: 562 case MMC_TIMING_UHS_DDR50: 563 ddr = true; 564 break; 565 566 default: 567 ddr = false; 568 break; 569 } 570 571 return meson_mmc_clk_set(host, ios->clock, ddr); 572 } 573 574 static void meson_mmc_check_resampling(struct meson_host *host, 575 struct mmc_ios *ios) 576 { 577 switch (ios->timing) { 578 case MMC_TIMING_LEGACY: 579 case MMC_TIMING_MMC_HS: 580 case MMC_TIMING_SD_HS: 581 case MMC_TIMING_MMC_DDR52: 582 meson_mmc_disable_resampling(host); 583 break; 584 } 585 } 586 587 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 588 { 589 struct meson_host *host = mmc_priv(mmc); 590 u32 bus_width, val; 591 int err; 592 593 /* 594 * GPIO regulator, only controls switching between 1v8 and 595 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 596 */ 597 switch (ios->power_mode) { 598 case MMC_POWER_OFF: 599 if (!IS_ERR(mmc->supply.vmmc)) 600 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 601 602 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 603 regulator_disable(mmc->supply.vqmmc); 604 host->vqmmc_enabled = false; 605 } 606 607 break; 608 609 case MMC_POWER_UP: 610 if (!IS_ERR(mmc->supply.vmmc)) 611 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 612 613 break; 614 615 case MMC_POWER_ON: 616 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 617 int ret = regulator_enable(mmc->supply.vqmmc); 618 619 if (ret < 0) 620 dev_err(host->dev, 621 "failed to enable vqmmc regulator\n"); 622 else 623 host->vqmmc_enabled = true; 624 } 625 626 break; 627 } 628 629 /* Bus width */ 630 switch (ios->bus_width) { 631 case MMC_BUS_WIDTH_1: 632 bus_width = CFG_BUS_WIDTH_1; 633 break; 634 case MMC_BUS_WIDTH_4: 635 bus_width = CFG_BUS_WIDTH_4; 636 break; 637 case MMC_BUS_WIDTH_8: 638 bus_width = CFG_BUS_WIDTH_8; 639 break; 640 default: 641 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 642 ios->bus_width); 643 bus_width = CFG_BUS_WIDTH_4; 644 } 645 646 val = readl(host->regs + SD_EMMC_CFG); 647 val &= ~CFG_BUS_WIDTH_MASK; 648 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 649 writel(val, host->regs + SD_EMMC_CFG); 650 651 meson_mmc_check_resampling(host, ios); 652 err = meson_mmc_prepare_ios_clock(host, ios); 653 if (err) 654 dev_err(host->dev, "Failed to set clock: %d\n,", err); 655 656 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 657 } 658 659 static void meson_mmc_request_done(struct mmc_host *mmc, 660 struct mmc_request *mrq) 661 { 662 struct meson_host *host = mmc_priv(mmc); 663 664 host->cmd = NULL; 665 mmc_request_done(host->mmc, mrq); 666 } 667 668 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 669 { 670 struct meson_host *host = mmc_priv(mmc); 671 u32 cfg, blksz_old; 672 673 cfg = readl(host->regs + SD_EMMC_CFG); 674 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 675 676 if (!is_power_of_2(blksz)) 677 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 678 679 blksz = ilog2(blksz); 680 681 /* check if block-size matches, if not update */ 682 if (blksz == blksz_old) 683 return; 684 685 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 686 blksz_old, blksz); 687 688 cfg &= ~CFG_BLK_LEN_MASK; 689 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 690 writel(cfg, host->regs + SD_EMMC_CFG); 691 } 692 693 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 694 { 695 if (cmd->flags & MMC_RSP_PRESENT) { 696 if (cmd->flags & MMC_RSP_136) 697 *cmd_cfg |= CMD_CFG_RESP_128; 698 *cmd_cfg |= CMD_CFG_RESP_NUM; 699 700 if (!(cmd->flags & MMC_RSP_CRC)) 701 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 702 703 if (cmd->flags & MMC_RSP_BUSY) 704 *cmd_cfg |= CMD_CFG_R1B; 705 } else { 706 *cmd_cfg |= CMD_CFG_NO_RESP; 707 } 708 } 709 710 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 711 { 712 struct meson_host *host = mmc_priv(mmc); 713 struct sd_emmc_desc *desc = host->descs; 714 struct mmc_data *data = host->cmd->data; 715 struct scatterlist *sg; 716 u32 start; 717 int i; 718 719 if (data->flags & MMC_DATA_WRITE) 720 cmd_cfg |= CMD_CFG_DATA_WR; 721 722 if (data->blocks > 1) { 723 cmd_cfg |= CMD_CFG_BLOCK_MODE; 724 meson_mmc_set_blksz(mmc, data->blksz); 725 } 726 727 for_each_sg(data->sg, sg, data->sg_count, i) { 728 unsigned int len = sg_dma_len(sg); 729 730 if (data->blocks > 1) 731 len /= data->blksz; 732 733 desc[i].cmd_cfg = cmd_cfg; 734 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 735 if (i > 0) 736 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 737 desc[i].cmd_arg = host->cmd->arg; 738 desc[i].cmd_resp = 0; 739 desc[i].cmd_data = sg_dma_address(sg); 740 } 741 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 742 743 dma_wmb(); /* ensure descriptor is written before kicked */ 744 start = host->descs_dma_addr | START_DESC_BUSY; 745 writel(start, host->regs + SD_EMMC_START); 746 } 747 748 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 749 { 750 struct meson_host *host = mmc_priv(mmc); 751 struct mmc_data *data = cmd->data; 752 u32 cmd_cfg = 0, cmd_data = 0; 753 unsigned int xfer_bytes = 0; 754 755 /* Setup descriptors */ 756 dma_rmb(); 757 758 host->cmd = cmd; 759 760 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 761 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 762 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 763 764 meson_mmc_set_response_bits(cmd, &cmd_cfg); 765 766 /* data? */ 767 if (data) { 768 data->bytes_xfered = 0; 769 cmd_cfg |= CMD_CFG_DATA_IO; 770 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 771 ilog2(meson_mmc_get_timeout_msecs(data))); 772 773 if (meson_mmc_desc_chain_mode(data)) { 774 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 775 return; 776 } 777 778 if (data->blocks > 1) { 779 cmd_cfg |= CMD_CFG_BLOCK_MODE; 780 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 781 data->blocks); 782 meson_mmc_set_blksz(mmc, data->blksz); 783 } else { 784 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 785 } 786 787 xfer_bytes = data->blksz * data->blocks; 788 if (data->flags & MMC_DATA_WRITE) { 789 cmd_cfg |= CMD_CFG_DATA_WR; 790 WARN_ON(xfer_bytes > host->bounce_buf_size); 791 sg_copy_to_buffer(data->sg, data->sg_len, 792 host->bounce_buf, xfer_bytes); 793 dma_wmb(); 794 } 795 796 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 797 } else { 798 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 799 ilog2(SD_EMMC_CMD_TIMEOUT)); 800 } 801 802 /* Last descriptor */ 803 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 804 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 805 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 806 writel(0, host->regs + SD_EMMC_CMD_RSP); 807 wmb(); /* ensure descriptor is written before kicked */ 808 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 809 } 810 811 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 812 { 813 struct meson_host *host = mmc_priv(mmc); 814 bool needs_pre_post_req = mrq->data && 815 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 816 817 if (needs_pre_post_req) { 818 meson_mmc_get_transfer_mode(mmc, mrq); 819 if (!meson_mmc_desc_chain_mode(mrq->data)) 820 needs_pre_post_req = false; 821 } 822 823 if (needs_pre_post_req) 824 meson_mmc_pre_req(mmc, mrq); 825 826 /* Stop execution */ 827 writel(0, host->regs + SD_EMMC_START); 828 829 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 830 831 if (needs_pre_post_req) 832 meson_mmc_post_req(mmc, mrq, 0); 833 } 834 835 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 836 { 837 struct meson_host *host = mmc_priv(mmc); 838 839 if (cmd->flags & MMC_RSP_136) { 840 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 841 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 842 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 843 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 844 } else if (cmd->flags & MMC_RSP_PRESENT) { 845 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 846 } 847 } 848 849 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 850 { 851 struct meson_host *host = dev_id; 852 struct mmc_command *cmd; 853 struct mmc_data *data; 854 u32 irq_en, status, raw_status; 855 irqreturn_t ret = IRQ_NONE; 856 857 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 858 raw_status = readl(host->regs + SD_EMMC_STATUS); 859 status = raw_status & irq_en; 860 861 if (!status) { 862 dev_dbg(host->dev, 863 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 864 irq_en, raw_status); 865 return IRQ_NONE; 866 } 867 868 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 869 return IRQ_NONE; 870 871 /* ack all raised interrupts */ 872 writel(status, host->regs + SD_EMMC_STATUS); 873 874 cmd = host->cmd; 875 data = cmd->data; 876 cmd->error = 0; 877 if (status & IRQ_CRC_ERR) { 878 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 879 cmd->error = -EILSEQ; 880 ret = IRQ_WAKE_THREAD; 881 goto out; 882 } 883 884 if (status & IRQ_TIMEOUTS) { 885 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 886 cmd->error = -ETIMEDOUT; 887 ret = IRQ_WAKE_THREAD; 888 goto out; 889 } 890 891 meson_mmc_read_resp(host->mmc, cmd); 892 893 if (status & IRQ_SDIO) { 894 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 895 ret = IRQ_HANDLED; 896 } 897 898 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 899 if (data && !cmd->error) 900 data->bytes_xfered = data->blksz * data->blocks; 901 if (meson_mmc_bounce_buf_read(data) || 902 meson_mmc_get_next_command(cmd)) 903 ret = IRQ_WAKE_THREAD; 904 else 905 ret = IRQ_HANDLED; 906 } 907 908 out: 909 if (cmd->error) { 910 /* Stop desc in case of errors */ 911 u32 start = readl(host->regs + SD_EMMC_START); 912 913 start &= ~START_DESC_BUSY; 914 writel(start, host->regs + SD_EMMC_START); 915 } 916 917 if (ret == IRQ_HANDLED) 918 meson_mmc_request_done(host->mmc, cmd->mrq); 919 920 return ret; 921 } 922 923 static int meson_mmc_wait_desc_stop(struct meson_host *host) 924 { 925 u32 status; 926 927 /* 928 * It may sometimes take a while for it to actually halt. Here, we 929 * are giving it 5ms to comply 930 * 931 * If we don't confirm the descriptor is stopped, it might raise new 932 * IRQs after we have called mmc_request_done() which is bad. 933 */ 934 935 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 936 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 937 100, 5000); 938 } 939 940 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 941 { 942 struct meson_host *host = dev_id; 943 struct mmc_command *next_cmd, *cmd = host->cmd; 944 struct mmc_data *data; 945 unsigned int xfer_bytes; 946 947 if (WARN_ON(!cmd)) 948 return IRQ_NONE; 949 950 if (cmd->error) { 951 meson_mmc_wait_desc_stop(host); 952 meson_mmc_request_done(host->mmc, cmd->mrq); 953 954 return IRQ_HANDLED; 955 } 956 957 data = cmd->data; 958 if (meson_mmc_bounce_buf_read(data)) { 959 xfer_bytes = data->blksz * data->blocks; 960 WARN_ON(xfer_bytes > host->bounce_buf_size); 961 sg_copy_from_buffer(data->sg, data->sg_len, 962 host->bounce_buf, xfer_bytes); 963 } 964 965 next_cmd = meson_mmc_get_next_command(cmd); 966 if (next_cmd) 967 meson_mmc_start_cmd(host->mmc, next_cmd); 968 else 969 meson_mmc_request_done(host->mmc, cmd->mrq); 970 971 return IRQ_HANDLED; 972 } 973 974 /* 975 * NOTE: we only need this until the GPIO/pinctrl driver can handle 976 * interrupts. For now, the MMC core will use this for polling. 977 */ 978 static int meson_mmc_get_cd(struct mmc_host *mmc) 979 { 980 int status = mmc_gpio_get_cd(mmc); 981 982 if (status == -ENOSYS) 983 return 1; /* assume present */ 984 985 return status; 986 } 987 988 static void meson_mmc_cfg_init(struct meson_host *host) 989 { 990 u32 cfg = 0; 991 992 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 993 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 994 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 995 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 996 997 /* abort chain on R/W errors */ 998 cfg |= CFG_ERR_ABORT; 999 1000 writel(cfg, host->regs + SD_EMMC_CFG); 1001 } 1002 1003 static int meson_mmc_card_busy(struct mmc_host *mmc) 1004 { 1005 struct meson_host *host = mmc_priv(mmc); 1006 u32 regval; 1007 1008 regval = readl(host->regs + SD_EMMC_STATUS); 1009 1010 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1011 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1012 } 1013 1014 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1015 { 1016 int ret; 1017 1018 /* vqmmc regulator is available */ 1019 if (!IS_ERR(mmc->supply.vqmmc)) { 1020 /* 1021 * The usual amlogic setup uses a GPIO to switch from one 1022 * regulator to the other. While the voltage ramp up is 1023 * pretty fast, care must be taken when switching from 3.3v 1024 * to 1.8v. Please make sure the regulator framework is aware 1025 * of your own regulator constraints 1026 */ 1027 ret = mmc_regulator_set_vqmmc(mmc, ios); 1028 return ret < 0 ? ret : 0; 1029 } 1030 1031 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1032 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1033 return 0; 1034 1035 return -EINVAL; 1036 } 1037 1038 static const struct mmc_host_ops meson_mmc_ops = { 1039 .request = meson_mmc_request, 1040 .set_ios = meson_mmc_set_ios, 1041 .get_cd = meson_mmc_get_cd, 1042 .pre_req = meson_mmc_pre_req, 1043 .post_req = meson_mmc_post_req, 1044 .execute_tuning = meson_mmc_resampling_tuning, 1045 .card_busy = meson_mmc_card_busy, 1046 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1047 }; 1048 1049 static int meson_mmc_probe(struct platform_device *pdev) 1050 { 1051 struct resource *res; 1052 struct meson_host *host; 1053 struct mmc_host *mmc; 1054 int ret; 1055 1056 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1057 if (!mmc) 1058 return -ENOMEM; 1059 host = mmc_priv(mmc); 1060 host->mmc = mmc; 1061 host->dev = &pdev->dev; 1062 dev_set_drvdata(&pdev->dev, host); 1063 1064 /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1065 host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1066 "amlogic,dram-access-quirk"); 1067 1068 /* Get regulators and the supported OCR mask */ 1069 host->vqmmc_enabled = false; 1070 ret = mmc_regulator_get_supply(mmc); 1071 if (ret) 1072 goto free_host; 1073 1074 ret = mmc_of_parse(mmc); 1075 if (ret) { 1076 if (ret != -EPROBE_DEFER) 1077 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1078 goto free_host; 1079 } 1080 1081 host->data = (struct meson_mmc_data *) 1082 of_device_get_match_data(&pdev->dev); 1083 if (!host->data) { 1084 ret = -EINVAL; 1085 goto free_host; 1086 } 1087 1088 ret = device_reset_optional(&pdev->dev); 1089 if (ret) 1090 return dev_err_probe(&pdev->dev, ret, "device reset failed\n"); 1091 1092 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1093 host->regs = devm_ioremap_resource(&pdev->dev, res); 1094 if (IS_ERR(host->regs)) { 1095 ret = PTR_ERR(host->regs); 1096 goto free_host; 1097 } 1098 1099 host->irq = platform_get_irq(pdev, 0); 1100 if (host->irq <= 0) { 1101 ret = -EINVAL; 1102 goto free_host; 1103 } 1104 1105 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1106 if (IS_ERR(host->pinctrl)) { 1107 ret = PTR_ERR(host->pinctrl); 1108 goto free_host; 1109 } 1110 1111 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1112 "clk-gate"); 1113 if (IS_ERR(host->pins_clk_gate)) { 1114 dev_warn(&pdev->dev, 1115 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1116 host->pins_clk_gate = NULL; 1117 } 1118 1119 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1120 if (IS_ERR(host->core_clk)) { 1121 ret = PTR_ERR(host->core_clk); 1122 goto free_host; 1123 } 1124 1125 ret = clk_prepare_enable(host->core_clk); 1126 if (ret) 1127 goto free_host; 1128 1129 ret = meson_mmc_clk_init(host); 1130 if (ret) 1131 goto err_core_clk; 1132 1133 /* set config to sane default */ 1134 meson_mmc_cfg_init(host); 1135 1136 /* Stop execution */ 1137 writel(0, host->regs + SD_EMMC_START); 1138 1139 /* clear, ack and enable interrupts */ 1140 writel(0, host->regs + SD_EMMC_IRQ_EN); 1141 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1142 host->regs + SD_EMMC_STATUS); 1143 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1144 host->regs + SD_EMMC_IRQ_EN); 1145 1146 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1147 meson_mmc_irq_thread, IRQF_ONESHOT, 1148 dev_name(&pdev->dev), host); 1149 if (ret) 1150 goto err_init_clk; 1151 1152 mmc->caps |= MMC_CAP_CMD23; 1153 if (host->dram_access_quirk) { 1154 /* Limit segments to 1 due to low available sram memory */ 1155 mmc->max_segs = 1; 1156 /* Limit to the available sram memory */ 1157 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 1158 mmc->max_blk_size; 1159 } else { 1160 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1161 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1162 sizeof(struct sd_emmc_desc); 1163 } 1164 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1165 mmc->max_seg_size = mmc->max_req_size; 1166 1167 /* 1168 * At the moment, we don't know how to reliably enable HS400. 1169 * From the different datasheets, it is not even clear if this mode 1170 * is officially supported by any of the SoCs 1171 */ 1172 mmc->caps2 &= ~MMC_CAP2_HS400; 1173 1174 if (host->dram_access_quirk) { 1175 /* 1176 * The MMC Controller embeds 1,5KiB of internal SRAM 1177 * that can be used to be used as bounce buffer. 1178 * In the case of the G12A SDIO controller, use these 1179 * instead of the DDR memory 1180 */ 1181 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1182 host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1183 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1184 } else { 1185 /* data bounce buffer */ 1186 host->bounce_buf_size = mmc->max_req_size; 1187 host->bounce_buf = 1188 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1189 &host->bounce_dma_addr, GFP_KERNEL); 1190 if (host->bounce_buf == NULL) { 1191 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1192 ret = -ENOMEM; 1193 goto err_free_irq; 1194 } 1195 } 1196 1197 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1198 &host->descs_dma_addr, GFP_KERNEL); 1199 if (!host->descs) { 1200 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1201 ret = -ENOMEM; 1202 goto err_bounce_buf; 1203 } 1204 1205 mmc->ops = &meson_mmc_ops; 1206 mmc_add_host(mmc); 1207 1208 return 0; 1209 1210 err_bounce_buf: 1211 if (!host->dram_access_quirk) 1212 dma_free_coherent(host->dev, host->bounce_buf_size, 1213 host->bounce_buf, host->bounce_dma_addr); 1214 err_free_irq: 1215 free_irq(host->irq, host); 1216 err_init_clk: 1217 clk_disable_unprepare(host->mmc_clk); 1218 err_core_clk: 1219 clk_disable_unprepare(host->core_clk); 1220 free_host: 1221 mmc_free_host(mmc); 1222 return ret; 1223 } 1224 1225 static int meson_mmc_remove(struct platform_device *pdev) 1226 { 1227 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1228 1229 mmc_remove_host(host->mmc); 1230 1231 /* disable interrupts */ 1232 writel(0, host->regs + SD_EMMC_IRQ_EN); 1233 free_irq(host->irq, host); 1234 1235 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1236 host->descs, host->descs_dma_addr); 1237 1238 if (!host->dram_access_quirk) 1239 dma_free_coherent(host->dev, host->bounce_buf_size, 1240 host->bounce_buf, host->bounce_dma_addr); 1241 1242 clk_disable_unprepare(host->mmc_clk); 1243 clk_disable_unprepare(host->core_clk); 1244 1245 mmc_free_host(host->mmc); 1246 return 0; 1247 } 1248 1249 static const struct meson_mmc_data meson_gx_data = { 1250 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1251 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1252 .always_on = CLK_V2_ALWAYS_ON, 1253 .adjust = SD_EMMC_ADJUST, 1254 }; 1255 1256 static const struct meson_mmc_data meson_axg_data = { 1257 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1258 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1259 .always_on = CLK_V3_ALWAYS_ON, 1260 .adjust = SD_EMMC_V3_ADJUST, 1261 }; 1262 1263 static const struct of_device_id meson_mmc_of_match[] = { 1264 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1265 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1266 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1267 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1268 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1269 {} 1270 }; 1271 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1272 1273 static struct platform_driver meson_mmc_driver = { 1274 .probe = meson_mmc_probe, 1275 .remove = meson_mmc_remove, 1276 .driver = { 1277 .name = DRIVER_NAME, 1278 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1279 .of_match_table = meson_mmc_of_match, 1280 }, 1281 }; 1282 1283 module_platform_driver(meson_mmc_driver); 1284 1285 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1286 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1287 MODULE_LICENSE("GPL v2"); 1288