1 /* 2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Kevin Hilman <khilman@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * The full GNU General Public License is included in this distribution 19 * in the file called COPYING. 20 */ 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/device.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/ioport.h> 28 #include <linux/spinlock.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 #include <linux/io.h> 35 #include <linux/clk.h> 36 #include <linux/clk-provider.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/interrupt.h> 39 #include <linux/bitfield.h> 40 41 #define DRIVER_NAME "meson-gx-mmc" 42 43 #define SD_EMMC_CLOCK 0x0 44 #define CLK_DIV_MASK GENMASK(5, 0) 45 #define CLK_SRC_MASK GENMASK(7, 6) 46 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 47 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 48 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 49 #define CLK_TX_DELAY_MASK GENMASK(19, 16) 50 #define CLK_RX_DELAY_MASK GENMASK(23, 20) 51 #define CLK_DELAY_STEP_PS 200 52 #define CLK_PHASE_STEP 30 53 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) 54 #define CLK_ALWAYS_ON BIT(24) 55 56 #define SD_EMMC_DELAY 0x4 57 #define SD_EMMC_ADJUST 0x8 58 #define SD_EMMC_CALOUT 0x10 59 #define SD_EMMC_START 0x40 60 #define START_DESC_INIT BIT(0) 61 #define START_DESC_BUSY BIT(1) 62 #define START_DESC_ADDR_MASK GENMASK(31, 2) 63 64 #define SD_EMMC_CFG 0x44 65 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 66 #define CFG_BUS_WIDTH_1 0x0 67 #define CFG_BUS_WIDTH_4 0x1 68 #define CFG_BUS_WIDTH_8 0x2 69 #define CFG_DDR BIT(2) 70 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 71 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 72 #define CFG_RC_CC_MASK GENMASK(15, 12) 73 #define CFG_STOP_CLOCK BIT(22) 74 #define CFG_CLK_ALWAYS_ON BIT(18) 75 #define CFG_CHK_DS BIT(20) 76 #define CFG_AUTO_CLK BIT(23) 77 78 #define SD_EMMC_STATUS 0x48 79 #define STATUS_BUSY BIT(31) 80 #define STATUS_DATI GENMASK(23, 16) 81 82 #define SD_EMMC_IRQ_EN 0x4c 83 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 84 #define IRQ_TXD_ERR BIT(8) 85 #define IRQ_DESC_ERR BIT(9) 86 #define IRQ_RESP_ERR BIT(10) 87 #define IRQ_CRC_ERR \ 88 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 89 #define IRQ_RESP_TIMEOUT BIT(11) 90 #define IRQ_DESC_TIMEOUT BIT(12) 91 #define IRQ_TIMEOUTS \ 92 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 93 #define IRQ_END_OF_CHAIN BIT(13) 94 #define IRQ_RESP_STATUS BIT(14) 95 #define IRQ_SDIO BIT(15) 96 #define IRQ_EN_MASK \ 97 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 98 IRQ_SDIO) 99 100 #define SD_EMMC_CMD_CFG 0x50 101 #define SD_EMMC_CMD_ARG 0x54 102 #define SD_EMMC_CMD_DAT 0x58 103 #define SD_EMMC_CMD_RSP 0x5c 104 #define SD_EMMC_CMD_RSP1 0x60 105 #define SD_EMMC_CMD_RSP2 0x64 106 #define SD_EMMC_CMD_RSP3 0x68 107 108 #define SD_EMMC_RXD 0x94 109 #define SD_EMMC_TXD 0x94 110 #define SD_EMMC_LAST_REG SD_EMMC_TXD 111 112 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 113 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 114 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 115 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 116 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 117 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 118 119 #define SD_EMMC_PRE_REQ_DONE BIT(0) 120 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 121 122 #define MUX_CLK_NUM_PARENTS 2 123 124 struct sd_emmc_desc { 125 u32 cmd_cfg; 126 u32 cmd_arg; 127 u32 cmd_data; 128 u32 cmd_resp; 129 }; 130 131 struct meson_host { 132 struct device *dev; 133 struct mmc_host *mmc; 134 struct mmc_command *cmd; 135 136 spinlock_t lock; 137 void __iomem *regs; 138 struct clk *core_clk; 139 struct clk *mmc_clk; 140 struct clk *rx_clk; 141 struct clk *tx_clk; 142 unsigned long req_rate; 143 144 struct pinctrl *pinctrl; 145 struct pinctrl_state *pins_default; 146 struct pinctrl_state *pins_clk_gate; 147 148 unsigned int bounce_buf_size; 149 void *bounce_buf; 150 dma_addr_t bounce_dma_addr; 151 struct sd_emmc_desc *descs; 152 dma_addr_t descs_dma_addr; 153 154 bool vqmmc_enabled; 155 }; 156 157 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 158 #define CMD_CFG_BLOCK_MODE BIT(9) 159 #define CMD_CFG_R1B BIT(10) 160 #define CMD_CFG_END_OF_CHAIN BIT(11) 161 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 162 #define CMD_CFG_NO_RESP BIT(16) 163 #define CMD_CFG_NO_CMD BIT(17) 164 #define CMD_CFG_DATA_IO BIT(18) 165 #define CMD_CFG_DATA_WR BIT(19) 166 #define CMD_CFG_RESP_NOCRC BIT(20) 167 #define CMD_CFG_RESP_128 BIT(21) 168 #define CMD_CFG_RESP_NUM BIT(22) 169 #define CMD_CFG_DATA_NUM BIT(23) 170 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 171 #define CMD_CFG_ERROR BIT(30) 172 #define CMD_CFG_OWNER BIT(31) 173 174 #define CMD_DATA_MASK GENMASK(31, 2) 175 #define CMD_DATA_BIG_ENDIAN BIT(1) 176 #define CMD_DATA_SRAM BIT(0) 177 #define CMD_RESP_MASK GENMASK(31, 1) 178 #define CMD_RESP_SRAM BIT(0) 179 180 struct meson_mmc_phase { 181 struct clk_hw hw; 182 void __iomem *reg; 183 unsigned long phase_mask; 184 unsigned long delay_mask; 185 unsigned int delay_step_ps; 186 }; 187 188 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw) 189 190 static int meson_mmc_clk_get_phase(struct clk_hw *hw) 191 { 192 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); 193 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); 194 unsigned long period_ps, p, d; 195 int degrees; 196 u32 val; 197 198 val = readl(mmc->reg); 199 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask); 200 degrees = p * 360 / phase_num; 201 202 if (mmc->delay_mask) { 203 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, 204 clk_get_rate(hw->clk)); 205 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask); 206 degrees += d * mmc->delay_step_ps * 360 / period_ps; 207 degrees %= 360; 208 } 209 210 return degrees; 211 } 212 213 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc, 214 unsigned int phase, 215 unsigned int delay) 216 { 217 u32 val; 218 219 val = readl(mmc->reg); 220 val &= ~mmc->phase_mask; 221 val |= phase << __ffs(mmc->phase_mask); 222 223 if (mmc->delay_mask) { 224 val &= ~mmc->delay_mask; 225 val |= delay << __ffs(mmc->delay_mask); 226 } 227 228 writel(val, mmc->reg); 229 } 230 231 static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees) 232 { 233 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); 234 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); 235 unsigned long period_ps, d = 0, r; 236 uint64_t p; 237 238 p = degrees % 360; 239 240 if (!mmc->delay_mask) { 241 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); 242 } else { 243 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, 244 clk_get_rate(hw->clk)); 245 246 /* First compute the phase index (p), the remainder (r) is the 247 * part we'll try to acheive using the delays (d). 248 */ 249 r = do_div(p, 360 / phase_num); 250 d = DIV_ROUND_CLOSEST(r * period_ps, 251 360 * mmc->delay_step_ps); 252 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask)); 253 } 254 255 meson_mmc_apply_phase_delay(mmc, p, d); 256 return 0; 257 } 258 259 static const struct clk_ops meson_mmc_clk_phase_ops = { 260 .get_phase = meson_mmc_clk_get_phase, 261 .set_phase = meson_mmc_clk_set_phase, 262 }; 263 264 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 265 { 266 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 267 268 if (!timeout) 269 return SD_EMMC_CMD_TIMEOUT_DATA; 270 271 timeout = roundup_pow_of_two(timeout); 272 273 return min(timeout, 32768U); /* max. 2^15 ms */ 274 } 275 276 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 277 { 278 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 279 return cmd->mrq->cmd; 280 else if (mmc_op_multi(cmd->opcode) && 281 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 282 return cmd->mrq->stop; 283 else 284 return NULL; 285 } 286 287 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 288 struct mmc_request *mrq) 289 { 290 struct mmc_data *data = mrq->data; 291 struct scatterlist *sg; 292 int i; 293 bool use_desc_chain_mode = true; 294 295 /* 296 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 297 * reported. For some strange reason this occurs in descriptor 298 * chain mode only. So let's fall back to bounce buffer mode 299 * for command SD_IO_RW_EXTENDED. 300 */ 301 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 302 return; 303 304 for_each_sg(data->sg, sg, data->sg_len, i) 305 /* check for 8 byte alignment */ 306 if (sg->offset & 7) { 307 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 308 use_desc_chain_mode = false; 309 break; 310 } 311 312 if (use_desc_chain_mode) 313 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 314 } 315 316 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 317 { 318 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 319 } 320 321 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 322 { 323 return data && data->flags & MMC_DATA_READ && 324 !meson_mmc_desc_chain_mode(data); 325 } 326 327 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 328 { 329 struct mmc_data *data = mrq->data; 330 331 if (!data) 332 return; 333 334 meson_mmc_get_transfer_mode(mmc, mrq); 335 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 336 337 if (!meson_mmc_desc_chain_mode(data)) 338 return; 339 340 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 341 mmc_get_dma_dir(data)); 342 if (!data->sg_count) 343 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 344 } 345 346 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 347 int err) 348 { 349 struct mmc_data *data = mrq->data; 350 351 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 352 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 353 mmc_get_dma_dir(data)); 354 } 355 356 static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) 357 { 358 if (ios->timing == MMC_TIMING_MMC_DDR52 || 359 ios->timing == MMC_TIMING_UHS_DDR50 || 360 ios->timing == MMC_TIMING_MMC_HS400) 361 return true; 362 363 return false; 364 } 365 366 /* 367 * Gating the clock on this controller is tricky. It seems the mmc clock 368 * is also used by the controller. It may crash during some operation if the 369 * clock is stopped. The safest thing to do, whenever possible, is to keep 370 * clock running at stop it at the pad using the pinmux. 371 */ 372 static void meson_mmc_clk_gate(struct meson_host *host) 373 { 374 u32 cfg; 375 376 if (host->pins_clk_gate) { 377 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 378 } else { 379 /* 380 * If the pinmux is not provided - default to the classic and 381 * unsafe method 382 */ 383 cfg = readl(host->regs + SD_EMMC_CFG); 384 cfg |= CFG_STOP_CLOCK; 385 writel(cfg, host->regs + SD_EMMC_CFG); 386 } 387 } 388 389 static void meson_mmc_clk_ungate(struct meson_host *host) 390 { 391 u32 cfg; 392 393 if (host->pins_clk_gate) 394 pinctrl_select_state(host->pinctrl, host->pins_default); 395 396 /* Make sure the clock is not stopped in the controller */ 397 cfg = readl(host->regs + SD_EMMC_CFG); 398 cfg &= ~CFG_STOP_CLOCK; 399 writel(cfg, host->regs + SD_EMMC_CFG); 400 } 401 402 static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) 403 { 404 struct mmc_host *mmc = host->mmc; 405 unsigned long rate = ios->clock; 406 int ret; 407 u32 cfg; 408 409 /* DDR modes require higher module clock */ 410 if (meson_mmc_timing_is_ddr(ios)) 411 rate <<= 1; 412 413 /* Same request - bail-out */ 414 if (host->req_rate == rate) 415 return 0; 416 417 /* stop clock */ 418 meson_mmc_clk_gate(host); 419 host->req_rate = 0; 420 421 if (!rate) { 422 mmc->actual_clock = 0; 423 /* return with clock being stopped */ 424 return 0; 425 } 426 427 /* Stop the clock during rate change to avoid glitches */ 428 cfg = readl(host->regs + SD_EMMC_CFG); 429 cfg |= CFG_STOP_CLOCK; 430 writel(cfg, host->regs + SD_EMMC_CFG); 431 432 ret = clk_set_rate(host->mmc_clk, rate); 433 if (ret) { 434 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 435 rate, ret); 436 return ret; 437 } 438 439 host->req_rate = rate; 440 mmc->actual_clock = clk_get_rate(host->mmc_clk); 441 442 /* We should report the real output frequency of the controller */ 443 if (meson_mmc_timing_is_ddr(ios)) 444 mmc->actual_clock >>= 1; 445 446 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 447 if (ios->clock != mmc->actual_clock) 448 dev_dbg(host->dev, "requested rate was %u\n", ios->clock); 449 450 /* (re)start clock */ 451 meson_mmc_clk_ungate(host); 452 453 return 0; 454 } 455 456 /* 457 * The SD/eMMC IP block has an internal mux and divider used for 458 * generating the MMC clock. Use the clock framework to create and 459 * manage these clocks. 460 */ 461 static int meson_mmc_clk_init(struct meson_host *host) 462 { 463 struct clk_init_data init; 464 struct clk_mux *mux; 465 struct clk_divider *div; 466 struct meson_mmc_phase *core, *tx, *rx; 467 struct clk *clk; 468 char clk_name[32]; 469 int i, ret = 0; 470 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 471 const char *clk_parent[1]; 472 u32 clk_reg; 473 474 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 475 clk_reg = 0; 476 clk_reg |= CLK_ALWAYS_ON; 477 clk_reg |= CLK_DIV_MASK; 478 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 479 480 /* get the mux parents */ 481 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 482 struct clk *clk; 483 char name[16]; 484 485 snprintf(name, sizeof(name), "clkin%d", i); 486 clk = devm_clk_get(host->dev, name); 487 if (IS_ERR(clk)) { 488 if (clk != ERR_PTR(-EPROBE_DEFER)) 489 dev_err(host->dev, "Missing clock %s\n", name); 490 return PTR_ERR(clk); 491 } 492 493 mux_parent_names[i] = __clk_get_name(clk); 494 } 495 496 /* create the mux */ 497 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 498 if (!mux) 499 return -ENOMEM; 500 501 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 502 init.name = clk_name; 503 init.ops = &clk_mux_ops; 504 init.flags = 0; 505 init.parent_names = mux_parent_names; 506 init.num_parents = MUX_CLK_NUM_PARENTS; 507 508 mux->reg = host->regs + SD_EMMC_CLOCK; 509 mux->shift = __ffs(CLK_SRC_MASK); 510 mux->mask = CLK_SRC_MASK >> mux->shift; 511 mux->hw.init = &init; 512 513 clk = devm_clk_register(host->dev, &mux->hw); 514 if (WARN_ON(IS_ERR(clk))) 515 return PTR_ERR(clk); 516 517 /* create the divider */ 518 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 519 if (!div) 520 return -ENOMEM; 521 522 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 523 init.name = clk_name; 524 init.ops = &clk_divider_ops; 525 init.flags = CLK_SET_RATE_PARENT; 526 clk_parent[0] = __clk_get_name(clk); 527 init.parent_names = clk_parent; 528 init.num_parents = 1; 529 530 div->reg = host->regs + SD_EMMC_CLOCK; 531 div->shift = __ffs(CLK_DIV_MASK); 532 div->width = __builtin_popcountl(CLK_DIV_MASK); 533 div->hw.init = &init; 534 div->flags = (CLK_DIVIDER_ONE_BASED | 535 CLK_DIVIDER_ROUND_CLOSEST); 536 537 clk = devm_clk_register(host->dev, &div->hw); 538 if (WARN_ON(IS_ERR(clk))) 539 return PTR_ERR(clk); 540 541 /* create the mmc core clock */ 542 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL); 543 if (!core) 544 return -ENOMEM; 545 546 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev)); 547 init.name = clk_name; 548 init.ops = &meson_mmc_clk_phase_ops; 549 init.flags = CLK_SET_RATE_PARENT; 550 clk_parent[0] = __clk_get_name(clk); 551 init.parent_names = clk_parent; 552 init.num_parents = 1; 553 554 core->reg = host->regs + SD_EMMC_CLOCK; 555 core->phase_mask = CLK_CORE_PHASE_MASK; 556 core->hw.init = &init; 557 558 host->mmc_clk = devm_clk_register(host->dev, &core->hw); 559 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) 560 return PTR_ERR(host->mmc_clk); 561 562 /* create the mmc tx clock */ 563 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL); 564 if (!tx) 565 return -ENOMEM; 566 567 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev)); 568 init.name = clk_name; 569 init.ops = &meson_mmc_clk_phase_ops; 570 init.flags = 0; 571 clk_parent[0] = __clk_get_name(host->mmc_clk); 572 init.parent_names = clk_parent; 573 init.num_parents = 1; 574 575 tx->reg = host->regs + SD_EMMC_CLOCK; 576 tx->phase_mask = CLK_TX_PHASE_MASK; 577 tx->delay_mask = CLK_TX_DELAY_MASK; 578 tx->delay_step_ps = CLK_DELAY_STEP_PS; 579 tx->hw.init = &init; 580 581 host->tx_clk = devm_clk_register(host->dev, &tx->hw); 582 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk))) 583 return PTR_ERR(host->tx_clk); 584 585 /* create the mmc rx clock */ 586 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL); 587 if (!rx) 588 return -ENOMEM; 589 590 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev)); 591 init.name = clk_name; 592 init.ops = &meson_mmc_clk_phase_ops; 593 init.flags = 0; 594 clk_parent[0] = __clk_get_name(host->mmc_clk); 595 init.parent_names = clk_parent; 596 init.num_parents = 1; 597 598 rx->reg = host->regs + SD_EMMC_CLOCK; 599 rx->phase_mask = CLK_RX_PHASE_MASK; 600 rx->delay_mask = CLK_RX_DELAY_MASK; 601 rx->delay_step_ps = CLK_DELAY_STEP_PS; 602 rx->hw.init = &init; 603 604 host->rx_clk = devm_clk_register(host->dev, &rx->hw); 605 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) 606 return PTR_ERR(host->rx_clk); 607 608 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 609 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 610 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 611 if (ret) 612 return ret; 613 614 /* 615 * Set phases : These values are mostly the datasheet recommended ones 616 * except for the Tx phase. Datasheet recommends 180 but some cards 617 * fail at initialisation with it. 270 works just fine, it fixes these 618 * initialisation issues and enable eMMC DDR52 mode. 619 */ 620 clk_set_phase(host->mmc_clk, 180); 621 clk_set_phase(host->tx_clk, 270); 622 clk_set_phase(host->rx_clk, 0); 623 624 return clk_prepare_enable(host->mmc_clk); 625 } 626 627 static void meson_mmc_shift_map(unsigned long *map, unsigned long shift) 628 { 629 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM); 630 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM); 631 632 /* 633 * shift the bitmap right and reintroduce the dropped bits on the left 634 * of the bitmap 635 */ 636 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM); 637 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift, 638 CLK_PHASE_POINT_NUM); 639 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM); 640 } 641 642 static void meson_mmc_find_next_region(unsigned long *map, 643 unsigned long *start, 644 unsigned long *stop) 645 { 646 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start); 647 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start); 648 } 649 650 static int meson_mmc_find_tuning_point(unsigned long *test) 651 { 652 unsigned long shift, stop, offset = 0, start = 0, size = 0; 653 654 /* Get the all good/all bad situation out the way */ 655 if (bitmap_full(test, CLK_PHASE_POINT_NUM)) 656 return 0; /* All points are good so point 0 will do */ 657 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM)) 658 return -EIO; /* No successful tuning point */ 659 660 /* 661 * Now we know there is a least one region find. Make sure it does 662 * not wrap by the shifting the bitmap if necessary 663 */ 664 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM); 665 if (shift != 0) 666 meson_mmc_shift_map(test, shift); 667 668 while (start < CLK_PHASE_POINT_NUM) { 669 meson_mmc_find_next_region(test, &start, &stop); 670 671 if ((stop - start) > size) { 672 offset = start; 673 size = stop - start; 674 } 675 676 start = stop; 677 } 678 679 /* Get the center point of the region */ 680 offset += (size / 2); 681 682 /* Shift the result back */ 683 offset = (offset + shift) % CLK_PHASE_POINT_NUM; 684 685 return offset; 686 } 687 688 static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, 689 struct clk *clk) 690 { 691 int point, ret; 692 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM); 693 694 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n", 695 __clk_get_name(clk)); 696 bitmap_zero(test, CLK_PHASE_POINT_NUM); 697 698 /* Explore tuning points */ 699 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) { 700 clk_set_phase(clk, point * CLK_PHASE_STEP); 701 ret = mmc_send_tuning(mmc, opcode, NULL); 702 if (!ret) 703 set_bit(point, test); 704 } 705 706 /* Find the optimal tuning point and apply it */ 707 point = meson_mmc_find_tuning_point(test); 708 if (point < 0) 709 return point; /* tuning failed */ 710 711 clk_set_phase(clk, point * CLK_PHASE_STEP); 712 dev_dbg(mmc_dev(mmc), "success with phase: %d\n", 713 clk_get_phase(clk)); 714 return 0; 715 } 716 717 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 718 { 719 struct meson_host *host = mmc_priv(mmc); 720 721 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); 722 } 723 724 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 725 { 726 struct meson_host *host = mmc_priv(mmc); 727 u32 bus_width, val; 728 int err; 729 730 /* 731 * GPIO regulator, only controls switching between 1v8 and 732 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 733 */ 734 switch (ios->power_mode) { 735 case MMC_POWER_OFF: 736 if (!IS_ERR(mmc->supply.vmmc)) 737 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 738 739 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 740 regulator_disable(mmc->supply.vqmmc); 741 host->vqmmc_enabled = false; 742 } 743 744 break; 745 746 case MMC_POWER_UP: 747 if (!IS_ERR(mmc->supply.vmmc)) 748 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 749 break; 750 751 case MMC_POWER_ON: 752 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 753 int ret = regulator_enable(mmc->supply.vqmmc); 754 755 if (ret < 0) 756 dev_err(host->dev, 757 "failed to enable vqmmc regulator\n"); 758 else 759 host->vqmmc_enabled = true; 760 } 761 762 /* Reset rx phase */ 763 clk_set_phase(host->rx_clk, 0); 764 break; 765 } 766 767 /* Bus width */ 768 switch (ios->bus_width) { 769 case MMC_BUS_WIDTH_1: 770 bus_width = CFG_BUS_WIDTH_1; 771 break; 772 case MMC_BUS_WIDTH_4: 773 bus_width = CFG_BUS_WIDTH_4; 774 break; 775 case MMC_BUS_WIDTH_8: 776 bus_width = CFG_BUS_WIDTH_8; 777 break; 778 default: 779 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 780 ios->bus_width); 781 bus_width = CFG_BUS_WIDTH_4; 782 } 783 784 val = readl(host->regs + SD_EMMC_CFG); 785 val &= ~CFG_BUS_WIDTH_MASK; 786 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 787 788 val &= ~CFG_DDR; 789 if (meson_mmc_timing_is_ddr(ios)) 790 val |= CFG_DDR; 791 792 val &= ~CFG_CHK_DS; 793 if (ios->timing == MMC_TIMING_MMC_HS400) 794 val |= CFG_CHK_DS; 795 796 err = meson_mmc_clk_set(host, ios); 797 if (err) 798 dev_err(host->dev, "Failed to set clock: %d\n,", err); 799 800 writel(val, host->regs + SD_EMMC_CFG); 801 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 802 } 803 804 static void meson_mmc_request_done(struct mmc_host *mmc, 805 struct mmc_request *mrq) 806 { 807 struct meson_host *host = mmc_priv(mmc); 808 809 host->cmd = NULL; 810 mmc_request_done(host->mmc, mrq); 811 } 812 813 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 814 { 815 struct meson_host *host = mmc_priv(mmc); 816 u32 cfg, blksz_old; 817 818 cfg = readl(host->regs + SD_EMMC_CFG); 819 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 820 821 if (!is_power_of_2(blksz)) 822 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 823 824 blksz = ilog2(blksz); 825 826 /* check if block-size matches, if not update */ 827 if (blksz == blksz_old) 828 return; 829 830 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 831 blksz_old, blksz); 832 833 cfg &= ~CFG_BLK_LEN_MASK; 834 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 835 writel(cfg, host->regs + SD_EMMC_CFG); 836 } 837 838 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 839 { 840 if (cmd->flags & MMC_RSP_PRESENT) { 841 if (cmd->flags & MMC_RSP_136) 842 *cmd_cfg |= CMD_CFG_RESP_128; 843 *cmd_cfg |= CMD_CFG_RESP_NUM; 844 845 if (!(cmd->flags & MMC_RSP_CRC)) 846 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 847 848 if (cmd->flags & MMC_RSP_BUSY) 849 *cmd_cfg |= CMD_CFG_R1B; 850 } else { 851 *cmd_cfg |= CMD_CFG_NO_RESP; 852 } 853 } 854 855 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 856 { 857 struct meson_host *host = mmc_priv(mmc); 858 struct sd_emmc_desc *desc = host->descs; 859 struct mmc_data *data = host->cmd->data; 860 struct scatterlist *sg; 861 u32 start; 862 int i; 863 864 if (data->flags & MMC_DATA_WRITE) 865 cmd_cfg |= CMD_CFG_DATA_WR; 866 867 if (data->blocks > 1) { 868 cmd_cfg |= CMD_CFG_BLOCK_MODE; 869 meson_mmc_set_blksz(mmc, data->blksz); 870 } 871 872 for_each_sg(data->sg, sg, data->sg_count, i) { 873 unsigned int len = sg_dma_len(sg); 874 875 if (data->blocks > 1) 876 len /= data->blksz; 877 878 desc[i].cmd_cfg = cmd_cfg; 879 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 880 if (i > 0) 881 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 882 desc[i].cmd_arg = host->cmd->arg; 883 desc[i].cmd_resp = 0; 884 desc[i].cmd_data = sg_dma_address(sg); 885 } 886 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 887 888 dma_wmb(); /* ensure descriptor is written before kicked */ 889 start = host->descs_dma_addr | START_DESC_BUSY; 890 writel(start, host->regs + SD_EMMC_START); 891 } 892 893 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 894 { 895 struct meson_host *host = mmc_priv(mmc); 896 struct mmc_data *data = cmd->data; 897 u32 cmd_cfg = 0, cmd_data = 0; 898 unsigned int xfer_bytes = 0; 899 900 /* Setup descriptors */ 901 dma_rmb(); 902 903 host->cmd = cmd; 904 905 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 906 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 907 908 meson_mmc_set_response_bits(cmd, &cmd_cfg); 909 910 /* data? */ 911 if (data) { 912 data->bytes_xfered = 0; 913 cmd_cfg |= CMD_CFG_DATA_IO; 914 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 915 ilog2(meson_mmc_get_timeout_msecs(data))); 916 917 if (meson_mmc_desc_chain_mode(data)) { 918 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 919 return; 920 } 921 922 if (data->blocks > 1) { 923 cmd_cfg |= CMD_CFG_BLOCK_MODE; 924 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 925 data->blocks); 926 meson_mmc_set_blksz(mmc, data->blksz); 927 } else { 928 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 929 } 930 931 xfer_bytes = data->blksz * data->blocks; 932 if (data->flags & MMC_DATA_WRITE) { 933 cmd_cfg |= CMD_CFG_DATA_WR; 934 WARN_ON(xfer_bytes > host->bounce_buf_size); 935 sg_copy_to_buffer(data->sg, data->sg_len, 936 host->bounce_buf, xfer_bytes); 937 dma_wmb(); 938 } 939 940 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 941 } else { 942 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 943 ilog2(SD_EMMC_CMD_TIMEOUT)); 944 } 945 946 /* Last descriptor */ 947 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 948 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 949 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 950 writel(0, host->regs + SD_EMMC_CMD_RSP); 951 wmb(); /* ensure descriptor is written before kicked */ 952 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 953 } 954 955 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 956 { 957 struct meson_host *host = mmc_priv(mmc); 958 bool needs_pre_post_req = mrq->data && 959 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 960 961 if (needs_pre_post_req) { 962 meson_mmc_get_transfer_mode(mmc, mrq); 963 if (!meson_mmc_desc_chain_mode(mrq->data)) 964 needs_pre_post_req = false; 965 } 966 967 if (needs_pre_post_req) 968 meson_mmc_pre_req(mmc, mrq); 969 970 /* Stop execution */ 971 writel(0, host->regs + SD_EMMC_START); 972 973 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 974 975 if (needs_pre_post_req) 976 meson_mmc_post_req(mmc, mrq, 0); 977 } 978 979 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 980 { 981 struct meson_host *host = mmc_priv(mmc); 982 983 if (cmd->flags & MMC_RSP_136) { 984 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 985 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 986 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 987 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 988 } else if (cmd->flags & MMC_RSP_PRESENT) { 989 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 990 } 991 } 992 993 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 994 { 995 struct meson_host *host = dev_id; 996 struct mmc_command *cmd; 997 struct mmc_data *data; 998 u32 irq_en, status, raw_status; 999 irqreturn_t ret = IRQ_NONE; 1000 1001 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 1002 return IRQ_NONE; 1003 1004 spin_lock(&host->lock); 1005 1006 cmd = host->cmd; 1007 data = cmd->data; 1008 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 1009 raw_status = readl(host->regs + SD_EMMC_STATUS); 1010 status = raw_status & irq_en; 1011 1012 cmd->error = 0; 1013 if (status & IRQ_CRC_ERR) { 1014 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 1015 cmd->error = -EILSEQ; 1016 ret = IRQ_HANDLED; 1017 goto out; 1018 } 1019 1020 if (status & IRQ_TIMEOUTS) { 1021 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 1022 cmd->error = -ETIMEDOUT; 1023 ret = IRQ_HANDLED; 1024 goto out; 1025 } 1026 1027 meson_mmc_read_resp(host->mmc, cmd); 1028 1029 if (status & IRQ_SDIO) { 1030 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 1031 ret = IRQ_HANDLED; 1032 } 1033 1034 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 1035 if (data && !cmd->error) 1036 data->bytes_xfered = data->blksz * data->blocks; 1037 if (meson_mmc_bounce_buf_read(data) || 1038 meson_mmc_get_next_command(cmd)) 1039 ret = IRQ_WAKE_THREAD; 1040 else 1041 ret = IRQ_HANDLED; 1042 } 1043 1044 out: 1045 /* ack all enabled interrupts */ 1046 writel(irq_en, host->regs + SD_EMMC_STATUS); 1047 1048 if (ret == IRQ_HANDLED) 1049 meson_mmc_request_done(host->mmc, cmd->mrq); 1050 else if (ret == IRQ_NONE) 1051 dev_warn(host->dev, 1052 "Unexpected IRQ! status=0x%08x, irq_en=0x%08x\n", 1053 raw_status, irq_en); 1054 1055 spin_unlock(&host->lock); 1056 return ret; 1057 } 1058 1059 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 1060 { 1061 struct meson_host *host = dev_id; 1062 struct mmc_command *next_cmd, *cmd = host->cmd; 1063 struct mmc_data *data; 1064 unsigned int xfer_bytes; 1065 1066 if (WARN_ON(!cmd)) 1067 return IRQ_NONE; 1068 1069 data = cmd->data; 1070 if (meson_mmc_bounce_buf_read(data)) { 1071 xfer_bytes = data->blksz * data->blocks; 1072 WARN_ON(xfer_bytes > host->bounce_buf_size); 1073 sg_copy_from_buffer(data->sg, data->sg_len, 1074 host->bounce_buf, xfer_bytes); 1075 } 1076 1077 next_cmd = meson_mmc_get_next_command(cmd); 1078 if (next_cmd) 1079 meson_mmc_start_cmd(host->mmc, next_cmd); 1080 else 1081 meson_mmc_request_done(host->mmc, cmd->mrq); 1082 1083 return IRQ_HANDLED; 1084 } 1085 1086 /* 1087 * NOTE: we only need this until the GPIO/pinctrl driver can handle 1088 * interrupts. For now, the MMC core will use this for polling. 1089 */ 1090 static int meson_mmc_get_cd(struct mmc_host *mmc) 1091 { 1092 int status = mmc_gpio_get_cd(mmc); 1093 1094 if (status == -ENOSYS) 1095 return 1; /* assume present */ 1096 1097 return status; 1098 } 1099 1100 static void meson_mmc_cfg_init(struct meson_host *host) 1101 { 1102 u32 cfg = 0; 1103 1104 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 1105 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 1106 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 1107 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 1108 1109 writel(cfg, host->regs + SD_EMMC_CFG); 1110 } 1111 1112 static int meson_mmc_card_busy(struct mmc_host *mmc) 1113 { 1114 struct meson_host *host = mmc_priv(mmc); 1115 u32 regval; 1116 1117 regval = readl(host->regs + SD_EMMC_STATUS); 1118 1119 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1120 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1121 } 1122 1123 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1124 { 1125 /* vqmmc regulator is available */ 1126 if (!IS_ERR(mmc->supply.vqmmc)) { 1127 /* 1128 * The usual amlogic setup uses a GPIO to switch from one 1129 * regulator to the other. While the voltage ramp up is 1130 * pretty fast, care must be taken when switching from 3.3v 1131 * to 1.8v. Please make sure the regulator framework is aware 1132 * of your own regulator constraints 1133 */ 1134 return mmc_regulator_set_vqmmc(mmc, ios); 1135 } 1136 1137 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1138 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1139 return 0; 1140 1141 return -EINVAL; 1142 } 1143 1144 static const struct mmc_host_ops meson_mmc_ops = { 1145 .request = meson_mmc_request, 1146 .set_ios = meson_mmc_set_ios, 1147 .get_cd = meson_mmc_get_cd, 1148 .pre_req = meson_mmc_pre_req, 1149 .post_req = meson_mmc_post_req, 1150 .execute_tuning = meson_mmc_execute_tuning, 1151 .card_busy = meson_mmc_card_busy, 1152 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1153 }; 1154 1155 static int meson_mmc_probe(struct platform_device *pdev) 1156 { 1157 struct resource *res; 1158 struct meson_host *host; 1159 struct mmc_host *mmc; 1160 int ret, irq; 1161 1162 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1163 if (!mmc) 1164 return -ENOMEM; 1165 host = mmc_priv(mmc); 1166 host->mmc = mmc; 1167 host->dev = &pdev->dev; 1168 dev_set_drvdata(&pdev->dev, host); 1169 1170 spin_lock_init(&host->lock); 1171 1172 /* Get regulators and the supported OCR mask */ 1173 host->vqmmc_enabled = false; 1174 ret = mmc_regulator_get_supply(mmc); 1175 if (ret == -EPROBE_DEFER) 1176 goto free_host; 1177 1178 ret = mmc_of_parse(mmc); 1179 if (ret) { 1180 if (ret != -EPROBE_DEFER) 1181 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1182 goto free_host; 1183 } 1184 1185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1186 host->regs = devm_ioremap_resource(&pdev->dev, res); 1187 if (IS_ERR(host->regs)) { 1188 ret = PTR_ERR(host->regs); 1189 goto free_host; 1190 } 1191 1192 irq = platform_get_irq(pdev, 0); 1193 if (!irq) { 1194 dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 1195 ret = -EINVAL; 1196 goto free_host; 1197 } 1198 1199 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1200 if (IS_ERR(host->pinctrl)) { 1201 ret = PTR_ERR(host->pinctrl); 1202 goto free_host; 1203 } 1204 1205 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1206 PINCTRL_STATE_DEFAULT); 1207 if (IS_ERR(host->pins_default)) { 1208 ret = PTR_ERR(host->pins_default); 1209 goto free_host; 1210 } 1211 1212 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1213 "clk-gate"); 1214 if (IS_ERR(host->pins_clk_gate)) { 1215 dev_warn(&pdev->dev, 1216 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1217 host->pins_clk_gate = NULL; 1218 } 1219 1220 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1221 if (IS_ERR(host->core_clk)) { 1222 ret = PTR_ERR(host->core_clk); 1223 goto free_host; 1224 } 1225 1226 ret = clk_prepare_enable(host->core_clk); 1227 if (ret) 1228 goto free_host; 1229 1230 ret = meson_mmc_clk_init(host); 1231 if (ret) 1232 goto err_core_clk; 1233 1234 /* set config to sane default */ 1235 meson_mmc_cfg_init(host); 1236 1237 /* Stop execution */ 1238 writel(0, host->regs + SD_EMMC_START); 1239 1240 /* clear, ack and enable interrupts */ 1241 writel(0, host->regs + SD_EMMC_IRQ_EN); 1242 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1243 host->regs + SD_EMMC_STATUS); 1244 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1245 host->regs + SD_EMMC_IRQ_EN); 1246 1247 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq, 1248 meson_mmc_irq_thread, IRQF_SHARED, 1249 NULL, host); 1250 if (ret) 1251 goto err_init_clk; 1252 1253 mmc->caps |= MMC_CAP_CMD23; 1254 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1255 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1256 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); 1257 mmc->max_seg_size = mmc->max_req_size; 1258 1259 /* data bounce buffer */ 1260 host->bounce_buf_size = mmc->max_req_size; 1261 host->bounce_buf = 1262 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1263 &host->bounce_dma_addr, GFP_KERNEL); 1264 if (host->bounce_buf == NULL) { 1265 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1266 ret = -ENOMEM; 1267 goto err_init_clk; 1268 } 1269 1270 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1271 &host->descs_dma_addr, GFP_KERNEL); 1272 if (!host->descs) { 1273 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1274 ret = -ENOMEM; 1275 goto err_bounce_buf; 1276 } 1277 1278 mmc->ops = &meson_mmc_ops; 1279 mmc_add_host(mmc); 1280 1281 return 0; 1282 1283 err_bounce_buf: 1284 dma_free_coherent(host->dev, host->bounce_buf_size, 1285 host->bounce_buf, host->bounce_dma_addr); 1286 err_init_clk: 1287 clk_disable_unprepare(host->mmc_clk); 1288 err_core_clk: 1289 clk_disable_unprepare(host->core_clk); 1290 free_host: 1291 mmc_free_host(mmc); 1292 return ret; 1293 } 1294 1295 static int meson_mmc_remove(struct platform_device *pdev) 1296 { 1297 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1298 1299 mmc_remove_host(host->mmc); 1300 1301 /* disable interrupts */ 1302 writel(0, host->regs + SD_EMMC_IRQ_EN); 1303 1304 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1305 host->descs, host->descs_dma_addr); 1306 dma_free_coherent(host->dev, host->bounce_buf_size, 1307 host->bounce_buf, host->bounce_dma_addr); 1308 1309 clk_disable_unprepare(host->mmc_clk); 1310 clk_disable_unprepare(host->core_clk); 1311 1312 mmc_free_host(host->mmc); 1313 return 0; 1314 } 1315 1316 static const struct of_device_id meson_mmc_of_match[] = { 1317 { .compatible = "amlogic,meson-gx-mmc", }, 1318 { .compatible = "amlogic,meson-gxbb-mmc", }, 1319 { .compatible = "amlogic,meson-gxl-mmc", }, 1320 { .compatible = "amlogic,meson-gxm-mmc", }, 1321 {} 1322 }; 1323 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1324 1325 static struct platform_driver meson_mmc_driver = { 1326 .probe = meson_mmc_probe, 1327 .remove = meson_mmc_remove, 1328 .driver = { 1329 .name = DRIVER_NAME, 1330 .of_match_table = of_match_ptr(meson_mmc_of_match), 1331 }, 1332 }; 1333 1334 module_platform_driver(meson_mmc_driver); 1335 1336 MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver"); 1337 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1338 MODULE_LICENSE("GPL v2"); 1339