1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ioport.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/slot-gpio.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitfield.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "meson-gx-mmc" 32 33 #define SD_EMMC_CLOCK 0x0 34 #define CLK_DIV_MASK GENMASK(5, 0) 35 #define CLK_SRC_MASK GENMASK(7, 6) 36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 39 #define CLK_PHASE_0 0 40 #define CLK_PHASE_180 2 41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43 #define CLK_V2_ALWAYS_ON BIT(24) 44 45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 47 #define CLK_V3_ALWAYS_ON BIT(28) 48 49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 51 #define CLK_ALWAYS_ON(h) (h->data->always_on) 52 53 #define SD_EMMC_DELAY 0x4 54 #define SD_EMMC_ADJUST 0x8 55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 56 #define ADJUST_DS_EN BIT(15) 57 #define ADJUST_ADJ_EN BIT(13) 58 59 #define SD_EMMC_DELAY1 0x4 60 #define SD_EMMC_DELAY2 0x8 61 #define SD_EMMC_V3_ADJUST 0xc 62 63 #define SD_EMMC_CALOUT 0x10 64 #define SD_EMMC_START 0x40 65 #define START_DESC_INIT BIT(0) 66 #define START_DESC_BUSY BIT(1) 67 #define START_DESC_ADDR_MASK GENMASK(31, 2) 68 69 #define SD_EMMC_CFG 0x44 70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 71 #define CFG_BUS_WIDTH_1 0x0 72 #define CFG_BUS_WIDTH_4 0x1 73 #define CFG_BUS_WIDTH_8 0x2 74 #define CFG_DDR BIT(2) 75 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 77 #define CFG_RC_CC_MASK GENMASK(15, 12) 78 #define CFG_STOP_CLOCK BIT(22) 79 #define CFG_CLK_ALWAYS_ON BIT(18) 80 #define CFG_CHK_DS BIT(20) 81 #define CFG_AUTO_CLK BIT(23) 82 #define CFG_ERR_ABORT BIT(27) 83 84 #define SD_EMMC_STATUS 0x48 85 #define STATUS_BUSY BIT(31) 86 #define STATUS_DESC_BUSY BIT(30) 87 #define STATUS_DATI GENMASK(23, 16) 88 89 #define SD_EMMC_IRQ_EN 0x4c 90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 91 #define IRQ_TXD_ERR BIT(8) 92 #define IRQ_DESC_ERR BIT(9) 93 #define IRQ_RESP_ERR BIT(10) 94 #define IRQ_CRC_ERR \ 95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 96 #define IRQ_RESP_TIMEOUT BIT(11) 97 #define IRQ_DESC_TIMEOUT BIT(12) 98 #define IRQ_TIMEOUTS \ 99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 100 #define IRQ_END_OF_CHAIN BIT(13) 101 #define IRQ_RESP_STATUS BIT(14) 102 #define IRQ_SDIO BIT(15) 103 #define IRQ_EN_MASK \ 104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 105 IRQ_SDIO) 106 107 #define SD_EMMC_CMD_CFG 0x50 108 #define SD_EMMC_CMD_ARG 0x54 109 #define SD_EMMC_CMD_DAT 0x58 110 #define SD_EMMC_CMD_RSP 0x5c 111 #define SD_EMMC_CMD_RSP1 0x60 112 #define SD_EMMC_CMD_RSP2 0x64 113 #define SD_EMMC_CMD_RSP3 0x68 114 115 #define SD_EMMC_RXD 0x94 116 #define SD_EMMC_TXD 0x94 117 #define SD_EMMC_LAST_REG SD_EMMC_TXD 118 119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536 120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 121 122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 128 129 #define SD_EMMC_PRE_REQ_DONE BIT(0) 130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 131 132 #define MUX_CLK_NUM_PARENTS 2 133 134 struct meson_mmc_data { 135 unsigned int tx_delay_mask; 136 unsigned int rx_delay_mask; 137 unsigned int always_on; 138 unsigned int adjust; 139 }; 140 141 struct sd_emmc_desc { 142 u32 cmd_cfg; 143 u32 cmd_arg; 144 u32 cmd_data; 145 u32 cmd_resp; 146 }; 147 148 struct meson_host { 149 struct device *dev; 150 struct meson_mmc_data *data; 151 struct mmc_host *mmc; 152 struct mmc_command *cmd; 153 154 void __iomem *regs; 155 struct clk *core_clk; 156 struct clk *mux_clk; 157 struct clk *mmc_clk; 158 unsigned long req_rate; 159 bool ddr; 160 161 bool dram_access_quirk; 162 163 struct pinctrl *pinctrl; 164 struct pinctrl_state *pins_clk_gate; 165 166 unsigned int bounce_buf_size; 167 void *bounce_buf; 168 dma_addr_t bounce_dma_addr; 169 struct sd_emmc_desc *descs; 170 dma_addr_t descs_dma_addr; 171 172 int irq; 173 174 bool vqmmc_enabled; 175 }; 176 177 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 178 #define CMD_CFG_BLOCK_MODE BIT(9) 179 #define CMD_CFG_R1B BIT(10) 180 #define CMD_CFG_END_OF_CHAIN BIT(11) 181 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 182 #define CMD_CFG_NO_RESP BIT(16) 183 #define CMD_CFG_NO_CMD BIT(17) 184 #define CMD_CFG_DATA_IO BIT(18) 185 #define CMD_CFG_DATA_WR BIT(19) 186 #define CMD_CFG_RESP_NOCRC BIT(20) 187 #define CMD_CFG_RESP_128 BIT(21) 188 #define CMD_CFG_RESP_NUM BIT(22) 189 #define CMD_CFG_DATA_NUM BIT(23) 190 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 191 #define CMD_CFG_ERROR BIT(30) 192 #define CMD_CFG_OWNER BIT(31) 193 194 #define CMD_DATA_MASK GENMASK(31, 2) 195 #define CMD_DATA_BIG_ENDIAN BIT(1) 196 #define CMD_DATA_SRAM BIT(0) 197 #define CMD_RESP_MASK GENMASK(31, 1) 198 #define CMD_RESP_SRAM BIT(0) 199 200 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 201 { 202 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 203 204 if (!timeout) 205 return SD_EMMC_CMD_TIMEOUT_DATA; 206 207 timeout = roundup_pow_of_two(timeout); 208 209 return min(timeout, 32768U); /* max. 2^15 ms */ 210 } 211 212 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 213 { 214 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 215 return cmd->mrq->cmd; 216 else if (mmc_op_multi(cmd->opcode) && 217 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 218 return cmd->mrq->stop; 219 else 220 return NULL; 221 } 222 223 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 224 struct mmc_request *mrq) 225 { 226 struct meson_host *host = mmc_priv(mmc); 227 struct mmc_data *data = mrq->data; 228 struct scatterlist *sg; 229 int i; 230 bool use_desc_chain_mode = true; 231 232 /* 233 * When Controller DMA cannot directly access DDR memory, disable 234 * support for Chain Mode to directly use the internal SRAM using 235 * the bounce buffer mode. 236 */ 237 if (host->dram_access_quirk) 238 return; 239 240 /* 241 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 242 * reported. For some strange reason this occurs in descriptor 243 * chain mode only. So let's fall back to bounce buffer mode 244 * for command SD_IO_RW_EXTENDED. 245 */ 246 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 247 return; 248 249 for_each_sg(data->sg, sg, data->sg_len, i) 250 /* check for 8 byte alignment */ 251 if (sg->offset & 7) { 252 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 253 use_desc_chain_mode = false; 254 break; 255 } 256 257 if (use_desc_chain_mode) 258 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 259 } 260 261 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 262 { 263 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 264 } 265 266 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 267 { 268 return data && data->flags & MMC_DATA_READ && 269 !meson_mmc_desc_chain_mode(data); 270 } 271 272 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 273 { 274 struct mmc_data *data = mrq->data; 275 276 if (!data) 277 return; 278 279 meson_mmc_get_transfer_mode(mmc, mrq); 280 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 281 282 if (!meson_mmc_desc_chain_mode(data)) 283 return; 284 285 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 286 mmc_get_dma_dir(data)); 287 if (!data->sg_count) 288 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 289 } 290 291 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 292 int err) 293 { 294 struct mmc_data *data = mrq->data; 295 296 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 297 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 298 mmc_get_dma_dir(data)); 299 } 300 301 /* 302 * Gating the clock on this controller is tricky. It seems the mmc clock 303 * is also used by the controller. It may crash during some operation if the 304 * clock is stopped. The safest thing to do, whenever possible, is to keep 305 * clock running at stop it at the pad using the pinmux. 306 */ 307 static void meson_mmc_clk_gate(struct meson_host *host) 308 { 309 u32 cfg; 310 311 if (host->pins_clk_gate) { 312 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 313 } else { 314 /* 315 * If the pinmux is not provided - default to the classic and 316 * unsafe method 317 */ 318 cfg = readl(host->regs + SD_EMMC_CFG); 319 cfg |= CFG_STOP_CLOCK; 320 writel(cfg, host->regs + SD_EMMC_CFG); 321 } 322 } 323 324 static void meson_mmc_clk_ungate(struct meson_host *host) 325 { 326 u32 cfg; 327 328 if (host->pins_clk_gate) 329 pinctrl_select_default_state(host->dev); 330 331 /* Make sure the clock is not stopped in the controller */ 332 cfg = readl(host->regs + SD_EMMC_CFG); 333 cfg &= ~CFG_STOP_CLOCK; 334 writel(cfg, host->regs + SD_EMMC_CFG); 335 } 336 337 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 338 bool ddr) 339 { 340 struct mmc_host *mmc = host->mmc; 341 int ret; 342 u32 cfg; 343 344 /* Same request - bail-out */ 345 if (host->ddr == ddr && host->req_rate == rate) 346 return 0; 347 348 /* stop clock */ 349 meson_mmc_clk_gate(host); 350 host->req_rate = 0; 351 mmc->actual_clock = 0; 352 353 /* return with clock being stopped */ 354 if (!rate) 355 return 0; 356 357 /* Stop the clock during rate change to avoid glitches */ 358 cfg = readl(host->regs + SD_EMMC_CFG); 359 cfg |= CFG_STOP_CLOCK; 360 writel(cfg, host->regs + SD_EMMC_CFG); 361 362 if (ddr) { 363 /* DDR modes require higher module clock */ 364 rate <<= 1; 365 cfg |= CFG_DDR; 366 } else { 367 cfg &= ~CFG_DDR; 368 } 369 writel(cfg, host->regs + SD_EMMC_CFG); 370 host->ddr = ddr; 371 372 ret = clk_set_rate(host->mmc_clk, rate); 373 if (ret) { 374 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 375 rate, ret); 376 return ret; 377 } 378 379 host->req_rate = rate; 380 mmc->actual_clock = clk_get_rate(host->mmc_clk); 381 382 /* We should report the real output frequency of the controller */ 383 if (ddr) { 384 host->req_rate >>= 1; 385 mmc->actual_clock >>= 1; 386 } 387 388 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 389 if (rate != mmc->actual_clock) 390 dev_dbg(host->dev, "requested rate was %lu\n", rate); 391 392 /* (re)start clock */ 393 meson_mmc_clk_ungate(host); 394 395 return 0; 396 } 397 398 /* 399 * The SD/eMMC IP block has an internal mux and divider used for 400 * generating the MMC clock. Use the clock framework to create and 401 * manage these clocks. 402 */ 403 static int meson_mmc_clk_init(struct meson_host *host) 404 { 405 struct clk_init_data init; 406 struct clk_mux *mux; 407 struct clk_divider *div; 408 char clk_name[32]; 409 int i, ret = 0; 410 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 411 const char *clk_parent[1]; 412 u32 clk_reg; 413 414 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 415 clk_reg = CLK_ALWAYS_ON(host); 416 clk_reg |= CLK_DIV_MASK; 417 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 418 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 419 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 420 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 421 422 /* get the mux parents */ 423 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 424 struct clk *clk; 425 char name[16]; 426 427 snprintf(name, sizeof(name), "clkin%d", i); 428 clk = devm_clk_get(host->dev, name); 429 if (IS_ERR(clk)) 430 return dev_err_probe(host->dev, PTR_ERR(clk), 431 "Missing clock %s\n", name); 432 433 mux_parent_names[i] = __clk_get_name(clk); 434 } 435 436 /* create the mux */ 437 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 438 if (!mux) 439 return -ENOMEM; 440 441 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 442 init.name = clk_name; 443 init.ops = &clk_mux_ops; 444 init.flags = 0; 445 init.parent_names = mux_parent_names; 446 init.num_parents = MUX_CLK_NUM_PARENTS; 447 448 mux->reg = host->regs + SD_EMMC_CLOCK; 449 mux->shift = __ffs(CLK_SRC_MASK); 450 mux->mask = CLK_SRC_MASK >> mux->shift; 451 mux->hw.init = &init; 452 453 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 454 if (WARN_ON(IS_ERR(host->mux_clk))) 455 return PTR_ERR(host->mux_clk); 456 457 /* create the divider */ 458 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 459 if (!div) 460 return -ENOMEM; 461 462 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 463 init.name = clk_name; 464 init.ops = &clk_divider_ops; 465 init.flags = CLK_SET_RATE_PARENT; 466 clk_parent[0] = __clk_get_name(host->mux_clk); 467 init.parent_names = clk_parent; 468 init.num_parents = 1; 469 470 div->reg = host->regs + SD_EMMC_CLOCK; 471 div->shift = __ffs(CLK_DIV_MASK); 472 div->width = __builtin_popcountl(CLK_DIV_MASK); 473 div->hw.init = &init; 474 div->flags = CLK_DIVIDER_ONE_BASED; 475 476 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 477 if (WARN_ON(IS_ERR(host->mmc_clk))) 478 return PTR_ERR(host->mmc_clk); 479 480 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 481 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 482 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 483 if (ret) 484 return ret; 485 486 return clk_prepare_enable(host->mmc_clk); 487 } 488 489 static void meson_mmc_disable_resampling(struct meson_host *host) 490 { 491 unsigned int val = readl(host->regs + host->data->adjust); 492 493 val &= ~ADJUST_ADJ_EN; 494 writel(val, host->regs + host->data->adjust); 495 } 496 497 static void meson_mmc_reset_resampling(struct meson_host *host) 498 { 499 unsigned int val; 500 501 meson_mmc_disable_resampling(host); 502 503 val = readl(host->regs + host->data->adjust); 504 val &= ~ADJUST_ADJ_DELAY_MASK; 505 writel(val, host->regs + host->data->adjust); 506 } 507 508 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 509 { 510 struct meson_host *host = mmc_priv(mmc); 511 unsigned int val, dly, max_dly, i; 512 int ret; 513 514 /* Resampling is done using the source clock */ 515 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 516 clk_get_rate(host->mmc_clk)); 517 518 val = readl(host->regs + host->data->adjust); 519 val |= ADJUST_ADJ_EN; 520 writel(val, host->regs + host->data->adjust); 521 522 if (mmc_doing_retune(mmc)) 523 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 524 else 525 dly = 0; 526 527 for (i = 0; i < max_dly; i++) { 528 val &= ~ADJUST_ADJ_DELAY_MASK; 529 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 530 writel(val, host->regs + host->data->adjust); 531 532 ret = mmc_send_tuning(mmc, opcode, NULL); 533 if (!ret) { 534 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 535 (dly + i) % max_dly); 536 return 0; 537 } 538 } 539 540 meson_mmc_reset_resampling(host); 541 return -EIO; 542 } 543 544 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 545 struct mmc_ios *ios) 546 { 547 bool ddr; 548 549 switch (ios->timing) { 550 case MMC_TIMING_MMC_DDR52: 551 case MMC_TIMING_UHS_DDR50: 552 ddr = true; 553 break; 554 555 default: 556 ddr = false; 557 break; 558 } 559 560 return meson_mmc_clk_set(host, ios->clock, ddr); 561 } 562 563 static void meson_mmc_check_resampling(struct meson_host *host, 564 struct mmc_ios *ios) 565 { 566 switch (ios->timing) { 567 case MMC_TIMING_LEGACY: 568 case MMC_TIMING_MMC_HS: 569 case MMC_TIMING_SD_HS: 570 case MMC_TIMING_MMC_DDR52: 571 meson_mmc_disable_resampling(host); 572 break; 573 } 574 } 575 576 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 577 { 578 struct meson_host *host = mmc_priv(mmc); 579 u32 bus_width, val; 580 int err; 581 582 /* 583 * GPIO regulator, only controls switching between 1v8 and 584 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 585 */ 586 switch (ios->power_mode) { 587 case MMC_POWER_OFF: 588 if (!IS_ERR(mmc->supply.vmmc)) 589 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 590 591 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 592 regulator_disable(mmc->supply.vqmmc); 593 host->vqmmc_enabled = false; 594 } 595 596 break; 597 598 case MMC_POWER_UP: 599 if (!IS_ERR(mmc->supply.vmmc)) 600 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 601 602 break; 603 604 case MMC_POWER_ON: 605 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 606 int ret = regulator_enable(mmc->supply.vqmmc); 607 608 if (ret < 0) 609 dev_err(host->dev, 610 "failed to enable vqmmc regulator\n"); 611 else 612 host->vqmmc_enabled = true; 613 } 614 615 break; 616 } 617 618 /* Bus width */ 619 switch (ios->bus_width) { 620 case MMC_BUS_WIDTH_1: 621 bus_width = CFG_BUS_WIDTH_1; 622 break; 623 case MMC_BUS_WIDTH_4: 624 bus_width = CFG_BUS_WIDTH_4; 625 break; 626 case MMC_BUS_WIDTH_8: 627 bus_width = CFG_BUS_WIDTH_8; 628 break; 629 default: 630 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 631 ios->bus_width); 632 bus_width = CFG_BUS_WIDTH_4; 633 } 634 635 val = readl(host->regs + SD_EMMC_CFG); 636 val &= ~CFG_BUS_WIDTH_MASK; 637 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 638 writel(val, host->regs + SD_EMMC_CFG); 639 640 meson_mmc_check_resampling(host, ios); 641 err = meson_mmc_prepare_ios_clock(host, ios); 642 if (err) 643 dev_err(host->dev, "Failed to set clock: %d\n,", err); 644 645 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 646 } 647 648 static void meson_mmc_request_done(struct mmc_host *mmc, 649 struct mmc_request *mrq) 650 { 651 struct meson_host *host = mmc_priv(mmc); 652 653 host->cmd = NULL; 654 mmc_request_done(host->mmc, mrq); 655 } 656 657 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 658 { 659 struct meson_host *host = mmc_priv(mmc); 660 u32 cfg, blksz_old; 661 662 cfg = readl(host->regs + SD_EMMC_CFG); 663 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 664 665 if (!is_power_of_2(blksz)) 666 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 667 668 blksz = ilog2(blksz); 669 670 /* check if block-size matches, if not update */ 671 if (blksz == blksz_old) 672 return; 673 674 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 675 blksz_old, blksz); 676 677 cfg &= ~CFG_BLK_LEN_MASK; 678 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 679 writel(cfg, host->regs + SD_EMMC_CFG); 680 } 681 682 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 683 { 684 if (cmd->flags & MMC_RSP_PRESENT) { 685 if (cmd->flags & MMC_RSP_136) 686 *cmd_cfg |= CMD_CFG_RESP_128; 687 *cmd_cfg |= CMD_CFG_RESP_NUM; 688 689 if (!(cmd->flags & MMC_RSP_CRC)) 690 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 691 692 if (cmd->flags & MMC_RSP_BUSY) 693 *cmd_cfg |= CMD_CFG_R1B; 694 } else { 695 *cmd_cfg |= CMD_CFG_NO_RESP; 696 } 697 } 698 699 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 700 { 701 struct meson_host *host = mmc_priv(mmc); 702 struct sd_emmc_desc *desc = host->descs; 703 struct mmc_data *data = host->cmd->data; 704 struct scatterlist *sg; 705 u32 start; 706 int i; 707 708 if (data->flags & MMC_DATA_WRITE) 709 cmd_cfg |= CMD_CFG_DATA_WR; 710 711 if (data->blocks > 1) { 712 cmd_cfg |= CMD_CFG_BLOCK_MODE; 713 meson_mmc_set_blksz(mmc, data->blksz); 714 } 715 716 for_each_sg(data->sg, sg, data->sg_count, i) { 717 unsigned int len = sg_dma_len(sg); 718 719 if (data->blocks > 1) 720 len /= data->blksz; 721 722 desc[i].cmd_cfg = cmd_cfg; 723 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 724 if (i > 0) 725 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 726 desc[i].cmd_arg = host->cmd->arg; 727 desc[i].cmd_resp = 0; 728 desc[i].cmd_data = sg_dma_address(sg); 729 } 730 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 731 732 dma_wmb(); /* ensure descriptor is written before kicked */ 733 start = host->descs_dma_addr | START_DESC_BUSY; 734 writel(start, host->regs + SD_EMMC_START); 735 } 736 737 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 738 { 739 struct meson_host *host = mmc_priv(mmc); 740 struct mmc_data *data = cmd->data; 741 u32 cmd_cfg = 0, cmd_data = 0; 742 unsigned int xfer_bytes = 0; 743 744 /* Setup descriptors */ 745 dma_rmb(); 746 747 host->cmd = cmd; 748 749 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 750 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 751 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 752 753 meson_mmc_set_response_bits(cmd, &cmd_cfg); 754 755 /* data? */ 756 if (data) { 757 data->bytes_xfered = 0; 758 cmd_cfg |= CMD_CFG_DATA_IO; 759 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 760 ilog2(meson_mmc_get_timeout_msecs(data))); 761 762 if (meson_mmc_desc_chain_mode(data)) { 763 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 764 return; 765 } 766 767 if (data->blocks > 1) { 768 cmd_cfg |= CMD_CFG_BLOCK_MODE; 769 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 770 data->blocks); 771 meson_mmc_set_blksz(mmc, data->blksz); 772 } else { 773 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 774 } 775 776 xfer_bytes = data->blksz * data->blocks; 777 if (data->flags & MMC_DATA_WRITE) { 778 cmd_cfg |= CMD_CFG_DATA_WR; 779 WARN_ON(xfer_bytes > host->bounce_buf_size); 780 sg_copy_to_buffer(data->sg, data->sg_len, 781 host->bounce_buf, xfer_bytes); 782 dma_wmb(); 783 } 784 785 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 786 } else { 787 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 788 ilog2(SD_EMMC_CMD_TIMEOUT)); 789 } 790 791 /* Last descriptor */ 792 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 793 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 794 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 795 writel(0, host->regs + SD_EMMC_CMD_RSP); 796 wmb(); /* ensure descriptor is written before kicked */ 797 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 798 } 799 800 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 801 { 802 struct meson_host *host = mmc_priv(mmc); 803 bool needs_pre_post_req = mrq->data && 804 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 805 806 if (needs_pre_post_req) { 807 meson_mmc_get_transfer_mode(mmc, mrq); 808 if (!meson_mmc_desc_chain_mode(mrq->data)) 809 needs_pre_post_req = false; 810 } 811 812 if (needs_pre_post_req) 813 meson_mmc_pre_req(mmc, mrq); 814 815 /* Stop execution */ 816 writel(0, host->regs + SD_EMMC_START); 817 818 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 819 820 if (needs_pre_post_req) 821 meson_mmc_post_req(mmc, mrq, 0); 822 } 823 824 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 825 { 826 struct meson_host *host = mmc_priv(mmc); 827 828 if (cmd->flags & MMC_RSP_136) { 829 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 830 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 831 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 832 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 833 } else if (cmd->flags & MMC_RSP_PRESENT) { 834 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 835 } 836 } 837 838 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 839 { 840 struct meson_host *host = dev_id; 841 struct mmc_command *cmd; 842 struct mmc_data *data; 843 u32 irq_en, status, raw_status; 844 irqreturn_t ret = IRQ_NONE; 845 846 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 847 raw_status = readl(host->regs + SD_EMMC_STATUS); 848 status = raw_status & irq_en; 849 850 if (!status) { 851 dev_dbg(host->dev, 852 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 853 irq_en, raw_status); 854 return IRQ_NONE; 855 } 856 857 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 858 return IRQ_NONE; 859 860 /* ack all raised interrupts */ 861 writel(status, host->regs + SD_EMMC_STATUS); 862 863 cmd = host->cmd; 864 data = cmd->data; 865 cmd->error = 0; 866 if (status & IRQ_CRC_ERR) { 867 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 868 cmd->error = -EILSEQ; 869 ret = IRQ_WAKE_THREAD; 870 goto out; 871 } 872 873 if (status & IRQ_TIMEOUTS) { 874 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 875 cmd->error = -ETIMEDOUT; 876 ret = IRQ_WAKE_THREAD; 877 goto out; 878 } 879 880 meson_mmc_read_resp(host->mmc, cmd); 881 882 if (status & IRQ_SDIO) { 883 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 884 ret = IRQ_HANDLED; 885 } 886 887 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 888 if (data && !cmd->error) 889 data->bytes_xfered = data->blksz * data->blocks; 890 if (meson_mmc_bounce_buf_read(data) || 891 meson_mmc_get_next_command(cmd)) 892 ret = IRQ_WAKE_THREAD; 893 else 894 ret = IRQ_HANDLED; 895 } 896 897 out: 898 if (cmd->error) { 899 /* Stop desc in case of errors */ 900 u32 start = readl(host->regs + SD_EMMC_START); 901 902 start &= ~START_DESC_BUSY; 903 writel(start, host->regs + SD_EMMC_START); 904 } 905 906 if (ret == IRQ_HANDLED) 907 meson_mmc_request_done(host->mmc, cmd->mrq); 908 909 return ret; 910 } 911 912 static int meson_mmc_wait_desc_stop(struct meson_host *host) 913 { 914 u32 status; 915 916 /* 917 * It may sometimes take a while for it to actually halt. Here, we 918 * are giving it 5ms to comply 919 * 920 * If we don't confirm the descriptor is stopped, it might raise new 921 * IRQs after we have called mmc_request_done() which is bad. 922 */ 923 924 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 925 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 926 100, 5000); 927 } 928 929 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 930 { 931 struct meson_host *host = dev_id; 932 struct mmc_command *next_cmd, *cmd = host->cmd; 933 struct mmc_data *data; 934 unsigned int xfer_bytes; 935 936 if (WARN_ON(!cmd)) 937 return IRQ_NONE; 938 939 if (cmd->error) { 940 meson_mmc_wait_desc_stop(host); 941 meson_mmc_request_done(host->mmc, cmd->mrq); 942 943 return IRQ_HANDLED; 944 } 945 946 data = cmd->data; 947 if (meson_mmc_bounce_buf_read(data)) { 948 xfer_bytes = data->blksz * data->blocks; 949 WARN_ON(xfer_bytes > host->bounce_buf_size); 950 sg_copy_from_buffer(data->sg, data->sg_len, 951 host->bounce_buf, xfer_bytes); 952 } 953 954 next_cmd = meson_mmc_get_next_command(cmd); 955 if (next_cmd) 956 meson_mmc_start_cmd(host->mmc, next_cmd); 957 else 958 meson_mmc_request_done(host->mmc, cmd->mrq); 959 960 return IRQ_HANDLED; 961 } 962 963 /* 964 * NOTE: we only need this until the GPIO/pinctrl driver can handle 965 * interrupts. For now, the MMC core will use this for polling. 966 */ 967 static int meson_mmc_get_cd(struct mmc_host *mmc) 968 { 969 int status = mmc_gpio_get_cd(mmc); 970 971 if (status == -ENOSYS) 972 return 1; /* assume present */ 973 974 return status; 975 } 976 977 static void meson_mmc_cfg_init(struct meson_host *host) 978 { 979 u32 cfg = 0; 980 981 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 982 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 983 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 984 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 985 986 /* abort chain on R/W errors */ 987 cfg |= CFG_ERR_ABORT; 988 989 writel(cfg, host->regs + SD_EMMC_CFG); 990 } 991 992 static int meson_mmc_card_busy(struct mmc_host *mmc) 993 { 994 struct meson_host *host = mmc_priv(mmc); 995 u32 regval; 996 997 regval = readl(host->regs + SD_EMMC_STATUS); 998 999 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1000 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1001 } 1002 1003 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1004 { 1005 int ret; 1006 1007 /* vqmmc regulator is available */ 1008 if (!IS_ERR(mmc->supply.vqmmc)) { 1009 /* 1010 * The usual amlogic setup uses a GPIO to switch from one 1011 * regulator to the other. While the voltage ramp up is 1012 * pretty fast, care must be taken when switching from 3.3v 1013 * to 1.8v. Please make sure the regulator framework is aware 1014 * of your own regulator constraints 1015 */ 1016 ret = mmc_regulator_set_vqmmc(mmc, ios); 1017 return ret < 0 ? ret : 0; 1018 } 1019 1020 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1021 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1022 return 0; 1023 1024 return -EINVAL; 1025 } 1026 1027 static const struct mmc_host_ops meson_mmc_ops = { 1028 .request = meson_mmc_request, 1029 .set_ios = meson_mmc_set_ios, 1030 .get_cd = meson_mmc_get_cd, 1031 .pre_req = meson_mmc_pre_req, 1032 .post_req = meson_mmc_post_req, 1033 .execute_tuning = meson_mmc_resampling_tuning, 1034 .card_busy = meson_mmc_card_busy, 1035 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1036 }; 1037 1038 static int meson_mmc_probe(struct platform_device *pdev) 1039 { 1040 struct resource *res; 1041 struct meson_host *host; 1042 struct mmc_host *mmc; 1043 int ret; 1044 1045 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1046 if (!mmc) 1047 return -ENOMEM; 1048 host = mmc_priv(mmc); 1049 host->mmc = mmc; 1050 host->dev = &pdev->dev; 1051 dev_set_drvdata(&pdev->dev, host); 1052 1053 /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1054 host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1055 "amlogic,dram-access-quirk"); 1056 1057 /* Get regulators and the supported OCR mask */ 1058 host->vqmmc_enabled = false; 1059 ret = mmc_regulator_get_supply(mmc); 1060 if (ret) 1061 goto free_host; 1062 1063 ret = mmc_of_parse(mmc); 1064 if (ret) { 1065 if (ret != -EPROBE_DEFER) 1066 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1067 goto free_host; 1068 } 1069 1070 host->data = (struct meson_mmc_data *) 1071 of_device_get_match_data(&pdev->dev); 1072 if (!host->data) { 1073 ret = -EINVAL; 1074 goto free_host; 1075 } 1076 1077 ret = device_reset_optional(&pdev->dev); 1078 if (ret) 1079 return dev_err_probe(&pdev->dev, ret, "device reset failed\n"); 1080 1081 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1082 host->regs = devm_ioremap_resource(&pdev->dev, res); 1083 if (IS_ERR(host->regs)) { 1084 ret = PTR_ERR(host->regs); 1085 goto free_host; 1086 } 1087 1088 host->irq = platform_get_irq(pdev, 0); 1089 if (host->irq <= 0) { 1090 ret = -EINVAL; 1091 goto free_host; 1092 } 1093 1094 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1095 if (IS_ERR(host->pinctrl)) { 1096 ret = PTR_ERR(host->pinctrl); 1097 goto free_host; 1098 } 1099 1100 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1101 "clk-gate"); 1102 if (IS_ERR(host->pins_clk_gate)) { 1103 dev_warn(&pdev->dev, 1104 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1105 host->pins_clk_gate = NULL; 1106 } 1107 1108 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1109 if (IS_ERR(host->core_clk)) { 1110 ret = PTR_ERR(host->core_clk); 1111 goto free_host; 1112 } 1113 1114 ret = clk_prepare_enable(host->core_clk); 1115 if (ret) 1116 goto free_host; 1117 1118 ret = meson_mmc_clk_init(host); 1119 if (ret) 1120 goto err_core_clk; 1121 1122 /* set config to sane default */ 1123 meson_mmc_cfg_init(host); 1124 1125 /* Stop execution */ 1126 writel(0, host->regs + SD_EMMC_START); 1127 1128 /* clear, ack and enable interrupts */ 1129 writel(0, host->regs + SD_EMMC_IRQ_EN); 1130 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1131 host->regs + SD_EMMC_STATUS); 1132 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1133 host->regs + SD_EMMC_IRQ_EN); 1134 1135 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1136 meson_mmc_irq_thread, IRQF_ONESHOT, 1137 dev_name(&pdev->dev), host); 1138 if (ret) 1139 goto err_init_clk; 1140 1141 mmc->caps |= MMC_CAP_CMD23; 1142 if (host->dram_access_quirk) { 1143 /* Limit segments to 1 due to low available sram memory */ 1144 mmc->max_segs = 1; 1145 /* Limit to the available sram memory */ 1146 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 1147 mmc->max_blk_size; 1148 } else { 1149 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1150 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1151 sizeof(struct sd_emmc_desc); 1152 } 1153 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1154 mmc->max_seg_size = mmc->max_req_size; 1155 1156 /* 1157 * At the moment, we don't know how to reliably enable HS400. 1158 * From the different datasheets, it is not even clear if this mode 1159 * is officially supported by any of the SoCs 1160 */ 1161 mmc->caps2 &= ~MMC_CAP2_HS400; 1162 1163 if (host->dram_access_quirk) { 1164 /* 1165 * The MMC Controller embeds 1,5KiB of internal SRAM 1166 * that can be used to be used as bounce buffer. 1167 * In the case of the G12A SDIO controller, use these 1168 * instead of the DDR memory 1169 */ 1170 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1171 host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1172 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1173 } else { 1174 /* data bounce buffer */ 1175 host->bounce_buf_size = mmc->max_req_size; 1176 host->bounce_buf = 1177 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1178 &host->bounce_dma_addr, GFP_KERNEL); 1179 if (host->bounce_buf == NULL) { 1180 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1181 ret = -ENOMEM; 1182 goto err_free_irq; 1183 } 1184 } 1185 1186 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1187 &host->descs_dma_addr, GFP_KERNEL); 1188 if (!host->descs) { 1189 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1190 ret = -ENOMEM; 1191 goto err_bounce_buf; 1192 } 1193 1194 mmc->ops = &meson_mmc_ops; 1195 mmc_add_host(mmc); 1196 1197 return 0; 1198 1199 err_bounce_buf: 1200 if (!host->dram_access_quirk) 1201 dma_free_coherent(host->dev, host->bounce_buf_size, 1202 host->bounce_buf, host->bounce_dma_addr); 1203 err_free_irq: 1204 free_irq(host->irq, host); 1205 err_init_clk: 1206 clk_disable_unprepare(host->mmc_clk); 1207 err_core_clk: 1208 clk_disable_unprepare(host->core_clk); 1209 free_host: 1210 mmc_free_host(mmc); 1211 return ret; 1212 } 1213 1214 static int meson_mmc_remove(struct platform_device *pdev) 1215 { 1216 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1217 1218 mmc_remove_host(host->mmc); 1219 1220 /* disable interrupts */ 1221 writel(0, host->regs + SD_EMMC_IRQ_EN); 1222 free_irq(host->irq, host); 1223 1224 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1225 host->descs, host->descs_dma_addr); 1226 1227 if (!host->dram_access_quirk) 1228 dma_free_coherent(host->dev, host->bounce_buf_size, 1229 host->bounce_buf, host->bounce_dma_addr); 1230 1231 clk_disable_unprepare(host->mmc_clk); 1232 clk_disable_unprepare(host->core_clk); 1233 1234 mmc_free_host(host->mmc); 1235 return 0; 1236 } 1237 1238 static const struct meson_mmc_data meson_gx_data = { 1239 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1240 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1241 .always_on = CLK_V2_ALWAYS_ON, 1242 .adjust = SD_EMMC_ADJUST, 1243 }; 1244 1245 static const struct meson_mmc_data meson_axg_data = { 1246 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1247 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1248 .always_on = CLK_V3_ALWAYS_ON, 1249 .adjust = SD_EMMC_V3_ADJUST, 1250 }; 1251 1252 static const struct of_device_id meson_mmc_of_match[] = { 1253 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1254 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1255 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1256 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1257 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1258 {} 1259 }; 1260 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1261 1262 static struct platform_driver meson_mmc_driver = { 1263 .probe = meson_mmc_probe, 1264 .remove = meson_mmc_remove, 1265 .driver = { 1266 .name = DRIVER_NAME, 1267 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1268 .of_match_table = of_match_ptr(meson_mmc_of_match), 1269 }, 1270 }; 1271 1272 module_platform_driver(meson_mmc_driver); 1273 1274 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1275 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1276 MODULE_LICENSE("GPL v2"); 1277