1 /* 2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Kevin Hilman <khilman@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * The full GNU General Public License is included in this distribution 19 * in the file called COPYING. 20 */ 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/iopoll.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/ioport.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/sdio.h> 34 #include <linux/mmc/slot-gpio.h> 35 #include <linux/io.h> 36 #include <linux/clk.h> 37 #include <linux/clk-provider.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/reset.h> 40 #include <linux/interrupt.h> 41 #include <linux/bitfield.h> 42 #include <linux/pinctrl/consumer.h> 43 44 #define DRIVER_NAME "meson-gx-mmc" 45 46 #define SD_EMMC_CLOCK 0x0 47 #define CLK_DIV_MASK GENMASK(5, 0) 48 #define CLK_SRC_MASK GENMASK(7, 6) 49 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 50 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 51 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 52 #define CLK_PHASE_0 0 53 #define CLK_PHASE_180 2 54 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 55 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 56 #define CLK_V2_ALWAYS_ON BIT(24) 57 58 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 59 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 60 #define CLK_V3_ALWAYS_ON BIT(28) 61 62 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 63 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 64 #define CLK_ALWAYS_ON(h) (h->data->always_on) 65 66 #define SD_EMMC_DELAY 0x4 67 #define SD_EMMC_ADJUST 0x8 68 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 69 #define ADJUST_DS_EN BIT(15) 70 #define ADJUST_ADJ_EN BIT(13) 71 72 #define SD_EMMC_DELAY1 0x4 73 #define SD_EMMC_DELAY2 0x8 74 #define SD_EMMC_V3_ADJUST 0xc 75 76 #define SD_EMMC_CALOUT 0x10 77 #define SD_EMMC_START 0x40 78 #define START_DESC_INIT BIT(0) 79 #define START_DESC_BUSY BIT(1) 80 #define START_DESC_ADDR_MASK GENMASK(31, 2) 81 82 #define SD_EMMC_CFG 0x44 83 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 84 #define CFG_BUS_WIDTH_1 0x0 85 #define CFG_BUS_WIDTH_4 0x1 86 #define CFG_BUS_WIDTH_8 0x2 87 #define CFG_DDR BIT(2) 88 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 89 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 90 #define CFG_RC_CC_MASK GENMASK(15, 12) 91 #define CFG_STOP_CLOCK BIT(22) 92 #define CFG_CLK_ALWAYS_ON BIT(18) 93 #define CFG_CHK_DS BIT(20) 94 #define CFG_AUTO_CLK BIT(23) 95 #define CFG_ERR_ABORT BIT(27) 96 97 #define SD_EMMC_STATUS 0x48 98 #define STATUS_BUSY BIT(31) 99 #define STATUS_DESC_BUSY BIT(30) 100 #define STATUS_DATI GENMASK(23, 16) 101 102 #define SD_EMMC_IRQ_EN 0x4c 103 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 104 #define IRQ_TXD_ERR BIT(8) 105 #define IRQ_DESC_ERR BIT(9) 106 #define IRQ_RESP_ERR BIT(10) 107 #define IRQ_CRC_ERR \ 108 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 109 #define IRQ_RESP_TIMEOUT BIT(11) 110 #define IRQ_DESC_TIMEOUT BIT(12) 111 #define IRQ_TIMEOUTS \ 112 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 113 #define IRQ_END_OF_CHAIN BIT(13) 114 #define IRQ_RESP_STATUS BIT(14) 115 #define IRQ_SDIO BIT(15) 116 #define IRQ_EN_MASK \ 117 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 118 IRQ_SDIO) 119 120 #define SD_EMMC_CMD_CFG 0x50 121 #define SD_EMMC_CMD_ARG 0x54 122 #define SD_EMMC_CMD_DAT 0x58 123 #define SD_EMMC_CMD_RSP 0x5c 124 #define SD_EMMC_CMD_RSP1 0x60 125 #define SD_EMMC_CMD_RSP2 0x64 126 #define SD_EMMC_CMD_RSP3 0x68 127 128 #define SD_EMMC_RXD 0x94 129 #define SD_EMMC_TXD 0x94 130 #define SD_EMMC_LAST_REG SD_EMMC_TXD 131 132 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 133 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 134 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 135 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 136 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 137 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 138 139 #define SD_EMMC_PRE_REQ_DONE BIT(0) 140 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 141 142 #define MUX_CLK_NUM_PARENTS 2 143 144 struct meson_mmc_data { 145 unsigned int tx_delay_mask; 146 unsigned int rx_delay_mask; 147 unsigned int always_on; 148 unsigned int adjust; 149 }; 150 151 struct sd_emmc_desc { 152 u32 cmd_cfg; 153 u32 cmd_arg; 154 u32 cmd_data; 155 u32 cmd_resp; 156 }; 157 158 struct meson_host { 159 struct device *dev; 160 struct meson_mmc_data *data; 161 struct mmc_host *mmc; 162 struct mmc_command *cmd; 163 164 void __iomem *regs; 165 struct clk *core_clk; 166 struct clk *mux_clk; 167 struct clk *mmc_clk; 168 unsigned long req_rate; 169 bool ddr; 170 171 struct pinctrl *pinctrl; 172 struct pinctrl_state *pins_default; 173 struct pinctrl_state *pins_clk_gate; 174 175 unsigned int bounce_buf_size; 176 void *bounce_buf; 177 dma_addr_t bounce_dma_addr; 178 struct sd_emmc_desc *descs; 179 dma_addr_t descs_dma_addr; 180 181 int irq; 182 183 bool vqmmc_enabled; 184 }; 185 186 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 187 #define CMD_CFG_BLOCK_MODE BIT(9) 188 #define CMD_CFG_R1B BIT(10) 189 #define CMD_CFG_END_OF_CHAIN BIT(11) 190 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 191 #define CMD_CFG_NO_RESP BIT(16) 192 #define CMD_CFG_NO_CMD BIT(17) 193 #define CMD_CFG_DATA_IO BIT(18) 194 #define CMD_CFG_DATA_WR BIT(19) 195 #define CMD_CFG_RESP_NOCRC BIT(20) 196 #define CMD_CFG_RESP_128 BIT(21) 197 #define CMD_CFG_RESP_NUM BIT(22) 198 #define CMD_CFG_DATA_NUM BIT(23) 199 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 200 #define CMD_CFG_ERROR BIT(30) 201 #define CMD_CFG_OWNER BIT(31) 202 203 #define CMD_DATA_MASK GENMASK(31, 2) 204 #define CMD_DATA_BIG_ENDIAN BIT(1) 205 #define CMD_DATA_SRAM BIT(0) 206 #define CMD_RESP_MASK GENMASK(31, 1) 207 #define CMD_RESP_SRAM BIT(0) 208 209 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 210 { 211 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 212 213 if (!timeout) 214 return SD_EMMC_CMD_TIMEOUT_DATA; 215 216 timeout = roundup_pow_of_two(timeout); 217 218 return min(timeout, 32768U); /* max. 2^15 ms */ 219 } 220 221 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 222 { 223 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 224 return cmd->mrq->cmd; 225 else if (mmc_op_multi(cmd->opcode) && 226 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 227 return cmd->mrq->stop; 228 else 229 return NULL; 230 } 231 232 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 233 struct mmc_request *mrq) 234 { 235 struct mmc_data *data = mrq->data; 236 struct scatterlist *sg; 237 int i; 238 bool use_desc_chain_mode = true; 239 240 /* 241 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 242 * reported. For some strange reason this occurs in descriptor 243 * chain mode only. So let's fall back to bounce buffer mode 244 * for command SD_IO_RW_EXTENDED. 245 */ 246 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 247 return; 248 249 for_each_sg(data->sg, sg, data->sg_len, i) 250 /* check for 8 byte alignment */ 251 if (sg->offset & 7) { 252 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 253 use_desc_chain_mode = false; 254 break; 255 } 256 257 if (use_desc_chain_mode) 258 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 259 } 260 261 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 262 { 263 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 264 } 265 266 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 267 { 268 return data && data->flags & MMC_DATA_READ && 269 !meson_mmc_desc_chain_mode(data); 270 } 271 272 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 273 { 274 struct mmc_data *data = mrq->data; 275 276 if (!data) 277 return; 278 279 meson_mmc_get_transfer_mode(mmc, mrq); 280 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 281 282 if (!meson_mmc_desc_chain_mode(data)) 283 return; 284 285 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 286 mmc_get_dma_dir(data)); 287 if (!data->sg_count) 288 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 289 } 290 291 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 292 int err) 293 { 294 struct mmc_data *data = mrq->data; 295 296 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 297 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 298 mmc_get_dma_dir(data)); 299 } 300 301 /* 302 * Gating the clock on this controller is tricky. It seems the mmc clock 303 * is also used by the controller. It may crash during some operation if the 304 * clock is stopped. The safest thing to do, whenever possible, is to keep 305 * clock running at stop it at the pad using the pinmux. 306 */ 307 static void meson_mmc_clk_gate(struct meson_host *host) 308 { 309 u32 cfg; 310 311 if (host->pins_clk_gate) { 312 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 313 } else { 314 /* 315 * If the pinmux is not provided - default to the classic and 316 * unsafe method 317 */ 318 cfg = readl(host->regs + SD_EMMC_CFG); 319 cfg |= CFG_STOP_CLOCK; 320 writel(cfg, host->regs + SD_EMMC_CFG); 321 } 322 } 323 324 static void meson_mmc_clk_ungate(struct meson_host *host) 325 { 326 u32 cfg; 327 328 if (host->pins_clk_gate) 329 pinctrl_select_state(host->pinctrl, host->pins_default); 330 331 /* Make sure the clock is not stopped in the controller */ 332 cfg = readl(host->regs + SD_EMMC_CFG); 333 cfg &= ~CFG_STOP_CLOCK; 334 writel(cfg, host->regs + SD_EMMC_CFG); 335 } 336 337 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 338 bool ddr) 339 { 340 struct mmc_host *mmc = host->mmc; 341 int ret; 342 u32 cfg; 343 344 /* Same request - bail-out */ 345 if (host->ddr == ddr && host->req_rate == rate) 346 return 0; 347 348 /* stop clock */ 349 meson_mmc_clk_gate(host); 350 host->req_rate = 0; 351 mmc->actual_clock = 0; 352 353 /* return with clock being stopped */ 354 if (!rate) 355 return 0; 356 357 /* Stop the clock during rate change to avoid glitches */ 358 cfg = readl(host->regs + SD_EMMC_CFG); 359 cfg |= CFG_STOP_CLOCK; 360 writel(cfg, host->regs + SD_EMMC_CFG); 361 362 if (ddr) { 363 /* DDR modes require higher module clock */ 364 rate <<= 1; 365 cfg |= CFG_DDR; 366 } else { 367 cfg &= ~CFG_DDR; 368 } 369 writel(cfg, host->regs + SD_EMMC_CFG); 370 host->ddr = ddr; 371 372 ret = clk_set_rate(host->mmc_clk, rate); 373 if (ret) { 374 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 375 rate, ret); 376 return ret; 377 } 378 379 host->req_rate = rate; 380 mmc->actual_clock = clk_get_rate(host->mmc_clk); 381 382 /* We should report the real output frequency of the controller */ 383 if (ddr) { 384 host->req_rate >>= 1; 385 mmc->actual_clock >>= 1; 386 } 387 388 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 389 if (rate != mmc->actual_clock) 390 dev_dbg(host->dev, "requested rate was %lu\n", rate); 391 392 /* (re)start clock */ 393 meson_mmc_clk_ungate(host); 394 395 return 0; 396 } 397 398 /* 399 * The SD/eMMC IP block has an internal mux and divider used for 400 * generating the MMC clock. Use the clock framework to create and 401 * manage these clocks. 402 */ 403 static int meson_mmc_clk_init(struct meson_host *host) 404 { 405 struct clk_init_data init; 406 struct clk_mux *mux; 407 struct clk_divider *div; 408 char clk_name[32]; 409 int i, ret = 0; 410 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 411 const char *clk_parent[1]; 412 u32 clk_reg; 413 414 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 415 clk_reg = CLK_ALWAYS_ON(host); 416 clk_reg |= CLK_DIV_MASK; 417 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 418 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 419 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 420 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 421 422 /* get the mux parents */ 423 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 424 struct clk *clk; 425 char name[16]; 426 427 snprintf(name, sizeof(name), "clkin%d", i); 428 clk = devm_clk_get(host->dev, name); 429 if (IS_ERR(clk)) { 430 if (clk != ERR_PTR(-EPROBE_DEFER)) 431 dev_err(host->dev, "Missing clock %s\n", name); 432 return PTR_ERR(clk); 433 } 434 435 mux_parent_names[i] = __clk_get_name(clk); 436 } 437 438 /* create the mux */ 439 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 440 if (!mux) 441 return -ENOMEM; 442 443 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 444 init.name = clk_name; 445 init.ops = &clk_mux_ops; 446 init.flags = 0; 447 init.parent_names = mux_parent_names; 448 init.num_parents = MUX_CLK_NUM_PARENTS; 449 450 mux->reg = host->regs + SD_EMMC_CLOCK; 451 mux->shift = __ffs(CLK_SRC_MASK); 452 mux->mask = CLK_SRC_MASK >> mux->shift; 453 mux->hw.init = &init; 454 455 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 456 if (WARN_ON(IS_ERR(host->mux_clk))) 457 return PTR_ERR(host->mux_clk); 458 459 /* create the divider */ 460 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 461 if (!div) 462 return -ENOMEM; 463 464 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 465 init.name = clk_name; 466 init.ops = &clk_divider_ops; 467 init.flags = CLK_SET_RATE_PARENT; 468 clk_parent[0] = __clk_get_name(host->mux_clk); 469 init.parent_names = clk_parent; 470 init.num_parents = 1; 471 472 div->reg = host->regs + SD_EMMC_CLOCK; 473 div->shift = __ffs(CLK_DIV_MASK); 474 div->width = __builtin_popcountl(CLK_DIV_MASK); 475 div->hw.init = &init; 476 div->flags = CLK_DIVIDER_ONE_BASED; 477 478 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 479 if (WARN_ON(IS_ERR(host->mmc_clk))) 480 return PTR_ERR(host->mmc_clk); 481 482 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 483 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 484 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 485 if (ret) 486 return ret; 487 488 return clk_prepare_enable(host->mmc_clk); 489 } 490 491 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 492 struct mmc_ios *ios) 493 { 494 bool ddr; 495 496 switch (ios->timing) { 497 case MMC_TIMING_MMC_DDR52: 498 case MMC_TIMING_UHS_DDR50: 499 ddr = true; 500 break; 501 502 default: 503 ddr = false; 504 break; 505 } 506 507 return meson_mmc_clk_set(host, ios->clock, ddr); 508 } 509 510 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 511 { 512 struct meson_host *host = mmc_priv(mmc); 513 u32 bus_width, val; 514 int err; 515 516 /* 517 * GPIO regulator, only controls switching between 1v8 and 518 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 519 */ 520 switch (ios->power_mode) { 521 case MMC_POWER_OFF: 522 if (!IS_ERR(mmc->supply.vmmc)) 523 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 524 525 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 526 regulator_disable(mmc->supply.vqmmc); 527 host->vqmmc_enabled = false; 528 } 529 530 break; 531 532 case MMC_POWER_UP: 533 if (!IS_ERR(mmc->supply.vmmc)) 534 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 535 536 /* disable signal resampling */ 537 writel(0, host->regs + host->data->adjust); 538 539 break; 540 541 case MMC_POWER_ON: 542 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 543 int ret = regulator_enable(mmc->supply.vqmmc); 544 545 if (ret < 0) 546 dev_err(host->dev, 547 "failed to enable vqmmc regulator\n"); 548 else 549 host->vqmmc_enabled = true; 550 } 551 552 break; 553 } 554 555 /* Bus width */ 556 switch (ios->bus_width) { 557 case MMC_BUS_WIDTH_1: 558 bus_width = CFG_BUS_WIDTH_1; 559 break; 560 case MMC_BUS_WIDTH_4: 561 bus_width = CFG_BUS_WIDTH_4; 562 break; 563 case MMC_BUS_WIDTH_8: 564 bus_width = CFG_BUS_WIDTH_8; 565 break; 566 default: 567 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 568 ios->bus_width); 569 bus_width = CFG_BUS_WIDTH_4; 570 } 571 572 val = readl(host->regs + SD_EMMC_CFG); 573 val &= ~CFG_BUS_WIDTH_MASK; 574 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 575 writel(val, host->regs + SD_EMMC_CFG); 576 577 err = meson_mmc_prepare_ios_clock(host, ios); 578 if (err) 579 dev_err(host->dev, "Failed to set clock: %d\n,", err); 580 581 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 582 } 583 584 static void meson_mmc_request_done(struct mmc_host *mmc, 585 struct mmc_request *mrq) 586 { 587 struct meson_host *host = mmc_priv(mmc); 588 589 host->cmd = NULL; 590 mmc_request_done(host->mmc, mrq); 591 } 592 593 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 594 { 595 struct meson_host *host = mmc_priv(mmc); 596 u32 cfg, blksz_old; 597 598 cfg = readl(host->regs + SD_EMMC_CFG); 599 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 600 601 if (!is_power_of_2(blksz)) 602 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 603 604 blksz = ilog2(blksz); 605 606 /* check if block-size matches, if not update */ 607 if (blksz == blksz_old) 608 return; 609 610 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 611 blksz_old, blksz); 612 613 cfg &= ~CFG_BLK_LEN_MASK; 614 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 615 writel(cfg, host->regs + SD_EMMC_CFG); 616 } 617 618 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 619 { 620 if (cmd->flags & MMC_RSP_PRESENT) { 621 if (cmd->flags & MMC_RSP_136) 622 *cmd_cfg |= CMD_CFG_RESP_128; 623 *cmd_cfg |= CMD_CFG_RESP_NUM; 624 625 if (!(cmd->flags & MMC_RSP_CRC)) 626 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 627 628 if (cmd->flags & MMC_RSP_BUSY) 629 *cmd_cfg |= CMD_CFG_R1B; 630 } else { 631 *cmd_cfg |= CMD_CFG_NO_RESP; 632 } 633 } 634 635 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 636 { 637 struct meson_host *host = mmc_priv(mmc); 638 struct sd_emmc_desc *desc = host->descs; 639 struct mmc_data *data = host->cmd->data; 640 struct scatterlist *sg; 641 u32 start; 642 int i; 643 644 if (data->flags & MMC_DATA_WRITE) 645 cmd_cfg |= CMD_CFG_DATA_WR; 646 647 if (data->blocks > 1) { 648 cmd_cfg |= CMD_CFG_BLOCK_MODE; 649 meson_mmc_set_blksz(mmc, data->blksz); 650 } 651 652 for_each_sg(data->sg, sg, data->sg_count, i) { 653 unsigned int len = sg_dma_len(sg); 654 655 if (data->blocks > 1) 656 len /= data->blksz; 657 658 desc[i].cmd_cfg = cmd_cfg; 659 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 660 if (i > 0) 661 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 662 desc[i].cmd_arg = host->cmd->arg; 663 desc[i].cmd_resp = 0; 664 desc[i].cmd_data = sg_dma_address(sg); 665 } 666 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 667 668 dma_wmb(); /* ensure descriptor is written before kicked */ 669 start = host->descs_dma_addr | START_DESC_BUSY; 670 writel(start, host->regs + SD_EMMC_START); 671 } 672 673 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 674 { 675 struct meson_host *host = mmc_priv(mmc); 676 struct mmc_data *data = cmd->data; 677 u32 cmd_cfg = 0, cmd_data = 0; 678 unsigned int xfer_bytes = 0; 679 680 /* Setup descriptors */ 681 dma_rmb(); 682 683 host->cmd = cmd; 684 685 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 686 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 687 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 688 689 meson_mmc_set_response_bits(cmd, &cmd_cfg); 690 691 /* data? */ 692 if (data) { 693 data->bytes_xfered = 0; 694 cmd_cfg |= CMD_CFG_DATA_IO; 695 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 696 ilog2(meson_mmc_get_timeout_msecs(data))); 697 698 if (meson_mmc_desc_chain_mode(data)) { 699 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 700 return; 701 } 702 703 if (data->blocks > 1) { 704 cmd_cfg |= CMD_CFG_BLOCK_MODE; 705 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 706 data->blocks); 707 meson_mmc_set_blksz(mmc, data->blksz); 708 } else { 709 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 710 } 711 712 xfer_bytes = data->blksz * data->blocks; 713 if (data->flags & MMC_DATA_WRITE) { 714 cmd_cfg |= CMD_CFG_DATA_WR; 715 WARN_ON(xfer_bytes > host->bounce_buf_size); 716 sg_copy_to_buffer(data->sg, data->sg_len, 717 host->bounce_buf, xfer_bytes); 718 dma_wmb(); 719 } 720 721 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 722 } else { 723 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 724 ilog2(SD_EMMC_CMD_TIMEOUT)); 725 } 726 727 /* Last descriptor */ 728 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 729 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 730 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 731 writel(0, host->regs + SD_EMMC_CMD_RSP); 732 wmb(); /* ensure descriptor is written before kicked */ 733 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 734 } 735 736 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 737 { 738 struct meson_host *host = mmc_priv(mmc); 739 bool needs_pre_post_req = mrq->data && 740 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 741 742 if (needs_pre_post_req) { 743 meson_mmc_get_transfer_mode(mmc, mrq); 744 if (!meson_mmc_desc_chain_mode(mrq->data)) 745 needs_pre_post_req = false; 746 } 747 748 if (needs_pre_post_req) 749 meson_mmc_pre_req(mmc, mrq); 750 751 /* Stop execution */ 752 writel(0, host->regs + SD_EMMC_START); 753 754 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 755 756 if (needs_pre_post_req) 757 meson_mmc_post_req(mmc, mrq, 0); 758 } 759 760 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 761 { 762 struct meson_host *host = mmc_priv(mmc); 763 764 if (cmd->flags & MMC_RSP_136) { 765 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 766 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 767 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 768 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 769 } else if (cmd->flags & MMC_RSP_PRESENT) { 770 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 771 } 772 } 773 774 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 775 { 776 struct meson_host *host = dev_id; 777 struct mmc_command *cmd; 778 struct mmc_data *data; 779 u32 irq_en, status, raw_status; 780 irqreturn_t ret = IRQ_NONE; 781 782 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 783 raw_status = readl(host->regs + SD_EMMC_STATUS); 784 status = raw_status & irq_en; 785 786 if (!status) { 787 dev_dbg(host->dev, 788 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 789 irq_en, raw_status); 790 return IRQ_NONE; 791 } 792 793 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 794 return IRQ_NONE; 795 796 cmd = host->cmd; 797 data = cmd->data; 798 cmd->error = 0; 799 if (status & IRQ_CRC_ERR) { 800 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 801 cmd->error = -EILSEQ; 802 ret = IRQ_WAKE_THREAD; 803 goto out; 804 } 805 806 if (status & IRQ_TIMEOUTS) { 807 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 808 cmd->error = -ETIMEDOUT; 809 ret = IRQ_WAKE_THREAD; 810 goto out; 811 } 812 813 meson_mmc_read_resp(host->mmc, cmd); 814 815 if (status & IRQ_SDIO) { 816 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 817 ret = IRQ_HANDLED; 818 } 819 820 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 821 if (data && !cmd->error) 822 data->bytes_xfered = data->blksz * data->blocks; 823 if (meson_mmc_bounce_buf_read(data) || 824 meson_mmc_get_next_command(cmd)) 825 ret = IRQ_WAKE_THREAD; 826 else 827 ret = IRQ_HANDLED; 828 } 829 830 out: 831 if (cmd->error) { 832 /* Stop desc in case of errors */ 833 u32 start = readl(host->regs + SD_EMMC_START); 834 835 start &= ~START_DESC_BUSY; 836 writel(start, host->regs + SD_EMMC_START); 837 } 838 839 if (ret == IRQ_HANDLED) 840 meson_mmc_request_done(host->mmc, cmd->mrq); 841 842 /* ack all raised interrupts */ 843 writel(status, host->regs + SD_EMMC_STATUS); 844 845 return ret; 846 } 847 848 static int meson_mmc_wait_desc_stop(struct meson_host *host) 849 { 850 u32 status; 851 852 /* 853 * It may sometimes take a while for it to actually halt. Here, we 854 * are giving it 5ms to comply 855 * 856 * If we don't confirm the descriptor is stopped, it might raise new 857 * IRQs after we have called mmc_request_done() which is bad. 858 */ 859 860 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 861 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 862 100, 5000); 863 } 864 865 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 866 { 867 struct meson_host *host = dev_id; 868 struct mmc_command *next_cmd, *cmd = host->cmd; 869 struct mmc_data *data; 870 unsigned int xfer_bytes; 871 872 if (WARN_ON(!cmd)) 873 return IRQ_NONE; 874 875 if (cmd->error) { 876 meson_mmc_wait_desc_stop(host); 877 meson_mmc_request_done(host->mmc, cmd->mrq); 878 879 return IRQ_HANDLED; 880 } 881 882 data = cmd->data; 883 if (meson_mmc_bounce_buf_read(data)) { 884 xfer_bytes = data->blksz * data->blocks; 885 WARN_ON(xfer_bytes > host->bounce_buf_size); 886 sg_copy_from_buffer(data->sg, data->sg_len, 887 host->bounce_buf, xfer_bytes); 888 } 889 890 next_cmd = meson_mmc_get_next_command(cmd); 891 if (next_cmd) 892 meson_mmc_start_cmd(host->mmc, next_cmd); 893 else 894 meson_mmc_request_done(host->mmc, cmd->mrq); 895 896 return IRQ_HANDLED; 897 } 898 899 /* 900 * NOTE: we only need this until the GPIO/pinctrl driver can handle 901 * interrupts. For now, the MMC core will use this for polling. 902 */ 903 static int meson_mmc_get_cd(struct mmc_host *mmc) 904 { 905 int status = mmc_gpio_get_cd(mmc); 906 907 if (status == -ENOSYS) 908 return 1; /* assume present */ 909 910 return status; 911 } 912 913 static void meson_mmc_cfg_init(struct meson_host *host) 914 { 915 u32 cfg = 0; 916 917 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 918 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 919 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 920 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 921 922 /* abort chain on R/W errors */ 923 cfg |= CFG_ERR_ABORT; 924 925 writel(cfg, host->regs + SD_EMMC_CFG); 926 } 927 928 static int meson_mmc_card_busy(struct mmc_host *mmc) 929 { 930 struct meson_host *host = mmc_priv(mmc); 931 u32 regval; 932 933 regval = readl(host->regs + SD_EMMC_STATUS); 934 935 /* We are only interrested in lines 0 to 3, so mask the other ones */ 936 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 937 } 938 939 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 940 { 941 /* vqmmc regulator is available */ 942 if (!IS_ERR(mmc->supply.vqmmc)) { 943 /* 944 * The usual amlogic setup uses a GPIO to switch from one 945 * regulator to the other. While the voltage ramp up is 946 * pretty fast, care must be taken when switching from 3.3v 947 * to 1.8v. Please make sure the regulator framework is aware 948 * of your own regulator constraints 949 */ 950 return mmc_regulator_set_vqmmc(mmc, ios); 951 } 952 953 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 954 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 955 return 0; 956 957 return -EINVAL; 958 } 959 960 static const struct mmc_host_ops meson_mmc_ops = { 961 .request = meson_mmc_request, 962 .set_ios = meson_mmc_set_ios, 963 .get_cd = meson_mmc_get_cd, 964 .pre_req = meson_mmc_pre_req, 965 .post_req = meson_mmc_post_req, 966 .card_busy = meson_mmc_card_busy, 967 .start_signal_voltage_switch = meson_mmc_voltage_switch, 968 }; 969 970 static int meson_mmc_probe(struct platform_device *pdev) 971 { 972 struct resource *res; 973 struct meson_host *host; 974 struct mmc_host *mmc; 975 int ret; 976 977 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 978 if (!mmc) 979 return -ENOMEM; 980 host = mmc_priv(mmc); 981 host->mmc = mmc; 982 host->dev = &pdev->dev; 983 dev_set_drvdata(&pdev->dev, host); 984 985 /* Get regulators and the supported OCR mask */ 986 host->vqmmc_enabled = false; 987 ret = mmc_regulator_get_supply(mmc); 988 if (ret) 989 goto free_host; 990 991 ret = mmc_of_parse(mmc); 992 if (ret) { 993 if (ret != -EPROBE_DEFER) 994 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 995 goto free_host; 996 } 997 998 host->data = (struct meson_mmc_data *) 999 of_device_get_match_data(&pdev->dev); 1000 if (!host->data) { 1001 ret = -EINVAL; 1002 goto free_host; 1003 } 1004 1005 ret = device_reset_optional(&pdev->dev); 1006 if (ret) { 1007 if (ret != -EPROBE_DEFER) 1008 dev_err(&pdev->dev, "device reset failed: %d\n", ret); 1009 1010 return ret; 1011 } 1012 1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1014 host->regs = devm_ioremap_resource(&pdev->dev, res); 1015 if (IS_ERR(host->regs)) { 1016 ret = PTR_ERR(host->regs); 1017 goto free_host; 1018 } 1019 1020 host->irq = platform_get_irq(pdev, 0); 1021 if (host->irq <= 0) { 1022 dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 1023 ret = -EINVAL; 1024 goto free_host; 1025 } 1026 1027 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1028 if (IS_ERR(host->pinctrl)) { 1029 ret = PTR_ERR(host->pinctrl); 1030 goto free_host; 1031 } 1032 1033 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1034 PINCTRL_STATE_DEFAULT); 1035 if (IS_ERR(host->pins_default)) { 1036 ret = PTR_ERR(host->pins_default); 1037 goto free_host; 1038 } 1039 1040 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1041 "clk-gate"); 1042 if (IS_ERR(host->pins_clk_gate)) { 1043 dev_warn(&pdev->dev, 1044 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1045 host->pins_clk_gate = NULL; 1046 } 1047 1048 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1049 if (IS_ERR(host->core_clk)) { 1050 ret = PTR_ERR(host->core_clk); 1051 goto free_host; 1052 } 1053 1054 ret = clk_prepare_enable(host->core_clk); 1055 if (ret) 1056 goto free_host; 1057 1058 ret = meson_mmc_clk_init(host); 1059 if (ret) 1060 goto err_core_clk; 1061 1062 /* set config to sane default */ 1063 meson_mmc_cfg_init(host); 1064 1065 /* Stop execution */ 1066 writel(0, host->regs + SD_EMMC_START); 1067 1068 /* clear, ack and enable interrupts */ 1069 writel(0, host->regs + SD_EMMC_IRQ_EN); 1070 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1071 host->regs + SD_EMMC_STATUS); 1072 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1073 host->regs + SD_EMMC_IRQ_EN); 1074 1075 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1076 meson_mmc_irq_thread, IRQF_ONESHOT, 1077 dev_name(&pdev->dev), host); 1078 if (ret) 1079 goto err_init_clk; 1080 1081 mmc->caps |= MMC_CAP_CMD23; 1082 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1083 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1084 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); 1085 mmc->max_seg_size = mmc->max_req_size; 1086 1087 /* 1088 * At the moment, we don't know how to reliably enable HS400. 1089 * From the different datasheets, it is not even clear if this mode 1090 * is officially supported by any of the SoCs 1091 */ 1092 mmc->caps2 &= ~MMC_CAP2_HS400; 1093 1094 /* data bounce buffer */ 1095 host->bounce_buf_size = mmc->max_req_size; 1096 host->bounce_buf = 1097 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1098 &host->bounce_dma_addr, GFP_KERNEL); 1099 if (host->bounce_buf == NULL) { 1100 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1101 ret = -ENOMEM; 1102 goto err_free_irq; 1103 } 1104 1105 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1106 &host->descs_dma_addr, GFP_KERNEL); 1107 if (!host->descs) { 1108 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1109 ret = -ENOMEM; 1110 goto err_bounce_buf; 1111 } 1112 1113 mmc->ops = &meson_mmc_ops; 1114 mmc_add_host(mmc); 1115 1116 return 0; 1117 1118 err_bounce_buf: 1119 dma_free_coherent(host->dev, host->bounce_buf_size, 1120 host->bounce_buf, host->bounce_dma_addr); 1121 err_free_irq: 1122 free_irq(host->irq, host); 1123 err_init_clk: 1124 clk_disable_unprepare(host->mmc_clk); 1125 err_core_clk: 1126 clk_disable_unprepare(host->core_clk); 1127 free_host: 1128 mmc_free_host(mmc); 1129 return ret; 1130 } 1131 1132 static int meson_mmc_remove(struct platform_device *pdev) 1133 { 1134 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1135 1136 mmc_remove_host(host->mmc); 1137 1138 /* disable interrupts */ 1139 writel(0, host->regs + SD_EMMC_IRQ_EN); 1140 free_irq(host->irq, host); 1141 1142 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1143 host->descs, host->descs_dma_addr); 1144 dma_free_coherent(host->dev, host->bounce_buf_size, 1145 host->bounce_buf, host->bounce_dma_addr); 1146 1147 clk_disable_unprepare(host->mmc_clk); 1148 clk_disable_unprepare(host->core_clk); 1149 1150 mmc_free_host(host->mmc); 1151 return 0; 1152 } 1153 1154 static const struct meson_mmc_data meson_gx_data = { 1155 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1156 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1157 .always_on = CLK_V2_ALWAYS_ON, 1158 .adjust = SD_EMMC_ADJUST, 1159 }; 1160 1161 static const struct meson_mmc_data meson_axg_data = { 1162 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1163 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1164 .always_on = CLK_V3_ALWAYS_ON, 1165 .adjust = SD_EMMC_V3_ADJUST, 1166 }; 1167 1168 static const struct of_device_id meson_mmc_of_match[] = { 1169 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1170 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1171 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1172 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1173 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1174 {} 1175 }; 1176 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1177 1178 static struct platform_driver meson_mmc_driver = { 1179 .probe = meson_mmc_probe, 1180 .remove = meson_mmc_remove, 1181 .driver = { 1182 .name = DRIVER_NAME, 1183 .of_match_table = of_match_ptr(meson_mmc_of_match), 1184 }, 1185 }; 1186 1187 module_platform_driver(meson_mmc_driver); 1188 1189 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1190 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1191 MODULE_LICENSE("GPL v2"); 1192