1 /* 2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Kevin Hilman <khilman@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * The full GNU General Public License is included in this distribution 19 * in the file called COPYING. 20 */ 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/ioport.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 #include <linux/io.h> 35 #include <linux/clk.h> 36 #include <linux/clk-provider.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/interrupt.h> 40 #include <linux/bitfield.h> 41 #include <linux/pinctrl/consumer.h> 42 43 #define DRIVER_NAME "meson-gx-mmc" 44 45 #define SD_EMMC_CLOCK 0x0 46 #define CLK_DIV_MASK GENMASK(5, 0) 47 #define CLK_SRC_MASK GENMASK(7, 6) 48 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 49 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 50 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 51 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 52 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 53 #define CLK_V2_ALWAYS_ON BIT(24) 54 55 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 56 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 57 #define CLK_V3_ALWAYS_ON BIT(28) 58 59 #define CLK_DELAY_STEP_PS 200 60 #define CLK_PHASE_STEP 30 61 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) 62 63 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 64 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 65 #define CLK_ALWAYS_ON(h) (h->data->always_on) 66 67 #define SD_EMMC_DELAY 0x4 68 #define SD_EMMC_ADJUST 0x8 69 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 70 #define ADJUST_DS_EN BIT(15) 71 #define ADJUST_ADJ_EN BIT(13) 72 73 #define SD_EMMC_DELAY1 0x4 74 #define SD_EMMC_DELAY2 0x8 75 #define SD_EMMC_V3_ADJUST 0xc 76 77 #define SD_EMMC_CALOUT 0x10 78 #define SD_EMMC_START 0x40 79 #define START_DESC_INIT BIT(0) 80 #define START_DESC_BUSY BIT(1) 81 #define START_DESC_ADDR_MASK GENMASK(31, 2) 82 83 #define SD_EMMC_CFG 0x44 84 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 85 #define CFG_BUS_WIDTH_1 0x0 86 #define CFG_BUS_WIDTH_4 0x1 87 #define CFG_BUS_WIDTH_8 0x2 88 #define CFG_DDR BIT(2) 89 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 90 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 91 #define CFG_RC_CC_MASK GENMASK(15, 12) 92 #define CFG_STOP_CLOCK BIT(22) 93 #define CFG_CLK_ALWAYS_ON BIT(18) 94 #define CFG_CHK_DS BIT(20) 95 #define CFG_AUTO_CLK BIT(23) 96 #define CFG_ERR_ABORT BIT(27) 97 98 #define SD_EMMC_STATUS 0x48 99 #define STATUS_BUSY BIT(31) 100 #define STATUS_DESC_BUSY BIT(30) 101 #define STATUS_DATI GENMASK(23, 16) 102 103 #define SD_EMMC_IRQ_EN 0x4c 104 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 105 #define IRQ_TXD_ERR BIT(8) 106 #define IRQ_DESC_ERR BIT(9) 107 #define IRQ_RESP_ERR BIT(10) 108 #define IRQ_CRC_ERR \ 109 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 110 #define IRQ_RESP_TIMEOUT BIT(11) 111 #define IRQ_DESC_TIMEOUT BIT(12) 112 #define IRQ_TIMEOUTS \ 113 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 114 #define IRQ_END_OF_CHAIN BIT(13) 115 #define IRQ_RESP_STATUS BIT(14) 116 #define IRQ_SDIO BIT(15) 117 #define IRQ_EN_MASK \ 118 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 119 IRQ_SDIO) 120 121 #define SD_EMMC_CMD_CFG 0x50 122 #define SD_EMMC_CMD_ARG 0x54 123 #define SD_EMMC_CMD_DAT 0x58 124 #define SD_EMMC_CMD_RSP 0x5c 125 #define SD_EMMC_CMD_RSP1 0x60 126 #define SD_EMMC_CMD_RSP2 0x64 127 #define SD_EMMC_CMD_RSP3 0x68 128 129 #define SD_EMMC_RXD 0x94 130 #define SD_EMMC_TXD 0x94 131 #define SD_EMMC_LAST_REG SD_EMMC_TXD 132 133 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 134 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 135 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 136 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 137 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 138 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 139 140 #define SD_EMMC_PRE_REQ_DONE BIT(0) 141 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 142 143 #define MUX_CLK_NUM_PARENTS 2 144 145 struct meson_mmc_data { 146 unsigned int tx_delay_mask; 147 unsigned int rx_delay_mask; 148 unsigned int always_on; 149 unsigned int adjust; 150 }; 151 152 struct sd_emmc_desc { 153 u32 cmd_cfg; 154 u32 cmd_arg; 155 u32 cmd_data; 156 u32 cmd_resp; 157 }; 158 159 struct meson_host { 160 struct device *dev; 161 struct meson_mmc_data *data; 162 struct mmc_host *mmc; 163 struct mmc_command *cmd; 164 165 void __iomem *regs; 166 struct clk *core_clk; 167 struct clk *mmc_clk; 168 struct clk *rx_clk; 169 struct clk *tx_clk; 170 unsigned long req_rate; 171 172 struct pinctrl *pinctrl; 173 struct pinctrl_state *pins_default; 174 struct pinctrl_state *pins_clk_gate; 175 176 unsigned int bounce_buf_size; 177 void *bounce_buf; 178 dma_addr_t bounce_dma_addr; 179 struct sd_emmc_desc *descs; 180 dma_addr_t descs_dma_addr; 181 182 int irq; 183 184 bool vqmmc_enabled; 185 }; 186 187 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 188 #define CMD_CFG_BLOCK_MODE BIT(9) 189 #define CMD_CFG_R1B BIT(10) 190 #define CMD_CFG_END_OF_CHAIN BIT(11) 191 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 192 #define CMD_CFG_NO_RESP BIT(16) 193 #define CMD_CFG_NO_CMD BIT(17) 194 #define CMD_CFG_DATA_IO BIT(18) 195 #define CMD_CFG_DATA_WR BIT(19) 196 #define CMD_CFG_RESP_NOCRC BIT(20) 197 #define CMD_CFG_RESP_128 BIT(21) 198 #define CMD_CFG_RESP_NUM BIT(22) 199 #define CMD_CFG_DATA_NUM BIT(23) 200 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 201 #define CMD_CFG_ERROR BIT(30) 202 #define CMD_CFG_OWNER BIT(31) 203 204 #define CMD_DATA_MASK GENMASK(31, 2) 205 #define CMD_DATA_BIG_ENDIAN BIT(1) 206 #define CMD_DATA_SRAM BIT(0) 207 #define CMD_RESP_MASK GENMASK(31, 1) 208 #define CMD_RESP_SRAM BIT(0) 209 210 struct meson_mmc_phase { 211 struct clk_hw hw; 212 void __iomem *reg; 213 unsigned long phase_mask; 214 unsigned long delay_mask; 215 unsigned int delay_step_ps; 216 }; 217 218 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw) 219 220 static int meson_mmc_clk_get_phase(struct clk_hw *hw) 221 { 222 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); 223 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); 224 unsigned long period_ps, p, d; 225 int degrees; 226 u32 val; 227 228 val = readl(mmc->reg); 229 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask); 230 degrees = p * 360 / phase_num; 231 232 if (mmc->delay_mask) { 233 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, 234 clk_get_rate(hw->clk)); 235 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask); 236 degrees += d * mmc->delay_step_ps * 360 / period_ps; 237 degrees %= 360; 238 } 239 240 return degrees; 241 } 242 243 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc, 244 unsigned int phase, 245 unsigned int delay) 246 { 247 u32 val; 248 249 val = readl(mmc->reg); 250 val &= ~mmc->phase_mask; 251 val |= phase << __ffs(mmc->phase_mask); 252 253 if (mmc->delay_mask) { 254 val &= ~mmc->delay_mask; 255 val |= delay << __ffs(mmc->delay_mask); 256 } 257 258 writel(val, mmc->reg); 259 } 260 261 static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees) 262 { 263 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); 264 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); 265 unsigned long period_ps, d = 0, r; 266 uint64_t p; 267 268 p = degrees % 360; 269 270 if (!mmc->delay_mask) { 271 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); 272 } else { 273 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, 274 clk_get_rate(hw->clk)); 275 276 /* First compute the phase index (p), the remainder (r) is the 277 * part we'll try to acheive using the delays (d). 278 */ 279 r = do_div(p, 360 / phase_num); 280 d = DIV_ROUND_CLOSEST(r * period_ps, 281 360 * mmc->delay_step_ps); 282 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask)); 283 } 284 285 meson_mmc_apply_phase_delay(mmc, p, d); 286 return 0; 287 } 288 289 static const struct clk_ops meson_mmc_clk_phase_ops = { 290 .get_phase = meson_mmc_clk_get_phase, 291 .set_phase = meson_mmc_clk_set_phase, 292 }; 293 294 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 295 { 296 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 297 298 if (!timeout) 299 return SD_EMMC_CMD_TIMEOUT_DATA; 300 301 timeout = roundup_pow_of_two(timeout); 302 303 return min(timeout, 32768U); /* max. 2^15 ms */ 304 } 305 306 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 307 { 308 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 309 return cmd->mrq->cmd; 310 else if (mmc_op_multi(cmd->opcode) && 311 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 312 return cmd->mrq->stop; 313 else 314 return NULL; 315 } 316 317 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 318 struct mmc_request *mrq) 319 { 320 struct mmc_data *data = mrq->data; 321 struct scatterlist *sg; 322 int i; 323 bool use_desc_chain_mode = true; 324 325 /* 326 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 327 * reported. For some strange reason this occurs in descriptor 328 * chain mode only. So let's fall back to bounce buffer mode 329 * for command SD_IO_RW_EXTENDED. 330 */ 331 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 332 return; 333 334 for_each_sg(data->sg, sg, data->sg_len, i) 335 /* check for 8 byte alignment */ 336 if (sg->offset & 7) { 337 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 338 use_desc_chain_mode = false; 339 break; 340 } 341 342 if (use_desc_chain_mode) 343 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 344 } 345 346 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 347 { 348 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 349 } 350 351 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 352 { 353 return data && data->flags & MMC_DATA_READ && 354 !meson_mmc_desc_chain_mode(data); 355 } 356 357 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 358 { 359 struct mmc_data *data = mrq->data; 360 361 if (!data) 362 return; 363 364 meson_mmc_get_transfer_mode(mmc, mrq); 365 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 366 367 if (!meson_mmc_desc_chain_mode(data)) 368 return; 369 370 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 371 mmc_get_dma_dir(data)); 372 if (!data->sg_count) 373 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 374 } 375 376 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 377 int err) 378 { 379 struct mmc_data *data = mrq->data; 380 381 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 382 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 383 mmc_get_dma_dir(data)); 384 } 385 386 static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) 387 { 388 if (ios->timing == MMC_TIMING_MMC_DDR52 || 389 ios->timing == MMC_TIMING_UHS_DDR50 || 390 ios->timing == MMC_TIMING_MMC_HS400) 391 return true; 392 393 return false; 394 } 395 396 /* 397 * Gating the clock on this controller is tricky. It seems the mmc clock 398 * is also used by the controller. It may crash during some operation if the 399 * clock is stopped. The safest thing to do, whenever possible, is to keep 400 * clock running at stop it at the pad using the pinmux. 401 */ 402 static void meson_mmc_clk_gate(struct meson_host *host) 403 { 404 u32 cfg; 405 406 if (host->pins_clk_gate) { 407 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 408 } else { 409 /* 410 * If the pinmux is not provided - default to the classic and 411 * unsafe method 412 */ 413 cfg = readl(host->regs + SD_EMMC_CFG); 414 cfg |= CFG_STOP_CLOCK; 415 writel(cfg, host->regs + SD_EMMC_CFG); 416 } 417 } 418 419 static void meson_mmc_clk_ungate(struct meson_host *host) 420 { 421 u32 cfg; 422 423 if (host->pins_clk_gate) 424 pinctrl_select_state(host->pinctrl, host->pins_default); 425 426 /* Make sure the clock is not stopped in the controller */ 427 cfg = readl(host->regs + SD_EMMC_CFG); 428 cfg &= ~CFG_STOP_CLOCK; 429 writel(cfg, host->regs + SD_EMMC_CFG); 430 } 431 432 static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) 433 { 434 struct mmc_host *mmc = host->mmc; 435 unsigned long rate = ios->clock; 436 int ret; 437 u32 cfg; 438 439 /* DDR modes require higher module clock */ 440 if (meson_mmc_timing_is_ddr(ios)) 441 rate <<= 1; 442 443 /* Same request - bail-out */ 444 if (host->req_rate == rate) 445 return 0; 446 447 /* stop clock */ 448 meson_mmc_clk_gate(host); 449 host->req_rate = 0; 450 451 if (!rate) { 452 mmc->actual_clock = 0; 453 /* return with clock being stopped */ 454 return 0; 455 } 456 457 /* Stop the clock during rate change to avoid glitches */ 458 cfg = readl(host->regs + SD_EMMC_CFG); 459 cfg |= CFG_STOP_CLOCK; 460 writel(cfg, host->regs + SD_EMMC_CFG); 461 462 ret = clk_set_rate(host->mmc_clk, rate); 463 if (ret) { 464 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 465 rate, ret); 466 return ret; 467 } 468 469 host->req_rate = rate; 470 mmc->actual_clock = clk_get_rate(host->mmc_clk); 471 472 /* We should report the real output frequency of the controller */ 473 if (meson_mmc_timing_is_ddr(ios)) 474 mmc->actual_clock >>= 1; 475 476 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 477 if (ios->clock != mmc->actual_clock) 478 dev_dbg(host->dev, "requested rate was %u\n", ios->clock); 479 480 /* (re)start clock */ 481 meson_mmc_clk_ungate(host); 482 483 return 0; 484 } 485 486 /* 487 * The SD/eMMC IP block has an internal mux and divider used for 488 * generating the MMC clock. Use the clock framework to create and 489 * manage these clocks. 490 */ 491 static int meson_mmc_clk_init(struct meson_host *host) 492 { 493 struct clk_init_data init; 494 struct clk_mux *mux; 495 struct clk_divider *div; 496 struct meson_mmc_phase *core, *tx, *rx; 497 struct clk *clk; 498 char clk_name[32]; 499 int i, ret = 0; 500 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 501 const char *clk_parent[1]; 502 u32 clk_reg; 503 504 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 505 clk_reg = 0; 506 clk_reg |= CLK_ALWAYS_ON(host); 507 clk_reg |= CLK_DIV_MASK; 508 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 509 510 /* get the mux parents */ 511 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 512 struct clk *clk; 513 char name[16]; 514 515 snprintf(name, sizeof(name), "clkin%d", i); 516 clk = devm_clk_get(host->dev, name); 517 if (IS_ERR(clk)) { 518 if (clk != ERR_PTR(-EPROBE_DEFER)) 519 dev_err(host->dev, "Missing clock %s\n", name); 520 return PTR_ERR(clk); 521 } 522 523 mux_parent_names[i] = __clk_get_name(clk); 524 } 525 526 /* create the mux */ 527 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 528 if (!mux) 529 return -ENOMEM; 530 531 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 532 init.name = clk_name; 533 init.ops = &clk_mux_ops; 534 init.flags = 0; 535 init.parent_names = mux_parent_names; 536 init.num_parents = MUX_CLK_NUM_PARENTS; 537 538 mux->reg = host->regs + SD_EMMC_CLOCK; 539 mux->shift = __ffs(CLK_SRC_MASK); 540 mux->mask = CLK_SRC_MASK >> mux->shift; 541 mux->hw.init = &init; 542 543 clk = devm_clk_register(host->dev, &mux->hw); 544 if (WARN_ON(IS_ERR(clk))) 545 return PTR_ERR(clk); 546 547 /* create the divider */ 548 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 549 if (!div) 550 return -ENOMEM; 551 552 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 553 init.name = clk_name; 554 init.ops = &clk_divider_ops; 555 init.flags = CLK_SET_RATE_PARENT; 556 clk_parent[0] = __clk_get_name(clk); 557 init.parent_names = clk_parent; 558 init.num_parents = 1; 559 560 div->reg = host->regs + SD_EMMC_CLOCK; 561 div->shift = __ffs(CLK_DIV_MASK); 562 div->width = __builtin_popcountl(CLK_DIV_MASK); 563 div->hw.init = &init; 564 div->flags = CLK_DIVIDER_ONE_BASED; 565 566 clk = devm_clk_register(host->dev, &div->hw); 567 if (WARN_ON(IS_ERR(clk))) 568 return PTR_ERR(clk); 569 570 /* create the mmc core clock */ 571 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL); 572 if (!core) 573 return -ENOMEM; 574 575 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev)); 576 init.name = clk_name; 577 init.ops = &meson_mmc_clk_phase_ops; 578 init.flags = CLK_SET_RATE_PARENT; 579 clk_parent[0] = __clk_get_name(clk); 580 init.parent_names = clk_parent; 581 init.num_parents = 1; 582 583 core->reg = host->regs + SD_EMMC_CLOCK; 584 core->phase_mask = CLK_CORE_PHASE_MASK; 585 core->hw.init = &init; 586 587 host->mmc_clk = devm_clk_register(host->dev, &core->hw); 588 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) 589 return PTR_ERR(host->mmc_clk); 590 591 /* create the mmc tx clock */ 592 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL); 593 if (!tx) 594 return -ENOMEM; 595 596 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev)); 597 init.name = clk_name; 598 init.ops = &meson_mmc_clk_phase_ops; 599 init.flags = 0; 600 clk_parent[0] = __clk_get_name(host->mmc_clk); 601 init.parent_names = clk_parent; 602 init.num_parents = 1; 603 604 tx->reg = host->regs + SD_EMMC_CLOCK; 605 tx->phase_mask = CLK_TX_PHASE_MASK; 606 tx->delay_mask = CLK_TX_DELAY_MASK(host); 607 tx->delay_step_ps = CLK_DELAY_STEP_PS; 608 tx->hw.init = &init; 609 610 host->tx_clk = devm_clk_register(host->dev, &tx->hw); 611 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk))) 612 return PTR_ERR(host->tx_clk); 613 614 /* create the mmc rx clock */ 615 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL); 616 if (!rx) 617 return -ENOMEM; 618 619 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev)); 620 init.name = clk_name; 621 init.ops = &meson_mmc_clk_phase_ops; 622 init.flags = 0; 623 clk_parent[0] = __clk_get_name(host->mmc_clk); 624 init.parent_names = clk_parent; 625 init.num_parents = 1; 626 627 rx->reg = host->regs + SD_EMMC_CLOCK; 628 rx->phase_mask = CLK_RX_PHASE_MASK; 629 rx->delay_mask = CLK_RX_DELAY_MASK(host); 630 rx->delay_step_ps = CLK_DELAY_STEP_PS; 631 rx->hw.init = &init; 632 633 host->rx_clk = devm_clk_register(host->dev, &rx->hw); 634 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) 635 return PTR_ERR(host->rx_clk); 636 637 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 638 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 639 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 640 if (ret) 641 return ret; 642 643 clk_set_phase(host->mmc_clk, 180); 644 clk_set_phase(host->tx_clk, 0); 645 clk_set_phase(host->rx_clk, 0); 646 647 return clk_prepare_enable(host->mmc_clk); 648 } 649 650 static void meson_mmc_shift_map(unsigned long *map, unsigned long shift) 651 { 652 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM); 653 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM); 654 655 /* 656 * shift the bitmap right and reintroduce the dropped bits on the left 657 * of the bitmap 658 */ 659 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM); 660 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift, 661 CLK_PHASE_POINT_NUM); 662 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM); 663 } 664 665 static void meson_mmc_find_next_region(unsigned long *map, 666 unsigned long *start, 667 unsigned long *stop) 668 { 669 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start); 670 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start); 671 } 672 673 static int meson_mmc_find_tuning_point(unsigned long *test) 674 { 675 unsigned long shift, stop, offset = 0, start = 0, size = 0; 676 677 /* Get the all good/all bad situation out the way */ 678 if (bitmap_full(test, CLK_PHASE_POINT_NUM)) 679 return 0; /* All points are good so point 0 will do */ 680 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM)) 681 return -EIO; /* No successful tuning point */ 682 683 /* 684 * Now we know there is a least one region find. Make sure it does 685 * not wrap by the shifting the bitmap if necessary 686 */ 687 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM); 688 if (shift != 0) 689 meson_mmc_shift_map(test, shift); 690 691 while (start < CLK_PHASE_POINT_NUM) { 692 meson_mmc_find_next_region(test, &start, &stop); 693 694 if ((stop - start) > size) { 695 offset = start; 696 size = stop - start; 697 } 698 699 start = stop; 700 } 701 702 /* Get the center point of the region */ 703 offset += (size / 2); 704 705 /* Shift the result back */ 706 offset = (offset + shift) % CLK_PHASE_POINT_NUM; 707 708 return offset; 709 } 710 711 static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, 712 struct clk *clk) 713 { 714 int point, ret; 715 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM); 716 717 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n", 718 __clk_get_name(clk)); 719 bitmap_zero(test, CLK_PHASE_POINT_NUM); 720 721 /* Explore tuning points */ 722 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) { 723 clk_set_phase(clk, point * CLK_PHASE_STEP); 724 ret = mmc_send_tuning(mmc, opcode, NULL); 725 if (!ret) 726 set_bit(point, test); 727 } 728 729 /* Find the optimal tuning point and apply it */ 730 point = meson_mmc_find_tuning_point(test); 731 if (point < 0) 732 return point; /* tuning failed */ 733 734 clk_set_phase(clk, point * CLK_PHASE_STEP); 735 dev_dbg(mmc_dev(mmc), "success with phase: %d\n", 736 clk_get_phase(clk)); 737 return 0; 738 } 739 740 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 741 { 742 struct meson_host *host = mmc_priv(mmc); 743 int adj = 0; 744 745 /* enable signal resampling w/o delay */ 746 adj = ADJUST_ADJ_EN; 747 writel(adj, host->regs + host->data->adjust); 748 749 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); 750 } 751 752 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 753 { 754 struct meson_host *host = mmc_priv(mmc); 755 u32 bus_width, val; 756 int err; 757 758 /* 759 * GPIO regulator, only controls switching between 1v8 and 760 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 761 */ 762 switch (ios->power_mode) { 763 case MMC_POWER_OFF: 764 if (!IS_ERR(mmc->supply.vmmc)) 765 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 766 767 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 768 regulator_disable(mmc->supply.vqmmc); 769 host->vqmmc_enabled = false; 770 } 771 772 break; 773 774 case MMC_POWER_UP: 775 if (!IS_ERR(mmc->supply.vmmc)) 776 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 777 778 /* disable signal resampling */ 779 writel(0, host->regs + host->data->adjust); 780 781 /* Reset rx phase */ 782 clk_set_phase(host->rx_clk, 0); 783 784 break; 785 786 case MMC_POWER_ON: 787 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 788 int ret = regulator_enable(mmc->supply.vqmmc); 789 790 if (ret < 0) 791 dev_err(host->dev, 792 "failed to enable vqmmc regulator\n"); 793 else 794 host->vqmmc_enabled = true; 795 } 796 797 break; 798 } 799 800 /* Bus width */ 801 switch (ios->bus_width) { 802 case MMC_BUS_WIDTH_1: 803 bus_width = CFG_BUS_WIDTH_1; 804 break; 805 case MMC_BUS_WIDTH_4: 806 bus_width = CFG_BUS_WIDTH_4; 807 break; 808 case MMC_BUS_WIDTH_8: 809 bus_width = CFG_BUS_WIDTH_8; 810 break; 811 default: 812 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 813 ios->bus_width); 814 bus_width = CFG_BUS_WIDTH_4; 815 } 816 817 val = readl(host->regs + SD_EMMC_CFG); 818 val &= ~CFG_BUS_WIDTH_MASK; 819 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 820 821 val &= ~CFG_DDR; 822 if (meson_mmc_timing_is_ddr(ios)) 823 val |= CFG_DDR; 824 825 val &= ~CFG_CHK_DS; 826 if (ios->timing == MMC_TIMING_MMC_HS400) 827 val |= CFG_CHK_DS; 828 829 err = meson_mmc_clk_set(host, ios); 830 if (err) 831 dev_err(host->dev, "Failed to set clock: %d\n,", err); 832 833 writel(val, host->regs + SD_EMMC_CFG); 834 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 835 } 836 837 static void meson_mmc_request_done(struct mmc_host *mmc, 838 struct mmc_request *mrq) 839 { 840 struct meson_host *host = mmc_priv(mmc); 841 842 host->cmd = NULL; 843 mmc_request_done(host->mmc, mrq); 844 } 845 846 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 847 { 848 struct meson_host *host = mmc_priv(mmc); 849 u32 cfg, blksz_old; 850 851 cfg = readl(host->regs + SD_EMMC_CFG); 852 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 853 854 if (!is_power_of_2(blksz)) 855 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 856 857 blksz = ilog2(blksz); 858 859 /* check if block-size matches, if not update */ 860 if (blksz == blksz_old) 861 return; 862 863 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 864 blksz_old, blksz); 865 866 cfg &= ~CFG_BLK_LEN_MASK; 867 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 868 writel(cfg, host->regs + SD_EMMC_CFG); 869 } 870 871 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 872 { 873 if (cmd->flags & MMC_RSP_PRESENT) { 874 if (cmd->flags & MMC_RSP_136) 875 *cmd_cfg |= CMD_CFG_RESP_128; 876 *cmd_cfg |= CMD_CFG_RESP_NUM; 877 878 if (!(cmd->flags & MMC_RSP_CRC)) 879 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 880 881 if (cmd->flags & MMC_RSP_BUSY) 882 *cmd_cfg |= CMD_CFG_R1B; 883 } else { 884 *cmd_cfg |= CMD_CFG_NO_RESP; 885 } 886 } 887 888 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 889 { 890 struct meson_host *host = mmc_priv(mmc); 891 struct sd_emmc_desc *desc = host->descs; 892 struct mmc_data *data = host->cmd->data; 893 struct scatterlist *sg; 894 u32 start; 895 int i; 896 897 if (data->flags & MMC_DATA_WRITE) 898 cmd_cfg |= CMD_CFG_DATA_WR; 899 900 if (data->blocks > 1) { 901 cmd_cfg |= CMD_CFG_BLOCK_MODE; 902 meson_mmc_set_blksz(mmc, data->blksz); 903 } 904 905 for_each_sg(data->sg, sg, data->sg_count, i) { 906 unsigned int len = sg_dma_len(sg); 907 908 if (data->blocks > 1) 909 len /= data->blksz; 910 911 desc[i].cmd_cfg = cmd_cfg; 912 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 913 if (i > 0) 914 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 915 desc[i].cmd_arg = host->cmd->arg; 916 desc[i].cmd_resp = 0; 917 desc[i].cmd_data = sg_dma_address(sg); 918 } 919 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 920 921 dma_wmb(); /* ensure descriptor is written before kicked */ 922 start = host->descs_dma_addr | START_DESC_BUSY; 923 writel(start, host->regs + SD_EMMC_START); 924 } 925 926 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 927 { 928 struct meson_host *host = mmc_priv(mmc); 929 struct mmc_data *data = cmd->data; 930 u32 cmd_cfg = 0, cmd_data = 0; 931 unsigned int xfer_bytes = 0; 932 933 /* Setup descriptors */ 934 dma_rmb(); 935 936 host->cmd = cmd; 937 938 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 939 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 940 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 941 942 meson_mmc_set_response_bits(cmd, &cmd_cfg); 943 944 /* data? */ 945 if (data) { 946 data->bytes_xfered = 0; 947 cmd_cfg |= CMD_CFG_DATA_IO; 948 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 949 ilog2(meson_mmc_get_timeout_msecs(data))); 950 951 if (meson_mmc_desc_chain_mode(data)) { 952 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 953 return; 954 } 955 956 if (data->blocks > 1) { 957 cmd_cfg |= CMD_CFG_BLOCK_MODE; 958 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 959 data->blocks); 960 meson_mmc_set_blksz(mmc, data->blksz); 961 } else { 962 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 963 } 964 965 xfer_bytes = data->blksz * data->blocks; 966 if (data->flags & MMC_DATA_WRITE) { 967 cmd_cfg |= CMD_CFG_DATA_WR; 968 WARN_ON(xfer_bytes > host->bounce_buf_size); 969 sg_copy_to_buffer(data->sg, data->sg_len, 970 host->bounce_buf, xfer_bytes); 971 dma_wmb(); 972 } 973 974 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 975 } else { 976 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 977 ilog2(SD_EMMC_CMD_TIMEOUT)); 978 } 979 980 /* Last descriptor */ 981 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 982 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 983 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 984 writel(0, host->regs + SD_EMMC_CMD_RSP); 985 wmb(); /* ensure descriptor is written before kicked */ 986 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 987 } 988 989 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 990 { 991 struct meson_host *host = mmc_priv(mmc); 992 bool needs_pre_post_req = mrq->data && 993 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 994 995 if (needs_pre_post_req) { 996 meson_mmc_get_transfer_mode(mmc, mrq); 997 if (!meson_mmc_desc_chain_mode(mrq->data)) 998 needs_pre_post_req = false; 999 } 1000 1001 if (needs_pre_post_req) 1002 meson_mmc_pre_req(mmc, mrq); 1003 1004 /* Stop execution */ 1005 writel(0, host->regs + SD_EMMC_START); 1006 1007 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 1008 1009 if (needs_pre_post_req) 1010 meson_mmc_post_req(mmc, mrq, 0); 1011 } 1012 1013 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 1014 { 1015 struct meson_host *host = mmc_priv(mmc); 1016 1017 if (cmd->flags & MMC_RSP_136) { 1018 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 1019 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 1020 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 1021 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 1022 } else if (cmd->flags & MMC_RSP_PRESENT) { 1023 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 1024 } 1025 } 1026 1027 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 1028 { 1029 struct meson_host *host = dev_id; 1030 struct mmc_command *cmd; 1031 struct mmc_data *data; 1032 u32 irq_en, status, raw_status; 1033 irqreturn_t ret = IRQ_NONE; 1034 1035 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 1036 raw_status = readl(host->regs + SD_EMMC_STATUS); 1037 status = raw_status & irq_en; 1038 1039 if (!status) { 1040 dev_dbg(host->dev, 1041 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 1042 irq_en, raw_status); 1043 return IRQ_NONE; 1044 } 1045 1046 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 1047 return IRQ_NONE; 1048 1049 cmd = host->cmd; 1050 data = cmd->data; 1051 cmd->error = 0; 1052 if (status & IRQ_CRC_ERR) { 1053 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 1054 cmd->error = -EILSEQ; 1055 ret = IRQ_WAKE_THREAD; 1056 goto out; 1057 } 1058 1059 if (status & IRQ_TIMEOUTS) { 1060 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 1061 cmd->error = -ETIMEDOUT; 1062 ret = IRQ_WAKE_THREAD; 1063 goto out; 1064 } 1065 1066 meson_mmc_read_resp(host->mmc, cmd); 1067 1068 if (status & IRQ_SDIO) { 1069 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 1070 ret = IRQ_HANDLED; 1071 } 1072 1073 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 1074 if (data && !cmd->error) 1075 data->bytes_xfered = data->blksz * data->blocks; 1076 if (meson_mmc_bounce_buf_read(data) || 1077 meson_mmc_get_next_command(cmd)) 1078 ret = IRQ_WAKE_THREAD; 1079 else 1080 ret = IRQ_HANDLED; 1081 } 1082 1083 out: 1084 /* ack all enabled interrupts */ 1085 writel(irq_en, host->regs + SD_EMMC_STATUS); 1086 1087 if (cmd->error) { 1088 /* Stop desc in case of errors */ 1089 u32 start = readl(host->regs + SD_EMMC_START); 1090 1091 start &= ~START_DESC_BUSY; 1092 writel(start, host->regs + SD_EMMC_START); 1093 } 1094 1095 if (ret == IRQ_HANDLED) 1096 meson_mmc_request_done(host->mmc, cmd->mrq); 1097 1098 return ret; 1099 } 1100 1101 static int meson_mmc_wait_desc_stop(struct meson_host *host) 1102 { 1103 int loop; 1104 u32 status; 1105 1106 /* 1107 * It may sometimes take a while for it to actually halt. Here, we 1108 * are giving it 5ms to comply 1109 * 1110 * If we don't confirm the descriptor is stopped, it might raise new 1111 * IRQs after we have called mmc_request_done() which is bad. 1112 */ 1113 for (loop = 50; loop; loop--) { 1114 status = readl(host->regs + SD_EMMC_STATUS); 1115 if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) 1116 udelay(100); 1117 else 1118 break; 1119 } 1120 1121 if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) { 1122 dev_err(host->dev, "Timed out waiting for host to stop\n"); 1123 return -ETIMEDOUT; 1124 } 1125 1126 return 0; 1127 } 1128 1129 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 1130 { 1131 struct meson_host *host = dev_id; 1132 struct mmc_command *next_cmd, *cmd = host->cmd; 1133 struct mmc_data *data; 1134 unsigned int xfer_bytes; 1135 1136 if (WARN_ON(!cmd)) 1137 return IRQ_NONE; 1138 1139 if (cmd->error) { 1140 meson_mmc_wait_desc_stop(host); 1141 meson_mmc_request_done(host->mmc, cmd->mrq); 1142 1143 return IRQ_HANDLED; 1144 } 1145 1146 data = cmd->data; 1147 if (meson_mmc_bounce_buf_read(data)) { 1148 xfer_bytes = data->blksz * data->blocks; 1149 WARN_ON(xfer_bytes > host->bounce_buf_size); 1150 sg_copy_from_buffer(data->sg, data->sg_len, 1151 host->bounce_buf, xfer_bytes); 1152 } 1153 1154 next_cmd = meson_mmc_get_next_command(cmd); 1155 if (next_cmd) 1156 meson_mmc_start_cmd(host->mmc, next_cmd); 1157 else 1158 meson_mmc_request_done(host->mmc, cmd->mrq); 1159 1160 return IRQ_HANDLED; 1161 } 1162 1163 /* 1164 * NOTE: we only need this until the GPIO/pinctrl driver can handle 1165 * interrupts. For now, the MMC core will use this for polling. 1166 */ 1167 static int meson_mmc_get_cd(struct mmc_host *mmc) 1168 { 1169 int status = mmc_gpio_get_cd(mmc); 1170 1171 if (status == -ENOSYS) 1172 return 1; /* assume present */ 1173 1174 return status; 1175 } 1176 1177 static void meson_mmc_cfg_init(struct meson_host *host) 1178 { 1179 u32 cfg = 0; 1180 1181 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 1182 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 1183 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 1184 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 1185 1186 /* abort chain on R/W errors */ 1187 cfg |= CFG_ERR_ABORT; 1188 1189 writel(cfg, host->regs + SD_EMMC_CFG); 1190 } 1191 1192 static int meson_mmc_card_busy(struct mmc_host *mmc) 1193 { 1194 struct meson_host *host = mmc_priv(mmc); 1195 u32 regval; 1196 1197 regval = readl(host->regs + SD_EMMC_STATUS); 1198 1199 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1200 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1201 } 1202 1203 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1204 { 1205 /* vqmmc regulator is available */ 1206 if (!IS_ERR(mmc->supply.vqmmc)) { 1207 /* 1208 * The usual amlogic setup uses a GPIO to switch from one 1209 * regulator to the other. While the voltage ramp up is 1210 * pretty fast, care must be taken when switching from 3.3v 1211 * to 1.8v. Please make sure the regulator framework is aware 1212 * of your own regulator constraints 1213 */ 1214 return mmc_regulator_set_vqmmc(mmc, ios); 1215 } 1216 1217 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1218 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1219 return 0; 1220 1221 return -EINVAL; 1222 } 1223 1224 static const struct mmc_host_ops meson_mmc_ops = { 1225 .request = meson_mmc_request, 1226 .set_ios = meson_mmc_set_ios, 1227 .get_cd = meson_mmc_get_cd, 1228 .pre_req = meson_mmc_pre_req, 1229 .post_req = meson_mmc_post_req, 1230 .execute_tuning = meson_mmc_execute_tuning, 1231 .card_busy = meson_mmc_card_busy, 1232 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1233 }; 1234 1235 static int meson_mmc_probe(struct platform_device *pdev) 1236 { 1237 struct resource *res; 1238 struct meson_host *host; 1239 struct mmc_host *mmc; 1240 int ret; 1241 1242 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1243 if (!mmc) 1244 return -ENOMEM; 1245 host = mmc_priv(mmc); 1246 host->mmc = mmc; 1247 host->dev = &pdev->dev; 1248 dev_set_drvdata(&pdev->dev, host); 1249 1250 /* Get regulators and the supported OCR mask */ 1251 host->vqmmc_enabled = false; 1252 ret = mmc_regulator_get_supply(mmc); 1253 if (ret) 1254 goto free_host; 1255 1256 ret = mmc_of_parse(mmc); 1257 if (ret) { 1258 if (ret != -EPROBE_DEFER) 1259 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1260 goto free_host; 1261 } 1262 1263 host->data = (struct meson_mmc_data *) 1264 of_device_get_match_data(&pdev->dev); 1265 if (!host->data) { 1266 ret = -EINVAL; 1267 goto free_host; 1268 } 1269 1270 ret = device_reset_optional(&pdev->dev); 1271 if (ret) { 1272 if (ret != -EPROBE_DEFER) 1273 dev_err(&pdev->dev, "device reset failed: %d\n", ret); 1274 1275 return ret; 1276 } 1277 1278 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1279 host->regs = devm_ioremap_resource(&pdev->dev, res); 1280 if (IS_ERR(host->regs)) { 1281 ret = PTR_ERR(host->regs); 1282 goto free_host; 1283 } 1284 1285 host->irq = platform_get_irq(pdev, 0); 1286 if (host->irq <= 0) { 1287 dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 1288 ret = -EINVAL; 1289 goto free_host; 1290 } 1291 1292 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1293 if (IS_ERR(host->pinctrl)) { 1294 ret = PTR_ERR(host->pinctrl); 1295 goto free_host; 1296 } 1297 1298 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1299 PINCTRL_STATE_DEFAULT); 1300 if (IS_ERR(host->pins_default)) { 1301 ret = PTR_ERR(host->pins_default); 1302 goto free_host; 1303 } 1304 1305 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1306 "clk-gate"); 1307 if (IS_ERR(host->pins_clk_gate)) { 1308 dev_warn(&pdev->dev, 1309 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1310 host->pins_clk_gate = NULL; 1311 } 1312 1313 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1314 if (IS_ERR(host->core_clk)) { 1315 ret = PTR_ERR(host->core_clk); 1316 goto free_host; 1317 } 1318 1319 ret = clk_prepare_enable(host->core_clk); 1320 if (ret) 1321 goto free_host; 1322 1323 ret = meson_mmc_clk_init(host); 1324 if (ret) 1325 goto err_core_clk; 1326 1327 /* set config to sane default */ 1328 meson_mmc_cfg_init(host); 1329 1330 /* Stop execution */ 1331 writel(0, host->regs + SD_EMMC_START); 1332 1333 /* clear, ack and enable interrupts */ 1334 writel(0, host->regs + SD_EMMC_IRQ_EN); 1335 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1336 host->regs + SD_EMMC_STATUS); 1337 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1338 host->regs + SD_EMMC_IRQ_EN); 1339 1340 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1341 meson_mmc_irq_thread, IRQF_SHARED, 1342 dev_name(&pdev->dev), host); 1343 if (ret) 1344 goto err_init_clk; 1345 1346 mmc->caps |= MMC_CAP_CMD23; 1347 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1348 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1349 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); 1350 mmc->max_seg_size = mmc->max_req_size; 1351 1352 /* data bounce buffer */ 1353 host->bounce_buf_size = mmc->max_req_size; 1354 host->bounce_buf = 1355 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1356 &host->bounce_dma_addr, GFP_KERNEL); 1357 if (host->bounce_buf == NULL) { 1358 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1359 ret = -ENOMEM; 1360 goto err_free_irq; 1361 } 1362 1363 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1364 &host->descs_dma_addr, GFP_KERNEL); 1365 if (!host->descs) { 1366 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1367 ret = -ENOMEM; 1368 goto err_bounce_buf; 1369 } 1370 1371 mmc->ops = &meson_mmc_ops; 1372 mmc_add_host(mmc); 1373 1374 return 0; 1375 1376 err_bounce_buf: 1377 dma_free_coherent(host->dev, host->bounce_buf_size, 1378 host->bounce_buf, host->bounce_dma_addr); 1379 err_free_irq: 1380 free_irq(host->irq, host); 1381 err_init_clk: 1382 clk_disable_unprepare(host->mmc_clk); 1383 err_core_clk: 1384 clk_disable_unprepare(host->core_clk); 1385 free_host: 1386 mmc_free_host(mmc); 1387 return ret; 1388 } 1389 1390 static int meson_mmc_remove(struct platform_device *pdev) 1391 { 1392 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1393 1394 mmc_remove_host(host->mmc); 1395 1396 /* disable interrupts */ 1397 writel(0, host->regs + SD_EMMC_IRQ_EN); 1398 free_irq(host->irq, host); 1399 1400 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1401 host->descs, host->descs_dma_addr); 1402 dma_free_coherent(host->dev, host->bounce_buf_size, 1403 host->bounce_buf, host->bounce_dma_addr); 1404 1405 clk_disable_unprepare(host->mmc_clk); 1406 clk_disable_unprepare(host->core_clk); 1407 1408 mmc_free_host(host->mmc); 1409 return 0; 1410 } 1411 1412 static const struct meson_mmc_data meson_gx_data = { 1413 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1414 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1415 .always_on = CLK_V2_ALWAYS_ON, 1416 .adjust = SD_EMMC_ADJUST, 1417 }; 1418 1419 static const struct meson_mmc_data meson_axg_data = { 1420 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1421 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1422 .always_on = CLK_V3_ALWAYS_ON, 1423 .adjust = SD_EMMC_V3_ADJUST, 1424 }; 1425 1426 static const struct of_device_id meson_mmc_of_match[] = { 1427 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1428 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1429 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1430 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1431 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1432 {} 1433 }; 1434 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1435 1436 static struct platform_driver meson_mmc_driver = { 1437 .probe = meson_mmc_probe, 1438 .remove = meson_mmc_remove, 1439 .driver = { 1440 .name = DRIVER_NAME, 1441 .of_match_table = of_match_ptr(meson_mmc_of_match), 1442 }, 1443 }; 1444 1445 module_platform_driver(meson_mmc_driver); 1446 1447 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1448 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1449 MODULE_LICENSE("GPL v2"); 1450