1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ioport.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/slot-gpio.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitfield.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "meson-gx-mmc" 32 33 #define SD_EMMC_CLOCK 0x0 34 #define CLK_DIV_MASK GENMASK(5, 0) 35 #define CLK_SRC_MASK GENMASK(7, 6) 36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 39 #define CLK_PHASE_0 0 40 #define CLK_PHASE_180 2 41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43 #define CLK_V2_ALWAYS_ON BIT(24) 44 45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 47 #define CLK_V3_ALWAYS_ON BIT(28) 48 49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 51 #define CLK_ALWAYS_ON(h) (h->data->always_on) 52 53 #define SD_EMMC_DELAY 0x4 54 #define SD_EMMC_ADJUST 0x8 55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 56 #define ADJUST_DS_EN BIT(15) 57 #define ADJUST_ADJ_EN BIT(13) 58 59 #define SD_EMMC_DELAY1 0x4 60 #define SD_EMMC_DELAY2 0x8 61 #define SD_EMMC_V3_ADJUST 0xc 62 63 #define SD_EMMC_CALOUT 0x10 64 #define SD_EMMC_START 0x40 65 #define START_DESC_INIT BIT(0) 66 #define START_DESC_BUSY BIT(1) 67 #define START_DESC_ADDR_MASK GENMASK(31, 2) 68 69 #define SD_EMMC_CFG 0x44 70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 71 #define CFG_BUS_WIDTH_1 0x0 72 #define CFG_BUS_WIDTH_4 0x1 73 #define CFG_BUS_WIDTH_8 0x2 74 #define CFG_DDR BIT(2) 75 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 77 #define CFG_RC_CC_MASK GENMASK(15, 12) 78 #define CFG_STOP_CLOCK BIT(22) 79 #define CFG_CLK_ALWAYS_ON BIT(18) 80 #define CFG_CHK_DS BIT(20) 81 #define CFG_AUTO_CLK BIT(23) 82 #define CFG_ERR_ABORT BIT(27) 83 84 #define SD_EMMC_STATUS 0x48 85 #define STATUS_BUSY BIT(31) 86 #define STATUS_DESC_BUSY BIT(30) 87 #define STATUS_DATI GENMASK(23, 16) 88 89 #define SD_EMMC_IRQ_EN 0x4c 90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 91 #define IRQ_TXD_ERR BIT(8) 92 #define IRQ_DESC_ERR BIT(9) 93 #define IRQ_RESP_ERR BIT(10) 94 #define IRQ_CRC_ERR \ 95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 96 #define IRQ_RESP_TIMEOUT BIT(11) 97 #define IRQ_DESC_TIMEOUT BIT(12) 98 #define IRQ_TIMEOUTS \ 99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 100 #define IRQ_END_OF_CHAIN BIT(13) 101 #define IRQ_RESP_STATUS BIT(14) 102 #define IRQ_SDIO BIT(15) 103 #define IRQ_EN_MASK \ 104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 105 IRQ_SDIO) 106 107 #define SD_EMMC_CMD_CFG 0x50 108 #define SD_EMMC_CMD_ARG 0x54 109 #define SD_EMMC_CMD_DAT 0x58 110 #define SD_EMMC_CMD_RSP 0x5c 111 #define SD_EMMC_CMD_RSP1 0x60 112 #define SD_EMMC_CMD_RSP2 0x64 113 #define SD_EMMC_CMD_RSP3 0x68 114 115 #define SD_EMMC_RXD 0x94 116 #define SD_EMMC_TXD 0x94 117 #define SD_EMMC_LAST_REG SD_EMMC_TXD 118 119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536 120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 121 122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 128 129 #define SD_EMMC_PRE_REQ_DONE BIT(0) 130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 131 132 #define MUX_CLK_NUM_PARENTS 2 133 134 struct meson_mmc_data { 135 unsigned int tx_delay_mask; 136 unsigned int rx_delay_mask; 137 unsigned int always_on; 138 unsigned int adjust; 139 }; 140 141 struct sd_emmc_desc { 142 u32 cmd_cfg; 143 u32 cmd_arg; 144 u32 cmd_data; 145 u32 cmd_resp; 146 }; 147 148 struct meson_host { 149 struct device *dev; 150 struct meson_mmc_data *data; 151 struct mmc_host *mmc; 152 struct mmc_command *cmd; 153 154 void __iomem *regs; 155 struct clk *core_clk; 156 struct clk *mux_clk; 157 struct clk *mmc_clk; 158 unsigned long req_rate; 159 bool ddr; 160 161 bool dram_access_quirk; 162 163 struct pinctrl *pinctrl; 164 struct pinctrl_state *pins_clk_gate; 165 166 unsigned int bounce_buf_size; 167 void *bounce_buf; 168 dma_addr_t bounce_dma_addr; 169 struct sd_emmc_desc *descs; 170 dma_addr_t descs_dma_addr; 171 172 int irq; 173 174 bool vqmmc_enabled; 175 }; 176 177 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 178 #define CMD_CFG_BLOCK_MODE BIT(9) 179 #define CMD_CFG_R1B BIT(10) 180 #define CMD_CFG_END_OF_CHAIN BIT(11) 181 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 182 #define CMD_CFG_NO_RESP BIT(16) 183 #define CMD_CFG_NO_CMD BIT(17) 184 #define CMD_CFG_DATA_IO BIT(18) 185 #define CMD_CFG_DATA_WR BIT(19) 186 #define CMD_CFG_RESP_NOCRC BIT(20) 187 #define CMD_CFG_RESP_128 BIT(21) 188 #define CMD_CFG_RESP_NUM BIT(22) 189 #define CMD_CFG_DATA_NUM BIT(23) 190 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 191 #define CMD_CFG_ERROR BIT(30) 192 #define CMD_CFG_OWNER BIT(31) 193 194 #define CMD_DATA_MASK GENMASK(31, 2) 195 #define CMD_DATA_BIG_ENDIAN BIT(1) 196 #define CMD_DATA_SRAM BIT(0) 197 #define CMD_RESP_MASK GENMASK(31, 1) 198 #define CMD_RESP_SRAM BIT(0) 199 200 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 201 { 202 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 203 204 if (!timeout) 205 return SD_EMMC_CMD_TIMEOUT_DATA; 206 207 timeout = roundup_pow_of_two(timeout); 208 209 return min(timeout, 32768U); /* max. 2^15 ms */ 210 } 211 212 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 213 { 214 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 215 return cmd->mrq->cmd; 216 else if (mmc_op_multi(cmd->opcode) && 217 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 218 return cmd->mrq->stop; 219 else 220 return NULL; 221 } 222 223 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 224 struct mmc_request *mrq) 225 { 226 struct meson_host *host = mmc_priv(mmc); 227 struct mmc_data *data = mrq->data; 228 struct scatterlist *sg; 229 int i; 230 bool use_desc_chain_mode = true; 231 232 /* 233 * When Controller DMA cannot directly access DDR memory, disable 234 * support for Chain Mode to directly use the internal SRAM using 235 * the bounce buffer mode. 236 */ 237 if (host->dram_access_quirk) 238 return; 239 240 /* 241 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 242 * reported. For some strange reason this occurs in descriptor 243 * chain mode only. So let's fall back to bounce buffer mode 244 * for command SD_IO_RW_EXTENDED. 245 */ 246 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 247 return; 248 249 for_each_sg(data->sg, sg, data->sg_len, i) 250 /* check for 8 byte alignment */ 251 if (sg->offset & 7) { 252 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 253 use_desc_chain_mode = false; 254 break; 255 } 256 257 if (use_desc_chain_mode) 258 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 259 } 260 261 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 262 { 263 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 264 } 265 266 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 267 { 268 return data && data->flags & MMC_DATA_READ && 269 !meson_mmc_desc_chain_mode(data); 270 } 271 272 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 273 { 274 struct mmc_data *data = mrq->data; 275 276 if (!data) 277 return; 278 279 meson_mmc_get_transfer_mode(mmc, mrq); 280 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 281 282 if (!meson_mmc_desc_chain_mode(data)) 283 return; 284 285 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 286 mmc_get_dma_dir(data)); 287 if (!data->sg_count) 288 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 289 } 290 291 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 292 int err) 293 { 294 struct mmc_data *data = mrq->data; 295 296 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 297 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 298 mmc_get_dma_dir(data)); 299 } 300 301 /* 302 * Gating the clock on this controller is tricky. It seems the mmc clock 303 * is also used by the controller. It may crash during some operation if the 304 * clock is stopped. The safest thing to do, whenever possible, is to keep 305 * clock running at stop it at the pad using the pinmux. 306 */ 307 static void meson_mmc_clk_gate(struct meson_host *host) 308 { 309 u32 cfg; 310 311 if (host->pins_clk_gate) { 312 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 313 } else { 314 /* 315 * If the pinmux is not provided - default to the classic and 316 * unsafe method 317 */ 318 cfg = readl(host->regs + SD_EMMC_CFG); 319 cfg |= CFG_STOP_CLOCK; 320 writel(cfg, host->regs + SD_EMMC_CFG); 321 } 322 } 323 324 static void meson_mmc_clk_ungate(struct meson_host *host) 325 { 326 u32 cfg; 327 328 if (host->pins_clk_gate) 329 pinctrl_select_default_state(host->dev); 330 331 /* Make sure the clock is not stopped in the controller */ 332 cfg = readl(host->regs + SD_EMMC_CFG); 333 cfg &= ~CFG_STOP_CLOCK; 334 writel(cfg, host->regs + SD_EMMC_CFG); 335 } 336 337 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 338 bool ddr) 339 { 340 struct mmc_host *mmc = host->mmc; 341 int ret; 342 u32 cfg; 343 344 /* Same request - bail-out */ 345 if (host->ddr == ddr && host->req_rate == rate) 346 return 0; 347 348 /* stop clock */ 349 meson_mmc_clk_gate(host); 350 host->req_rate = 0; 351 mmc->actual_clock = 0; 352 353 /* return with clock being stopped */ 354 if (!rate) 355 return 0; 356 357 /* Stop the clock during rate change to avoid glitches */ 358 cfg = readl(host->regs + SD_EMMC_CFG); 359 cfg |= CFG_STOP_CLOCK; 360 writel(cfg, host->regs + SD_EMMC_CFG); 361 362 if (ddr) { 363 /* DDR modes require higher module clock */ 364 rate <<= 1; 365 cfg |= CFG_DDR; 366 } else { 367 cfg &= ~CFG_DDR; 368 } 369 writel(cfg, host->regs + SD_EMMC_CFG); 370 host->ddr = ddr; 371 372 ret = clk_set_rate(host->mmc_clk, rate); 373 if (ret) { 374 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 375 rate, ret); 376 return ret; 377 } 378 379 host->req_rate = rate; 380 mmc->actual_clock = clk_get_rate(host->mmc_clk); 381 382 /* We should report the real output frequency of the controller */ 383 if (ddr) { 384 host->req_rate >>= 1; 385 mmc->actual_clock >>= 1; 386 } 387 388 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 389 if (rate != mmc->actual_clock) 390 dev_dbg(host->dev, "requested rate was %lu\n", rate); 391 392 /* (re)start clock */ 393 meson_mmc_clk_ungate(host); 394 395 return 0; 396 } 397 398 /* 399 * The SD/eMMC IP block has an internal mux and divider used for 400 * generating the MMC clock. Use the clock framework to create and 401 * manage these clocks. 402 */ 403 static int meson_mmc_clk_init(struct meson_host *host) 404 { 405 struct clk_init_data init; 406 struct clk_mux *mux; 407 struct clk_divider *div; 408 char clk_name[32]; 409 int i, ret = 0; 410 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 411 const char *clk_parent[1]; 412 u32 clk_reg; 413 414 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 415 clk_reg = CLK_ALWAYS_ON(host); 416 clk_reg |= CLK_DIV_MASK; 417 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 418 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 419 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 420 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 421 422 /* get the mux parents */ 423 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 424 struct clk *clk; 425 char name[16]; 426 427 snprintf(name, sizeof(name), "clkin%d", i); 428 clk = devm_clk_get(host->dev, name); 429 if (IS_ERR(clk)) { 430 if (clk != ERR_PTR(-EPROBE_DEFER)) 431 dev_err(host->dev, "Missing clock %s\n", name); 432 return PTR_ERR(clk); 433 } 434 435 mux_parent_names[i] = __clk_get_name(clk); 436 } 437 438 /* create the mux */ 439 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 440 if (!mux) 441 return -ENOMEM; 442 443 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 444 init.name = clk_name; 445 init.ops = &clk_mux_ops; 446 init.flags = 0; 447 init.parent_names = mux_parent_names; 448 init.num_parents = MUX_CLK_NUM_PARENTS; 449 450 mux->reg = host->regs + SD_EMMC_CLOCK; 451 mux->shift = __ffs(CLK_SRC_MASK); 452 mux->mask = CLK_SRC_MASK >> mux->shift; 453 mux->hw.init = &init; 454 455 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 456 if (WARN_ON(IS_ERR(host->mux_clk))) 457 return PTR_ERR(host->mux_clk); 458 459 /* create the divider */ 460 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 461 if (!div) 462 return -ENOMEM; 463 464 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 465 init.name = clk_name; 466 init.ops = &clk_divider_ops; 467 init.flags = CLK_SET_RATE_PARENT; 468 clk_parent[0] = __clk_get_name(host->mux_clk); 469 init.parent_names = clk_parent; 470 init.num_parents = 1; 471 472 div->reg = host->regs + SD_EMMC_CLOCK; 473 div->shift = __ffs(CLK_DIV_MASK); 474 div->width = __builtin_popcountl(CLK_DIV_MASK); 475 div->hw.init = &init; 476 div->flags = CLK_DIVIDER_ONE_BASED; 477 478 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 479 if (WARN_ON(IS_ERR(host->mmc_clk))) 480 return PTR_ERR(host->mmc_clk); 481 482 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 483 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 484 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 485 if (ret) 486 return ret; 487 488 return clk_prepare_enable(host->mmc_clk); 489 } 490 491 static void meson_mmc_disable_resampling(struct meson_host *host) 492 { 493 unsigned int val = readl(host->regs + host->data->adjust); 494 495 val &= ~ADJUST_ADJ_EN; 496 writel(val, host->regs + host->data->adjust); 497 } 498 499 static void meson_mmc_reset_resampling(struct meson_host *host) 500 { 501 unsigned int val; 502 503 meson_mmc_disable_resampling(host); 504 505 val = readl(host->regs + host->data->adjust); 506 val &= ~ADJUST_ADJ_DELAY_MASK; 507 writel(val, host->regs + host->data->adjust); 508 } 509 510 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 511 { 512 struct meson_host *host = mmc_priv(mmc); 513 unsigned int val, dly, max_dly, i; 514 int ret; 515 516 /* Resampling is done using the source clock */ 517 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 518 clk_get_rate(host->mmc_clk)); 519 520 val = readl(host->regs + host->data->adjust); 521 val |= ADJUST_ADJ_EN; 522 writel(val, host->regs + host->data->adjust); 523 524 if (mmc->doing_retune) 525 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 526 else 527 dly = 0; 528 529 for (i = 0; i < max_dly; i++) { 530 val &= ~ADJUST_ADJ_DELAY_MASK; 531 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 532 writel(val, host->regs + host->data->adjust); 533 534 ret = mmc_send_tuning(mmc, opcode, NULL); 535 if (!ret) { 536 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 537 (dly + i) % max_dly); 538 return 0; 539 } 540 } 541 542 meson_mmc_reset_resampling(host); 543 return -EIO; 544 } 545 546 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 547 struct mmc_ios *ios) 548 { 549 bool ddr; 550 551 switch (ios->timing) { 552 case MMC_TIMING_MMC_DDR52: 553 case MMC_TIMING_UHS_DDR50: 554 ddr = true; 555 break; 556 557 default: 558 ddr = false; 559 break; 560 } 561 562 return meson_mmc_clk_set(host, ios->clock, ddr); 563 } 564 565 static void meson_mmc_check_resampling(struct meson_host *host, 566 struct mmc_ios *ios) 567 { 568 switch (ios->timing) { 569 case MMC_TIMING_LEGACY: 570 case MMC_TIMING_MMC_HS: 571 case MMC_TIMING_SD_HS: 572 case MMC_TIMING_MMC_DDR52: 573 meson_mmc_disable_resampling(host); 574 break; 575 } 576 } 577 578 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 579 { 580 struct meson_host *host = mmc_priv(mmc); 581 u32 bus_width, val; 582 int err; 583 584 /* 585 * GPIO regulator, only controls switching between 1v8 and 586 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 587 */ 588 switch (ios->power_mode) { 589 case MMC_POWER_OFF: 590 if (!IS_ERR(mmc->supply.vmmc)) 591 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 592 593 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 594 regulator_disable(mmc->supply.vqmmc); 595 host->vqmmc_enabled = false; 596 } 597 598 break; 599 600 case MMC_POWER_UP: 601 if (!IS_ERR(mmc->supply.vmmc)) 602 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 603 604 break; 605 606 case MMC_POWER_ON: 607 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 608 int ret = regulator_enable(mmc->supply.vqmmc); 609 610 if (ret < 0) 611 dev_err(host->dev, 612 "failed to enable vqmmc regulator\n"); 613 else 614 host->vqmmc_enabled = true; 615 } 616 617 break; 618 } 619 620 /* Bus width */ 621 switch (ios->bus_width) { 622 case MMC_BUS_WIDTH_1: 623 bus_width = CFG_BUS_WIDTH_1; 624 break; 625 case MMC_BUS_WIDTH_4: 626 bus_width = CFG_BUS_WIDTH_4; 627 break; 628 case MMC_BUS_WIDTH_8: 629 bus_width = CFG_BUS_WIDTH_8; 630 break; 631 default: 632 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 633 ios->bus_width); 634 bus_width = CFG_BUS_WIDTH_4; 635 } 636 637 val = readl(host->regs + SD_EMMC_CFG); 638 val &= ~CFG_BUS_WIDTH_MASK; 639 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 640 writel(val, host->regs + SD_EMMC_CFG); 641 642 meson_mmc_check_resampling(host, ios); 643 err = meson_mmc_prepare_ios_clock(host, ios); 644 if (err) 645 dev_err(host->dev, "Failed to set clock: %d\n,", err); 646 647 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 648 } 649 650 static void meson_mmc_request_done(struct mmc_host *mmc, 651 struct mmc_request *mrq) 652 { 653 struct meson_host *host = mmc_priv(mmc); 654 655 host->cmd = NULL; 656 mmc_request_done(host->mmc, mrq); 657 } 658 659 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 660 { 661 struct meson_host *host = mmc_priv(mmc); 662 u32 cfg, blksz_old; 663 664 cfg = readl(host->regs + SD_EMMC_CFG); 665 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 666 667 if (!is_power_of_2(blksz)) 668 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 669 670 blksz = ilog2(blksz); 671 672 /* check if block-size matches, if not update */ 673 if (blksz == blksz_old) 674 return; 675 676 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 677 blksz_old, blksz); 678 679 cfg &= ~CFG_BLK_LEN_MASK; 680 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 681 writel(cfg, host->regs + SD_EMMC_CFG); 682 } 683 684 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 685 { 686 if (cmd->flags & MMC_RSP_PRESENT) { 687 if (cmd->flags & MMC_RSP_136) 688 *cmd_cfg |= CMD_CFG_RESP_128; 689 *cmd_cfg |= CMD_CFG_RESP_NUM; 690 691 if (!(cmd->flags & MMC_RSP_CRC)) 692 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 693 694 if (cmd->flags & MMC_RSP_BUSY) 695 *cmd_cfg |= CMD_CFG_R1B; 696 } else { 697 *cmd_cfg |= CMD_CFG_NO_RESP; 698 } 699 } 700 701 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 702 { 703 struct meson_host *host = mmc_priv(mmc); 704 struct sd_emmc_desc *desc = host->descs; 705 struct mmc_data *data = host->cmd->data; 706 struct scatterlist *sg; 707 u32 start; 708 int i; 709 710 if (data->flags & MMC_DATA_WRITE) 711 cmd_cfg |= CMD_CFG_DATA_WR; 712 713 if (data->blocks > 1) { 714 cmd_cfg |= CMD_CFG_BLOCK_MODE; 715 meson_mmc_set_blksz(mmc, data->blksz); 716 } 717 718 for_each_sg(data->sg, sg, data->sg_count, i) { 719 unsigned int len = sg_dma_len(sg); 720 721 if (data->blocks > 1) 722 len /= data->blksz; 723 724 desc[i].cmd_cfg = cmd_cfg; 725 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 726 if (i > 0) 727 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 728 desc[i].cmd_arg = host->cmd->arg; 729 desc[i].cmd_resp = 0; 730 desc[i].cmd_data = sg_dma_address(sg); 731 } 732 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 733 734 dma_wmb(); /* ensure descriptor is written before kicked */ 735 start = host->descs_dma_addr | START_DESC_BUSY; 736 writel(start, host->regs + SD_EMMC_START); 737 } 738 739 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 740 { 741 struct meson_host *host = mmc_priv(mmc); 742 struct mmc_data *data = cmd->data; 743 u32 cmd_cfg = 0, cmd_data = 0; 744 unsigned int xfer_bytes = 0; 745 746 /* Setup descriptors */ 747 dma_rmb(); 748 749 host->cmd = cmd; 750 751 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 752 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 753 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 754 755 meson_mmc_set_response_bits(cmd, &cmd_cfg); 756 757 /* data? */ 758 if (data) { 759 data->bytes_xfered = 0; 760 cmd_cfg |= CMD_CFG_DATA_IO; 761 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 762 ilog2(meson_mmc_get_timeout_msecs(data))); 763 764 if (meson_mmc_desc_chain_mode(data)) { 765 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 766 return; 767 } 768 769 if (data->blocks > 1) { 770 cmd_cfg |= CMD_CFG_BLOCK_MODE; 771 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 772 data->blocks); 773 meson_mmc_set_blksz(mmc, data->blksz); 774 } else { 775 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 776 } 777 778 xfer_bytes = data->blksz * data->blocks; 779 if (data->flags & MMC_DATA_WRITE) { 780 cmd_cfg |= CMD_CFG_DATA_WR; 781 WARN_ON(xfer_bytes > host->bounce_buf_size); 782 sg_copy_to_buffer(data->sg, data->sg_len, 783 host->bounce_buf, xfer_bytes); 784 dma_wmb(); 785 } 786 787 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 788 } else { 789 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 790 ilog2(SD_EMMC_CMD_TIMEOUT)); 791 } 792 793 /* Last descriptor */ 794 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 795 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 796 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 797 writel(0, host->regs + SD_EMMC_CMD_RSP); 798 wmb(); /* ensure descriptor is written before kicked */ 799 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 800 } 801 802 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 803 { 804 struct meson_host *host = mmc_priv(mmc); 805 bool needs_pre_post_req = mrq->data && 806 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 807 808 if (needs_pre_post_req) { 809 meson_mmc_get_transfer_mode(mmc, mrq); 810 if (!meson_mmc_desc_chain_mode(mrq->data)) 811 needs_pre_post_req = false; 812 } 813 814 if (needs_pre_post_req) 815 meson_mmc_pre_req(mmc, mrq); 816 817 /* Stop execution */ 818 writel(0, host->regs + SD_EMMC_START); 819 820 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 821 822 if (needs_pre_post_req) 823 meson_mmc_post_req(mmc, mrq, 0); 824 } 825 826 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 827 { 828 struct meson_host *host = mmc_priv(mmc); 829 830 if (cmd->flags & MMC_RSP_136) { 831 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 832 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 833 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 834 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 835 } else if (cmd->flags & MMC_RSP_PRESENT) { 836 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 837 } 838 } 839 840 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 841 { 842 struct meson_host *host = dev_id; 843 struct mmc_command *cmd; 844 struct mmc_data *data; 845 u32 irq_en, status, raw_status; 846 irqreturn_t ret = IRQ_NONE; 847 848 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 849 raw_status = readl(host->regs + SD_EMMC_STATUS); 850 status = raw_status & irq_en; 851 852 if (!status) { 853 dev_dbg(host->dev, 854 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 855 irq_en, raw_status); 856 return IRQ_NONE; 857 } 858 859 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 860 return IRQ_NONE; 861 862 /* ack all raised interrupts */ 863 writel(status, host->regs + SD_EMMC_STATUS); 864 865 cmd = host->cmd; 866 data = cmd->data; 867 cmd->error = 0; 868 if (status & IRQ_CRC_ERR) { 869 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 870 cmd->error = -EILSEQ; 871 ret = IRQ_WAKE_THREAD; 872 goto out; 873 } 874 875 if (status & IRQ_TIMEOUTS) { 876 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 877 cmd->error = -ETIMEDOUT; 878 ret = IRQ_WAKE_THREAD; 879 goto out; 880 } 881 882 meson_mmc_read_resp(host->mmc, cmd); 883 884 if (status & IRQ_SDIO) { 885 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 886 ret = IRQ_HANDLED; 887 } 888 889 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 890 if (data && !cmd->error) 891 data->bytes_xfered = data->blksz * data->blocks; 892 if (meson_mmc_bounce_buf_read(data) || 893 meson_mmc_get_next_command(cmd)) 894 ret = IRQ_WAKE_THREAD; 895 else 896 ret = IRQ_HANDLED; 897 } 898 899 out: 900 if (cmd->error) { 901 /* Stop desc in case of errors */ 902 u32 start = readl(host->regs + SD_EMMC_START); 903 904 start &= ~START_DESC_BUSY; 905 writel(start, host->regs + SD_EMMC_START); 906 } 907 908 if (ret == IRQ_HANDLED) 909 meson_mmc_request_done(host->mmc, cmd->mrq); 910 911 return ret; 912 } 913 914 static int meson_mmc_wait_desc_stop(struct meson_host *host) 915 { 916 u32 status; 917 918 /* 919 * It may sometimes take a while for it to actually halt. Here, we 920 * are giving it 5ms to comply 921 * 922 * If we don't confirm the descriptor is stopped, it might raise new 923 * IRQs after we have called mmc_request_done() which is bad. 924 */ 925 926 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 927 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 928 100, 5000); 929 } 930 931 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 932 { 933 struct meson_host *host = dev_id; 934 struct mmc_command *next_cmd, *cmd = host->cmd; 935 struct mmc_data *data; 936 unsigned int xfer_bytes; 937 938 if (WARN_ON(!cmd)) 939 return IRQ_NONE; 940 941 if (cmd->error) { 942 meson_mmc_wait_desc_stop(host); 943 meson_mmc_request_done(host->mmc, cmd->mrq); 944 945 return IRQ_HANDLED; 946 } 947 948 data = cmd->data; 949 if (meson_mmc_bounce_buf_read(data)) { 950 xfer_bytes = data->blksz * data->blocks; 951 WARN_ON(xfer_bytes > host->bounce_buf_size); 952 sg_copy_from_buffer(data->sg, data->sg_len, 953 host->bounce_buf, xfer_bytes); 954 } 955 956 next_cmd = meson_mmc_get_next_command(cmd); 957 if (next_cmd) 958 meson_mmc_start_cmd(host->mmc, next_cmd); 959 else 960 meson_mmc_request_done(host->mmc, cmd->mrq); 961 962 return IRQ_HANDLED; 963 } 964 965 /* 966 * NOTE: we only need this until the GPIO/pinctrl driver can handle 967 * interrupts. For now, the MMC core will use this for polling. 968 */ 969 static int meson_mmc_get_cd(struct mmc_host *mmc) 970 { 971 int status = mmc_gpio_get_cd(mmc); 972 973 if (status == -ENOSYS) 974 return 1; /* assume present */ 975 976 return status; 977 } 978 979 static void meson_mmc_cfg_init(struct meson_host *host) 980 { 981 u32 cfg = 0; 982 983 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 984 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 985 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 986 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 987 988 /* abort chain on R/W errors */ 989 cfg |= CFG_ERR_ABORT; 990 991 writel(cfg, host->regs + SD_EMMC_CFG); 992 } 993 994 static int meson_mmc_card_busy(struct mmc_host *mmc) 995 { 996 struct meson_host *host = mmc_priv(mmc); 997 u32 regval; 998 999 regval = readl(host->regs + SD_EMMC_STATUS); 1000 1001 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1002 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1003 } 1004 1005 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1006 { 1007 int ret; 1008 1009 /* vqmmc regulator is available */ 1010 if (!IS_ERR(mmc->supply.vqmmc)) { 1011 /* 1012 * The usual amlogic setup uses a GPIO to switch from one 1013 * regulator to the other. While the voltage ramp up is 1014 * pretty fast, care must be taken when switching from 3.3v 1015 * to 1.8v. Please make sure the regulator framework is aware 1016 * of your own regulator constraints 1017 */ 1018 ret = mmc_regulator_set_vqmmc(mmc, ios); 1019 return ret < 0 ? ret : 0; 1020 } 1021 1022 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1023 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1024 return 0; 1025 1026 return -EINVAL; 1027 } 1028 1029 static const struct mmc_host_ops meson_mmc_ops = { 1030 .request = meson_mmc_request, 1031 .set_ios = meson_mmc_set_ios, 1032 .get_cd = meson_mmc_get_cd, 1033 .pre_req = meson_mmc_pre_req, 1034 .post_req = meson_mmc_post_req, 1035 .execute_tuning = meson_mmc_resampling_tuning, 1036 .card_busy = meson_mmc_card_busy, 1037 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1038 }; 1039 1040 static int meson_mmc_probe(struct platform_device *pdev) 1041 { 1042 struct resource *res; 1043 struct meson_host *host; 1044 struct mmc_host *mmc; 1045 int ret; 1046 1047 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1048 if (!mmc) 1049 return -ENOMEM; 1050 host = mmc_priv(mmc); 1051 host->mmc = mmc; 1052 host->dev = &pdev->dev; 1053 dev_set_drvdata(&pdev->dev, host); 1054 1055 /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1056 host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1057 "amlogic,dram-access-quirk"); 1058 1059 /* Get regulators and the supported OCR mask */ 1060 host->vqmmc_enabled = false; 1061 ret = mmc_regulator_get_supply(mmc); 1062 if (ret) 1063 goto free_host; 1064 1065 ret = mmc_of_parse(mmc); 1066 if (ret) { 1067 if (ret != -EPROBE_DEFER) 1068 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1069 goto free_host; 1070 } 1071 1072 host->data = (struct meson_mmc_data *) 1073 of_device_get_match_data(&pdev->dev); 1074 if (!host->data) { 1075 ret = -EINVAL; 1076 goto free_host; 1077 } 1078 1079 ret = device_reset_optional(&pdev->dev); 1080 if (ret) { 1081 if (ret != -EPROBE_DEFER) 1082 dev_err(&pdev->dev, "device reset failed: %d\n", ret); 1083 1084 return ret; 1085 } 1086 1087 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1088 host->regs = devm_ioremap_resource(&pdev->dev, res); 1089 if (IS_ERR(host->regs)) { 1090 ret = PTR_ERR(host->regs); 1091 goto free_host; 1092 } 1093 1094 host->irq = platform_get_irq(pdev, 0); 1095 if (host->irq <= 0) { 1096 ret = -EINVAL; 1097 goto free_host; 1098 } 1099 1100 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1101 if (IS_ERR(host->pinctrl)) { 1102 ret = PTR_ERR(host->pinctrl); 1103 goto free_host; 1104 } 1105 1106 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1107 "clk-gate"); 1108 if (IS_ERR(host->pins_clk_gate)) { 1109 dev_warn(&pdev->dev, 1110 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1111 host->pins_clk_gate = NULL; 1112 } 1113 1114 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1115 if (IS_ERR(host->core_clk)) { 1116 ret = PTR_ERR(host->core_clk); 1117 goto free_host; 1118 } 1119 1120 ret = clk_prepare_enable(host->core_clk); 1121 if (ret) 1122 goto free_host; 1123 1124 ret = meson_mmc_clk_init(host); 1125 if (ret) 1126 goto err_core_clk; 1127 1128 /* set config to sane default */ 1129 meson_mmc_cfg_init(host); 1130 1131 /* Stop execution */ 1132 writel(0, host->regs + SD_EMMC_START); 1133 1134 /* clear, ack and enable interrupts */ 1135 writel(0, host->regs + SD_EMMC_IRQ_EN); 1136 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1137 host->regs + SD_EMMC_STATUS); 1138 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1139 host->regs + SD_EMMC_IRQ_EN); 1140 1141 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1142 meson_mmc_irq_thread, IRQF_ONESHOT, 1143 dev_name(&pdev->dev), host); 1144 if (ret) 1145 goto err_init_clk; 1146 1147 mmc->caps |= MMC_CAP_CMD23; 1148 if (host->dram_access_quirk) { 1149 /* Limit segments to 1 due to low available sram memory */ 1150 mmc->max_segs = 1; 1151 /* Limit to the available sram memory */ 1152 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 1153 mmc->max_blk_size; 1154 } else { 1155 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1156 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1157 sizeof(struct sd_emmc_desc); 1158 } 1159 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1160 mmc->max_seg_size = mmc->max_req_size; 1161 1162 /* 1163 * At the moment, we don't know how to reliably enable HS400. 1164 * From the different datasheets, it is not even clear if this mode 1165 * is officially supported by any of the SoCs 1166 */ 1167 mmc->caps2 &= ~MMC_CAP2_HS400; 1168 1169 if (host->dram_access_quirk) { 1170 /* 1171 * The MMC Controller embeds 1,5KiB of internal SRAM 1172 * that can be used to be used as bounce buffer. 1173 * In the case of the G12A SDIO controller, use these 1174 * instead of the DDR memory 1175 */ 1176 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1177 host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1178 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1179 } else { 1180 /* data bounce buffer */ 1181 host->bounce_buf_size = mmc->max_req_size; 1182 host->bounce_buf = 1183 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1184 &host->bounce_dma_addr, GFP_KERNEL); 1185 if (host->bounce_buf == NULL) { 1186 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1187 ret = -ENOMEM; 1188 goto err_free_irq; 1189 } 1190 } 1191 1192 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1193 &host->descs_dma_addr, GFP_KERNEL); 1194 if (!host->descs) { 1195 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1196 ret = -ENOMEM; 1197 goto err_bounce_buf; 1198 } 1199 1200 mmc->ops = &meson_mmc_ops; 1201 mmc_add_host(mmc); 1202 1203 return 0; 1204 1205 err_bounce_buf: 1206 if (!host->dram_access_quirk) 1207 dma_free_coherent(host->dev, host->bounce_buf_size, 1208 host->bounce_buf, host->bounce_dma_addr); 1209 err_free_irq: 1210 free_irq(host->irq, host); 1211 err_init_clk: 1212 clk_disable_unprepare(host->mmc_clk); 1213 err_core_clk: 1214 clk_disable_unprepare(host->core_clk); 1215 free_host: 1216 mmc_free_host(mmc); 1217 return ret; 1218 } 1219 1220 static int meson_mmc_remove(struct platform_device *pdev) 1221 { 1222 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1223 1224 mmc_remove_host(host->mmc); 1225 1226 /* disable interrupts */ 1227 writel(0, host->regs + SD_EMMC_IRQ_EN); 1228 free_irq(host->irq, host); 1229 1230 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1231 host->descs, host->descs_dma_addr); 1232 1233 if (!host->dram_access_quirk) 1234 dma_free_coherent(host->dev, host->bounce_buf_size, 1235 host->bounce_buf, host->bounce_dma_addr); 1236 1237 clk_disable_unprepare(host->mmc_clk); 1238 clk_disable_unprepare(host->core_clk); 1239 1240 mmc_free_host(host->mmc); 1241 return 0; 1242 } 1243 1244 static const struct meson_mmc_data meson_gx_data = { 1245 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1246 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1247 .always_on = CLK_V2_ALWAYS_ON, 1248 .adjust = SD_EMMC_ADJUST, 1249 }; 1250 1251 static const struct meson_mmc_data meson_axg_data = { 1252 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1253 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1254 .always_on = CLK_V3_ALWAYS_ON, 1255 .adjust = SD_EMMC_V3_ADJUST, 1256 }; 1257 1258 static const struct of_device_id meson_mmc_of_match[] = { 1259 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1260 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1261 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1262 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1263 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1264 {} 1265 }; 1266 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1267 1268 static struct platform_driver meson_mmc_driver = { 1269 .probe = meson_mmc_probe, 1270 .remove = meson_mmc_remove, 1271 .driver = { 1272 .name = DRIVER_NAME, 1273 .of_match_table = of_match_ptr(meson_mmc_of_match), 1274 }, 1275 }; 1276 1277 module_platform_driver(meson_mmc_driver); 1278 1279 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1280 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1281 MODULE_LICENSE("GPL v2"); 1282