1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ioport.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/slot-gpio.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitfield.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "meson-gx-mmc" 32 33 #define SD_EMMC_CLOCK 0x0 34 #define CLK_DIV_MASK GENMASK(5, 0) 35 #define CLK_SRC_MASK GENMASK(7, 6) 36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 39 #define CLK_PHASE_0 0 40 #define CLK_PHASE_180 2 41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43 #define CLK_V2_ALWAYS_ON BIT(24) 44 45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 47 #define CLK_V3_ALWAYS_ON BIT(28) 48 49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 51 #define CLK_ALWAYS_ON(h) (h->data->always_on) 52 53 #define SD_EMMC_DELAY 0x4 54 #define SD_EMMC_ADJUST 0x8 55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 56 #define ADJUST_DS_EN BIT(15) 57 #define ADJUST_ADJ_EN BIT(13) 58 59 #define SD_EMMC_DELAY1 0x4 60 #define SD_EMMC_DELAY2 0x8 61 #define SD_EMMC_V3_ADJUST 0xc 62 63 #define SD_EMMC_CALOUT 0x10 64 #define SD_EMMC_START 0x40 65 #define START_DESC_INIT BIT(0) 66 #define START_DESC_BUSY BIT(1) 67 #define START_DESC_ADDR_MASK GENMASK(31, 2) 68 69 #define SD_EMMC_CFG 0x44 70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 71 #define CFG_BUS_WIDTH_1 0x0 72 #define CFG_BUS_WIDTH_4 0x1 73 #define CFG_BUS_WIDTH_8 0x2 74 #define CFG_DDR BIT(2) 75 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 77 #define CFG_RC_CC_MASK GENMASK(15, 12) 78 #define CFG_STOP_CLOCK BIT(22) 79 #define CFG_CLK_ALWAYS_ON BIT(18) 80 #define CFG_CHK_DS BIT(20) 81 #define CFG_AUTO_CLK BIT(23) 82 #define CFG_ERR_ABORT BIT(27) 83 84 #define SD_EMMC_STATUS 0x48 85 #define STATUS_BUSY BIT(31) 86 #define STATUS_DESC_BUSY BIT(30) 87 #define STATUS_DATI GENMASK(23, 16) 88 89 #define SD_EMMC_IRQ_EN 0x4c 90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 91 #define IRQ_TXD_ERR BIT(8) 92 #define IRQ_DESC_ERR BIT(9) 93 #define IRQ_RESP_ERR BIT(10) 94 #define IRQ_CRC_ERR \ 95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 96 #define IRQ_RESP_TIMEOUT BIT(11) 97 #define IRQ_DESC_TIMEOUT BIT(12) 98 #define IRQ_TIMEOUTS \ 99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 100 #define IRQ_END_OF_CHAIN BIT(13) 101 #define IRQ_RESP_STATUS BIT(14) 102 #define IRQ_SDIO BIT(15) 103 #define IRQ_EN_MASK \ 104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 105 IRQ_SDIO) 106 107 #define SD_EMMC_CMD_CFG 0x50 108 #define SD_EMMC_CMD_ARG 0x54 109 #define SD_EMMC_CMD_DAT 0x58 110 #define SD_EMMC_CMD_RSP 0x5c 111 #define SD_EMMC_CMD_RSP1 0x60 112 #define SD_EMMC_CMD_RSP2 0x64 113 #define SD_EMMC_CMD_RSP3 0x68 114 115 #define SD_EMMC_RXD 0x94 116 #define SD_EMMC_TXD 0x94 117 #define SD_EMMC_LAST_REG SD_EMMC_TXD 118 119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536 120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 121 122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 128 129 #define SD_EMMC_PRE_REQ_DONE BIT(0) 130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 131 132 #define MUX_CLK_NUM_PARENTS 2 133 134 struct meson_mmc_data { 135 unsigned int tx_delay_mask; 136 unsigned int rx_delay_mask; 137 unsigned int always_on; 138 unsigned int adjust; 139 }; 140 141 struct sd_emmc_desc { 142 u32 cmd_cfg; 143 u32 cmd_arg; 144 u32 cmd_data; 145 u32 cmd_resp; 146 }; 147 148 struct meson_host { 149 struct device *dev; 150 struct meson_mmc_data *data; 151 struct mmc_host *mmc; 152 struct mmc_command *cmd; 153 154 void __iomem *regs; 155 struct clk *core_clk; 156 struct clk *mux_clk; 157 struct clk *mmc_clk; 158 unsigned long req_rate; 159 bool ddr; 160 161 bool dram_access_quirk; 162 163 struct pinctrl *pinctrl; 164 struct pinctrl_state *pins_clk_gate; 165 166 unsigned int bounce_buf_size; 167 void *bounce_buf; 168 dma_addr_t bounce_dma_addr; 169 struct sd_emmc_desc *descs; 170 dma_addr_t descs_dma_addr; 171 172 int irq; 173 174 bool vqmmc_enabled; 175 }; 176 177 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 178 #define CMD_CFG_BLOCK_MODE BIT(9) 179 #define CMD_CFG_R1B BIT(10) 180 #define CMD_CFG_END_OF_CHAIN BIT(11) 181 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 182 #define CMD_CFG_NO_RESP BIT(16) 183 #define CMD_CFG_NO_CMD BIT(17) 184 #define CMD_CFG_DATA_IO BIT(18) 185 #define CMD_CFG_DATA_WR BIT(19) 186 #define CMD_CFG_RESP_NOCRC BIT(20) 187 #define CMD_CFG_RESP_128 BIT(21) 188 #define CMD_CFG_RESP_NUM BIT(22) 189 #define CMD_CFG_DATA_NUM BIT(23) 190 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 191 #define CMD_CFG_ERROR BIT(30) 192 #define CMD_CFG_OWNER BIT(31) 193 194 #define CMD_DATA_MASK GENMASK(31, 2) 195 #define CMD_DATA_BIG_ENDIAN BIT(1) 196 #define CMD_DATA_SRAM BIT(0) 197 #define CMD_RESP_MASK GENMASK(31, 1) 198 #define CMD_RESP_SRAM BIT(0) 199 200 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 201 { 202 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 203 204 if (!timeout) 205 return SD_EMMC_CMD_TIMEOUT_DATA; 206 207 timeout = roundup_pow_of_two(timeout); 208 209 return min(timeout, 32768U); /* max. 2^15 ms */ 210 } 211 212 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 213 { 214 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 215 return cmd->mrq->cmd; 216 else if (mmc_op_multi(cmd->opcode) && 217 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 218 return cmd->mrq->stop; 219 else 220 return NULL; 221 } 222 223 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 224 struct mmc_request *mrq) 225 { 226 struct meson_host *host = mmc_priv(mmc); 227 struct mmc_data *data = mrq->data; 228 struct scatterlist *sg; 229 int i; 230 231 /* 232 * When Controller DMA cannot directly access DDR memory, disable 233 * support for Chain Mode to directly use the internal SRAM using 234 * the bounce buffer mode. 235 */ 236 if (host->dram_access_quirk) 237 return; 238 239 if (data->blocks > 1) { 240 /* 241 * In block mode DMA descriptor format, "length" field indicates 242 * number of blocks and there is no way to pass DMA size that 243 * is not multiple of SDIO block size, making it impossible to 244 * tie more than one memory buffer with single SDIO block. 245 * Block mode sg buffer size should be aligned with SDIO block 246 * size, otherwise chain mode could not be used. 247 */ 248 for_each_sg(data->sg, sg, data->sg_len, i) { 249 if (sg->length % data->blksz) { 250 dev_warn_once(mmc_dev(mmc), 251 "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n", 252 sg->length, data->blksz); 253 return; 254 } 255 } 256 } 257 258 for_each_sg(data->sg, sg, data->sg_len, i) { 259 /* check for 8 byte alignment */ 260 if (sg->offset % 8) { 261 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 262 return; 263 } 264 } 265 266 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 267 } 268 269 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 270 { 271 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 272 } 273 274 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 275 { 276 return data && data->flags & MMC_DATA_READ && 277 !meson_mmc_desc_chain_mode(data); 278 } 279 280 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 281 { 282 struct mmc_data *data = mrq->data; 283 284 if (!data) 285 return; 286 287 meson_mmc_get_transfer_mode(mmc, mrq); 288 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 289 290 if (!meson_mmc_desc_chain_mode(data)) 291 return; 292 293 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 294 mmc_get_dma_dir(data)); 295 if (!data->sg_count) 296 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 297 } 298 299 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 300 int err) 301 { 302 struct mmc_data *data = mrq->data; 303 304 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 305 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 306 mmc_get_dma_dir(data)); 307 } 308 309 /* 310 * Gating the clock on this controller is tricky. It seems the mmc clock 311 * is also used by the controller. It may crash during some operation if the 312 * clock is stopped. The safest thing to do, whenever possible, is to keep 313 * clock running at stop it at the pad using the pinmux. 314 */ 315 static void meson_mmc_clk_gate(struct meson_host *host) 316 { 317 u32 cfg; 318 319 if (host->pins_clk_gate) { 320 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 321 } else { 322 /* 323 * If the pinmux is not provided - default to the classic and 324 * unsafe method 325 */ 326 cfg = readl(host->regs + SD_EMMC_CFG); 327 cfg |= CFG_STOP_CLOCK; 328 writel(cfg, host->regs + SD_EMMC_CFG); 329 } 330 } 331 332 static void meson_mmc_clk_ungate(struct meson_host *host) 333 { 334 u32 cfg; 335 336 if (host->pins_clk_gate) 337 pinctrl_select_default_state(host->dev); 338 339 /* Make sure the clock is not stopped in the controller */ 340 cfg = readl(host->regs + SD_EMMC_CFG); 341 cfg &= ~CFG_STOP_CLOCK; 342 writel(cfg, host->regs + SD_EMMC_CFG); 343 } 344 345 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 346 bool ddr) 347 { 348 struct mmc_host *mmc = host->mmc; 349 int ret; 350 u32 cfg; 351 352 /* Same request - bail-out */ 353 if (host->ddr == ddr && host->req_rate == rate) 354 return 0; 355 356 /* stop clock */ 357 meson_mmc_clk_gate(host); 358 host->req_rate = 0; 359 mmc->actual_clock = 0; 360 361 /* return with clock being stopped */ 362 if (!rate) 363 return 0; 364 365 /* Stop the clock during rate change to avoid glitches */ 366 cfg = readl(host->regs + SD_EMMC_CFG); 367 cfg |= CFG_STOP_CLOCK; 368 writel(cfg, host->regs + SD_EMMC_CFG); 369 370 if (ddr) { 371 /* DDR modes require higher module clock */ 372 rate <<= 1; 373 cfg |= CFG_DDR; 374 } else { 375 cfg &= ~CFG_DDR; 376 } 377 writel(cfg, host->regs + SD_EMMC_CFG); 378 host->ddr = ddr; 379 380 ret = clk_set_rate(host->mmc_clk, rate); 381 if (ret) { 382 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 383 rate, ret); 384 return ret; 385 } 386 387 host->req_rate = rate; 388 mmc->actual_clock = clk_get_rate(host->mmc_clk); 389 390 /* We should report the real output frequency of the controller */ 391 if (ddr) { 392 host->req_rate >>= 1; 393 mmc->actual_clock >>= 1; 394 } 395 396 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 397 if (rate != mmc->actual_clock) 398 dev_dbg(host->dev, "requested rate was %lu\n", rate); 399 400 /* (re)start clock */ 401 meson_mmc_clk_ungate(host); 402 403 return 0; 404 } 405 406 /* 407 * The SD/eMMC IP block has an internal mux and divider used for 408 * generating the MMC clock. Use the clock framework to create and 409 * manage these clocks. 410 */ 411 static int meson_mmc_clk_init(struct meson_host *host) 412 { 413 struct clk_init_data init; 414 struct clk_mux *mux; 415 struct clk_divider *div; 416 char clk_name[32]; 417 int i, ret = 0; 418 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 419 const char *clk_parent[1]; 420 u32 clk_reg; 421 422 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 423 clk_reg = CLK_ALWAYS_ON(host); 424 clk_reg |= CLK_DIV_MASK; 425 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 426 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 427 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 428 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 429 430 /* get the mux parents */ 431 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 432 struct clk *clk; 433 char name[16]; 434 435 snprintf(name, sizeof(name), "clkin%d", i); 436 clk = devm_clk_get(host->dev, name); 437 if (IS_ERR(clk)) 438 return dev_err_probe(host->dev, PTR_ERR(clk), 439 "Missing clock %s\n", name); 440 441 mux_parent_names[i] = __clk_get_name(clk); 442 } 443 444 /* create the mux */ 445 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 446 if (!mux) 447 return -ENOMEM; 448 449 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 450 init.name = clk_name; 451 init.ops = &clk_mux_ops; 452 init.flags = 0; 453 init.parent_names = mux_parent_names; 454 init.num_parents = MUX_CLK_NUM_PARENTS; 455 456 mux->reg = host->regs + SD_EMMC_CLOCK; 457 mux->shift = __ffs(CLK_SRC_MASK); 458 mux->mask = CLK_SRC_MASK >> mux->shift; 459 mux->hw.init = &init; 460 461 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 462 if (WARN_ON(IS_ERR(host->mux_clk))) 463 return PTR_ERR(host->mux_clk); 464 465 /* create the divider */ 466 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 467 if (!div) 468 return -ENOMEM; 469 470 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 471 init.name = clk_name; 472 init.ops = &clk_divider_ops; 473 init.flags = CLK_SET_RATE_PARENT; 474 clk_parent[0] = __clk_get_name(host->mux_clk); 475 init.parent_names = clk_parent; 476 init.num_parents = 1; 477 478 div->reg = host->regs + SD_EMMC_CLOCK; 479 div->shift = __ffs(CLK_DIV_MASK); 480 div->width = __builtin_popcountl(CLK_DIV_MASK); 481 div->hw.init = &init; 482 div->flags = CLK_DIVIDER_ONE_BASED; 483 484 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 485 if (WARN_ON(IS_ERR(host->mmc_clk))) 486 return PTR_ERR(host->mmc_clk); 487 488 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 489 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 490 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 491 if (ret) 492 return ret; 493 494 return clk_prepare_enable(host->mmc_clk); 495 } 496 497 static void meson_mmc_disable_resampling(struct meson_host *host) 498 { 499 unsigned int val = readl(host->regs + host->data->adjust); 500 501 val &= ~ADJUST_ADJ_EN; 502 writel(val, host->regs + host->data->adjust); 503 } 504 505 static void meson_mmc_reset_resampling(struct meson_host *host) 506 { 507 unsigned int val; 508 509 meson_mmc_disable_resampling(host); 510 511 val = readl(host->regs + host->data->adjust); 512 val &= ~ADJUST_ADJ_DELAY_MASK; 513 writel(val, host->regs + host->data->adjust); 514 } 515 516 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 517 { 518 struct meson_host *host = mmc_priv(mmc); 519 unsigned int val, dly, max_dly, i; 520 int ret; 521 522 /* Resampling is done using the source clock */ 523 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 524 clk_get_rate(host->mmc_clk)); 525 526 val = readl(host->regs + host->data->adjust); 527 val |= ADJUST_ADJ_EN; 528 writel(val, host->regs + host->data->adjust); 529 530 if (mmc_doing_retune(mmc)) 531 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 532 else 533 dly = 0; 534 535 for (i = 0; i < max_dly; i++) { 536 val &= ~ADJUST_ADJ_DELAY_MASK; 537 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 538 writel(val, host->regs + host->data->adjust); 539 540 ret = mmc_send_tuning(mmc, opcode, NULL); 541 if (!ret) { 542 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 543 (dly + i) % max_dly); 544 return 0; 545 } 546 } 547 548 meson_mmc_reset_resampling(host); 549 return -EIO; 550 } 551 552 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 553 struct mmc_ios *ios) 554 { 555 bool ddr; 556 557 switch (ios->timing) { 558 case MMC_TIMING_MMC_DDR52: 559 case MMC_TIMING_UHS_DDR50: 560 ddr = true; 561 break; 562 563 default: 564 ddr = false; 565 break; 566 } 567 568 return meson_mmc_clk_set(host, ios->clock, ddr); 569 } 570 571 static void meson_mmc_check_resampling(struct meson_host *host, 572 struct mmc_ios *ios) 573 { 574 switch (ios->timing) { 575 case MMC_TIMING_LEGACY: 576 case MMC_TIMING_MMC_HS: 577 case MMC_TIMING_SD_HS: 578 case MMC_TIMING_MMC_DDR52: 579 meson_mmc_disable_resampling(host); 580 break; 581 } 582 } 583 584 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 585 { 586 struct meson_host *host = mmc_priv(mmc); 587 u32 bus_width, val; 588 int err; 589 590 /* 591 * GPIO regulator, only controls switching between 1v8 and 592 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 593 */ 594 switch (ios->power_mode) { 595 case MMC_POWER_OFF: 596 if (!IS_ERR(mmc->supply.vmmc)) 597 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 598 599 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 600 regulator_disable(mmc->supply.vqmmc); 601 host->vqmmc_enabled = false; 602 } 603 604 break; 605 606 case MMC_POWER_UP: 607 if (!IS_ERR(mmc->supply.vmmc)) 608 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 609 610 break; 611 612 case MMC_POWER_ON: 613 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 614 int ret = regulator_enable(mmc->supply.vqmmc); 615 616 if (ret < 0) 617 dev_err(host->dev, 618 "failed to enable vqmmc regulator\n"); 619 else 620 host->vqmmc_enabled = true; 621 } 622 623 break; 624 } 625 626 /* Bus width */ 627 switch (ios->bus_width) { 628 case MMC_BUS_WIDTH_1: 629 bus_width = CFG_BUS_WIDTH_1; 630 break; 631 case MMC_BUS_WIDTH_4: 632 bus_width = CFG_BUS_WIDTH_4; 633 break; 634 case MMC_BUS_WIDTH_8: 635 bus_width = CFG_BUS_WIDTH_8; 636 break; 637 default: 638 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 639 ios->bus_width); 640 bus_width = CFG_BUS_WIDTH_4; 641 } 642 643 val = readl(host->regs + SD_EMMC_CFG); 644 val &= ~CFG_BUS_WIDTH_MASK; 645 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 646 writel(val, host->regs + SD_EMMC_CFG); 647 648 meson_mmc_check_resampling(host, ios); 649 err = meson_mmc_prepare_ios_clock(host, ios); 650 if (err) 651 dev_err(host->dev, "Failed to set clock: %d\n,", err); 652 653 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 654 } 655 656 static void meson_mmc_request_done(struct mmc_host *mmc, 657 struct mmc_request *mrq) 658 { 659 struct meson_host *host = mmc_priv(mmc); 660 661 host->cmd = NULL; 662 mmc_request_done(host->mmc, mrq); 663 } 664 665 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 666 { 667 struct meson_host *host = mmc_priv(mmc); 668 u32 cfg, blksz_old; 669 670 cfg = readl(host->regs + SD_EMMC_CFG); 671 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 672 673 if (!is_power_of_2(blksz)) 674 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 675 676 blksz = ilog2(blksz); 677 678 /* check if block-size matches, if not update */ 679 if (blksz == blksz_old) 680 return; 681 682 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 683 blksz_old, blksz); 684 685 cfg &= ~CFG_BLK_LEN_MASK; 686 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 687 writel(cfg, host->regs + SD_EMMC_CFG); 688 } 689 690 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 691 { 692 if (cmd->flags & MMC_RSP_PRESENT) { 693 if (cmd->flags & MMC_RSP_136) 694 *cmd_cfg |= CMD_CFG_RESP_128; 695 *cmd_cfg |= CMD_CFG_RESP_NUM; 696 697 if (!(cmd->flags & MMC_RSP_CRC)) 698 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 699 700 if (cmd->flags & MMC_RSP_BUSY) 701 *cmd_cfg |= CMD_CFG_R1B; 702 } else { 703 *cmd_cfg |= CMD_CFG_NO_RESP; 704 } 705 } 706 707 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 708 { 709 struct meson_host *host = mmc_priv(mmc); 710 struct sd_emmc_desc *desc = host->descs; 711 struct mmc_data *data = host->cmd->data; 712 struct scatterlist *sg; 713 u32 start; 714 int i; 715 716 if (data->flags & MMC_DATA_WRITE) 717 cmd_cfg |= CMD_CFG_DATA_WR; 718 719 if (data->blocks > 1) { 720 cmd_cfg |= CMD_CFG_BLOCK_MODE; 721 meson_mmc_set_blksz(mmc, data->blksz); 722 } 723 724 for_each_sg(data->sg, sg, data->sg_count, i) { 725 unsigned int len = sg_dma_len(sg); 726 727 if (data->blocks > 1) 728 len /= data->blksz; 729 730 desc[i].cmd_cfg = cmd_cfg; 731 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 732 if (i > 0) 733 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 734 desc[i].cmd_arg = host->cmd->arg; 735 desc[i].cmd_resp = 0; 736 desc[i].cmd_data = sg_dma_address(sg); 737 } 738 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 739 740 dma_wmb(); /* ensure descriptor is written before kicked */ 741 start = host->descs_dma_addr | START_DESC_BUSY; 742 writel(start, host->regs + SD_EMMC_START); 743 } 744 745 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 746 { 747 struct meson_host *host = mmc_priv(mmc); 748 struct mmc_data *data = cmd->data; 749 u32 cmd_cfg = 0, cmd_data = 0; 750 unsigned int xfer_bytes = 0; 751 752 /* Setup descriptors */ 753 dma_rmb(); 754 755 host->cmd = cmd; 756 757 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 758 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 759 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 760 761 meson_mmc_set_response_bits(cmd, &cmd_cfg); 762 763 /* data? */ 764 if (data) { 765 data->bytes_xfered = 0; 766 cmd_cfg |= CMD_CFG_DATA_IO; 767 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 768 ilog2(meson_mmc_get_timeout_msecs(data))); 769 770 if (meson_mmc_desc_chain_mode(data)) { 771 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 772 return; 773 } 774 775 if (data->blocks > 1) { 776 cmd_cfg |= CMD_CFG_BLOCK_MODE; 777 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 778 data->blocks); 779 meson_mmc_set_blksz(mmc, data->blksz); 780 } else { 781 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 782 } 783 784 xfer_bytes = data->blksz * data->blocks; 785 if (data->flags & MMC_DATA_WRITE) { 786 cmd_cfg |= CMD_CFG_DATA_WR; 787 WARN_ON(xfer_bytes > host->bounce_buf_size); 788 sg_copy_to_buffer(data->sg, data->sg_len, 789 host->bounce_buf, xfer_bytes); 790 dma_wmb(); 791 } 792 793 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 794 } else { 795 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 796 ilog2(SD_EMMC_CMD_TIMEOUT)); 797 } 798 799 /* Last descriptor */ 800 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 801 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 802 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 803 writel(0, host->regs + SD_EMMC_CMD_RSP); 804 wmb(); /* ensure descriptor is written before kicked */ 805 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 806 } 807 808 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 809 { 810 struct meson_host *host = mmc_priv(mmc); 811 bool needs_pre_post_req = mrq->data && 812 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 813 814 if (needs_pre_post_req) { 815 meson_mmc_get_transfer_mode(mmc, mrq); 816 if (!meson_mmc_desc_chain_mode(mrq->data)) 817 needs_pre_post_req = false; 818 } 819 820 if (needs_pre_post_req) 821 meson_mmc_pre_req(mmc, mrq); 822 823 /* Stop execution */ 824 writel(0, host->regs + SD_EMMC_START); 825 826 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 827 828 if (needs_pre_post_req) 829 meson_mmc_post_req(mmc, mrq, 0); 830 } 831 832 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 833 { 834 struct meson_host *host = mmc_priv(mmc); 835 836 if (cmd->flags & MMC_RSP_136) { 837 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 838 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 839 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 840 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 841 } else if (cmd->flags & MMC_RSP_PRESENT) { 842 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 843 } 844 } 845 846 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 847 { 848 struct meson_host *host = dev_id; 849 struct mmc_command *cmd; 850 struct mmc_data *data; 851 u32 irq_en, status, raw_status; 852 irqreturn_t ret = IRQ_NONE; 853 854 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 855 raw_status = readl(host->regs + SD_EMMC_STATUS); 856 status = raw_status & irq_en; 857 858 if (!status) { 859 dev_dbg(host->dev, 860 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 861 irq_en, raw_status); 862 return IRQ_NONE; 863 } 864 865 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 866 return IRQ_NONE; 867 868 /* ack all raised interrupts */ 869 writel(status, host->regs + SD_EMMC_STATUS); 870 871 cmd = host->cmd; 872 data = cmd->data; 873 cmd->error = 0; 874 if (status & IRQ_CRC_ERR) { 875 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 876 cmd->error = -EILSEQ; 877 ret = IRQ_WAKE_THREAD; 878 goto out; 879 } 880 881 if (status & IRQ_TIMEOUTS) { 882 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 883 cmd->error = -ETIMEDOUT; 884 ret = IRQ_WAKE_THREAD; 885 goto out; 886 } 887 888 meson_mmc_read_resp(host->mmc, cmd); 889 890 if (status & IRQ_SDIO) { 891 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 892 ret = IRQ_HANDLED; 893 } 894 895 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 896 if (data && !cmd->error) 897 data->bytes_xfered = data->blksz * data->blocks; 898 if (meson_mmc_bounce_buf_read(data) || 899 meson_mmc_get_next_command(cmd)) 900 ret = IRQ_WAKE_THREAD; 901 else 902 ret = IRQ_HANDLED; 903 } 904 905 out: 906 if (cmd->error) { 907 /* Stop desc in case of errors */ 908 u32 start = readl(host->regs + SD_EMMC_START); 909 910 start &= ~START_DESC_BUSY; 911 writel(start, host->regs + SD_EMMC_START); 912 } 913 914 if (ret == IRQ_HANDLED) 915 meson_mmc_request_done(host->mmc, cmd->mrq); 916 917 return ret; 918 } 919 920 static int meson_mmc_wait_desc_stop(struct meson_host *host) 921 { 922 u32 status; 923 924 /* 925 * It may sometimes take a while for it to actually halt. Here, we 926 * are giving it 5ms to comply 927 * 928 * If we don't confirm the descriptor is stopped, it might raise new 929 * IRQs after we have called mmc_request_done() which is bad. 930 */ 931 932 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 933 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 934 100, 5000); 935 } 936 937 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 938 { 939 struct meson_host *host = dev_id; 940 struct mmc_command *next_cmd, *cmd = host->cmd; 941 struct mmc_data *data; 942 unsigned int xfer_bytes; 943 944 if (WARN_ON(!cmd)) 945 return IRQ_NONE; 946 947 if (cmd->error) { 948 meson_mmc_wait_desc_stop(host); 949 meson_mmc_request_done(host->mmc, cmd->mrq); 950 951 return IRQ_HANDLED; 952 } 953 954 data = cmd->data; 955 if (meson_mmc_bounce_buf_read(data)) { 956 xfer_bytes = data->blksz * data->blocks; 957 WARN_ON(xfer_bytes > host->bounce_buf_size); 958 sg_copy_from_buffer(data->sg, data->sg_len, 959 host->bounce_buf, xfer_bytes); 960 } 961 962 next_cmd = meson_mmc_get_next_command(cmd); 963 if (next_cmd) 964 meson_mmc_start_cmd(host->mmc, next_cmd); 965 else 966 meson_mmc_request_done(host->mmc, cmd->mrq); 967 968 return IRQ_HANDLED; 969 } 970 971 /* 972 * NOTE: we only need this until the GPIO/pinctrl driver can handle 973 * interrupts. For now, the MMC core will use this for polling. 974 */ 975 static int meson_mmc_get_cd(struct mmc_host *mmc) 976 { 977 int status = mmc_gpio_get_cd(mmc); 978 979 if (status == -ENOSYS) 980 return 1; /* assume present */ 981 982 return status; 983 } 984 985 static void meson_mmc_cfg_init(struct meson_host *host) 986 { 987 u32 cfg = 0; 988 989 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 990 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 991 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 992 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 993 994 /* abort chain on R/W errors */ 995 cfg |= CFG_ERR_ABORT; 996 997 writel(cfg, host->regs + SD_EMMC_CFG); 998 } 999 1000 static int meson_mmc_card_busy(struct mmc_host *mmc) 1001 { 1002 struct meson_host *host = mmc_priv(mmc); 1003 u32 regval; 1004 1005 regval = readl(host->regs + SD_EMMC_STATUS); 1006 1007 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1008 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1009 } 1010 1011 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1012 { 1013 int ret; 1014 1015 /* vqmmc regulator is available */ 1016 if (!IS_ERR(mmc->supply.vqmmc)) { 1017 /* 1018 * The usual amlogic setup uses a GPIO to switch from one 1019 * regulator to the other. While the voltage ramp up is 1020 * pretty fast, care must be taken when switching from 3.3v 1021 * to 1.8v. Please make sure the regulator framework is aware 1022 * of your own regulator constraints 1023 */ 1024 ret = mmc_regulator_set_vqmmc(mmc, ios); 1025 return ret < 0 ? ret : 0; 1026 } 1027 1028 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1029 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1030 return 0; 1031 1032 return -EINVAL; 1033 } 1034 1035 static const struct mmc_host_ops meson_mmc_ops = { 1036 .request = meson_mmc_request, 1037 .set_ios = meson_mmc_set_ios, 1038 .get_cd = meson_mmc_get_cd, 1039 .pre_req = meson_mmc_pre_req, 1040 .post_req = meson_mmc_post_req, 1041 .execute_tuning = meson_mmc_resampling_tuning, 1042 .card_busy = meson_mmc_card_busy, 1043 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1044 }; 1045 1046 static int meson_mmc_probe(struct platform_device *pdev) 1047 { 1048 struct resource *res; 1049 struct meson_host *host; 1050 struct mmc_host *mmc; 1051 int ret; 1052 1053 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1054 if (!mmc) 1055 return -ENOMEM; 1056 host = mmc_priv(mmc); 1057 host->mmc = mmc; 1058 host->dev = &pdev->dev; 1059 dev_set_drvdata(&pdev->dev, host); 1060 1061 /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1062 host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1063 "amlogic,dram-access-quirk"); 1064 1065 /* Get regulators and the supported OCR mask */ 1066 host->vqmmc_enabled = false; 1067 ret = mmc_regulator_get_supply(mmc); 1068 if (ret) 1069 goto free_host; 1070 1071 ret = mmc_of_parse(mmc); 1072 if (ret) { 1073 if (ret != -EPROBE_DEFER) 1074 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1075 goto free_host; 1076 } 1077 1078 host->data = (struct meson_mmc_data *) 1079 of_device_get_match_data(&pdev->dev); 1080 if (!host->data) { 1081 ret = -EINVAL; 1082 goto free_host; 1083 } 1084 1085 ret = device_reset_optional(&pdev->dev); 1086 if (ret) 1087 return dev_err_probe(&pdev->dev, ret, "device reset failed\n"); 1088 1089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1090 host->regs = devm_ioremap_resource(&pdev->dev, res); 1091 if (IS_ERR(host->regs)) { 1092 ret = PTR_ERR(host->regs); 1093 goto free_host; 1094 } 1095 1096 host->irq = platform_get_irq(pdev, 0); 1097 if (host->irq <= 0) { 1098 ret = -EINVAL; 1099 goto free_host; 1100 } 1101 1102 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1103 if (IS_ERR(host->pinctrl)) { 1104 ret = PTR_ERR(host->pinctrl); 1105 goto free_host; 1106 } 1107 1108 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1109 "clk-gate"); 1110 if (IS_ERR(host->pins_clk_gate)) { 1111 dev_warn(&pdev->dev, 1112 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1113 host->pins_clk_gate = NULL; 1114 } 1115 1116 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1117 if (IS_ERR(host->core_clk)) { 1118 ret = PTR_ERR(host->core_clk); 1119 goto free_host; 1120 } 1121 1122 ret = clk_prepare_enable(host->core_clk); 1123 if (ret) 1124 goto free_host; 1125 1126 ret = meson_mmc_clk_init(host); 1127 if (ret) 1128 goto err_core_clk; 1129 1130 /* set config to sane default */ 1131 meson_mmc_cfg_init(host); 1132 1133 /* Stop execution */ 1134 writel(0, host->regs + SD_EMMC_START); 1135 1136 /* clear, ack and enable interrupts */ 1137 writel(0, host->regs + SD_EMMC_IRQ_EN); 1138 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1139 host->regs + SD_EMMC_STATUS); 1140 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1141 host->regs + SD_EMMC_IRQ_EN); 1142 1143 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1144 meson_mmc_irq_thread, IRQF_ONESHOT, 1145 dev_name(&pdev->dev), host); 1146 if (ret) 1147 goto err_init_clk; 1148 1149 mmc->caps |= MMC_CAP_CMD23; 1150 if (host->dram_access_quirk) { 1151 /* Limit segments to 1 due to low available sram memory */ 1152 mmc->max_segs = 1; 1153 /* Limit to the available sram memory */ 1154 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 1155 mmc->max_blk_size; 1156 } else { 1157 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1158 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1159 sizeof(struct sd_emmc_desc); 1160 } 1161 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1162 mmc->max_seg_size = mmc->max_req_size; 1163 1164 /* 1165 * At the moment, we don't know how to reliably enable HS400. 1166 * From the different datasheets, it is not even clear if this mode 1167 * is officially supported by any of the SoCs 1168 */ 1169 mmc->caps2 &= ~MMC_CAP2_HS400; 1170 1171 if (host->dram_access_quirk) { 1172 /* 1173 * The MMC Controller embeds 1,5KiB of internal SRAM 1174 * that can be used to be used as bounce buffer. 1175 * In the case of the G12A SDIO controller, use these 1176 * instead of the DDR memory 1177 */ 1178 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1179 host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1180 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1181 } else { 1182 /* data bounce buffer */ 1183 host->bounce_buf_size = mmc->max_req_size; 1184 host->bounce_buf = 1185 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1186 &host->bounce_dma_addr, GFP_KERNEL); 1187 if (host->bounce_buf == NULL) { 1188 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1189 ret = -ENOMEM; 1190 goto err_free_irq; 1191 } 1192 } 1193 1194 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1195 &host->descs_dma_addr, GFP_KERNEL); 1196 if (!host->descs) { 1197 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1198 ret = -ENOMEM; 1199 goto err_bounce_buf; 1200 } 1201 1202 mmc->ops = &meson_mmc_ops; 1203 mmc_add_host(mmc); 1204 1205 return 0; 1206 1207 err_bounce_buf: 1208 if (!host->dram_access_quirk) 1209 dma_free_coherent(host->dev, host->bounce_buf_size, 1210 host->bounce_buf, host->bounce_dma_addr); 1211 err_free_irq: 1212 free_irq(host->irq, host); 1213 err_init_clk: 1214 clk_disable_unprepare(host->mmc_clk); 1215 err_core_clk: 1216 clk_disable_unprepare(host->core_clk); 1217 free_host: 1218 mmc_free_host(mmc); 1219 return ret; 1220 } 1221 1222 static int meson_mmc_remove(struct platform_device *pdev) 1223 { 1224 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1225 1226 mmc_remove_host(host->mmc); 1227 1228 /* disable interrupts */ 1229 writel(0, host->regs + SD_EMMC_IRQ_EN); 1230 free_irq(host->irq, host); 1231 1232 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1233 host->descs, host->descs_dma_addr); 1234 1235 if (!host->dram_access_quirk) 1236 dma_free_coherent(host->dev, host->bounce_buf_size, 1237 host->bounce_buf, host->bounce_dma_addr); 1238 1239 clk_disable_unprepare(host->mmc_clk); 1240 clk_disable_unprepare(host->core_clk); 1241 1242 mmc_free_host(host->mmc); 1243 return 0; 1244 } 1245 1246 static const struct meson_mmc_data meson_gx_data = { 1247 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1248 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1249 .always_on = CLK_V2_ALWAYS_ON, 1250 .adjust = SD_EMMC_ADJUST, 1251 }; 1252 1253 static const struct meson_mmc_data meson_axg_data = { 1254 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1255 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1256 .always_on = CLK_V3_ALWAYS_ON, 1257 .adjust = SD_EMMC_V3_ADJUST, 1258 }; 1259 1260 static const struct of_device_id meson_mmc_of_match[] = { 1261 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1262 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1263 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1264 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1265 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1266 {} 1267 }; 1268 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1269 1270 static struct platform_driver meson_mmc_driver = { 1271 .probe = meson_mmc_probe, 1272 .remove = meson_mmc_remove, 1273 .driver = { 1274 .name = DRIVER_NAME, 1275 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1276 .of_match_table = meson_mmc_of_match, 1277 }, 1278 }; 1279 1280 module_platform_driver(meson_mmc_driver); 1281 1282 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1283 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1284 MODULE_LICENSE("GPL v2"); 1285