1 /* 2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 3 * 4 * Copyright (c) 2016 BayLibre, SAS. 5 * Author: Kevin Hilman <khilman@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * The full GNU General Public License is included in this distribution 19 * in the file called COPYING. 20 */ 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/device.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/ioport.h> 28 #include <linux/spinlock.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 #include <linux/io.h> 35 #include <linux/clk.h> 36 #include <linux/clk-provider.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/interrupt.h> 39 40 #define DRIVER_NAME "meson-gx-mmc" 41 42 #define SD_EMMC_CLOCK 0x0 43 #define CLK_DIV_SHIFT 0 44 #define CLK_DIV_WIDTH 6 45 #define CLK_DIV_MASK 0x3f 46 #define CLK_DIV_MAX 63 47 #define CLK_SRC_SHIFT 6 48 #define CLK_SRC_WIDTH 2 49 #define CLK_SRC_MASK 0x3 50 #define CLK_SRC_XTAL 0 /* external crystal */ 51 #define CLK_SRC_XTAL_RATE 24000000 52 #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ 53 #define CLK_SRC_PLL_RATE 1000000000 54 #define CLK_PHASE_SHIFT 8 55 #define CLK_PHASE_MASK 0x3 56 #define CLK_PHASE_0 0 57 #define CLK_PHASE_90 1 58 #define CLK_PHASE_180 2 59 #define CLK_PHASE_270 3 60 #define CLK_ALWAYS_ON BIT(24) 61 62 #define SD_EMMC_DElAY 0x4 63 #define SD_EMMC_ADJUST 0x8 64 #define SD_EMMC_CALOUT 0x10 65 #define SD_EMMC_START 0x40 66 #define START_DESC_INIT BIT(0) 67 #define START_DESC_BUSY BIT(1) 68 #define START_DESC_ADDR_SHIFT 2 69 #define START_DESC_ADDR_MASK (~0x3) 70 71 #define SD_EMMC_CFG 0x44 72 #define CFG_BUS_WIDTH_SHIFT 0 73 #define CFG_BUS_WIDTH_MASK 0x3 74 #define CFG_BUS_WIDTH_1 0x0 75 #define CFG_BUS_WIDTH_4 0x1 76 #define CFG_BUS_WIDTH_8 0x2 77 #define CFG_DDR BIT(2) 78 #define CFG_BLK_LEN_SHIFT 4 79 #define CFG_BLK_LEN_MASK 0xf 80 #define CFG_RESP_TIMEOUT_SHIFT 8 81 #define CFG_RESP_TIMEOUT_MASK 0xf 82 #define CFG_RC_CC_SHIFT 12 83 #define CFG_RC_CC_MASK 0xf 84 #define CFG_STOP_CLOCK BIT(22) 85 #define CFG_CLK_ALWAYS_ON BIT(18) 86 #define CFG_CHK_DS BIT(20) 87 #define CFG_AUTO_CLK BIT(23) 88 89 #define SD_EMMC_STATUS 0x48 90 #define STATUS_BUSY BIT(31) 91 92 #define SD_EMMC_IRQ_EN 0x4c 93 #define IRQ_EN_MASK 0x3fff 94 #define IRQ_RXD_ERR_SHIFT 0 95 #define IRQ_RXD_ERR_MASK 0xff 96 #define IRQ_TXD_ERR BIT(8) 97 #define IRQ_DESC_ERR BIT(9) 98 #define IRQ_RESP_ERR BIT(10) 99 #define IRQ_RESP_TIMEOUT BIT(11) 100 #define IRQ_DESC_TIMEOUT BIT(12) 101 #define IRQ_END_OF_CHAIN BIT(13) 102 #define IRQ_RESP_STATUS BIT(14) 103 #define IRQ_SDIO BIT(15) 104 105 #define SD_EMMC_CMD_CFG 0x50 106 #define SD_EMMC_CMD_ARG 0x54 107 #define SD_EMMC_CMD_DAT 0x58 108 #define SD_EMMC_CMD_RSP 0x5c 109 #define SD_EMMC_CMD_RSP1 0x60 110 #define SD_EMMC_CMD_RSP2 0x64 111 #define SD_EMMC_CMD_RSP3 0x68 112 113 #define SD_EMMC_RXD 0x94 114 #define SD_EMMC_TXD 0x94 115 #define SD_EMMC_LAST_REG SD_EMMC_TXD 116 117 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 118 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 119 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 120 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 121 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 122 #define MUX_CLK_NUM_PARENTS 2 123 124 struct meson_host { 125 struct device *dev; 126 struct mmc_host *mmc; 127 struct mmc_command *cmd; 128 129 spinlock_t lock; 130 void __iomem *regs; 131 struct clk *core_clk; 132 struct clk_mux mux; 133 struct clk *mux_clk; 134 unsigned long current_clock; 135 136 struct clk_divider cfg_div; 137 struct clk *cfg_div_clk; 138 139 unsigned int bounce_buf_size; 140 void *bounce_buf; 141 dma_addr_t bounce_dma_addr; 142 143 bool vqmmc_enabled; 144 }; 145 146 struct sd_emmc_desc { 147 u32 cmd_cfg; 148 u32 cmd_arg; 149 u32 cmd_data; 150 u32 cmd_resp; 151 }; 152 #define CMD_CFG_LENGTH_SHIFT 0 153 #define CMD_CFG_LENGTH_MASK 0x1ff 154 #define CMD_CFG_BLOCK_MODE BIT(9) 155 #define CMD_CFG_R1B BIT(10) 156 #define CMD_CFG_END_OF_CHAIN BIT(11) 157 #define CMD_CFG_TIMEOUT_SHIFT 12 158 #define CMD_CFG_TIMEOUT_MASK 0xf 159 #define CMD_CFG_NO_RESP BIT(16) 160 #define CMD_CFG_NO_CMD BIT(17) 161 #define CMD_CFG_DATA_IO BIT(18) 162 #define CMD_CFG_DATA_WR BIT(19) 163 #define CMD_CFG_RESP_NOCRC BIT(20) 164 #define CMD_CFG_RESP_128 BIT(21) 165 #define CMD_CFG_RESP_NUM BIT(22) 166 #define CMD_CFG_DATA_NUM BIT(23) 167 #define CMD_CFG_CMD_INDEX_SHIFT 24 168 #define CMD_CFG_CMD_INDEX_MASK 0x3f 169 #define CMD_CFG_ERROR BIT(30) 170 #define CMD_CFG_OWNER BIT(31) 171 172 #define CMD_DATA_MASK (~0x3) 173 #define CMD_DATA_BIG_ENDIAN BIT(1) 174 #define CMD_DATA_SRAM BIT(0) 175 #define CMD_RESP_MASK (~0x1) 176 #define CMD_RESP_SRAM BIT(0) 177 178 static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) 179 { 180 struct mmc_host *mmc = host->mmc; 181 int ret; 182 u32 cfg; 183 184 if (clk_rate) { 185 if (WARN_ON(clk_rate > mmc->f_max)) 186 clk_rate = mmc->f_max; 187 else if (WARN_ON(clk_rate < mmc->f_min)) 188 clk_rate = mmc->f_min; 189 } 190 191 if (clk_rate == host->current_clock) 192 return 0; 193 194 /* stop clock */ 195 cfg = readl(host->regs + SD_EMMC_CFG); 196 if (!(cfg & CFG_STOP_CLOCK)) { 197 cfg |= CFG_STOP_CLOCK; 198 writel(cfg, host->regs + SD_EMMC_CFG); 199 } 200 201 dev_dbg(host->dev, "change clock rate %u -> %lu\n", 202 mmc->actual_clock, clk_rate); 203 204 if (!clk_rate) { 205 mmc->actual_clock = 0; 206 host->current_clock = 0; 207 /* return with clock being stopped */ 208 return 0; 209 } 210 211 ret = clk_set_rate(host->cfg_div_clk, clk_rate); 212 if (ret) { 213 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 214 clk_rate, ret); 215 return ret; 216 } 217 218 mmc->actual_clock = clk_get_rate(host->cfg_div_clk); 219 host->current_clock = clk_rate; 220 221 if (clk_rate != mmc->actual_clock) 222 dev_dbg(host->dev, 223 "divider requested rate %lu != actual rate %u\n", 224 clk_rate, mmc->actual_clock); 225 226 /* (re)start clock */ 227 cfg = readl(host->regs + SD_EMMC_CFG); 228 cfg &= ~CFG_STOP_CLOCK; 229 writel(cfg, host->regs + SD_EMMC_CFG); 230 231 return 0; 232 } 233 234 /* 235 * The SD/eMMC IP block has an internal mux and divider used for 236 * generating the MMC clock. Use the clock framework to create and 237 * manage these clocks. 238 */ 239 static int meson_mmc_clk_init(struct meson_host *host) 240 { 241 struct clk_init_data init; 242 char clk_name[32]; 243 int i, ret = 0; 244 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 245 const char *clk_div_parents[1]; 246 u32 clk_reg, cfg; 247 248 /* get the mux parents */ 249 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 250 struct clk *clk; 251 char name[16]; 252 253 snprintf(name, sizeof(name), "clkin%d", i); 254 clk = devm_clk_get(host->dev, name); 255 if (IS_ERR(clk)) { 256 if (clk != ERR_PTR(-EPROBE_DEFER)) 257 dev_err(host->dev, "Missing clock %s\n", name); 258 return PTR_ERR(clk); 259 } 260 261 mux_parent_names[i] = __clk_get_name(clk); 262 } 263 264 /* create the mux */ 265 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 266 init.name = clk_name; 267 init.ops = &clk_mux_ops; 268 init.flags = 0; 269 init.parent_names = mux_parent_names; 270 init.num_parents = MUX_CLK_NUM_PARENTS; 271 272 host->mux.reg = host->regs + SD_EMMC_CLOCK; 273 host->mux.shift = CLK_SRC_SHIFT; 274 host->mux.mask = CLK_SRC_MASK; 275 host->mux.flags = 0; 276 host->mux.table = NULL; 277 host->mux.hw.init = &init; 278 279 host->mux_clk = devm_clk_register(host->dev, &host->mux.hw); 280 if (WARN_ON(IS_ERR(host->mux_clk))) 281 return PTR_ERR(host->mux_clk); 282 283 /* create the divider */ 284 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 285 init.name = clk_name; 286 init.ops = &clk_divider_ops; 287 init.flags = CLK_SET_RATE_PARENT; 288 clk_div_parents[0] = __clk_get_name(host->mux_clk); 289 init.parent_names = clk_div_parents; 290 init.num_parents = ARRAY_SIZE(clk_div_parents); 291 292 host->cfg_div.reg = host->regs + SD_EMMC_CLOCK; 293 host->cfg_div.shift = CLK_DIV_SHIFT; 294 host->cfg_div.width = CLK_DIV_WIDTH; 295 host->cfg_div.hw.init = &init; 296 host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | 297 CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO; 298 299 host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); 300 if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) 301 return PTR_ERR(host->cfg_div_clk); 302 303 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 304 clk_reg = 0; 305 clk_reg |= CLK_PHASE_180 << CLK_PHASE_SHIFT; 306 clk_reg |= CLK_SRC_XTAL << CLK_SRC_SHIFT; 307 clk_reg |= CLK_DIV_MAX << CLK_DIV_SHIFT; 308 clk_reg &= ~CLK_ALWAYS_ON; 309 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 310 311 /* Ensure clock starts in "auto" mode, not "always on" */ 312 cfg = readl(host->regs + SD_EMMC_CFG); 313 cfg &= ~CFG_CLK_ALWAYS_ON; 314 cfg |= CFG_AUTO_CLK; 315 writel(cfg, host->regs + SD_EMMC_CFG); 316 317 ret = clk_prepare_enable(host->cfg_div_clk); 318 if (ret) 319 return ret; 320 321 /* Get the nearest minimum clock to 400KHz */ 322 host->mmc->f_min = clk_round_rate(host->cfg_div_clk, 400000); 323 324 ret = meson_mmc_clk_set(host, host->mmc->f_min); 325 if (ret) 326 clk_disable_unprepare(host->cfg_div_clk); 327 328 return ret; 329 } 330 331 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 332 { 333 struct meson_host *host = mmc_priv(mmc); 334 u32 bus_width; 335 u32 val, orig; 336 337 /* 338 * GPIO regulator, only controls switching between 1v8 and 339 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 340 */ 341 switch (ios->power_mode) { 342 case MMC_POWER_OFF: 343 if (!IS_ERR(mmc->supply.vmmc)) 344 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 345 346 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 347 regulator_disable(mmc->supply.vqmmc); 348 host->vqmmc_enabled = false; 349 } 350 351 break; 352 353 case MMC_POWER_UP: 354 if (!IS_ERR(mmc->supply.vmmc)) 355 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 356 break; 357 358 case MMC_POWER_ON: 359 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 360 int ret = regulator_enable(mmc->supply.vqmmc); 361 362 if (ret < 0) 363 dev_err(mmc_dev(mmc), 364 "failed to enable vqmmc regulator\n"); 365 else 366 host->vqmmc_enabled = true; 367 } 368 369 break; 370 } 371 372 373 meson_mmc_clk_set(host, ios->clock); 374 375 /* Bus width */ 376 switch (ios->bus_width) { 377 case MMC_BUS_WIDTH_1: 378 bus_width = CFG_BUS_WIDTH_1; 379 break; 380 case MMC_BUS_WIDTH_4: 381 bus_width = CFG_BUS_WIDTH_4; 382 break; 383 case MMC_BUS_WIDTH_8: 384 bus_width = CFG_BUS_WIDTH_8; 385 break; 386 default: 387 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 388 ios->bus_width); 389 bus_width = CFG_BUS_WIDTH_4; 390 } 391 392 val = readl(host->regs + SD_EMMC_CFG); 393 orig = val; 394 395 val &= ~(CFG_BUS_WIDTH_MASK << CFG_BUS_WIDTH_SHIFT); 396 val |= bus_width << CFG_BUS_WIDTH_SHIFT; 397 398 val &= ~CFG_DDR; 399 if (ios->timing == MMC_TIMING_UHS_DDR50 || 400 ios->timing == MMC_TIMING_MMC_DDR52 || 401 ios->timing == MMC_TIMING_MMC_HS400) 402 val |= CFG_DDR; 403 404 val &= ~CFG_CHK_DS; 405 if (ios->timing == MMC_TIMING_MMC_HS400) 406 val |= CFG_CHK_DS; 407 408 if (val != orig) { 409 writel(val, host->regs + SD_EMMC_CFG); 410 dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n", 411 __func__, orig, val); 412 } 413 } 414 415 static void meson_mmc_request_done(struct mmc_host *mmc, 416 struct mmc_request *mrq) 417 { 418 struct meson_host *host = mmc_priv(mmc); 419 420 host->cmd = NULL; 421 mmc_request_done(host->mmc, mrq); 422 } 423 424 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 425 { 426 struct meson_host *host = mmc_priv(mmc); 427 struct mmc_data *data = cmd->data; 428 u32 cfg, cmd_cfg = 0, cmd_data = 0; 429 u8 blk_len, cmd_cfg_timeout; 430 unsigned int xfer_bytes = 0; 431 432 /* Setup descriptors */ 433 dma_rmb(); 434 435 cmd_cfg |= (cmd->opcode & CMD_CFG_CMD_INDEX_MASK) << 436 CMD_CFG_CMD_INDEX_SHIFT; 437 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 438 439 /* Response */ 440 if (cmd->flags & MMC_RSP_PRESENT) { 441 if (cmd->flags & MMC_RSP_136) 442 cmd_cfg |= CMD_CFG_RESP_128; 443 cmd_cfg |= CMD_CFG_RESP_NUM; 444 445 if (!(cmd->flags & MMC_RSP_CRC)) 446 cmd_cfg |= CMD_CFG_RESP_NOCRC; 447 448 if (cmd->flags & MMC_RSP_BUSY) 449 cmd_cfg |= CMD_CFG_R1B; 450 } else { 451 cmd_cfg |= CMD_CFG_NO_RESP; 452 } 453 454 /* data? */ 455 if (data) { 456 cmd_cfg |= CMD_CFG_DATA_IO; 457 if (data->blocks > 1) { 458 cmd_cfg |= CMD_CFG_BLOCK_MODE; 459 cmd_cfg |= (data->blocks & CMD_CFG_LENGTH_MASK) << 460 CMD_CFG_LENGTH_SHIFT; 461 462 /* check if block-size matches, if not update */ 463 cfg = readl(host->regs + SD_EMMC_CFG); 464 blk_len = cfg & (CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 465 blk_len >>= CFG_BLK_LEN_SHIFT; 466 if (blk_len != ilog2(data->blksz)) { 467 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", 468 __func__, blk_len, 469 ilog2(data->blksz)); 470 blk_len = ilog2(data->blksz); 471 cfg &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 472 cfg |= blk_len << CFG_BLK_LEN_SHIFT; 473 writel(cfg, host->regs + SD_EMMC_CFG); 474 } 475 } else { 476 cmd_cfg |= (data->blksz & CMD_CFG_LENGTH_MASK) << 477 CMD_CFG_LENGTH_SHIFT; 478 } 479 480 data->bytes_xfered = 0; 481 xfer_bytes = data->blksz * data->blocks; 482 if (data->flags & MMC_DATA_WRITE) { 483 cmd_cfg |= CMD_CFG_DATA_WR; 484 WARN_ON(xfer_bytes > host->bounce_buf_size); 485 sg_copy_to_buffer(data->sg, data->sg_len, 486 host->bounce_buf, xfer_bytes); 487 data->bytes_xfered = xfer_bytes; 488 dma_wmb(); 489 } 490 491 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 492 493 cmd_cfg_timeout = ilog2(SD_EMMC_CMD_TIMEOUT_DATA); 494 } else { 495 cmd_cfg_timeout = ilog2(SD_EMMC_CMD_TIMEOUT); 496 } 497 cmd_cfg |= (cmd_cfg_timeout & CMD_CFG_TIMEOUT_MASK) << 498 CMD_CFG_TIMEOUT_SHIFT; 499 500 host->cmd = cmd; 501 502 /* Last descriptor */ 503 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 504 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 505 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 506 writel(0, host->regs + SD_EMMC_CMD_RSP); 507 wmb(); /* ensure descriptor is written before kicked */ 508 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 509 } 510 511 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 512 { 513 struct meson_host *host = mmc_priv(mmc); 514 515 /* Stop execution */ 516 writel(0, host->regs + SD_EMMC_START); 517 518 if (mrq->sbc) 519 meson_mmc_start_cmd(mmc, mrq->sbc); 520 else 521 meson_mmc_start_cmd(mmc, mrq->cmd); 522 } 523 524 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 525 { 526 struct meson_host *host = mmc_priv(mmc); 527 528 if (cmd->flags & MMC_RSP_136) { 529 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 530 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 531 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 532 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 533 } else if (cmd->flags & MMC_RSP_PRESENT) { 534 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 535 } 536 } 537 538 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 539 { 540 struct meson_host *host = dev_id; 541 struct mmc_command *cmd; 542 u32 irq_en, status, raw_status; 543 irqreturn_t ret = IRQ_HANDLED; 544 545 if (WARN_ON(!host)) 546 return IRQ_NONE; 547 548 cmd = host->cmd; 549 550 if (WARN_ON(!cmd)) 551 return IRQ_NONE; 552 553 spin_lock(&host->lock); 554 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 555 raw_status = readl(host->regs + SD_EMMC_STATUS); 556 status = raw_status & irq_en; 557 558 if (!status) { 559 dev_warn(host->dev, "Spurious IRQ! status=0x%08x, irq_en=0x%08x\n", 560 raw_status, irq_en); 561 ret = IRQ_NONE; 562 goto out; 563 } 564 565 meson_mmc_read_resp(host->mmc, cmd); 566 567 cmd->error = 0; 568 if (status & IRQ_RXD_ERR_MASK) { 569 dev_dbg(host->dev, "Unhandled IRQ: RXD error\n"); 570 cmd->error = -EILSEQ; 571 } 572 if (status & IRQ_TXD_ERR) { 573 dev_dbg(host->dev, "Unhandled IRQ: TXD error\n"); 574 cmd->error = -EILSEQ; 575 } 576 if (status & IRQ_DESC_ERR) 577 dev_dbg(host->dev, "Unhandled IRQ: Descriptor error\n"); 578 if (status & IRQ_RESP_ERR) { 579 dev_dbg(host->dev, "Unhandled IRQ: Response error\n"); 580 cmd->error = -EILSEQ; 581 } 582 if (status & IRQ_RESP_TIMEOUT) { 583 dev_dbg(host->dev, "Unhandled IRQ: Response timeout\n"); 584 cmd->error = -ETIMEDOUT; 585 } 586 if (status & IRQ_DESC_TIMEOUT) { 587 dev_dbg(host->dev, "Unhandled IRQ: Descriptor timeout\n"); 588 cmd->error = -ETIMEDOUT; 589 } 590 if (status & IRQ_SDIO) 591 dev_dbg(host->dev, "Unhandled IRQ: SDIO.\n"); 592 593 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) 594 ret = IRQ_WAKE_THREAD; 595 else { 596 dev_warn(host->dev, "Unknown IRQ! status=0x%04x: MMC CMD%u arg=0x%08x flags=0x%08x stop=%d\n", 597 status, cmd->opcode, cmd->arg, 598 cmd->flags, cmd->mrq->stop ? 1 : 0); 599 if (cmd->data) { 600 struct mmc_data *data = cmd->data; 601 602 dev_warn(host->dev, "\tblksz %u blocks %u flags 0x%08x (%s%s)", 603 data->blksz, data->blocks, data->flags, 604 data->flags & MMC_DATA_WRITE ? "write" : "", 605 data->flags & MMC_DATA_READ ? "read" : ""); 606 } 607 } 608 609 out: 610 /* ack all (enabled) interrupts */ 611 writel(status, host->regs + SD_EMMC_STATUS); 612 613 if (ret == IRQ_HANDLED) 614 meson_mmc_request_done(host->mmc, cmd->mrq); 615 616 spin_unlock(&host->lock); 617 return ret; 618 } 619 620 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 621 { 622 struct meson_host *host = dev_id; 623 struct mmc_command *cmd = host->cmd; 624 struct mmc_data *data; 625 unsigned int xfer_bytes; 626 627 if (WARN_ON(!cmd)) 628 return IRQ_NONE; 629 630 data = cmd->data; 631 if (data && data->flags & MMC_DATA_READ) { 632 xfer_bytes = data->blksz * data->blocks; 633 WARN_ON(xfer_bytes > host->bounce_buf_size); 634 sg_copy_from_buffer(data->sg, data->sg_len, 635 host->bounce_buf, xfer_bytes); 636 data->bytes_xfered = xfer_bytes; 637 } 638 639 if (!data || !data->stop || cmd->mrq->sbc) 640 meson_mmc_request_done(host->mmc, cmd->mrq); 641 else 642 meson_mmc_start_cmd(host->mmc, data->stop); 643 644 return IRQ_HANDLED; 645 } 646 647 /* 648 * NOTE: we only need this until the GPIO/pinctrl driver can handle 649 * interrupts. For now, the MMC core will use this for polling. 650 */ 651 static int meson_mmc_get_cd(struct mmc_host *mmc) 652 { 653 int status = mmc_gpio_get_cd(mmc); 654 655 if (status == -ENOSYS) 656 return 1; /* assume present */ 657 658 return status; 659 } 660 661 static void meson_mmc_cfg_init(struct meson_host *host) 662 { 663 u32 cfg = 0; 664 665 cfg |= ilog2(SD_EMMC_CFG_RESP_TIMEOUT) << CFG_RESP_TIMEOUT_SHIFT; 666 cfg |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT; 667 cfg |= ilog2(SD_EMMC_CFG_BLK_SIZE) << CFG_BLK_LEN_SHIFT; 668 669 writel(cfg, host->regs + SD_EMMC_CFG); 670 } 671 672 static const struct mmc_host_ops meson_mmc_ops = { 673 .request = meson_mmc_request, 674 .set_ios = meson_mmc_set_ios, 675 .get_cd = meson_mmc_get_cd, 676 }; 677 678 static int meson_mmc_probe(struct platform_device *pdev) 679 { 680 struct resource *res; 681 struct meson_host *host; 682 struct mmc_host *mmc; 683 int ret, irq; 684 685 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 686 if (!mmc) 687 return -ENOMEM; 688 host = mmc_priv(mmc); 689 host->mmc = mmc; 690 host->dev = &pdev->dev; 691 dev_set_drvdata(&pdev->dev, host); 692 693 spin_lock_init(&host->lock); 694 695 /* Get regulators and the supported OCR mask */ 696 host->vqmmc_enabled = false; 697 ret = mmc_regulator_get_supply(mmc); 698 if (ret == -EPROBE_DEFER) 699 goto free_host; 700 701 ret = mmc_of_parse(mmc); 702 if (ret) { 703 if (ret != -EPROBE_DEFER) 704 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 705 goto free_host; 706 } 707 708 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 709 host->regs = devm_ioremap_resource(&pdev->dev, res); 710 if (IS_ERR(host->regs)) { 711 ret = PTR_ERR(host->regs); 712 goto free_host; 713 } 714 715 irq = platform_get_irq(pdev, 0); 716 if (!irq) { 717 dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 718 ret = -EINVAL; 719 goto free_host; 720 } 721 722 host->core_clk = devm_clk_get(&pdev->dev, "core"); 723 if (IS_ERR(host->core_clk)) { 724 ret = PTR_ERR(host->core_clk); 725 goto free_host; 726 } 727 728 ret = clk_prepare_enable(host->core_clk); 729 if (ret) 730 goto free_host; 731 732 ret = meson_mmc_clk_init(host); 733 if (ret) 734 goto err_core_clk; 735 736 /* Stop execution */ 737 writel(0, host->regs + SD_EMMC_START); 738 739 /* clear, ack, enable all interrupts */ 740 writel(0, host->regs + SD_EMMC_IRQ_EN); 741 writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); 742 writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); 743 744 /* set config to sane default */ 745 meson_mmc_cfg_init(host); 746 747 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq, 748 meson_mmc_irq_thread, IRQF_SHARED, 749 DRIVER_NAME, host); 750 if (ret) 751 goto err_div_clk; 752 753 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 754 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 755 756 /* data bounce buffer */ 757 host->bounce_buf_size = mmc->max_req_size; 758 host->bounce_buf = 759 dma_alloc_coherent(host->dev, host->bounce_buf_size, 760 &host->bounce_dma_addr, GFP_KERNEL); 761 if (host->bounce_buf == NULL) { 762 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 763 ret = -ENOMEM; 764 goto err_div_clk; 765 } 766 767 mmc->ops = &meson_mmc_ops; 768 mmc_add_host(mmc); 769 770 return 0; 771 772 err_div_clk: 773 clk_disable_unprepare(host->cfg_div_clk); 774 err_core_clk: 775 clk_disable_unprepare(host->core_clk); 776 free_host: 777 mmc_free_host(mmc); 778 return ret; 779 } 780 781 static int meson_mmc_remove(struct platform_device *pdev) 782 { 783 struct meson_host *host = dev_get_drvdata(&pdev->dev); 784 785 mmc_remove_host(host->mmc); 786 787 /* disable interrupts */ 788 writel(0, host->regs + SD_EMMC_IRQ_EN); 789 790 dma_free_coherent(host->dev, host->bounce_buf_size, 791 host->bounce_buf, host->bounce_dma_addr); 792 793 clk_disable_unprepare(host->cfg_div_clk); 794 clk_disable_unprepare(host->core_clk); 795 796 mmc_free_host(host->mmc); 797 return 0; 798 } 799 800 static const struct of_device_id meson_mmc_of_match[] = { 801 { .compatible = "amlogic,meson-gx-mmc", }, 802 { .compatible = "amlogic,meson-gxbb-mmc", }, 803 { .compatible = "amlogic,meson-gxl-mmc", }, 804 { .compatible = "amlogic,meson-gxm-mmc", }, 805 {} 806 }; 807 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 808 809 static struct platform_driver meson_mmc_driver = { 810 .probe = meson_mmc_probe, 811 .remove = meson_mmc_remove, 812 .driver = { 813 .name = DRIVER_NAME, 814 .of_match_table = of_match_ptr(meson_mmc_of_match), 815 }, 816 }; 817 818 module_platform_driver(meson_mmc_driver); 819 820 MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver"); 821 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 822 MODULE_LICENSE("GPL v2"); 823