151c5d844SKevin Hilman /* 251c5d844SKevin Hilman * Amlogic SD/eMMC driver for the GX/S905 family SoCs 351c5d844SKevin Hilman * 451c5d844SKevin Hilman * Copyright (c) 2016 BayLibre, SAS. 551c5d844SKevin Hilman * Author: Kevin Hilman <khilman@baylibre.com> 651c5d844SKevin Hilman * 751c5d844SKevin Hilman * This program is free software; you can redistribute it and/or modify 851c5d844SKevin Hilman * it under the terms of version 2 of the GNU General Public License as 951c5d844SKevin Hilman * published by the Free Software Foundation. 1051c5d844SKevin Hilman * 1151c5d844SKevin Hilman * This program is distributed in the hope that it will be useful, but 1251c5d844SKevin Hilman * WITHOUT ANY WARRANTY; without even the implied warranty of 1351c5d844SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1451c5d844SKevin Hilman * General Public License for more details. 1551c5d844SKevin Hilman * 1651c5d844SKevin Hilman * You should have received a copy of the GNU General Public License 1751c5d844SKevin Hilman * along with this program; if not, see <http://www.gnu.org/licenses/>. 1851c5d844SKevin Hilman * The full GNU General Public License is included in this distribution 1951c5d844SKevin Hilman * in the file called COPYING. 2051c5d844SKevin Hilman */ 2151c5d844SKevin Hilman #include <linux/kernel.h> 2251c5d844SKevin Hilman #include <linux/module.h> 2351c5d844SKevin Hilman #include <linux/init.h> 2451c5d844SKevin Hilman #include <linux/device.h> 2551c5d844SKevin Hilman #include <linux/of_device.h> 2651c5d844SKevin Hilman #include <linux/platform_device.h> 2751c5d844SKevin Hilman #include <linux/ioport.h> 2851c5d844SKevin Hilman #include <linux/spinlock.h> 2951c5d844SKevin Hilman #include <linux/dma-mapping.h> 3051c5d844SKevin Hilman #include <linux/mmc/host.h> 3151c5d844SKevin Hilman #include <linux/mmc/mmc.h> 3251c5d844SKevin Hilman #include <linux/mmc/sdio.h> 3351c5d844SKevin Hilman #include <linux/mmc/slot-gpio.h> 3451c5d844SKevin Hilman #include <linux/io.h> 3551c5d844SKevin Hilman #include <linux/clk.h> 3651c5d844SKevin Hilman #include <linux/clk-provider.h> 3751c5d844SKevin Hilman #include <linux/regulator/consumer.h> 38b8789ec4SUlf Hansson #include <linux/interrupt.h> 3951c5d844SKevin Hilman 4051c5d844SKevin Hilman #define DRIVER_NAME "meson-gx-mmc" 4151c5d844SKevin Hilman 4251c5d844SKevin Hilman #define SD_EMMC_CLOCK 0x0 4351c5d844SKevin Hilman #define CLK_DIV_SHIFT 0 4451c5d844SKevin Hilman #define CLK_DIV_WIDTH 6 4551c5d844SKevin Hilman #define CLK_DIV_MASK 0x3f 4651c5d844SKevin Hilman #define CLK_DIV_MAX 63 4751c5d844SKevin Hilman #define CLK_SRC_SHIFT 6 4851c5d844SKevin Hilman #define CLK_SRC_WIDTH 2 4951c5d844SKevin Hilman #define CLK_SRC_MASK 0x3 5051c5d844SKevin Hilman #define CLK_SRC_XTAL 0 /* external crystal */ 5151c5d844SKevin Hilman #define CLK_SRC_XTAL_RATE 24000000 5251c5d844SKevin Hilman #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ 5351c5d844SKevin Hilman #define CLK_SRC_PLL_RATE 1000000000 5451c5d844SKevin Hilman #define CLK_PHASE_SHIFT 8 5551c5d844SKevin Hilman #define CLK_PHASE_MASK 0x3 5651c5d844SKevin Hilman #define CLK_PHASE_0 0 5751c5d844SKevin Hilman #define CLK_PHASE_90 1 5851c5d844SKevin Hilman #define CLK_PHASE_180 2 5951c5d844SKevin Hilman #define CLK_PHASE_270 3 6051c5d844SKevin Hilman #define CLK_ALWAYS_ON BIT(24) 6151c5d844SKevin Hilman 6251c5d844SKevin Hilman #define SD_EMMC_DElAY 0x4 6351c5d844SKevin Hilman #define SD_EMMC_ADJUST 0x8 6451c5d844SKevin Hilman #define SD_EMMC_CALOUT 0x10 6551c5d844SKevin Hilman #define SD_EMMC_START 0x40 6651c5d844SKevin Hilman #define START_DESC_INIT BIT(0) 6751c5d844SKevin Hilman #define START_DESC_BUSY BIT(1) 6851c5d844SKevin Hilman #define START_DESC_ADDR_SHIFT 2 6951c5d844SKevin Hilman #define START_DESC_ADDR_MASK (~0x3) 7051c5d844SKevin Hilman 7151c5d844SKevin Hilman #define SD_EMMC_CFG 0x44 7251c5d844SKevin Hilman #define CFG_BUS_WIDTH_SHIFT 0 7351c5d844SKevin Hilman #define CFG_BUS_WIDTH_MASK 0x3 7451c5d844SKevin Hilman #define CFG_BUS_WIDTH_1 0x0 7551c5d844SKevin Hilman #define CFG_BUS_WIDTH_4 0x1 7651c5d844SKevin Hilman #define CFG_BUS_WIDTH_8 0x2 7751c5d844SKevin Hilman #define CFG_DDR BIT(2) 7851c5d844SKevin Hilman #define CFG_BLK_LEN_SHIFT 4 7951c5d844SKevin Hilman #define CFG_BLK_LEN_MASK 0xf 8051c5d844SKevin Hilman #define CFG_RESP_TIMEOUT_SHIFT 8 8151c5d844SKevin Hilman #define CFG_RESP_TIMEOUT_MASK 0xf 8251c5d844SKevin Hilman #define CFG_RC_CC_SHIFT 12 8351c5d844SKevin Hilman #define CFG_RC_CC_MASK 0xf 8451c5d844SKevin Hilman #define CFG_STOP_CLOCK BIT(22) 8551c5d844SKevin Hilman #define CFG_CLK_ALWAYS_ON BIT(18) 86e21e6fddSHeiner Kallweit #define CFG_CHK_DS BIT(20) 8751c5d844SKevin Hilman #define CFG_AUTO_CLK BIT(23) 8851c5d844SKevin Hilman 8951c5d844SKevin Hilman #define SD_EMMC_STATUS 0x48 9051c5d844SKevin Hilman #define STATUS_BUSY BIT(31) 9151c5d844SKevin Hilman 9251c5d844SKevin Hilman #define SD_EMMC_IRQ_EN 0x4c 9351c5d844SKevin Hilman #define IRQ_EN_MASK 0x3fff 9451c5d844SKevin Hilman #define IRQ_RXD_ERR_SHIFT 0 9551c5d844SKevin Hilman #define IRQ_RXD_ERR_MASK 0xff 9651c5d844SKevin Hilman #define IRQ_TXD_ERR BIT(8) 9751c5d844SKevin Hilman #define IRQ_DESC_ERR BIT(9) 9851c5d844SKevin Hilman #define IRQ_RESP_ERR BIT(10) 9951c5d844SKevin Hilman #define IRQ_RESP_TIMEOUT BIT(11) 10051c5d844SKevin Hilman #define IRQ_DESC_TIMEOUT BIT(12) 10151c5d844SKevin Hilman #define IRQ_END_OF_CHAIN BIT(13) 10251c5d844SKevin Hilman #define IRQ_RESP_STATUS BIT(14) 10351c5d844SKevin Hilman #define IRQ_SDIO BIT(15) 10451c5d844SKevin Hilman 10551c5d844SKevin Hilman #define SD_EMMC_CMD_CFG 0x50 10651c5d844SKevin Hilman #define SD_EMMC_CMD_ARG 0x54 10751c5d844SKevin Hilman #define SD_EMMC_CMD_DAT 0x58 10851c5d844SKevin Hilman #define SD_EMMC_CMD_RSP 0x5c 10951c5d844SKevin Hilman #define SD_EMMC_CMD_RSP1 0x60 11051c5d844SKevin Hilman #define SD_EMMC_CMD_RSP2 0x64 11151c5d844SKevin Hilman #define SD_EMMC_CMD_RSP3 0x68 11251c5d844SKevin Hilman 11351c5d844SKevin Hilman #define SD_EMMC_RXD 0x94 11451c5d844SKevin Hilman #define SD_EMMC_TXD 0x94 11551c5d844SKevin Hilman #define SD_EMMC_LAST_REG SD_EMMC_TXD 11651c5d844SKevin Hilman 11751c5d844SKevin Hilman #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 11851c5d844SKevin Hilman #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 11951c5d844SKevin Hilman #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 12051c5d844SKevin Hilman #define MUX_CLK_NUM_PARENTS 2 12151c5d844SKevin Hilman 12251c5d844SKevin Hilman struct meson_host { 12351c5d844SKevin Hilman struct device *dev; 12451c5d844SKevin Hilman struct mmc_host *mmc; 12551c5d844SKevin Hilman struct mmc_request *mrq; 12651c5d844SKevin Hilman struct mmc_command *cmd; 12751c5d844SKevin Hilman 12851c5d844SKevin Hilman spinlock_t lock; 12951c5d844SKevin Hilman void __iomem *regs; 13051c5d844SKevin Hilman struct clk *core_clk; 13151c5d844SKevin Hilman struct clk_mux mux; 13251c5d844SKevin Hilman struct clk *mux_clk; 1335da86887SHeiner Kallweit unsigned long current_clock; 13451c5d844SKevin Hilman 13551c5d844SKevin Hilman struct clk_divider cfg_div; 13651c5d844SKevin Hilman struct clk *cfg_div_clk; 13751c5d844SKevin Hilman 13851c5d844SKevin Hilman unsigned int bounce_buf_size; 13951c5d844SKevin Hilman void *bounce_buf; 14051c5d844SKevin Hilman dma_addr_t bounce_dma_addr; 14151c5d844SKevin Hilman 14251c5d844SKevin Hilman bool vqmmc_enabled; 14351c5d844SKevin Hilman }; 14451c5d844SKevin Hilman 14551c5d844SKevin Hilman struct sd_emmc_desc { 14651c5d844SKevin Hilman u32 cmd_cfg; 14751c5d844SKevin Hilman u32 cmd_arg; 14851c5d844SKevin Hilman u32 cmd_data; 14951c5d844SKevin Hilman u32 cmd_resp; 15051c5d844SKevin Hilman }; 15151c5d844SKevin Hilman #define CMD_CFG_LENGTH_SHIFT 0 15251c5d844SKevin Hilman #define CMD_CFG_LENGTH_MASK 0x1ff 15351c5d844SKevin Hilman #define CMD_CFG_BLOCK_MODE BIT(9) 15451c5d844SKevin Hilman #define CMD_CFG_R1B BIT(10) 15551c5d844SKevin Hilman #define CMD_CFG_END_OF_CHAIN BIT(11) 15651c5d844SKevin Hilman #define CMD_CFG_TIMEOUT_SHIFT 12 15751c5d844SKevin Hilman #define CMD_CFG_TIMEOUT_MASK 0xf 15851c5d844SKevin Hilman #define CMD_CFG_NO_RESP BIT(16) 15951c5d844SKevin Hilman #define CMD_CFG_NO_CMD BIT(17) 16051c5d844SKevin Hilman #define CMD_CFG_DATA_IO BIT(18) 16151c5d844SKevin Hilman #define CMD_CFG_DATA_WR BIT(19) 16251c5d844SKevin Hilman #define CMD_CFG_RESP_NOCRC BIT(20) 16351c5d844SKevin Hilman #define CMD_CFG_RESP_128 BIT(21) 16451c5d844SKevin Hilman #define CMD_CFG_RESP_NUM BIT(22) 16551c5d844SKevin Hilman #define CMD_CFG_DATA_NUM BIT(23) 16651c5d844SKevin Hilman #define CMD_CFG_CMD_INDEX_SHIFT 24 16751c5d844SKevin Hilman #define CMD_CFG_CMD_INDEX_MASK 0x3f 16851c5d844SKevin Hilman #define CMD_CFG_ERROR BIT(30) 16951c5d844SKevin Hilman #define CMD_CFG_OWNER BIT(31) 17051c5d844SKevin Hilman 17151c5d844SKevin Hilman #define CMD_DATA_MASK (~0x3) 17251c5d844SKevin Hilman #define CMD_DATA_BIG_ENDIAN BIT(1) 17351c5d844SKevin Hilman #define CMD_DATA_SRAM BIT(0) 17451c5d844SKevin Hilman #define CMD_RESP_MASK (~0x1) 17551c5d844SKevin Hilman #define CMD_RESP_SRAM BIT(0) 17651c5d844SKevin Hilman 17751c5d844SKevin Hilman static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) 17851c5d844SKevin Hilman { 17951c5d844SKevin Hilman struct mmc_host *mmc = host->mmc; 1805da86887SHeiner Kallweit int ret; 18151c5d844SKevin Hilman u32 cfg; 18251c5d844SKevin Hilman 18351c5d844SKevin Hilman if (clk_rate) { 18451c5d844SKevin Hilman if (WARN_ON(clk_rate > mmc->f_max)) 18551c5d844SKevin Hilman clk_rate = mmc->f_max; 18651c5d844SKevin Hilman else if (WARN_ON(clk_rate < mmc->f_min)) 18751c5d844SKevin Hilman clk_rate = mmc->f_min; 18851c5d844SKevin Hilman } 18951c5d844SKevin Hilman 1905da86887SHeiner Kallweit if (clk_rate == host->current_clock) 19151c5d844SKevin Hilman return 0; 19251c5d844SKevin Hilman 19351c5d844SKevin Hilman /* stop clock */ 19451c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 19551c5d844SKevin Hilman if (!(cfg & CFG_STOP_CLOCK)) { 19651c5d844SKevin Hilman cfg |= CFG_STOP_CLOCK; 19751c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 19851c5d844SKevin Hilman } 19951c5d844SKevin Hilman 20051c5d844SKevin Hilman dev_dbg(host->dev, "change clock rate %u -> %lu\n", 20151c5d844SKevin Hilman mmc->actual_clock, clk_rate); 20251c5d844SKevin Hilman 2035da86887SHeiner Kallweit if (!clk_rate) { 20451c5d844SKevin Hilman mmc->actual_clock = 0; 2055da86887SHeiner Kallweit host->current_clock = 0; 2065da86887SHeiner Kallweit /* return with clock being stopped */ 20751c5d844SKevin Hilman return 0; 20851c5d844SKevin Hilman } 20951c5d844SKevin Hilman 21051c5d844SKevin Hilman ret = clk_set_rate(host->cfg_div_clk, clk_rate); 2115da86887SHeiner Kallweit if (ret) { 2125da86887SHeiner Kallweit dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 21351c5d844SKevin Hilman clk_rate, ret); 2145da86887SHeiner Kallweit return ret; 2155da86887SHeiner Kallweit } 21651c5d844SKevin Hilman 2175da86887SHeiner Kallweit mmc->actual_clock = clk_get_rate(host->cfg_div_clk); 2185da86887SHeiner Kallweit host->current_clock = clk_rate; 2195da86887SHeiner Kallweit 2205da86887SHeiner Kallweit if (clk_rate != mmc->actual_clock) 2215da86887SHeiner Kallweit dev_dbg(host->dev, 2225da86887SHeiner Kallweit "divider requested rate %lu != actual rate %u\n", 2235da86887SHeiner Kallweit clk_rate, mmc->actual_clock); 2245da86887SHeiner Kallweit 2255da86887SHeiner Kallweit /* (re)start clock */ 22651c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 22751c5d844SKevin Hilman cfg &= ~CFG_STOP_CLOCK; 22851c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 22951c5d844SKevin Hilman 2305da86887SHeiner Kallweit return 0; 23151c5d844SKevin Hilman } 23251c5d844SKevin Hilman 23351c5d844SKevin Hilman /* 23451c5d844SKevin Hilman * The SD/eMMC IP block has an internal mux and divider used for 23551c5d844SKevin Hilman * generating the MMC clock. Use the clock framework to create and 23651c5d844SKevin Hilman * manage these clocks. 23751c5d844SKevin Hilman */ 23851c5d844SKevin Hilman static int meson_mmc_clk_init(struct meson_host *host) 23951c5d844SKevin Hilman { 24051c5d844SKevin Hilman struct clk_init_data init; 24151c5d844SKevin Hilman char clk_name[32]; 24251c5d844SKevin Hilman int i, ret = 0; 24351c5d844SKevin Hilman const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 24451c5d844SKevin Hilman const char *clk_div_parents[1]; 24551c5d844SKevin Hilman u32 clk_reg, cfg; 24651c5d844SKevin Hilman 24751c5d844SKevin Hilman /* get the mux parents */ 24851c5d844SKevin Hilman for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 249e9883ef2SHeiner Kallweit struct clk *clk; 25051c5d844SKevin Hilman char name[16]; 25151c5d844SKevin Hilman 25251c5d844SKevin Hilman snprintf(name, sizeof(name), "clkin%d", i); 253e9883ef2SHeiner Kallweit clk = devm_clk_get(host->dev, name); 254e9883ef2SHeiner Kallweit if (IS_ERR(clk)) { 255e9883ef2SHeiner Kallweit if (clk != ERR_PTR(-EPROBE_DEFER)) 25651c5d844SKevin Hilman dev_err(host->dev, "Missing clock %s\n", name); 257e9883ef2SHeiner Kallweit return PTR_ERR(clk); 25851c5d844SKevin Hilman } 25951c5d844SKevin Hilman 260e9883ef2SHeiner Kallweit mux_parent_names[i] = __clk_get_name(clk); 26151c5d844SKevin Hilman } 26251c5d844SKevin Hilman 26351c5d844SKevin Hilman /* create the mux */ 26451c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 26551c5d844SKevin Hilman init.name = clk_name; 26651c5d844SKevin Hilman init.ops = &clk_mux_ops; 26751c5d844SKevin Hilman init.flags = 0; 26851c5d844SKevin Hilman init.parent_names = mux_parent_names; 2697558c113SHeiner Kallweit init.num_parents = MUX_CLK_NUM_PARENTS; 27051c5d844SKevin Hilman 27151c5d844SKevin Hilman host->mux.reg = host->regs + SD_EMMC_CLOCK; 27251c5d844SKevin Hilman host->mux.shift = CLK_SRC_SHIFT; 27351c5d844SKevin Hilman host->mux.mask = CLK_SRC_MASK; 27451c5d844SKevin Hilman host->mux.flags = 0; 27551c5d844SKevin Hilman host->mux.table = NULL; 27651c5d844SKevin Hilman host->mux.hw.init = &init; 27751c5d844SKevin Hilman 27851c5d844SKevin Hilman host->mux_clk = devm_clk_register(host->dev, &host->mux.hw); 27951c5d844SKevin Hilman if (WARN_ON(IS_ERR(host->mux_clk))) 28051c5d844SKevin Hilman return PTR_ERR(host->mux_clk); 28151c5d844SKevin Hilman 28251c5d844SKevin Hilman /* create the divider */ 28351c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 28451c5d844SKevin Hilman init.name = devm_kstrdup(host->dev, clk_name, GFP_KERNEL); 28551c5d844SKevin Hilman init.ops = &clk_divider_ops; 28651c5d844SKevin Hilman init.flags = CLK_SET_RATE_PARENT; 28751c5d844SKevin Hilman clk_div_parents[0] = __clk_get_name(host->mux_clk); 28851c5d844SKevin Hilman init.parent_names = clk_div_parents; 28951c5d844SKevin Hilman init.num_parents = ARRAY_SIZE(clk_div_parents); 29051c5d844SKevin Hilman 29151c5d844SKevin Hilman host->cfg_div.reg = host->regs + SD_EMMC_CLOCK; 29251c5d844SKevin Hilman host->cfg_div.shift = CLK_DIV_SHIFT; 29351c5d844SKevin Hilman host->cfg_div.width = CLK_DIV_WIDTH; 29451c5d844SKevin Hilman host->cfg_div.hw.init = &init; 29551c5d844SKevin Hilman host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | 29651c5d844SKevin Hilman CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO; 29751c5d844SKevin Hilman 29851c5d844SKevin Hilman host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); 29951c5d844SKevin Hilman if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) 30051c5d844SKevin Hilman return PTR_ERR(host->cfg_div_clk); 30151c5d844SKevin Hilman 30251c5d844SKevin Hilman /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 30351c5d844SKevin Hilman clk_reg = 0; 30451c5d844SKevin Hilman clk_reg |= CLK_PHASE_180 << CLK_PHASE_SHIFT; 30551c5d844SKevin Hilman clk_reg |= CLK_SRC_XTAL << CLK_SRC_SHIFT; 30651c5d844SKevin Hilman clk_reg |= CLK_DIV_MAX << CLK_DIV_SHIFT; 30751c5d844SKevin Hilman clk_reg &= ~CLK_ALWAYS_ON; 30851c5d844SKevin Hilman writel(clk_reg, host->regs + SD_EMMC_CLOCK); 30951c5d844SKevin Hilman 31051c5d844SKevin Hilman /* Ensure clock starts in "auto" mode, not "always on" */ 31151c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 31251c5d844SKevin Hilman cfg &= ~CFG_CLK_ALWAYS_ON; 31351c5d844SKevin Hilman cfg |= CFG_AUTO_CLK; 31451c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 31551c5d844SKevin Hilman 31651c5d844SKevin Hilman ret = clk_prepare_enable(host->cfg_div_clk); 317a4c38c8dSUlf Hansson if (ret) 318a4c38c8dSUlf Hansson return ret; 31951c5d844SKevin Hilman 320a4c38c8dSUlf Hansson /* Get the nearest minimum clock to 400KHz */ 321a4c38c8dSUlf Hansson host->mmc->f_min = clk_round_rate(host->cfg_div_clk, 400000); 322a4c38c8dSUlf Hansson 323a4c38c8dSUlf Hansson ret = meson_mmc_clk_set(host, host->mmc->f_min); 32451c5d844SKevin Hilman if (!ret) 32551c5d844SKevin Hilman clk_disable_unprepare(host->cfg_div_clk); 32651c5d844SKevin Hilman 32751c5d844SKevin Hilman return ret; 32851c5d844SKevin Hilman } 32951c5d844SKevin Hilman 33051c5d844SKevin Hilman static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 33151c5d844SKevin Hilman { 33251c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 33351c5d844SKevin Hilman u32 bus_width; 33451c5d844SKevin Hilman u32 val, orig; 33551c5d844SKevin Hilman 33651c5d844SKevin Hilman /* 33751c5d844SKevin Hilman * GPIO regulator, only controls switching between 1v8 and 33851c5d844SKevin Hilman * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 33951c5d844SKevin Hilman */ 34051c5d844SKevin Hilman switch (ios->power_mode) { 34151c5d844SKevin Hilman case MMC_POWER_OFF: 34251c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vmmc)) 34351c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 34451c5d844SKevin Hilman 34551c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 34651c5d844SKevin Hilman regulator_disable(mmc->supply.vqmmc); 34751c5d844SKevin Hilman host->vqmmc_enabled = false; 34851c5d844SKevin Hilman } 34951c5d844SKevin Hilman 35051c5d844SKevin Hilman break; 35151c5d844SKevin Hilman 35251c5d844SKevin Hilman case MMC_POWER_UP: 35351c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vmmc)) 35451c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 35551c5d844SKevin Hilman break; 35651c5d844SKevin Hilman 35751c5d844SKevin Hilman case MMC_POWER_ON: 35851c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 35951c5d844SKevin Hilman int ret = regulator_enable(mmc->supply.vqmmc); 36051c5d844SKevin Hilman 36151c5d844SKevin Hilman if (ret < 0) 36251c5d844SKevin Hilman dev_err(mmc_dev(mmc), 36351c5d844SKevin Hilman "failed to enable vqmmc regulator\n"); 36451c5d844SKevin Hilman else 36551c5d844SKevin Hilman host->vqmmc_enabled = true; 36651c5d844SKevin Hilman } 36751c5d844SKevin Hilman 36851c5d844SKevin Hilman break; 36951c5d844SKevin Hilman } 37051c5d844SKevin Hilman 37151c5d844SKevin Hilman 37251c5d844SKevin Hilman meson_mmc_clk_set(host, ios->clock); 37351c5d844SKevin Hilman 37451c5d844SKevin Hilman /* Bus width */ 37551c5d844SKevin Hilman switch (ios->bus_width) { 37651c5d844SKevin Hilman case MMC_BUS_WIDTH_1: 37751c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_1; 37851c5d844SKevin Hilman break; 37951c5d844SKevin Hilman case MMC_BUS_WIDTH_4: 38051c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4; 38151c5d844SKevin Hilman break; 38251c5d844SKevin Hilman case MMC_BUS_WIDTH_8: 38351c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_8; 38451c5d844SKevin Hilman break; 38551c5d844SKevin Hilman default: 38651c5d844SKevin Hilman dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 38751c5d844SKevin Hilman ios->bus_width); 38851c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4; 38951c5d844SKevin Hilman } 39051c5d844SKevin Hilman 39151c5d844SKevin Hilman val = readl(host->regs + SD_EMMC_CFG); 39251c5d844SKevin Hilman orig = val; 39351c5d844SKevin Hilman 39451c5d844SKevin Hilman val &= ~(CFG_BUS_WIDTH_MASK << CFG_BUS_WIDTH_SHIFT); 39551c5d844SKevin Hilman val |= bus_width << CFG_BUS_WIDTH_SHIFT; 39651c5d844SKevin Hilman 39751c5d844SKevin Hilman val &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 39851c5d844SKevin Hilman val |= ilog2(SD_EMMC_CFG_BLK_SIZE) << CFG_BLK_LEN_SHIFT; 39951c5d844SKevin Hilman 40051c5d844SKevin Hilman val &= ~(CFG_RESP_TIMEOUT_MASK << CFG_RESP_TIMEOUT_SHIFT); 40151c5d844SKevin Hilman val |= ilog2(SD_EMMC_CFG_RESP_TIMEOUT) << CFG_RESP_TIMEOUT_SHIFT; 40251c5d844SKevin Hilman 40351c5d844SKevin Hilman val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT); 40451c5d844SKevin Hilman val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT; 40551c5d844SKevin Hilman 406e21e6fddSHeiner Kallweit val &= ~CFG_DDR; 407e21e6fddSHeiner Kallweit if (ios->timing == MMC_TIMING_UHS_DDR50 || 408e21e6fddSHeiner Kallweit ios->timing == MMC_TIMING_MMC_DDR52 || 409e21e6fddSHeiner Kallweit ios->timing == MMC_TIMING_MMC_HS400) 410e21e6fddSHeiner Kallweit val |= CFG_DDR; 411e21e6fddSHeiner Kallweit 412e21e6fddSHeiner Kallweit val &= ~CFG_CHK_DS; 413e21e6fddSHeiner Kallweit if (ios->timing == MMC_TIMING_MMC_HS400) 414e21e6fddSHeiner Kallweit val |= CFG_CHK_DS; 415e21e6fddSHeiner Kallweit 41651c5d844SKevin Hilman writel(val, host->regs + SD_EMMC_CFG); 41751c5d844SKevin Hilman 41851c5d844SKevin Hilman if (val != orig) 41951c5d844SKevin Hilman dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n", 42051c5d844SKevin Hilman __func__, orig, val); 42151c5d844SKevin Hilman } 42251c5d844SKevin Hilman 4233d6c991bSHeiner Kallweit static void meson_mmc_request_done(struct mmc_host *mmc, 4243d6c991bSHeiner Kallweit struct mmc_request *mrq) 42551c5d844SKevin Hilman { 42651c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 42751c5d844SKevin Hilman 42851c5d844SKevin Hilman WARN_ON(host->mrq != mrq); 42951c5d844SKevin Hilman 43051c5d844SKevin Hilman host->mrq = NULL; 43151c5d844SKevin Hilman host->cmd = NULL; 43251c5d844SKevin Hilman mmc_request_done(host->mmc, mrq); 43351c5d844SKevin Hilman } 43451c5d844SKevin Hilman 43551c5d844SKevin Hilman static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 43651c5d844SKevin Hilman { 43751c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 43851c5d844SKevin Hilman struct sd_emmc_desc *desc, desc_tmp; 43951c5d844SKevin Hilman u32 cfg; 44051c5d844SKevin Hilman u8 blk_len, cmd_cfg_timeout; 44151c5d844SKevin Hilman unsigned int xfer_bytes = 0; 44251c5d844SKevin Hilman 44351c5d844SKevin Hilman /* Setup descriptors */ 44451c5d844SKevin Hilman dma_rmb(); 44551c5d844SKevin Hilman desc = &desc_tmp; 44651c5d844SKevin Hilman memset(desc, 0, sizeof(struct sd_emmc_desc)); 44751c5d844SKevin Hilman 44851c5d844SKevin Hilman desc->cmd_cfg |= (cmd->opcode & CMD_CFG_CMD_INDEX_MASK) << 44951c5d844SKevin Hilman CMD_CFG_CMD_INDEX_SHIFT; 45051c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 45151c5d844SKevin Hilman desc->cmd_arg = cmd->arg; 45251c5d844SKevin Hilman 45351c5d844SKevin Hilman /* Response */ 45451c5d844SKevin Hilman if (cmd->flags & MMC_RSP_PRESENT) { 45551c5d844SKevin Hilman desc->cmd_cfg &= ~CMD_CFG_NO_RESP; 45651c5d844SKevin Hilman if (cmd->flags & MMC_RSP_136) 45751c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_RESP_128; 45851c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_RESP_NUM; 45951c5d844SKevin Hilman desc->cmd_resp = 0; 46051c5d844SKevin Hilman 46151c5d844SKevin Hilman if (!(cmd->flags & MMC_RSP_CRC)) 46251c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_RESP_NOCRC; 46351c5d844SKevin Hilman 46451c5d844SKevin Hilman if (cmd->flags & MMC_RSP_BUSY) 46551c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_R1B; 46651c5d844SKevin Hilman } else { 46751c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_NO_RESP; 46851c5d844SKevin Hilman } 46951c5d844SKevin Hilman 47051c5d844SKevin Hilman /* data? */ 47151c5d844SKevin Hilman if (cmd->data) { 47251c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_DATA_IO; 47351c5d844SKevin Hilman if (cmd->data->blocks > 1) { 47451c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_BLOCK_MODE; 47551c5d844SKevin Hilman desc->cmd_cfg |= 47651c5d844SKevin Hilman (cmd->data->blocks & CMD_CFG_LENGTH_MASK) << 47751c5d844SKevin Hilman CMD_CFG_LENGTH_SHIFT; 47851c5d844SKevin Hilman 47951c5d844SKevin Hilman /* check if block-size matches, if not update */ 48051c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 48151c5d844SKevin Hilman blk_len = cfg & (CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 48251c5d844SKevin Hilman blk_len >>= CFG_BLK_LEN_SHIFT; 48351c5d844SKevin Hilman if (blk_len != ilog2(cmd->data->blksz)) { 484dc012058SKevin Hilman dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", 48551c5d844SKevin Hilman __func__, blk_len, 48651c5d844SKevin Hilman ilog2(cmd->data->blksz)); 48751c5d844SKevin Hilman blk_len = ilog2(cmd->data->blksz); 48851c5d844SKevin Hilman cfg &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT); 48951c5d844SKevin Hilman cfg |= blk_len << CFG_BLK_LEN_SHIFT; 49051c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 49151c5d844SKevin Hilman } 49251c5d844SKevin Hilman } else { 49351c5d844SKevin Hilman desc->cmd_cfg &= ~CMD_CFG_BLOCK_MODE; 49451c5d844SKevin Hilman desc->cmd_cfg |= 49551c5d844SKevin Hilman (cmd->data->blksz & CMD_CFG_LENGTH_MASK) << 49651c5d844SKevin Hilman CMD_CFG_LENGTH_SHIFT; 49751c5d844SKevin Hilman } 49851c5d844SKevin Hilman 49951c5d844SKevin Hilman cmd->data->bytes_xfered = 0; 50051c5d844SKevin Hilman xfer_bytes = cmd->data->blksz * cmd->data->blocks; 50151c5d844SKevin Hilman if (cmd->data->flags & MMC_DATA_WRITE) { 50251c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_DATA_WR; 50351c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size); 50451c5d844SKevin Hilman sg_copy_to_buffer(cmd->data->sg, cmd->data->sg_len, 50551c5d844SKevin Hilman host->bounce_buf, xfer_bytes); 50651c5d844SKevin Hilman cmd->data->bytes_xfered = xfer_bytes; 50751c5d844SKevin Hilman dma_wmb(); 50851c5d844SKevin Hilman } else { 50951c5d844SKevin Hilman desc->cmd_cfg &= ~CMD_CFG_DATA_WR; 51051c5d844SKevin Hilman } 51151c5d844SKevin Hilman 51251c5d844SKevin Hilman desc->cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 51351c5d844SKevin Hilman 51451c5d844SKevin Hilman cmd_cfg_timeout = 12; 51551c5d844SKevin Hilman } else { 51651c5d844SKevin Hilman desc->cmd_cfg &= ~CMD_CFG_DATA_IO; 51751c5d844SKevin Hilman cmd_cfg_timeout = 10; 51851c5d844SKevin Hilman } 51951c5d844SKevin Hilman desc->cmd_cfg |= (cmd_cfg_timeout & CMD_CFG_TIMEOUT_MASK) << 52051c5d844SKevin Hilman CMD_CFG_TIMEOUT_SHIFT; 52151c5d844SKevin Hilman 52251c5d844SKevin Hilman host->cmd = cmd; 52351c5d844SKevin Hilman 52451c5d844SKevin Hilman /* Last descriptor */ 52551c5d844SKevin Hilman desc->cmd_cfg |= CMD_CFG_END_OF_CHAIN; 52651c5d844SKevin Hilman writel(desc->cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 52751c5d844SKevin Hilman writel(desc->cmd_data, host->regs + SD_EMMC_CMD_DAT); 52851c5d844SKevin Hilman writel(desc->cmd_resp, host->regs + SD_EMMC_CMD_RSP); 52951c5d844SKevin Hilman wmb(); /* ensure descriptor is written before kicked */ 53051c5d844SKevin Hilman writel(desc->cmd_arg, host->regs + SD_EMMC_CMD_ARG); 53151c5d844SKevin Hilman } 53251c5d844SKevin Hilman 53351c5d844SKevin Hilman static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 53451c5d844SKevin Hilman { 53551c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 53651c5d844SKevin Hilman 53751c5d844SKevin Hilman WARN_ON(host->mrq != NULL); 53851c5d844SKevin Hilman 53951c5d844SKevin Hilman /* Stop execution */ 54051c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START); 54151c5d844SKevin Hilman 54251c5d844SKevin Hilman host->mrq = mrq; 54351c5d844SKevin Hilman 54451c5d844SKevin Hilman if (mrq->sbc) 54551c5d844SKevin Hilman meson_mmc_start_cmd(mmc, mrq->sbc); 54651c5d844SKevin Hilman else 54751c5d844SKevin Hilman meson_mmc_start_cmd(mmc, mrq->cmd); 54851c5d844SKevin Hilman } 54951c5d844SKevin Hilman 5503d6c991bSHeiner Kallweit static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 55151c5d844SKevin Hilman { 55251c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 55351c5d844SKevin Hilman 55451c5d844SKevin Hilman if (cmd->flags & MMC_RSP_136) { 55551c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 55651c5d844SKevin Hilman cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 55751c5d844SKevin Hilman cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 55851c5d844SKevin Hilman cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 55951c5d844SKevin Hilman } else if (cmd->flags & MMC_RSP_PRESENT) { 56051c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 56151c5d844SKevin Hilman } 56251c5d844SKevin Hilman } 56351c5d844SKevin Hilman 56451c5d844SKevin Hilman static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 56551c5d844SKevin Hilman { 56651c5d844SKevin Hilman struct meson_host *host = dev_id; 56751c5d844SKevin Hilman struct mmc_request *mrq; 56819a91dd4SHeinrich Schuchardt struct mmc_command *cmd; 56951c5d844SKevin Hilman u32 irq_en, status, raw_status; 57051c5d844SKevin Hilman irqreturn_t ret = IRQ_HANDLED; 57151c5d844SKevin Hilman 57251c5d844SKevin Hilman if (WARN_ON(!host)) 57351c5d844SKevin Hilman return IRQ_NONE; 57451c5d844SKevin Hilman 57519a91dd4SHeinrich Schuchardt cmd = host->cmd; 57619a91dd4SHeinrich Schuchardt 57751c5d844SKevin Hilman mrq = host->mrq; 57851c5d844SKevin Hilman 57951c5d844SKevin Hilman if (WARN_ON(!mrq)) 58051c5d844SKevin Hilman return IRQ_NONE; 58151c5d844SKevin Hilman 58251c5d844SKevin Hilman if (WARN_ON(!cmd)) 58351c5d844SKevin Hilman return IRQ_NONE; 58451c5d844SKevin Hilman 58551c5d844SKevin Hilman spin_lock(&host->lock); 58651c5d844SKevin Hilman irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 58751c5d844SKevin Hilman raw_status = readl(host->regs + SD_EMMC_STATUS); 58851c5d844SKevin Hilman status = raw_status & irq_en; 58951c5d844SKevin Hilman 59051c5d844SKevin Hilman if (!status) { 59151c5d844SKevin Hilman dev_warn(host->dev, "Spurious IRQ! status=0x%08x, irq_en=0x%08x\n", 59251c5d844SKevin Hilman raw_status, irq_en); 59351c5d844SKevin Hilman ret = IRQ_NONE; 59451c5d844SKevin Hilman goto out; 59551c5d844SKevin Hilman } 59651c5d844SKevin Hilman 59751c5d844SKevin Hilman cmd->error = 0; 59851c5d844SKevin Hilman if (status & IRQ_RXD_ERR_MASK) { 59951c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: RXD error\n"); 60051c5d844SKevin Hilman cmd->error = -EILSEQ; 60151c5d844SKevin Hilman } 60251c5d844SKevin Hilman if (status & IRQ_TXD_ERR) { 60351c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: TXD error\n"); 60451c5d844SKevin Hilman cmd->error = -EILSEQ; 60551c5d844SKevin Hilman } 60651c5d844SKevin Hilman if (status & IRQ_DESC_ERR) 60751c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Descriptor error\n"); 60851c5d844SKevin Hilman if (status & IRQ_RESP_ERR) { 60951c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Response error\n"); 61051c5d844SKevin Hilman cmd->error = -EILSEQ; 61151c5d844SKevin Hilman } 61251c5d844SKevin Hilman if (status & IRQ_RESP_TIMEOUT) { 61351c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Response timeout\n"); 61451c5d844SKevin Hilman cmd->error = -ETIMEDOUT; 61551c5d844SKevin Hilman } 61651c5d844SKevin Hilman if (status & IRQ_DESC_TIMEOUT) { 61751c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Descriptor timeout\n"); 61851c5d844SKevin Hilman cmd->error = -ETIMEDOUT; 61951c5d844SKevin Hilman } 62051c5d844SKevin Hilman if (status & IRQ_SDIO) 62151c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: SDIO.\n"); 62251c5d844SKevin Hilman 62351c5d844SKevin Hilman if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) 62451c5d844SKevin Hilman ret = IRQ_WAKE_THREAD; 62551c5d844SKevin Hilman else { 62651c5d844SKevin Hilman dev_warn(host->dev, "Unknown IRQ! status=0x%04x: MMC CMD%u arg=0x%08x flags=0x%08x stop=%d\n", 62751c5d844SKevin Hilman status, cmd->opcode, cmd->arg, 62851c5d844SKevin Hilman cmd->flags, mrq->stop ? 1 : 0); 62951c5d844SKevin Hilman if (cmd->data) { 63051c5d844SKevin Hilman struct mmc_data *data = cmd->data; 63151c5d844SKevin Hilman 63251c5d844SKevin Hilman dev_warn(host->dev, "\tblksz %u blocks %u flags 0x%08x (%s%s)", 63351c5d844SKevin Hilman data->blksz, data->blocks, data->flags, 63451c5d844SKevin Hilman data->flags & MMC_DATA_WRITE ? "write" : "", 63551c5d844SKevin Hilman data->flags & MMC_DATA_READ ? "read" : ""); 63651c5d844SKevin Hilman } 63751c5d844SKevin Hilman } 63851c5d844SKevin Hilman 63951c5d844SKevin Hilman out: 64051c5d844SKevin Hilman /* ack all (enabled) interrupts */ 64151c5d844SKevin Hilman writel(status, host->regs + SD_EMMC_STATUS); 64251c5d844SKevin Hilman 64351c5d844SKevin Hilman if (ret == IRQ_HANDLED) { 64451c5d844SKevin Hilman meson_mmc_read_resp(host->mmc, cmd); 64551c5d844SKevin Hilman meson_mmc_request_done(host->mmc, cmd->mrq); 64651c5d844SKevin Hilman } 64751c5d844SKevin Hilman 64851c5d844SKevin Hilman spin_unlock(&host->lock); 64951c5d844SKevin Hilman return ret; 65051c5d844SKevin Hilman } 65151c5d844SKevin Hilman 65251c5d844SKevin Hilman static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 65351c5d844SKevin Hilman { 65451c5d844SKevin Hilman struct meson_host *host = dev_id; 65551c5d844SKevin Hilman struct mmc_request *mrq = host->mrq; 65651c5d844SKevin Hilman struct mmc_command *cmd = host->cmd; 65751c5d844SKevin Hilman struct mmc_data *data; 65851c5d844SKevin Hilman unsigned int xfer_bytes; 65951c5d844SKevin Hilman 66051c5d844SKevin Hilman if (WARN_ON(!mrq)) 66119a91dd4SHeinrich Schuchardt return IRQ_NONE; 66251c5d844SKevin Hilman 66351c5d844SKevin Hilman if (WARN_ON(!cmd)) 66419a91dd4SHeinrich Schuchardt return IRQ_NONE; 66551c5d844SKevin Hilman 66651c5d844SKevin Hilman data = cmd->data; 667690f90b6SHeiner Kallweit if (data && data->flags & MMC_DATA_READ) { 66851c5d844SKevin Hilman xfer_bytes = data->blksz * data->blocks; 66951c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size); 67051c5d844SKevin Hilman sg_copy_from_buffer(data->sg, data->sg_len, 67151c5d844SKevin Hilman host->bounce_buf, xfer_bytes); 67251c5d844SKevin Hilman data->bytes_xfered = xfer_bytes; 67351c5d844SKevin Hilman } 67451c5d844SKevin Hilman 67551c5d844SKevin Hilman meson_mmc_read_resp(host->mmc, cmd); 67651c5d844SKevin Hilman if (!data || !data->stop || mrq->sbc) 67751c5d844SKevin Hilman meson_mmc_request_done(host->mmc, mrq); 67851c5d844SKevin Hilman else 67951c5d844SKevin Hilman meson_mmc_start_cmd(host->mmc, data->stop); 68051c5d844SKevin Hilman 681690f90b6SHeiner Kallweit return IRQ_HANDLED; 68251c5d844SKevin Hilman } 68351c5d844SKevin Hilman 68451c5d844SKevin Hilman /* 68551c5d844SKevin Hilman * NOTE: we only need this until the GPIO/pinctrl driver can handle 68651c5d844SKevin Hilman * interrupts. For now, the MMC core will use this for polling. 68751c5d844SKevin Hilman */ 68851c5d844SKevin Hilman static int meson_mmc_get_cd(struct mmc_host *mmc) 68951c5d844SKevin Hilman { 69051c5d844SKevin Hilman int status = mmc_gpio_get_cd(mmc); 69151c5d844SKevin Hilman 69251c5d844SKevin Hilman if (status == -ENOSYS) 69351c5d844SKevin Hilman return 1; /* assume present */ 69451c5d844SKevin Hilman 69551c5d844SKevin Hilman return status; 69651c5d844SKevin Hilman } 69751c5d844SKevin Hilman 69851c5d844SKevin Hilman static const struct mmc_host_ops meson_mmc_ops = { 69951c5d844SKevin Hilman .request = meson_mmc_request, 70051c5d844SKevin Hilman .set_ios = meson_mmc_set_ios, 70151c5d844SKevin Hilman .get_cd = meson_mmc_get_cd, 70251c5d844SKevin Hilman }; 70351c5d844SKevin Hilman 70451c5d844SKevin Hilman static int meson_mmc_probe(struct platform_device *pdev) 70551c5d844SKevin Hilman { 70651c5d844SKevin Hilman struct resource *res; 70751c5d844SKevin Hilman struct meson_host *host; 70851c5d844SKevin Hilman struct mmc_host *mmc; 7099a1da4dfSHeiner Kallweit int ret, irq; 71051c5d844SKevin Hilman 71151c5d844SKevin Hilman mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 71251c5d844SKevin Hilman if (!mmc) 71351c5d844SKevin Hilman return -ENOMEM; 71451c5d844SKevin Hilman host = mmc_priv(mmc); 71551c5d844SKevin Hilman host->mmc = mmc; 71651c5d844SKevin Hilman host->dev = &pdev->dev; 71751c5d844SKevin Hilman dev_set_drvdata(&pdev->dev, host); 71851c5d844SKevin Hilman 71951c5d844SKevin Hilman spin_lock_init(&host->lock); 72051c5d844SKevin Hilman 72151c5d844SKevin Hilman /* Get regulators and the supported OCR mask */ 72251c5d844SKevin Hilman host->vqmmc_enabled = false; 72351c5d844SKevin Hilman ret = mmc_regulator_get_supply(mmc); 72451c5d844SKevin Hilman if (ret == -EPROBE_DEFER) 72551c5d844SKevin Hilman goto free_host; 72651c5d844SKevin Hilman 72751c5d844SKevin Hilman ret = mmc_of_parse(mmc); 72851c5d844SKevin Hilman if (ret) { 729dc012058SKevin Hilman if (ret != -EPROBE_DEFER) 73051c5d844SKevin Hilman dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 73151c5d844SKevin Hilman goto free_host; 73251c5d844SKevin Hilman } 73351c5d844SKevin Hilman 73451c5d844SKevin Hilman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 73551c5d844SKevin Hilman host->regs = devm_ioremap_resource(&pdev->dev, res); 73651c5d844SKevin Hilman if (IS_ERR(host->regs)) { 73751c5d844SKevin Hilman ret = PTR_ERR(host->regs); 73851c5d844SKevin Hilman goto free_host; 73951c5d844SKevin Hilman } 74051c5d844SKevin Hilman 7419a1da4dfSHeiner Kallweit irq = platform_get_irq(pdev, 0); 7429a1da4dfSHeiner Kallweit if (!irq) { 74351c5d844SKevin Hilman dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 74451c5d844SKevin Hilman ret = -EINVAL; 74551c5d844SKevin Hilman goto free_host; 74651c5d844SKevin Hilman } 74751c5d844SKevin Hilman 74851c5d844SKevin Hilman host->core_clk = devm_clk_get(&pdev->dev, "core"); 74951c5d844SKevin Hilman if (IS_ERR(host->core_clk)) { 75051c5d844SKevin Hilman ret = PTR_ERR(host->core_clk); 75151c5d844SKevin Hilman goto free_host; 75251c5d844SKevin Hilman } 75351c5d844SKevin Hilman 75451c5d844SKevin Hilman ret = clk_prepare_enable(host->core_clk); 75551c5d844SKevin Hilman if (ret) 75651c5d844SKevin Hilman goto free_host; 75751c5d844SKevin Hilman 75851c5d844SKevin Hilman ret = meson_mmc_clk_init(host); 75951c5d844SKevin Hilman if (ret) 76051c5d844SKevin Hilman goto free_host; 76151c5d844SKevin Hilman 76251c5d844SKevin Hilman /* Stop execution */ 76351c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START); 76451c5d844SKevin Hilman 76551c5d844SKevin Hilman /* clear, ack, enable all interrupts */ 76651c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_IRQ_EN); 76751c5d844SKevin Hilman writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); 76892763b99SHeiner Kallweit writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); 76951c5d844SKevin Hilman 7709a1da4dfSHeiner Kallweit ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq, 7719a1da4dfSHeiner Kallweit meson_mmc_irq_thread, IRQF_SHARED, 7729a1da4dfSHeiner Kallweit DRIVER_NAME, host); 77351c5d844SKevin Hilman if (ret) 77451c5d844SKevin Hilman goto free_host; 77551c5d844SKevin Hilman 776efe0b669SHeiner Kallweit mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 777efe0b669SHeiner Kallweit mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 778efe0b669SHeiner Kallweit 77951c5d844SKevin Hilman /* data bounce buffer */ 7804136fcb5SHeiner Kallweit host->bounce_buf_size = mmc->max_req_size; 78151c5d844SKevin Hilman host->bounce_buf = 78251c5d844SKevin Hilman dma_alloc_coherent(host->dev, host->bounce_buf_size, 78351c5d844SKevin Hilman &host->bounce_dma_addr, GFP_KERNEL); 78451c5d844SKevin Hilman if (host->bounce_buf == NULL) { 78551c5d844SKevin Hilman dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 78651c5d844SKevin Hilman ret = -ENOMEM; 78751c5d844SKevin Hilman goto free_host; 78851c5d844SKevin Hilman } 78951c5d844SKevin Hilman 79051c5d844SKevin Hilman mmc->ops = &meson_mmc_ops; 79151c5d844SKevin Hilman mmc_add_host(mmc); 79251c5d844SKevin Hilman 79351c5d844SKevin Hilman return 0; 79451c5d844SKevin Hilman 79551c5d844SKevin Hilman free_host: 79651c5d844SKevin Hilman clk_disable_unprepare(host->cfg_div_clk); 79751c5d844SKevin Hilman clk_disable_unprepare(host->core_clk); 79851c5d844SKevin Hilman mmc_free_host(mmc); 79951c5d844SKevin Hilman return ret; 80051c5d844SKevin Hilman } 80151c5d844SKevin Hilman 80251c5d844SKevin Hilman static int meson_mmc_remove(struct platform_device *pdev) 80351c5d844SKevin Hilman { 80451c5d844SKevin Hilman struct meson_host *host = dev_get_drvdata(&pdev->dev); 80551c5d844SKevin Hilman 80692763b99SHeiner Kallweit /* disable interrupts */ 80792763b99SHeiner Kallweit writel(0, host->regs + SD_EMMC_IRQ_EN); 80892763b99SHeiner Kallweit 80951c5d844SKevin Hilman dma_free_coherent(host->dev, host->bounce_buf_size, 81051c5d844SKevin Hilman host->bounce_buf, host->bounce_dma_addr); 81151c5d844SKevin Hilman 81251c5d844SKevin Hilman clk_disable_unprepare(host->cfg_div_clk); 81351c5d844SKevin Hilman clk_disable_unprepare(host->core_clk); 81451c5d844SKevin Hilman 81551c5d844SKevin Hilman mmc_free_host(host->mmc); 81651c5d844SKevin Hilman return 0; 81751c5d844SKevin Hilman } 81851c5d844SKevin Hilman 81951c5d844SKevin Hilman static const struct of_device_id meson_mmc_of_match[] = { 82051c5d844SKevin Hilman { .compatible = "amlogic,meson-gx-mmc", }, 82151c5d844SKevin Hilman { .compatible = "amlogic,meson-gxbb-mmc", }, 82251c5d844SKevin Hilman { .compatible = "amlogic,meson-gxl-mmc", }, 82351c5d844SKevin Hilman { .compatible = "amlogic,meson-gxm-mmc", }, 82451c5d844SKevin Hilman {} 82551c5d844SKevin Hilman }; 82651c5d844SKevin Hilman MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 82751c5d844SKevin Hilman 82851c5d844SKevin Hilman static struct platform_driver meson_mmc_driver = { 82951c5d844SKevin Hilman .probe = meson_mmc_probe, 83051c5d844SKevin Hilman .remove = meson_mmc_remove, 83151c5d844SKevin Hilman .driver = { 83251c5d844SKevin Hilman .name = DRIVER_NAME, 83351c5d844SKevin Hilman .of_match_table = of_match_ptr(meson_mmc_of_match), 83451c5d844SKevin Hilman }, 83551c5d844SKevin Hilman }; 83651c5d844SKevin Hilman 83751c5d844SKevin Hilman module_platform_driver(meson_mmc_driver); 83851c5d844SKevin Hilman 83951c5d844SKevin Hilman MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver"); 84051c5d844SKevin Hilman MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 84151c5d844SKevin Hilman MODULE_LICENSE("GPL v2"); 842