138cf0d46SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 251c5d844SKevin Hilman /* 351c5d844SKevin Hilman * Amlogic SD/eMMC driver for the GX/S905 family SoCs 451c5d844SKevin Hilman * 551c5d844SKevin Hilman * Copyright (c) 2016 BayLibre, SAS. 651c5d844SKevin Hilman * Author: Kevin Hilman <khilman@baylibre.com> 751c5d844SKevin Hilman */ 851c5d844SKevin Hilman #include <linux/kernel.h> 951c5d844SKevin Hilman #include <linux/module.h> 1051c5d844SKevin Hilman #include <linux/init.h> 1118f92bc0SJerome Brunet #include <linux/delay.h> 1251c5d844SKevin Hilman #include <linux/device.h> 1398849da6SJerome Brunet #include <linux/iopoll.h> 1451c5d844SKevin Hilman #include <linux/of_device.h> 1551c5d844SKevin Hilman #include <linux/platform_device.h> 1651c5d844SKevin Hilman #include <linux/ioport.h> 1751c5d844SKevin Hilman #include <linux/dma-mapping.h> 1851c5d844SKevin Hilman #include <linux/mmc/host.h> 1951c5d844SKevin Hilman #include <linux/mmc/mmc.h> 2051c5d844SKevin Hilman #include <linux/mmc/sdio.h> 2151c5d844SKevin Hilman #include <linux/mmc/slot-gpio.h> 2251c5d844SKevin Hilman #include <linux/io.h> 2351c5d844SKevin Hilman #include <linux/clk.h> 2451c5d844SKevin Hilman #include <linux/clk-provider.h> 2551c5d844SKevin Hilman #include <linux/regulator/consumer.h> 2619c6beaaSJerome Brunet #include <linux/reset.h> 27b8789ec4SUlf Hansson #include <linux/interrupt.h> 281231e7ebSHeiner Kallweit #include <linux/bitfield.h> 298fb572acSThierry Reding #include <linux/pinctrl/consumer.h> 3051c5d844SKevin Hilman 3151c5d844SKevin Hilman #define DRIVER_NAME "meson-gx-mmc" 3251c5d844SKevin Hilman 3351c5d844SKevin Hilman #define SD_EMMC_CLOCK 0x0 341231e7ebSHeiner Kallweit #define CLK_DIV_MASK GENMASK(5, 0) 351231e7ebSHeiner Kallweit #define CLK_SRC_MASK GENMASK(7, 6) 361231e7ebSHeiner Kallweit #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37c08bcb6cSHeiner Kallweit #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38c08bcb6cSHeiner Kallweit #define CLK_RX_PHASE_MASK GENMASK(13, 12) 395e6f75f4SJerome Brunet #define CLK_PHASE_0 0 405e6f75f4SJerome Brunet #define CLK_PHASE_180 2 41df069815SNan Li #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42df069815SNan Li #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43df069815SNan Li #define CLK_V2_ALWAYS_ON BIT(24) 44066ecde6SHeiner Kallweit #define CLK_V2_IRQ_SDIO_SLEEP BIT(25) 45df069815SNan Li 46df069815SNan Li #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 47df069815SNan Li #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 48df069815SNan Li #define CLK_V3_ALWAYS_ON BIT(28) 49066ecde6SHeiner Kallweit #define CLK_V3_IRQ_SDIO_SLEEP BIT(29) 50df069815SNan Li 51df069815SNan Li #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 52df069815SNan Li #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 53df069815SNan Li #define CLK_ALWAYS_ON(h) (h->data->always_on) 54066ecde6SHeiner Kallweit #define CLK_IRQ_SDIO_SLEEP(h) (h->data->irq_sdio_sleep) 5551c5d844SKevin Hilman 5652899b99SJerome Brunet #define SD_EMMC_DELAY 0x4 5751c5d844SKevin Hilman #define SD_EMMC_ADJUST 0x8 5871645e65SJerome Brunet #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 5971645e65SJerome Brunet #define ADJUST_DS_EN BIT(15) 6071645e65SJerome Brunet #define ADJUST_ADJ_EN BIT(13) 61df069815SNan Li 62df069815SNan Li #define SD_EMMC_DELAY1 0x4 63df069815SNan Li #define SD_EMMC_DELAY2 0x8 64df069815SNan Li #define SD_EMMC_V3_ADJUST 0xc 65df069815SNan Li 6651c5d844SKevin Hilman #define SD_EMMC_CALOUT 0x10 6751c5d844SKevin Hilman #define SD_EMMC_START 0x40 6851c5d844SKevin Hilman #define START_DESC_INIT BIT(0) 6951c5d844SKevin Hilman #define START_DESC_BUSY BIT(1) 701231e7ebSHeiner Kallweit #define START_DESC_ADDR_MASK GENMASK(31, 2) 7151c5d844SKevin Hilman 7251c5d844SKevin Hilman #define SD_EMMC_CFG 0x44 731231e7ebSHeiner Kallweit #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 7451c5d844SKevin Hilman #define CFG_BUS_WIDTH_1 0x0 7551c5d844SKevin Hilman #define CFG_BUS_WIDTH_4 0x1 7651c5d844SKevin Hilman #define CFG_BUS_WIDTH_8 0x2 7751c5d844SKevin Hilman #define CFG_DDR BIT(2) 781231e7ebSHeiner Kallweit #define CFG_BLK_LEN_MASK GENMASK(7, 4) 791231e7ebSHeiner Kallweit #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 801231e7ebSHeiner Kallweit #define CFG_RC_CC_MASK GENMASK(15, 12) 8151c5d844SKevin Hilman #define CFG_STOP_CLOCK BIT(22) 8251c5d844SKevin Hilman #define CFG_CLK_ALWAYS_ON BIT(18) 83e21e6fddSHeiner Kallweit #define CFG_CHK_DS BIT(20) 8451c5d844SKevin Hilman #define CFG_AUTO_CLK BIT(23) 8518f92bc0SJerome Brunet #define CFG_ERR_ABORT BIT(27) 8651c5d844SKevin Hilman 8751c5d844SKevin Hilman #define SD_EMMC_STATUS 0x48 8851c5d844SKevin Hilman #define STATUS_BUSY BIT(31) 8918f92bc0SJerome Brunet #define STATUS_DESC_BUSY BIT(30) 90186cd8b7SJerome Brunet #define STATUS_DATI GENMASK(23, 16) 9151c5d844SKevin Hilman 9251c5d844SKevin Hilman #define SD_EMMC_IRQ_EN 0x4c 931231e7ebSHeiner Kallweit #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 9451c5d844SKevin Hilman #define IRQ_TXD_ERR BIT(8) 9551c5d844SKevin Hilman #define IRQ_DESC_ERR BIT(9) 9651c5d844SKevin Hilman #define IRQ_RESP_ERR BIT(10) 9774858655SJerome Brunet #define IRQ_CRC_ERR \ 9874858655SJerome Brunet (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 9951c5d844SKevin Hilman #define IRQ_RESP_TIMEOUT BIT(11) 10051c5d844SKevin Hilman #define IRQ_DESC_TIMEOUT BIT(12) 10174858655SJerome Brunet #define IRQ_TIMEOUTS \ 10274858655SJerome Brunet (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 10351c5d844SKevin Hilman #define IRQ_END_OF_CHAIN BIT(13) 10451c5d844SKevin Hilman #define IRQ_RESP_STATUS BIT(14) 10551c5d844SKevin Hilman #define IRQ_SDIO BIT(15) 10674858655SJerome Brunet #define IRQ_EN_MASK \ 1076f6fac8aSHeiner Kallweit (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN) 10851c5d844SKevin Hilman 10951c5d844SKevin Hilman #define SD_EMMC_CMD_CFG 0x50 11051c5d844SKevin Hilman #define SD_EMMC_CMD_ARG 0x54 11151c5d844SKevin Hilman #define SD_EMMC_CMD_DAT 0x58 11251c5d844SKevin Hilman #define SD_EMMC_CMD_RSP 0x5c 11351c5d844SKevin Hilman #define SD_EMMC_CMD_RSP1 0x60 11451c5d844SKevin Hilman #define SD_EMMC_CMD_RSP2 0x64 11551c5d844SKevin Hilman #define SD_EMMC_CMD_RSP3 0x68 11651c5d844SKevin Hilman 11751c5d844SKevin Hilman #define SD_EMMC_RXD 0x94 11851c5d844SKevin Hilman #define SD_EMMC_TXD 0x94 11951c5d844SKevin Hilman #define SD_EMMC_LAST_REG SD_EMMC_TXD 12051c5d844SKevin Hilman 121acdc8e71SNeil Armstrong #define SD_EMMC_SRAM_DATA_BUF_LEN 1536 122acdc8e71SNeil Armstrong #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 123acdc8e71SNeil Armstrong 12451c5d844SKevin Hilman #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 12551c5d844SKevin Hilman #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 126bb11eff1SHeiner Kallweit #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 127bb11eff1SHeiner Kallweit #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 12851c5d844SKevin Hilman #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 12979ed05e3SHeiner Kallweit #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 13079ed05e3SHeiner Kallweit 13179ed05e3SHeiner Kallweit #define SD_EMMC_PRE_REQ_DONE BIT(0) 13279ed05e3SHeiner Kallweit #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 13379ed05e3SHeiner Kallweit 13451c5d844SKevin Hilman #define MUX_CLK_NUM_PARENTS 2 13551c5d844SKevin Hilman 136df069815SNan Li struct meson_mmc_data { 137df069815SNan Li unsigned int tx_delay_mask; 138df069815SNan Li unsigned int rx_delay_mask; 139df069815SNan Li unsigned int always_on; 14071645e65SJerome Brunet unsigned int adjust; 141066ecde6SHeiner Kallweit unsigned int irq_sdio_sleep; 142df069815SNan Li }; 143df069815SNan Li 14479ed05e3SHeiner Kallweit struct sd_emmc_desc { 14579ed05e3SHeiner Kallweit u32 cmd_cfg; 14679ed05e3SHeiner Kallweit u32 cmd_arg; 14779ed05e3SHeiner Kallweit u32 cmd_data; 14879ed05e3SHeiner Kallweit u32 cmd_resp; 14979ed05e3SHeiner Kallweit }; 15079ed05e3SHeiner Kallweit 15151c5d844SKevin Hilman struct meson_host { 15251c5d844SKevin Hilman struct device *dev; 153df069815SNan Li struct meson_mmc_data *data; 15451c5d844SKevin Hilman struct mmc_host *mmc; 15551c5d844SKevin Hilman struct mmc_command *cmd; 15651c5d844SKevin Hilman 15751c5d844SKevin Hilman void __iomem *regs; 15851c5d844SKevin Hilman struct clk *core_clk; 1595e6f75f4SJerome Brunet struct clk *mux_clk; 160bd911ec4SJerome Brunet struct clk *mmc_clk; 161f89f55dfSJerome Brunet unsigned long req_rate; 162dc38ac81SJerome Brunet bool ddr; 16351c5d844SKevin Hilman 164acdc8e71SNeil Armstrong bool dram_access_quirk; 165acdc8e71SNeil Armstrong 1661e03331dSJerome Brunet struct pinctrl *pinctrl; 1671e03331dSJerome Brunet struct pinctrl_state *pins_clk_gate; 1681e03331dSJerome Brunet 16951c5d844SKevin Hilman unsigned int bounce_buf_size; 17051c5d844SKevin Hilman void *bounce_buf; 171103a5348SNeil Armstrong void __iomem *bounce_iomem_buf; 17251c5d844SKevin Hilman dma_addr_t bounce_dma_addr; 17379ed05e3SHeiner Kallweit struct sd_emmc_desc *descs; 17479ed05e3SHeiner Kallweit dma_addr_t descs_dma_addr; 17551c5d844SKevin Hilman 176bb364890SRemi Pommarel int irq; 177bb364890SRemi Pommarel 17851c5d844SKevin Hilman bool vqmmc_enabled; 179f0d2f153SRong Chen bool needs_pre_post_req; 180f0d2f153SRong Chen 181066ecde6SHeiner Kallweit spinlock_t lock; 18251c5d844SKevin Hilman }; 18351c5d844SKevin Hilman 1841231e7ebSHeiner Kallweit #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 18551c5d844SKevin Hilman #define CMD_CFG_BLOCK_MODE BIT(9) 18651c5d844SKevin Hilman #define CMD_CFG_R1B BIT(10) 18751c5d844SKevin Hilman #define CMD_CFG_END_OF_CHAIN BIT(11) 1881231e7ebSHeiner Kallweit #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 18951c5d844SKevin Hilman #define CMD_CFG_NO_RESP BIT(16) 19051c5d844SKevin Hilman #define CMD_CFG_NO_CMD BIT(17) 19151c5d844SKevin Hilman #define CMD_CFG_DATA_IO BIT(18) 19251c5d844SKevin Hilman #define CMD_CFG_DATA_WR BIT(19) 19351c5d844SKevin Hilman #define CMD_CFG_RESP_NOCRC BIT(20) 19451c5d844SKevin Hilman #define CMD_CFG_RESP_128 BIT(21) 19551c5d844SKevin Hilman #define CMD_CFG_RESP_NUM BIT(22) 19651c5d844SKevin Hilman #define CMD_CFG_DATA_NUM BIT(23) 1971231e7ebSHeiner Kallweit #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 19851c5d844SKevin Hilman #define CMD_CFG_ERROR BIT(30) 19951c5d844SKevin Hilman #define CMD_CFG_OWNER BIT(31) 20051c5d844SKevin Hilman 2011231e7ebSHeiner Kallweit #define CMD_DATA_MASK GENMASK(31, 2) 20251c5d844SKevin Hilman #define CMD_DATA_BIG_ENDIAN BIT(1) 20351c5d844SKevin Hilman #define CMD_DATA_SRAM BIT(0) 2041231e7ebSHeiner Kallweit #define CMD_RESP_MASK GENMASK(31, 1) 20551c5d844SKevin Hilman #define CMD_RESP_SRAM BIT(0) 20651c5d844SKevin Hilman 2074eee86c3SHeiner Kallweit static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 2084eee86c3SHeiner Kallweit { 2094eee86c3SHeiner Kallweit unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 2104eee86c3SHeiner Kallweit 2114eee86c3SHeiner Kallweit if (!timeout) 2124eee86c3SHeiner Kallweit return SD_EMMC_CMD_TIMEOUT_DATA; 2134eee86c3SHeiner Kallweit 2144eee86c3SHeiner Kallweit timeout = roundup_pow_of_two(timeout); 2154eee86c3SHeiner Kallweit 2164eee86c3SHeiner Kallweit return min(timeout, 32768U); /* max. 2^15 ms */ 2174eee86c3SHeiner Kallweit } 2184eee86c3SHeiner Kallweit 219e5e4a3ebSHeiner Kallweit static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 220e5e4a3ebSHeiner Kallweit { 221e5e4a3ebSHeiner Kallweit if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 222e5e4a3ebSHeiner Kallweit return cmd->mrq->cmd; 223e5e4a3ebSHeiner Kallweit else if (mmc_op_multi(cmd->opcode) && 224e5e4a3ebSHeiner Kallweit (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 225e5e4a3ebSHeiner Kallweit return cmd->mrq->stop; 226e5e4a3ebSHeiner Kallweit else 227e5e4a3ebSHeiner Kallweit return NULL; 228e5e4a3ebSHeiner Kallweit } 229e5e4a3ebSHeiner Kallweit 23079ed05e3SHeiner Kallweit static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 23179ed05e3SHeiner Kallweit struct mmc_request *mrq) 23279ed05e3SHeiner Kallweit { 233acdc8e71SNeil Armstrong struct meson_host *host = mmc_priv(mmc); 23479ed05e3SHeiner Kallweit struct mmc_data *data = mrq->data; 23579ed05e3SHeiner Kallweit struct scatterlist *sg; 23679ed05e3SHeiner Kallweit int i; 23779ed05e3SHeiner Kallweit 23824835611SHeiner Kallweit /* 239acdc8e71SNeil Armstrong * When Controller DMA cannot directly access DDR memory, disable 240acdc8e71SNeil Armstrong * support for Chain Mode to directly use the internal SRAM using 241acdc8e71SNeil Armstrong * the bounce buffer mode. 242acdc8e71SNeil Armstrong */ 243acdc8e71SNeil Armstrong if (host->dram_access_quirk) 244acdc8e71SNeil Armstrong return; 245acdc8e71SNeil Armstrong 2469b81354dSNeil Armstrong /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */ 2479b81354dSNeil Armstrong if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) { 248acdc8e71SNeil Armstrong /* 249e085b51cSDmitry Lebed * In block mode DMA descriptor format, "length" field indicates 250e085b51cSDmitry Lebed * number of blocks and there is no way to pass DMA size that 251e085b51cSDmitry Lebed * is not multiple of SDIO block size, making it impossible to 252e085b51cSDmitry Lebed * tie more than one memory buffer with single SDIO block. 253e085b51cSDmitry Lebed * Block mode sg buffer size should be aligned with SDIO block 254e085b51cSDmitry Lebed * size, otherwise chain mode could not be used. 25524835611SHeiner Kallweit */ 256e085b51cSDmitry Lebed for_each_sg(data->sg, sg, data->sg_len, i) { 257e085b51cSDmitry Lebed if (sg->length % data->blksz) { 2587412dee9SNeil Armstrong dev_warn_once(mmc_dev(mmc), 2597412dee9SNeil Armstrong "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n", 260e085b51cSDmitry Lebed sg->length, data->blksz); 26124835611SHeiner Kallweit return; 262e085b51cSDmitry Lebed } 263e085b51cSDmitry Lebed } 26479ed05e3SHeiner Kallweit } 26579ed05e3SHeiner Kallweit 266e085b51cSDmitry Lebed for_each_sg(data->sg, sg, data->sg_len, i) { 267e085b51cSDmitry Lebed /* check for 8 byte alignment */ 268e085b51cSDmitry Lebed if (sg->offset % 8) { 269cabb1bb6SNeil Armstrong dev_warn_once(mmc_dev(mmc), 270cabb1bb6SNeil Armstrong "unaligned sg offset %u, disabling descriptor DMA for transfer\n", 271cabb1bb6SNeil Armstrong sg->offset); 272e085b51cSDmitry Lebed return; 273e085b51cSDmitry Lebed } 274e085b51cSDmitry Lebed } 275e085b51cSDmitry Lebed 27679ed05e3SHeiner Kallweit data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 27779ed05e3SHeiner Kallweit } 27879ed05e3SHeiner Kallweit 27979ed05e3SHeiner Kallweit static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 28079ed05e3SHeiner Kallweit { 28179ed05e3SHeiner Kallweit return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 28279ed05e3SHeiner Kallweit } 28379ed05e3SHeiner Kallweit 28479ed05e3SHeiner Kallweit static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 28579ed05e3SHeiner Kallweit { 28679ed05e3SHeiner Kallweit return data && data->flags & MMC_DATA_READ && 28779ed05e3SHeiner Kallweit !meson_mmc_desc_chain_mode(data); 28879ed05e3SHeiner Kallweit } 28979ed05e3SHeiner Kallweit 29079ed05e3SHeiner Kallweit static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 29179ed05e3SHeiner Kallweit { 29279ed05e3SHeiner Kallweit struct mmc_data *data = mrq->data; 29379ed05e3SHeiner Kallweit 29479ed05e3SHeiner Kallweit if (!data) 29579ed05e3SHeiner Kallweit return; 29679ed05e3SHeiner Kallweit 29779ed05e3SHeiner Kallweit meson_mmc_get_transfer_mode(mmc, mrq); 29879ed05e3SHeiner Kallweit data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 29979ed05e3SHeiner Kallweit 30079ed05e3SHeiner Kallweit if (!meson_mmc_desc_chain_mode(data)) 30179ed05e3SHeiner Kallweit return; 30279ed05e3SHeiner Kallweit 30379ed05e3SHeiner Kallweit data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 30479ed05e3SHeiner Kallweit mmc_get_dma_dir(data)); 30579ed05e3SHeiner Kallweit if (!data->sg_count) 30679ed05e3SHeiner Kallweit dev_err(mmc_dev(mmc), "dma_map_sg failed"); 30779ed05e3SHeiner Kallweit } 30879ed05e3SHeiner Kallweit 30979ed05e3SHeiner Kallweit static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 31079ed05e3SHeiner Kallweit int err) 31179ed05e3SHeiner Kallweit { 31279ed05e3SHeiner Kallweit struct mmc_data *data = mrq->data; 31379ed05e3SHeiner Kallweit 31479ed05e3SHeiner Kallweit if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 31579ed05e3SHeiner Kallweit dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 31679ed05e3SHeiner Kallweit mmc_get_dma_dir(data)); 31779ed05e3SHeiner Kallweit } 31879ed05e3SHeiner Kallweit 3191e03331dSJerome Brunet /* 3201e03331dSJerome Brunet * Gating the clock on this controller is tricky. It seems the mmc clock 3211e03331dSJerome Brunet * is also used by the controller. It may crash during some operation if the 3221e03331dSJerome Brunet * clock is stopped. The safest thing to do, whenever possible, is to keep 3231e03331dSJerome Brunet * clock running at stop it at the pad using the pinmux. 3241e03331dSJerome Brunet */ 3251e03331dSJerome Brunet static void meson_mmc_clk_gate(struct meson_host *host) 3261e03331dSJerome Brunet { 3271e03331dSJerome Brunet u32 cfg; 3281e03331dSJerome Brunet 3291e03331dSJerome Brunet if (host->pins_clk_gate) { 3301e03331dSJerome Brunet pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 3311e03331dSJerome Brunet } else { 3321e03331dSJerome Brunet /* 3331e03331dSJerome Brunet * If the pinmux is not provided - default to the classic and 3341e03331dSJerome Brunet * unsafe method 3351e03331dSJerome Brunet */ 3361e03331dSJerome Brunet cfg = readl(host->regs + SD_EMMC_CFG); 3371e03331dSJerome Brunet cfg |= CFG_STOP_CLOCK; 3381e03331dSJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG); 3391e03331dSJerome Brunet } 3401e03331dSJerome Brunet } 3411e03331dSJerome Brunet 3421e03331dSJerome Brunet static void meson_mmc_clk_ungate(struct meson_host *host) 3431e03331dSJerome Brunet { 3441e03331dSJerome Brunet u32 cfg; 3451e03331dSJerome Brunet 3461e03331dSJerome Brunet if (host->pins_clk_gate) 347f9be7f9cSUlf Hansson pinctrl_select_default_state(host->dev); 3481e03331dSJerome Brunet 3491e03331dSJerome Brunet /* Make sure the clock is not stopped in the controller */ 3501e03331dSJerome Brunet cfg = readl(host->regs + SD_EMMC_CFG); 3511e03331dSJerome Brunet cfg &= ~CFG_STOP_CLOCK; 3521e03331dSJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG); 3531e03331dSJerome Brunet } 3541e03331dSJerome Brunet 355dc38ac81SJerome Brunet static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 356dc38ac81SJerome Brunet bool ddr) 35751c5d844SKevin Hilman { 35851c5d844SKevin Hilman struct mmc_host *mmc = host->mmc; 3595da86887SHeiner Kallweit int ret; 36051c5d844SKevin Hilman u32 cfg; 36151c5d844SKevin Hilman 362f89f55dfSJerome Brunet /* Same request - bail-out */ 363dc38ac81SJerome Brunet if (host->ddr == ddr && host->req_rate == rate) 36451c5d844SKevin Hilman return 0; 36551c5d844SKevin Hilman 36651c5d844SKevin Hilman /* stop clock */ 3671e03331dSJerome Brunet meson_mmc_clk_gate(host); 368f89f55dfSJerome Brunet host->req_rate = 0; 36951c5d844SKevin Hilman mmc->actual_clock = 0; 370dc38ac81SJerome Brunet 3715da86887SHeiner Kallweit /* return with clock being stopped */ 372dc38ac81SJerome Brunet if (!rate) 37351c5d844SKevin Hilman return 0; 37451c5d844SKevin Hilman 3751e03331dSJerome Brunet /* Stop the clock during rate change to avoid glitches */ 3761e03331dSJerome Brunet cfg = readl(host->regs + SD_EMMC_CFG); 3771e03331dSJerome Brunet cfg |= CFG_STOP_CLOCK; 3781e03331dSJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG); 3791e03331dSJerome Brunet 380dc38ac81SJerome Brunet if (ddr) { 381dc38ac81SJerome Brunet /* DDR modes require higher module clock */ 382dc38ac81SJerome Brunet rate <<= 1; 383dc38ac81SJerome Brunet cfg |= CFG_DDR; 384dc38ac81SJerome Brunet } else { 385dc38ac81SJerome Brunet cfg &= ~CFG_DDR; 386dc38ac81SJerome Brunet } 387dc38ac81SJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG); 388dc38ac81SJerome Brunet host->ddr = ddr; 389dc38ac81SJerome Brunet 390844c8a75SJerome Brunet ret = clk_set_rate(host->mmc_clk, rate); 3915da86887SHeiner Kallweit if (ret) { 3925da86887SHeiner Kallweit dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 393844c8a75SJerome Brunet rate, ret); 3945da86887SHeiner Kallweit return ret; 3955da86887SHeiner Kallweit } 39651c5d844SKevin Hilman 397844c8a75SJerome Brunet host->req_rate = rate; 398bd911ec4SJerome Brunet mmc->actual_clock = clk_get_rate(host->mmc_clk); 3995da86887SHeiner Kallweit 400844c8a75SJerome Brunet /* We should report the real output frequency of the controller */ 401dc38ac81SJerome Brunet if (ddr) { 402dc38ac81SJerome Brunet host->req_rate >>= 1; 403844c8a75SJerome Brunet mmc->actual_clock >>= 1; 404dc38ac81SJerome Brunet } 405844c8a75SJerome Brunet 406f89f55dfSJerome Brunet dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 407dc38ac81SJerome Brunet if (rate != mmc->actual_clock) 408dc38ac81SJerome Brunet dev_dbg(host->dev, "requested rate was %lu\n", rate); 4095da86887SHeiner Kallweit 4105da86887SHeiner Kallweit /* (re)start clock */ 4111e03331dSJerome Brunet meson_mmc_clk_ungate(host); 41251c5d844SKevin Hilman 4135da86887SHeiner Kallweit return 0; 41451c5d844SKevin Hilman } 41551c5d844SKevin Hilman 41651c5d844SKevin Hilman /* 41751c5d844SKevin Hilman * The SD/eMMC IP block has an internal mux and divider used for 41851c5d844SKevin Hilman * generating the MMC clock. Use the clock framework to create and 41951c5d844SKevin Hilman * manage these clocks. 42051c5d844SKevin Hilman */ 42151c5d844SKevin Hilman static int meson_mmc_clk_init(struct meson_host *host) 42251c5d844SKevin Hilman { 42351c5d844SKevin Hilman struct clk_init_data init; 424bd911ec4SJerome Brunet struct clk_mux *mux; 425bd911ec4SJerome Brunet struct clk_divider *div; 42651c5d844SKevin Hilman char clk_name[32]; 42751c5d844SKevin Hilman int i, ret = 0; 42851c5d844SKevin Hilman const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 429bd911ec4SJerome Brunet const char *clk_parent[1]; 4303c39e2caSJerome Brunet u32 clk_reg; 43151c5d844SKevin Hilman 432ef5c4815SJerome Brunet /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 4335e6f75f4SJerome Brunet clk_reg = CLK_ALWAYS_ON(host); 434ef5c4815SJerome Brunet clk_reg |= CLK_DIV_MASK; 4355e6f75f4SJerome Brunet clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 4365e6f75f4SJerome Brunet clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 4375e6f75f4SJerome Brunet clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 438066ecde6SHeiner Kallweit clk_reg |= CLK_IRQ_SDIO_SLEEP(host); 439ef5c4815SJerome Brunet writel(clk_reg, host->regs + SD_EMMC_CLOCK); 440ef5c4815SJerome Brunet 44151c5d844SKevin Hilman /* get the mux parents */ 44251c5d844SKevin Hilman for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 443e9883ef2SHeiner Kallweit struct clk *clk; 44451c5d844SKevin Hilman char name[16]; 44551c5d844SKevin Hilman 44651c5d844SKevin Hilman snprintf(name, sizeof(name), "clkin%d", i); 447e9883ef2SHeiner Kallweit clk = devm_clk_get(host->dev, name); 44889280d09SKrzysztof Kozlowski if (IS_ERR(clk)) 44989280d09SKrzysztof Kozlowski return dev_err_probe(host->dev, PTR_ERR(clk), 45089280d09SKrzysztof Kozlowski "Missing clock %s\n", name); 45151c5d844SKevin Hilman 452e9883ef2SHeiner Kallweit mux_parent_names[i] = __clk_get_name(clk); 45351c5d844SKevin Hilman } 45451c5d844SKevin Hilman 45551c5d844SKevin Hilman /* create the mux */ 456bd911ec4SJerome Brunet mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 457bd911ec4SJerome Brunet if (!mux) 458bd911ec4SJerome Brunet return -ENOMEM; 459bd911ec4SJerome Brunet 46051c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 46151c5d844SKevin Hilman init.name = clk_name; 46251c5d844SKevin Hilman init.ops = &clk_mux_ops; 46351c5d844SKevin Hilman init.flags = 0; 46451c5d844SKevin Hilman init.parent_names = mux_parent_names; 4657558c113SHeiner Kallweit init.num_parents = MUX_CLK_NUM_PARENTS; 46651c5d844SKevin Hilman 467bd911ec4SJerome Brunet mux->reg = host->regs + SD_EMMC_CLOCK; 468795c633fSJerome Brunet mux->shift = __ffs(CLK_SRC_MASK); 469bd911ec4SJerome Brunet mux->mask = CLK_SRC_MASK >> mux->shift; 470bd911ec4SJerome Brunet mux->hw.init = &init; 471bd911ec4SJerome Brunet 4725e6f75f4SJerome Brunet host->mux_clk = devm_clk_register(host->dev, &mux->hw); 4735e6f75f4SJerome Brunet if (WARN_ON(IS_ERR(host->mux_clk))) 4745e6f75f4SJerome Brunet return PTR_ERR(host->mux_clk); 47551c5d844SKevin Hilman 47651c5d844SKevin Hilman /* create the divider */ 477bd911ec4SJerome Brunet div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 478bd911ec4SJerome Brunet if (!div) 479bd911ec4SJerome Brunet return -ENOMEM; 480bd911ec4SJerome Brunet 48151c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 4827b9ebad3SHeiner Kallweit init.name = clk_name; 48351c5d844SKevin Hilman init.ops = &clk_divider_ops; 48451c5d844SKevin Hilman init.flags = CLK_SET_RATE_PARENT; 4855e6f75f4SJerome Brunet clk_parent[0] = __clk_get_name(host->mux_clk); 486bd911ec4SJerome Brunet init.parent_names = clk_parent; 487bd911ec4SJerome Brunet init.num_parents = 1; 48851c5d844SKevin Hilman 489bd911ec4SJerome Brunet div->reg = host->regs + SD_EMMC_CLOCK; 490795c633fSJerome Brunet div->shift = __ffs(CLK_DIV_MASK); 491bd911ec4SJerome Brunet div->width = __builtin_popcountl(CLK_DIV_MASK); 492bd911ec4SJerome Brunet div->hw.init = &init; 493ca3dcd3fSJerome Brunet div->flags = CLK_DIVIDER_ONE_BASED; 49451c5d844SKevin Hilman 4955e6f75f4SJerome Brunet host->mmc_clk = devm_clk_register(host->dev, &div->hw); 4965e6f75f4SJerome Brunet if (WARN_ON(IS_ERR(host->mmc_clk))) 497bd911ec4SJerome Brunet return PTR_ERR(host->mmc_clk); 49851c5d844SKevin Hilman 499bd911ec4SJerome Brunet /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 500bd911ec4SJerome Brunet host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 501bd911ec4SJerome Brunet ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 502a4c38c8dSUlf Hansson if (ret) 503a4c38c8dSUlf Hansson return ret; 50451c5d844SKevin Hilman 505bd911ec4SJerome Brunet return clk_prepare_enable(host->mmc_clk); 50651c5d844SKevin Hilman } 50751c5d844SKevin Hilman 508f50b7ac5SJerome Brunet static void meson_mmc_disable_resampling(struct meson_host *host) 509f50b7ac5SJerome Brunet { 510f50b7ac5SJerome Brunet unsigned int val = readl(host->regs + host->data->adjust); 511f50b7ac5SJerome Brunet 512f50b7ac5SJerome Brunet val &= ~ADJUST_ADJ_EN; 513f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust); 514f50b7ac5SJerome Brunet } 515f50b7ac5SJerome Brunet 516f50b7ac5SJerome Brunet static void meson_mmc_reset_resampling(struct meson_host *host) 517f50b7ac5SJerome Brunet { 518f50b7ac5SJerome Brunet unsigned int val; 519f50b7ac5SJerome Brunet 520f50b7ac5SJerome Brunet meson_mmc_disable_resampling(host); 521f50b7ac5SJerome Brunet 522f50b7ac5SJerome Brunet val = readl(host->regs + host->data->adjust); 523f50b7ac5SJerome Brunet val &= ~ADJUST_ADJ_DELAY_MASK; 524f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust); 525f50b7ac5SJerome Brunet } 526f50b7ac5SJerome Brunet 527f50b7ac5SJerome Brunet static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 528f50b7ac5SJerome Brunet { 529f50b7ac5SJerome Brunet struct meson_host *host = mmc_priv(mmc); 530f50b7ac5SJerome Brunet unsigned int val, dly, max_dly, i; 531f50b7ac5SJerome Brunet int ret; 532f50b7ac5SJerome Brunet 533f50b7ac5SJerome Brunet /* Resampling is done using the source clock */ 534f50b7ac5SJerome Brunet max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 535f50b7ac5SJerome Brunet clk_get_rate(host->mmc_clk)); 536f50b7ac5SJerome Brunet 537f50b7ac5SJerome Brunet val = readl(host->regs + host->data->adjust); 538f50b7ac5SJerome Brunet val |= ADJUST_ADJ_EN; 539f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust); 540f50b7ac5SJerome Brunet 541e0c29be6SWolfram Sang if (mmc_doing_retune(mmc)) 542f50b7ac5SJerome Brunet dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 543f50b7ac5SJerome Brunet else 544f50b7ac5SJerome Brunet dly = 0; 545f50b7ac5SJerome Brunet 546f50b7ac5SJerome Brunet for (i = 0; i < max_dly; i++) { 547f50b7ac5SJerome Brunet val &= ~ADJUST_ADJ_DELAY_MASK; 548f50b7ac5SJerome Brunet val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 549f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust); 550f50b7ac5SJerome Brunet 551f50b7ac5SJerome Brunet ret = mmc_send_tuning(mmc, opcode, NULL); 552f50b7ac5SJerome Brunet if (!ret) { 553f50b7ac5SJerome Brunet dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 554f50b7ac5SJerome Brunet (dly + i) % max_dly); 555f50b7ac5SJerome Brunet return 0; 556f50b7ac5SJerome Brunet } 557f50b7ac5SJerome Brunet } 558f50b7ac5SJerome Brunet 559f50b7ac5SJerome Brunet meson_mmc_reset_resampling(host); 560f50b7ac5SJerome Brunet return -EIO; 561f50b7ac5SJerome Brunet } 562f50b7ac5SJerome Brunet 563dc38ac81SJerome Brunet static int meson_mmc_prepare_ios_clock(struct meson_host *host, 564dc38ac81SJerome Brunet struct mmc_ios *ios) 565dc38ac81SJerome Brunet { 566dc38ac81SJerome Brunet bool ddr; 567dc38ac81SJerome Brunet 568dc38ac81SJerome Brunet switch (ios->timing) { 569dc38ac81SJerome Brunet case MMC_TIMING_MMC_DDR52: 570dc38ac81SJerome Brunet case MMC_TIMING_UHS_DDR50: 571dc38ac81SJerome Brunet ddr = true; 572dc38ac81SJerome Brunet break; 573dc38ac81SJerome Brunet 574dc38ac81SJerome Brunet default: 575dc38ac81SJerome Brunet ddr = false; 576dc38ac81SJerome Brunet break; 577dc38ac81SJerome Brunet } 578dc38ac81SJerome Brunet 579dc38ac81SJerome Brunet return meson_mmc_clk_set(host, ios->clock, ddr); 580dc38ac81SJerome Brunet } 581dc38ac81SJerome Brunet 582f50b7ac5SJerome Brunet static void meson_mmc_check_resampling(struct meson_host *host, 583f50b7ac5SJerome Brunet struct mmc_ios *ios) 584f50b7ac5SJerome Brunet { 585f50b7ac5SJerome Brunet switch (ios->timing) { 586f50b7ac5SJerome Brunet case MMC_TIMING_LEGACY: 587f50b7ac5SJerome Brunet case MMC_TIMING_MMC_HS: 588f50b7ac5SJerome Brunet case MMC_TIMING_SD_HS: 589f50b7ac5SJerome Brunet case MMC_TIMING_MMC_DDR52: 590f50b7ac5SJerome Brunet meson_mmc_disable_resampling(host); 591f50b7ac5SJerome Brunet break; 592f50b7ac5SJerome Brunet } 593f50b7ac5SJerome Brunet } 594f50b7ac5SJerome Brunet 59551c5d844SKevin Hilman static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 59651c5d844SKevin Hilman { 59751c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 598c36cf125SJerome Brunet u32 bus_width, val; 599c36cf125SJerome Brunet int err; 60051c5d844SKevin Hilman 60151c5d844SKevin Hilman /* 60251c5d844SKevin Hilman * GPIO regulator, only controls switching between 1v8 and 60351c5d844SKevin Hilman * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 60451c5d844SKevin Hilman */ 60551c5d844SKevin Hilman switch (ios->power_mode) { 60651c5d844SKevin Hilman case MMC_POWER_OFF: 60751c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vmmc)) 60851c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 60951c5d844SKevin Hilman 61051c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 61151c5d844SKevin Hilman regulator_disable(mmc->supply.vqmmc); 61251c5d844SKevin Hilman host->vqmmc_enabled = false; 61351c5d844SKevin Hilman } 61451c5d844SKevin Hilman 61551c5d844SKevin Hilman break; 61651c5d844SKevin Hilman 61751c5d844SKevin Hilman case MMC_POWER_UP: 61851c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vmmc)) 61951c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 6203e2b0af4SJerome Brunet 62151c5d844SKevin Hilman break; 62251c5d844SKevin Hilman 62351c5d844SKevin Hilman case MMC_POWER_ON: 62451c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 62551c5d844SKevin Hilman int ret = regulator_enable(mmc->supply.vqmmc); 62651c5d844SKevin Hilman 62751c5d844SKevin Hilman if (ret < 0) 628c36cf125SJerome Brunet dev_err(host->dev, 62951c5d844SKevin Hilman "failed to enable vqmmc regulator\n"); 63051c5d844SKevin Hilman else 63151c5d844SKevin Hilman host->vqmmc_enabled = true; 63251c5d844SKevin Hilman } 63351c5d844SKevin Hilman 63451c5d844SKevin Hilman break; 63551c5d844SKevin Hilman } 63651c5d844SKevin Hilman 63751c5d844SKevin Hilman /* Bus width */ 63851c5d844SKevin Hilman switch (ios->bus_width) { 63951c5d844SKevin Hilman case MMC_BUS_WIDTH_1: 64051c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_1; 64151c5d844SKevin Hilman break; 64251c5d844SKevin Hilman case MMC_BUS_WIDTH_4: 64351c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4; 64451c5d844SKevin Hilman break; 64551c5d844SKevin Hilman case MMC_BUS_WIDTH_8: 64651c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_8; 64751c5d844SKevin Hilman break; 64851c5d844SKevin Hilman default: 64951c5d844SKevin Hilman dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 65051c5d844SKevin Hilman ios->bus_width); 65151c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4; 65251c5d844SKevin Hilman } 65351c5d844SKevin Hilman 65451c5d844SKevin Hilman val = readl(host->regs + SD_EMMC_CFG); 6551231e7ebSHeiner Kallweit val &= ~CFG_BUS_WIDTH_MASK; 6561231e7ebSHeiner Kallweit val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 657dc38ac81SJerome Brunet writel(val, host->regs + SD_EMMC_CFG); 65851c5d844SKevin Hilman 659f50b7ac5SJerome Brunet meson_mmc_check_resampling(host, ios); 660dc38ac81SJerome Brunet err = meson_mmc_prepare_ios_clock(host, ios); 661c36cf125SJerome Brunet if (err) 662c36cf125SJerome Brunet dev_err(host->dev, "Failed to set clock: %d\n,", err); 663c36cf125SJerome Brunet 664c36cf125SJerome Brunet dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 665c01d1219SHeiner Kallweit } 66651c5d844SKevin Hilman 6673d6c991bSHeiner Kallweit static void meson_mmc_request_done(struct mmc_host *mmc, 6683d6c991bSHeiner Kallweit struct mmc_request *mrq) 66951c5d844SKevin Hilman { 67051c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 67151c5d844SKevin Hilman 67251c5d844SKevin Hilman host->cmd = NULL; 673f0d2f153SRong Chen if (host->needs_pre_post_req) 674f0d2f153SRong Chen meson_mmc_post_req(mmc, mrq, 0); 67551c5d844SKevin Hilman mmc_request_done(host->mmc, mrq); 67651c5d844SKevin Hilman } 67751c5d844SKevin Hilman 6783d03f6a9SHeiner Kallweit static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 6793d03f6a9SHeiner Kallweit { 6803d03f6a9SHeiner Kallweit struct meson_host *host = mmc_priv(mmc); 6813d03f6a9SHeiner Kallweit u32 cfg, blksz_old; 6823d03f6a9SHeiner Kallweit 6833d03f6a9SHeiner Kallweit cfg = readl(host->regs + SD_EMMC_CFG); 6843d03f6a9SHeiner Kallweit blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 6853d03f6a9SHeiner Kallweit 6863d03f6a9SHeiner Kallweit if (!is_power_of_2(blksz)) 6873d03f6a9SHeiner Kallweit dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 6883d03f6a9SHeiner Kallweit 6893d03f6a9SHeiner Kallweit blksz = ilog2(blksz); 6903d03f6a9SHeiner Kallweit 6913d03f6a9SHeiner Kallweit /* check if block-size matches, if not update */ 6923d03f6a9SHeiner Kallweit if (blksz == blksz_old) 6933d03f6a9SHeiner Kallweit return; 6943d03f6a9SHeiner Kallweit 6953d03f6a9SHeiner Kallweit dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 6963d03f6a9SHeiner Kallweit blksz_old, blksz); 6973d03f6a9SHeiner Kallweit 6983d03f6a9SHeiner Kallweit cfg &= ~CFG_BLK_LEN_MASK; 6993d03f6a9SHeiner Kallweit cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 7003d03f6a9SHeiner Kallweit writel(cfg, host->regs + SD_EMMC_CFG); 7013d03f6a9SHeiner Kallweit } 7023d03f6a9SHeiner Kallweit 70375c7fd96SHeiner Kallweit static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 70475c7fd96SHeiner Kallweit { 70575c7fd96SHeiner Kallweit if (cmd->flags & MMC_RSP_PRESENT) { 70675c7fd96SHeiner Kallweit if (cmd->flags & MMC_RSP_136) 70775c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_RESP_128; 70875c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_RESP_NUM; 70975c7fd96SHeiner Kallweit 71075c7fd96SHeiner Kallweit if (!(cmd->flags & MMC_RSP_CRC)) 71175c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_RESP_NOCRC; 71275c7fd96SHeiner Kallweit 71375c7fd96SHeiner Kallweit if (cmd->flags & MMC_RSP_BUSY) 71475c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_R1B; 71575c7fd96SHeiner Kallweit } else { 71675c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_NO_RESP; 71775c7fd96SHeiner Kallweit } 71875c7fd96SHeiner Kallweit } 71975c7fd96SHeiner Kallweit 72079ed05e3SHeiner Kallweit static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 72179ed05e3SHeiner Kallweit { 72279ed05e3SHeiner Kallweit struct meson_host *host = mmc_priv(mmc); 72379ed05e3SHeiner Kallweit struct sd_emmc_desc *desc = host->descs; 72479ed05e3SHeiner Kallweit struct mmc_data *data = host->cmd->data; 72579ed05e3SHeiner Kallweit struct scatterlist *sg; 72679ed05e3SHeiner Kallweit u32 start; 72779ed05e3SHeiner Kallweit int i; 72879ed05e3SHeiner Kallweit 72979ed05e3SHeiner Kallweit if (data->flags & MMC_DATA_WRITE) 73079ed05e3SHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_WR; 73179ed05e3SHeiner Kallweit 73279ed05e3SHeiner Kallweit if (data->blocks > 1) { 73379ed05e3SHeiner Kallweit cmd_cfg |= CMD_CFG_BLOCK_MODE; 73479ed05e3SHeiner Kallweit meson_mmc_set_blksz(mmc, data->blksz); 73579ed05e3SHeiner Kallweit } 73679ed05e3SHeiner Kallweit 73779ed05e3SHeiner Kallweit for_each_sg(data->sg, sg, data->sg_count, i) { 73879ed05e3SHeiner Kallweit unsigned int len = sg_dma_len(sg); 73979ed05e3SHeiner Kallweit 74079ed05e3SHeiner Kallweit if (data->blocks > 1) 74179ed05e3SHeiner Kallweit len /= data->blksz; 74279ed05e3SHeiner Kallweit 74379ed05e3SHeiner Kallweit desc[i].cmd_cfg = cmd_cfg; 74479ed05e3SHeiner Kallweit desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 74579ed05e3SHeiner Kallweit if (i > 0) 74679ed05e3SHeiner Kallweit desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 74779ed05e3SHeiner Kallweit desc[i].cmd_arg = host->cmd->arg; 74879ed05e3SHeiner Kallweit desc[i].cmd_resp = 0; 74979ed05e3SHeiner Kallweit desc[i].cmd_data = sg_dma_address(sg); 75079ed05e3SHeiner Kallweit } 75179ed05e3SHeiner Kallweit desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 75279ed05e3SHeiner Kallweit 75379ed05e3SHeiner Kallweit dma_wmb(); /* ensure descriptor is written before kicked */ 75479ed05e3SHeiner Kallweit start = host->descs_dma_addr | START_DESC_BUSY; 75579ed05e3SHeiner Kallweit writel(start, host->regs + SD_EMMC_START); 75679ed05e3SHeiner Kallweit } 75779ed05e3SHeiner Kallweit 7588a38a4d5SNeil Armstrong /* local sg copy for dram_access_quirk */ 759103a5348SNeil Armstrong static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data, 760103a5348SNeil Armstrong size_t buflen, bool to_buffer) 761103a5348SNeil Armstrong { 762103a5348SNeil Armstrong unsigned int sg_flags = SG_MITER_ATOMIC; 763103a5348SNeil Armstrong struct scatterlist *sgl = data->sg; 764103a5348SNeil Armstrong unsigned int nents = data->sg_len; 765103a5348SNeil Armstrong struct sg_mapping_iter miter; 766103a5348SNeil Armstrong unsigned int offset = 0; 767103a5348SNeil Armstrong 768103a5348SNeil Armstrong if (to_buffer) 769103a5348SNeil Armstrong sg_flags |= SG_MITER_FROM_SG; 770103a5348SNeil Armstrong else 771103a5348SNeil Armstrong sg_flags |= SG_MITER_TO_SG; 772103a5348SNeil Armstrong 773103a5348SNeil Armstrong sg_miter_start(&miter, sgl, nents, sg_flags); 774103a5348SNeil Armstrong 775103a5348SNeil Armstrong while ((offset < buflen) && sg_miter_next(&miter)) { 7768a38a4d5SNeil Armstrong unsigned int buf_offset = 0; 7778a38a4d5SNeil Armstrong unsigned int len, left; 7788a38a4d5SNeil Armstrong u32 *buf = miter.addr; 779103a5348SNeil Armstrong 780103a5348SNeil Armstrong len = min(miter.length, buflen - offset); 7818a38a4d5SNeil Armstrong left = len; 782103a5348SNeil Armstrong 7838a38a4d5SNeil Armstrong if (to_buffer) { 7848a38a4d5SNeil Armstrong do { 7858a38a4d5SNeil Armstrong writel(*buf++, host->bounce_iomem_buf + offset + buf_offset); 7868a38a4d5SNeil Armstrong 7878a38a4d5SNeil Armstrong buf_offset += 4; 7888a38a4d5SNeil Armstrong left -= 4; 7898a38a4d5SNeil Armstrong } while (left); 790103a5348SNeil Armstrong } else { 7918a38a4d5SNeil Armstrong do { 7928a38a4d5SNeil Armstrong *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset); 7938a38a4d5SNeil Armstrong 7948a38a4d5SNeil Armstrong buf_offset += 4; 7958a38a4d5SNeil Armstrong left -= 4; 7968a38a4d5SNeil Armstrong } while (left); 797103a5348SNeil Armstrong } 798103a5348SNeil Armstrong 799103a5348SNeil Armstrong offset += len; 800103a5348SNeil Armstrong } 801103a5348SNeil Armstrong 802103a5348SNeil Armstrong sg_miter_stop(&miter); 803103a5348SNeil Armstrong } 804103a5348SNeil Armstrong 80551c5d844SKevin Hilman static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 80651c5d844SKevin Hilman { 80751c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 80800412ddcSHeiner Kallweit struct mmc_data *data = cmd->data; 8093d03f6a9SHeiner Kallweit u32 cmd_cfg = 0, cmd_data = 0; 81051c5d844SKevin Hilman unsigned int xfer_bytes = 0; 81151c5d844SKevin Hilman 81251c5d844SKevin Hilman /* Setup descriptors */ 81351c5d844SKevin Hilman dma_rmb(); 81451c5d844SKevin Hilman 81579ed05e3SHeiner Kallweit host->cmd = cmd; 81679ed05e3SHeiner Kallweit 8171231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 818a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 81918f92bc0SJerome Brunet cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 82051c5d844SKevin Hilman 82175c7fd96SHeiner Kallweit meson_mmc_set_response_bits(cmd, &cmd_cfg); 82251c5d844SKevin Hilman 82351c5d844SKevin Hilman /* data? */ 82400412ddcSHeiner Kallweit if (data) { 82579ed05e3SHeiner Kallweit data->bytes_xfered = 0; 826a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_IO; 8271231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 8284eee86c3SHeiner Kallweit ilog2(meson_mmc_get_timeout_msecs(data))); 829a744c6feSHeiner Kallweit 83079ed05e3SHeiner Kallweit if (meson_mmc_desc_chain_mode(data)) { 83179ed05e3SHeiner Kallweit meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 83279ed05e3SHeiner Kallweit return; 83379ed05e3SHeiner Kallweit } 83479ed05e3SHeiner Kallweit 83500412ddcSHeiner Kallweit if (data->blocks > 1) { 836a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_BLOCK_MODE; 8371231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 8381231e7ebSHeiner Kallweit data->blocks); 8393d03f6a9SHeiner Kallweit meson_mmc_set_blksz(mmc, data->blksz); 84051c5d844SKevin Hilman } else { 8411231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 84251c5d844SKevin Hilman } 84351c5d844SKevin Hilman 84400412ddcSHeiner Kallweit xfer_bytes = data->blksz * data->blocks; 84500412ddcSHeiner Kallweit if (data->flags & MMC_DATA_WRITE) { 846a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_WR; 84751c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size); 8488a38a4d5SNeil Armstrong if (host->dram_access_quirk) 849103a5348SNeil Armstrong meson_mmc_copy_buffer(host, data, xfer_bytes, true); 8508a38a4d5SNeil Armstrong else 8518a38a4d5SNeil Armstrong sg_copy_to_buffer(data->sg, data->sg_len, 8528a38a4d5SNeil Armstrong host->bounce_buf, xfer_bytes); 85351c5d844SKevin Hilman dma_wmb(); 85451c5d844SKevin Hilman } 85551c5d844SKevin Hilman 856a322febeSHeiner Kallweit cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 85751c5d844SKevin Hilman } else { 8581231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 8591231e7ebSHeiner Kallweit ilog2(SD_EMMC_CMD_TIMEOUT)); 86051c5d844SKevin Hilman } 86151c5d844SKevin Hilman 86251c5d844SKevin Hilman /* Last descriptor */ 863a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_END_OF_CHAIN; 864a322febeSHeiner Kallweit writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 865a322febeSHeiner Kallweit writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 866a322febeSHeiner Kallweit writel(0, host->regs + SD_EMMC_CMD_RSP); 86751c5d844SKevin Hilman wmb(); /* ensure descriptor is written before kicked */ 868a322febeSHeiner Kallweit writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 86951c5d844SKevin Hilman } 87051c5d844SKevin Hilman 8718a38a4d5SNeil Armstrong static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data) 8728a38a4d5SNeil Armstrong { 8738a38a4d5SNeil Armstrong struct scatterlist *sg; 8748a38a4d5SNeil Armstrong int i; 8758a38a4d5SNeil Armstrong 8768a38a4d5SNeil Armstrong /* Reject request if any element offset or size is not 32bit aligned */ 8778a38a4d5SNeil Armstrong for_each_sg(data->sg, sg, data->sg_len, i) { 8788a38a4d5SNeil Armstrong if (!IS_ALIGNED(sg->offset, sizeof(u32)) || 8798a38a4d5SNeil Armstrong !IS_ALIGNED(sg->length, sizeof(u32))) { 8808a38a4d5SNeil Armstrong dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n", 8818a38a4d5SNeil Armstrong data->sg->offset, data->sg->length); 8828a38a4d5SNeil Armstrong return -EINVAL; 8838a38a4d5SNeil Armstrong } 8848a38a4d5SNeil Armstrong } 8858a38a4d5SNeil Armstrong 8868a38a4d5SNeil Armstrong return 0; 8878a38a4d5SNeil Armstrong } 8888a38a4d5SNeil Armstrong 88951c5d844SKevin Hilman static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 89051c5d844SKevin Hilman { 89151c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 892f0d2f153SRong Chen host->needs_pre_post_req = mrq->data && 89379ed05e3SHeiner Kallweit !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 89479ed05e3SHeiner Kallweit 8958a38a4d5SNeil Armstrong /* 8968a38a4d5SNeil Armstrong * The memory at the end of the controller used as bounce buffer for 8978a38a4d5SNeil Armstrong * the dram_access_quirk only accepts 32bit read/write access, 8988a38a4d5SNeil Armstrong * check the aligment and length of the data before starting the request. 8998a38a4d5SNeil Armstrong */ 9008a38a4d5SNeil Armstrong if (host->dram_access_quirk && mrq->data) { 9018a38a4d5SNeil Armstrong mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data); 9028a38a4d5SNeil Armstrong if (mrq->cmd->error) { 9038a38a4d5SNeil Armstrong mmc_request_done(mmc, mrq); 9048a38a4d5SNeil Armstrong return; 9058a38a4d5SNeil Armstrong } 9068a38a4d5SNeil Armstrong } 9078a38a4d5SNeil Armstrong 908f0d2f153SRong Chen if (host->needs_pre_post_req) { 90979ed05e3SHeiner Kallweit meson_mmc_get_transfer_mode(mmc, mrq); 91079ed05e3SHeiner Kallweit if (!meson_mmc_desc_chain_mode(mrq->data)) 911f0d2f153SRong Chen host->needs_pre_post_req = false; 91279ed05e3SHeiner Kallweit } 91379ed05e3SHeiner Kallweit 914f0d2f153SRong Chen if (host->needs_pre_post_req) 91579ed05e3SHeiner Kallweit meson_mmc_pre_req(mmc, mrq); 91651c5d844SKevin Hilman 91751c5d844SKevin Hilman /* Stop execution */ 91851c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START); 91951c5d844SKevin Hilman 92079ed05e3SHeiner Kallweit meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 92151c5d844SKevin Hilman } 92251c5d844SKevin Hilman 9233d6c991bSHeiner Kallweit static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 92451c5d844SKevin Hilman { 92551c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 92651c5d844SKevin Hilman 92751c5d844SKevin Hilman if (cmd->flags & MMC_RSP_136) { 92851c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 92951c5d844SKevin Hilman cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 93051c5d844SKevin Hilman cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 93151c5d844SKevin Hilman cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 93251c5d844SKevin Hilman } else if (cmd->flags & MMC_RSP_PRESENT) { 93351c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 93451c5d844SKevin Hilman } 93551c5d844SKevin Hilman } 93651c5d844SKevin Hilman 937066ecde6SHeiner Kallweit static void __meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 938066ecde6SHeiner Kallweit { 939066ecde6SHeiner Kallweit struct meson_host *host = mmc_priv(mmc); 940066ecde6SHeiner Kallweit u32 reg_irqen = IRQ_EN_MASK; 941066ecde6SHeiner Kallweit 942066ecde6SHeiner Kallweit if (enable) 943066ecde6SHeiner Kallweit reg_irqen |= IRQ_SDIO; 944066ecde6SHeiner Kallweit writel(reg_irqen, host->regs + SD_EMMC_IRQ_EN); 945066ecde6SHeiner Kallweit } 946066ecde6SHeiner Kallweit 94751c5d844SKevin Hilman static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 94851c5d844SKevin Hilman { 94951c5d844SKevin Hilman struct meson_host *host = dev_id; 95019a91dd4SHeinrich Schuchardt struct mmc_command *cmd; 9516f6fac8aSHeiner Kallweit u32 status, raw_status; 95274858655SJerome Brunet irqreturn_t ret = IRQ_NONE; 95351c5d844SKevin Hilman 95418f92bc0SJerome Brunet raw_status = readl(host->regs + SD_EMMC_STATUS); 955066ecde6SHeiner Kallweit status = raw_status & (IRQ_EN_MASK | IRQ_SDIO); 95618f92bc0SJerome Brunet 95718f92bc0SJerome Brunet if (!status) { 95818f92bc0SJerome Brunet dev_dbg(host->dev, 9596f6fac8aSHeiner Kallweit "Unexpected IRQ! irq_en 0x%08lx - status 0x%08x\n", 960066ecde6SHeiner Kallweit IRQ_EN_MASK | IRQ_SDIO, raw_status); 96118f92bc0SJerome Brunet return IRQ_NONE; 96218f92bc0SJerome Brunet } 96318f92bc0SJerome Brunet 964066ecde6SHeiner Kallweit if (WARN_ON(!host)) 96551c5d844SKevin Hilman return IRQ_NONE; 96651c5d844SKevin Hilman 967c2c1e63aSJerome Brunet /* ack all raised interrupts */ 968c2c1e63aSJerome Brunet writel(status, host->regs + SD_EMMC_STATUS); 969c2c1e63aSJerome Brunet 97074858655SJerome Brunet cmd = host->cmd; 971066ecde6SHeiner Kallweit 972066ecde6SHeiner Kallweit if (status & IRQ_SDIO) { 973066ecde6SHeiner Kallweit spin_lock(&host->lock); 974066ecde6SHeiner Kallweit __meson_mmc_enable_sdio_irq(host->mmc, 0); 975066ecde6SHeiner Kallweit sdio_signal_irq(host->mmc); 976066ecde6SHeiner Kallweit spin_unlock(&host->lock); 977066ecde6SHeiner Kallweit status &= ~IRQ_SDIO; 978066ecde6SHeiner Kallweit if (!status) 979066ecde6SHeiner Kallweit return IRQ_HANDLED; 980066ecde6SHeiner Kallweit } 981066ecde6SHeiner Kallweit 982066ecde6SHeiner Kallweit if (WARN_ON(!cmd)) 983066ecde6SHeiner Kallweit return IRQ_NONE; 984066ecde6SHeiner Kallweit 98574858655SJerome Brunet cmd->error = 0; 98674858655SJerome Brunet if (status & IRQ_CRC_ERR) { 98774858655SJerome Brunet dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 98874858655SJerome Brunet cmd->error = -EILSEQ; 98918f92bc0SJerome Brunet ret = IRQ_WAKE_THREAD; 99074858655SJerome Brunet goto out; 99174858655SJerome Brunet } 99274858655SJerome Brunet 99374858655SJerome Brunet if (status & IRQ_TIMEOUTS) { 99474858655SJerome Brunet dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 99574858655SJerome Brunet cmd->error = -ETIMEDOUT; 99618f92bc0SJerome Brunet ret = IRQ_WAKE_THREAD; 99751c5d844SKevin Hilman goto out; 99851c5d844SKevin Hilman } 99951c5d844SKevin Hilman 10001f8066d9SHeiner Kallweit meson_mmc_read_resp(host->mmc, cmd); 10011f8066d9SHeiner Kallweit 10022c8d96a4SHeiner Kallweit if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 1003066ecde6SHeiner Kallweit struct mmc_data *data = cmd->data; 1004066ecde6SHeiner Kallweit 10052c8d96a4SHeiner Kallweit if (data && !cmd->error) 10062c8d96a4SHeiner Kallweit data->bytes_xfered = data->blksz * data->blocks; 100779ed05e3SHeiner Kallweit if (meson_mmc_bounce_buf_read(data) || 100879ed05e3SHeiner Kallweit meson_mmc_get_next_command(cmd)) 100951c5d844SKevin Hilman ret = IRQ_WAKE_THREAD; 101074858655SJerome Brunet else 101174858655SJerome Brunet ret = IRQ_HANDLED; 101251c5d844SKevin Hilman } 101351c5d844SKevin Hilman 101451c5d844SKevin Hilman out: 101518f92bc0SJerome Brunet if (cmd->error) { 101618f92bc0SJerome Brunet /* Stop desc in case of errors */ 101718f92bc0SJerome Brunet u32 start = readl(host->regs + SD_EMMC_START); 101818f92bc0SJerome Brunet 101918f92bc0SJerome Brunet start &= ~START_DESC_BUSY; 102018f92bc0SJerome Brunet writel(start, host->regs + SD_EMMC_START); 102118f92bc0SJerome Brunet } 102218f92bc0SJerome Brunet 10231f8066d9SHeiner Kallweit if (ret == IRQ_HANDLED) 102451c5d844SKevin Hilman meson_mmc_request_done(host->mmc, cmd->mrq); 102551c5d844SKevin Hilman 102651c5d844SKevin Hilman return ret; 102751c5d844SKevin Hilman } 102851c5d844SKevin Hilman 102918f92bc0SJerome Brunet static int meson_mmc_wait_desc_stop(struct meson_host *host) 103018f92bc0SJerome Brunet { 103118f92bc0SJerome Brunet u32 status; 103218f92bc0SJerome Brunet 103318f92bc0SJerome Brunet /* 103418f92bc0SJerome Brunet * It may sometimes take a while for it to actually halt. Here, we 103518f92bc0SJerome Brunet * are giving it 5ms to comply 103618f92bc0SJerome Brunet * 103718f92bc0SJerome Brunet * If we don't confirm the descriptor is stopped, it might raise new 103818f92bc0SJerome Brunet * IRQs after we have called mmc_request_done() which is bad. 103918f92bc0SJerome Brunet */ 104018f92bc0SJerome Brunet 104198849da6SJerome Brunet return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 104298849da6SJerome Brunet !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 104398849da6SJerome Brunet 100, 5000); 104418f92bc0SJerome Brunet } 104518f92bc0SJerome Brunet 104651c5d844SKevin Hilman static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 104751c5d844SKevin Hilman { 104851c5d844SKevin Hilman struct meson_host *host = dev_id; 1049e5e4a3ebSHeiner Kallweit struct mmc_command *next_cmd, *cmd = host->cmd; 105051c5d844SKevin Hilman struct mmc_data *data; 105151c5d844SKevin Hilman unsigned int xfer_bytes; 105251c5d844SKevin Hilman 105351c5d844SKevin Hilman if (WARN_ON(!cmd)) 105419a91dd4SHeinrich Schuchardt return IRQ_NONE; 105551c5d844SKevin Hilman 105618f92bc0SJerome Brunet if (cmd->error) { 105718f92bc0SJerome Brunet meson_mmc_wait_desc_stop(host); 105818f92bc0SJerome Brunet meson_mmc_request_done(host->mmc, cmd->mrq); 105918f92bc0SJerome Brunet 106018f92bc0SJerome Brunet return IRQ_HANDLED; 106118f92bc0SJerome Brunet } 106218f92bc0SJerome Brunet 106351c5d844SKevin Hilman data = cmd->data; 106479ed05e3SHeiner Kallweit if (meson_mmc_bounce_buf_read(data)) { 106551c5d844SKevin Hilman xfer_bytes = data->blksz * data->blocks; 106651c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size); 10678a38a4d5SNeil Armstrong if (host->dram_access_quirk) 1068103a5348SNeil Armstrong meson_mmc_copy_buffer(host, data, xfer_bytes, false); 10698a38a4d5SNeil Armstrong else 10708a38a4d5SNeil Armstrong sg_copy_from_buffer(data->sg, data->sg_len, 10718a38a4d5SNeil Armstrong host->bounce_buf, xfer_bytes); 107251c5d844SKevin Hilman } 107351c5d844SKevin Hilman 1074e5e4a3ebSHeiner Kallweit next_cmd = meson_mmc_get_next_command(cmd); 1075e5e4a3ebSHeiner Kallweit if (next_cmd) 1076e5e4a3ebSHeiner Kallweit meson_mmc_start_cmd(host->mmc, next_cmd); 107751c5d844SKevin Hilman else 1078e5e4a3ebSHeiner Kallweit meson_mmc_request_done(host->mmc, cmd->mrq); 107951c5d844SKevin Hilman 1080690f90b6SHeiner Kallweit return IRQ_HANDLED; 108151c5d844SKevin Hilman } 108251c5d844SKevin Hilman 108351c5d844SKevin Hilman /* 108451c5d844SKevin Hilman * NOTE: we only need this until the GPIO/pinctrl driver can handle 108551c5d844SKevin Hilman * interrupts. For now, the MMC core will use this for polling. 108651c5d844SKevin Hilman */ 108751c5d844SKevin Hilman static int meson_mmc_get_cd(struct mmc_host *mmc) 108851c5d844SKevin Hilman { 108951c5d844SKevin Hilman int status = mmc_gpio_get_cd(mmc); 109051c5d844SKevin Hilman 109151c5d844SKevin Hilman if (status == -ENOSYS) 109251c5d844SKevin Hilman return 1; /* assume present */ 109351c5d844SKevin Hilman 109451c5d844SKevin Hilman return status; 109551c5d844SKevin Hilman } 109651c5d844SKevin Hilman 1097c01d1219SHeiner Kallweit static void meson_mmc_cfg_init(struct meson_host *host) 1098c01d1219SHeiner Kallweit { 109971e3e00cSAndreas Fenkart u32 cfg = 0; 1100c01d1219SHeiner Kallweit 11011231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 11021231e7ebSHeiner Kallweit ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 11031231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 11041231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 1105c01d1219SHeiner Kallweit 110618f92bc0SJerome Brunet /* abort chain on R/W errors */ 110718f92bc0SJerome Brunet cfg |= CFG_ERR_ABORT; 110818f92bc0SJerome Brunet 1109c01d1219SHeiner Kallweit writel(cfg, host->regs + SD_EMMC_CFG); 1110c01d1219SHeiner Kallweit } 1111c01d1219SHeiner Kallweit 1112186cd8b7SJerome Brunet static int meson_mmc_card_busy(struct mmc_host *mmc) 1113186cd8b7SJerome Brunet { 1114186cd8b7SJerome Brunet struct meson_host *host = mmc_priv(mmc); 1115186cd8b7SJerome Brunet u32 regval; 1116186cd8b7SJerome Brunet 1117186cd8b7SJerome Brunet regval = readl(host->regs + SD_EMMC_STATUS); 1118186cd8b7SJerome Brunet 1119186cd8b7SJerome Brunet /* We are only interrested in lines 0 to 3, so mask the other ones */ 1120186cd8b7SJerome Brunet return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1121186cd8b7SJerome Brunet } 1122186cd8b7SJerome Brunet 1123b1231b2fSJerome Brunet static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1124b1231b2fSJerome Brunet { 11259cbe0fc8SMarek Vasut int ret; 11269cbe0fc8SMarek Vasut 1127b1231b2fSJerome Brunet /* vqmmc regulator is available */ 1128b1231b2fSJerome Brunet if (!IS_ERR(mmc->supply.vqmmc)) { 1129b1231b2fSJerome Brunet /* 1130b1231b2fSJerome Brunet * The usual amlogic setup uses a GPIO to switch from one 1131b1231b2fSJerome Brunet * regulator to the other. While the voltage ramp up is 1132b1231b2fSJerome Brunet * pretty fast, care must be taken when switching from 3.3v 1133b1231b2fSJerome Brunet * to 1.8v. Please make sure the regulator framework is aware 1134b1231b2fSJerome Brunet * of your own regulator constraints 1135b1231b2fSJerome Brunet */ 11369cbe0fc8SMarek Vasut ret = mmc_regulator_set_vqmmc(mmc, ios); 11379cbe0fc8SMarek Vasut return ret < 0 ? ret : 0; 1138b1231b2fSJerome Brunet } 1139b1231b2fSJerome Brunet 1140b1231b2fSJerome Brunet /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1141b1231b2fSJerome Brunet if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1142b1231b2fSJerome Brunet return 0; 1143b1231b2fSJerome Brunet 1144b1231b2fSJerome Brunet return -EINVAL; 1145b1231b2fSJerome Brunet } 1146b1231b2fSJerome Brunet 1147066ecde6SHeiner Kallweit static void meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 1148066ecde6SHeiner Kallweit { 1149066ecde6SHeiner Kallweit struct meson_host *host = mmc_priv(mmc); 1150066ecde6SHeiner Kallweit unsigned long flags; 1151066ecde6SHeiner Kallweit 1152066ecde6SHeiner Kallweit spin_lock_irqsave(&host->lock, flags); 1153066ecde6SHeiner Kallweit __meson_mmc_enable_sdio_irq(mmc, enable); 1154066ecde6SHeiner Kallweit spin_unlock_irqrestore(&host->lock, flags); 1155066ecde6SHeiner Kallweit } 1156066ecde6SHeiner Kallweit 1157066ecde6SHeiner Kallweit static void meson_mmc_ack_sdio_irq(struct mmc_host *mmc) 1158066ecde6SHeiner Kallweit { 1159066ecde6SHeiner Kallweit meson_mmc_enable_sdio_irq(mmc, 1); 1160066ecde6SHeiner Kallweit } 1161066ecde6SHeiner Kallweit 116251c5d844SKevin Hilman static const struct mmc_host_ops meson_mmc_ops = { 116351c5d844SKevin Hilman .request = meson_mmc_request, 116451c5d844SKevin Hilman .set_ios = meson_mmc_set_ios, 116551c5d844SKevin Hilman .get_cd = meson_mmc_get_cd, 116679ed05e3SHeiner Kallweit .pre_req = meson_mmc_pre_req, 116779ed05e3SHeiner Kallweit .post_req = meson_mmc_post_req, 1168f50b7ac5SJerome Brunet .execute_tuning = meson_mmc_resampling_tuning, 1169186cd8b7SJerome Brunet .card_busy = meson_mmc_card_busy, 1170b1231b2fSJerome Brunet .start_signal_voltage_switch = meson_mmc_voltage_switch, 1171066ecde6SHeiner Kallweit .enable_sdio_irq = meson_mmc_enable_sdio_irq, 1172066ecde6SHeiner Kallweit .ack_sdio_irq = meson_mmc_ack_sdio_irq, 117351c5d844SKevin Hilman }; 117451c5d844SKevin Hilman 117551c5d844SKevin Hilman static int meson_mmc_probe(struct platform_device *pdev) 117651c5d844SKevin Hilman { 117751c5d844SKevin Hilman struct resource *res; 117851c5d844SKevin Hilman struct meson_host *host; 117951c5d844SKevin Hilman struct mmc_host *mmc; 1180bb364890SRemi Pommarel int ret; 118151c5d844SKevin Hilman 1182*418f7c2dSHeiner Kallweit mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct meson_host)); 118351c5d844SKevin Hilman if (!mmc) 118451c5d844SKevin Hilman return -ENOMEM; 118551c5d844SKevin Hilman host = mmc_priv(mmc); 118651c5d844SKevin Hilman host->mmc = mmc; 118751c5d844SKevin Hilman host->dev = &pdev->dev; 118851c5d844SKevin Hilman dev_set_drvdata(&pdev->dev, host); 118951c5d844SKevin Hilman 1190acdc8e71SNeil Armstrong /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1191acdc8e71SNeil Armstrong host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1192acdc8e71SNeil Armstrong "amlogic,dram-access-quirk"); 1193acdc8e71SNeil Armstrong 119451c5d844SKevin Hilman /* Get regulators and the supported OCR mask */ 119551c5d844SKevin Hilman host->vqmmc_enabled = false; 119651c5d844SKevin Hilman ret = mmc_regulator_get_supply(mmc); 1197fa54f3e3SWolfram Sang if (ret) 1198*418f7c2dSHeiner Kallweit return ret; 119951c5d844SKevin Hilman 120051c5d844SKevin Hilman ret = mmc_of_parse(mmc); 1201*418f7c2dSHeiner Kallweit if (ret) 1202*418f7c2dSHeiner Kallweit return dev_err_probe(&pdev->dev, ret, "error parsing DT\n"); 120351c5d844SKevin Hilman 1204df069815SNan Li host->data = (struct meson_mmc_data *) 1205df069815SNan Li of_device_get_match_data(&pdev->dev); 1206*418f7c2dSHeiner Kallweit if (!host->data) 1207*418f7c2dSHeiner Kallweit return -EINVAL; 1208df069815SNan Li 120919c6beaaSJerome Brunet ret = device_reset_optional(&pdev->dev); 1210*418f7c2dSHeiner Kallweit if (ret) 1211*418f7c2dSHeiner Kallweit return dev_err_probe(&pdev->dev, ret, "device reset failed\n"); 121219c6beaaSJerome Brunet 121351c5d844SKevin Hilman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 121451c5d844SKevin Hilman host->regs = devm_ioremap_resource(&pdev->dev, res); 1215*418f7c2dSHeiner Kallweit if (IS_ERR(host->regs)) 1216*418f7c2dSHeiner Kallweit return PTR_ERR(host->regs); 121751c5d844SKevin Hilman 1218bb364890SRemi Pommarel host->irq = platform_get_irq(pdev, 0); 1219*418f7c2dSHeiner Kallweit if (host->irq <= 0) 1220*418f7c2dSHeiner Kallweit return -EINVAL; 122151c5d844SKevin Hilman 12221e03331dSJerome Brunet host->pinctrl = devm_pinctrl_get(&pdev->dev); 1223*418f7c2dSHeiner Kallweit if (IS_ERR(host->pinctrl)) 1224*418f7c2dSHeiner Kallweit return PTR_ERR(host->pinctrl); 12251e03331dSJerome Brunet 12261e03331dSJerome Brunet host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 12271e03331dSJerome Brunet "clk-gate"); 12281e03331dSJerome Brunet if (IS_ERR(host->pins_clk_gate)) { 12291e03331dSJerome Brunet dev_warn(&pdev->dev, 12301e03331dSJerome Brunet "can't get clk-gate pinctrl, using clk_stop bit\n"); 12311e03331dSJerome Brunet host->pins_clk_gate = NULL; 12321e03331dSJerome Brunet } 12331e03331dSJerome Brunet 123451c5d844SKevin Hilman host->core_clk = devm_clk_get(&pdev->dev, "core"); 1235*418f7c2dSHeiner Kallweit if (IS_ERR(host->core_clk)) 1236*418f7c2dSHeiner Kallweit return PTR_ERR(host->core_clk); 123751c5d844SKevin Hilman 123851c5d844SKevin Hilman ret = clk_prepare_enable(host->core_clk); 123951c5d844SKevin Hilman if (ret) 1240*418f7c2dSHeiner Kallweit return ret; 124151c5d844SKevin Hilman 124251c5d844SKevin Hilman ret = meson_mmc_clk_init(host); 124351c5d844SKevin Hilman if (ret) 1244ce473d5bSMichał Zegan goto err_core_clk; 124551c5d844SKevin Hilman 12463c39e2caSJerome Brunet /* set config to sane default */ 12473c39e2caSJerome Brunet meson_mmc_cfg_init(host); 12483c39e2caSJerome Brunet 124951c5d844SKevin Hilman /* Stop execution */ 125051c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START); 125151c5d844SKevin Hilman 125274858655SJerome Brunet /* clear, ack and enable interrupts */ 125351c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_IRQ_EN); 12546f6fac8aSHeiner Kallweit writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); 12556f6fac8aSHeiner Kallweit writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); 125651c5d844SKevin Hilman 1257bb364890SRemi Pommarel ret = request_threaded_irq(host->irq, meson_mmc_irq, 1258eb4d8112SJerome Brunet meson_mmc_irq_thread, IRQF_ONESHOT, 125983e418a8SMartin Blumenstingl dev_name(&pdev->dev), host); 126051c5d844SKevin Hilman if (ret) 1261bd911ec4SJerome Brunet goto err_init_clk; 126251c5d844SKevin Hilman 1263066ecde6SHeiner Kallweit spin_lock_init(&host->lock); 1264066ecde6SHeiner Kallweit 1265e5e4a3ebSHeiner Kallweit mmc->caps |= MMC_CAP_CMD23; 1266066ecde6SHeiner Kallweit 1267066ecde6SHeiner Kallweit if (mmc->caps & MMC_CAP_SDIO_IRQ) 1268066ecde6SHeiner Kallweit mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 1269066ecde6SHeiner Kallweit 1270acdc8e71SNeil Armstrong if (host->dram_access_quirk) { 127127a5e7d3SNeil Armstrong /* Limit segments to 1 due to low available sram memory */ 127227a5e7d3SNeil Armstrong mmc->max_segs = 1; 1273acdc8e71SNeil Armstrong /* Limit to the available sram memory */ 127427a5e7d3SNeil Armstrong mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 127527a5e7d3SNeil Armstrong mmc->max_blk_size; 1276acdc8e71SNeil Armstrong } else { 1277efe0b669SHeiner Kallweit mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1278acdc8e71SNeil Armstrong mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1279acdc8e71SNeil Armstrong sizeof(struct sd_emmc_desc); 1280acdc8e71SNeil Armstrong } 1281efe0b669SHeiner Kallweit mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 128279ed05e3SHeiner Kallweit mmc->max_seg_size = mmc->max_req_size; 1283efe0b669SHeiner Kallweit 1284d5f758f2SJerome Brunet /* 1285d5f758f2SJerome Brunet * At the moment, we don't know how to reliably enable HS400. 1286d5f758f2SJerome Brunet * From the different datasheets, it is not even clear if this mode 1287d5f758f2SJerome Brunet * is officially supported by any of the SoCs 1288d5f758f2SJerome Brunet */ 1289d5f758f2SJerome Brunet mmc->caps2 &= ~MMC_CAP2_HS400; 1290d5f758f2SJerome Brunet 1291acdc8e71SNeil Armstrong if (host->dram_access_quirk) { 1292acdc8e71SNeil Armstrong /* 1293acdc8e71SNeil Armstrong * The MMC Controller embeds 1,5KiB of internal SRAM 1294acdc8e71SNeil Armstrong * that can be used to be used as bounce buffer. 1295acdc8e71SNeil Armstrong * In the case of the G12A SDIO controller, use these 1296acdc8e71SNeil Armstrong * instead of the DDR memory 1297acdc8e71SNeil Armstrong */ 1298acdc8e71SNeil Armstrong host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1299103a5348SNeil Armstrong host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1300acdc8e71SNeil Armstrong host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1301acdc8e71SNeil Armstrong } else { 130251c5d844SKevin Hilman /* data bounce buffer */ 13034136fcb5SHeiner Kallweit host->bounce_buf_size = mmc->max_req_size; 130451c5d844SKevin Hilman host->bounce_buf = 1305238b638bSHeiner Kallweit dmam_alloc_coherent(host->dev, host->bounce_buf_size, 130651c5d844SKevin Hilman &host->bounce_dma_addr, GFP_KERNEL); 130751c5d844SKevin Hilman if (host->bounce_buf == NULL) { 130851c5d844SKevin Hilman dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 130951c5d844SKevin Hilman ret = -ENOMEM; 1310bb364890SRemi Pommarel goto err_free_irq; 131151c5d844SKevin Hilman } 1312acdc8e71SNeil Armstrong } 131351c5d844SKevin Hilman 1314238b638bSHeiner Kallweit host->descs = dmam_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 131579ed05e3SHeiner Kallweit &host->descs_dma_addr, GFP_KERNEL); 131679ed05e3SHeiner Kallweit if (!host->descs) { 131779ed05e3SHeiner Kallweit dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 131879ed05e3SHeiner Kallweit ret = -ENOMEM; 1319238b638bSHeiner Kallweit goto err_free_irq; 132079ed05e3SHeiner Kallweit } 132179ed05e3SHeiner Kallweit 132251c5d844SKevin Hilman mmc->ops = &meson_mmc_ops; 132390935f16SYang Yingliang ret = mmc_add_host(mmc); 132490935f16SYang Yingliang if (ret) 132590935f16SYang Yingliang goto err_free_irq; 132651c5d844SKevin Hilman 132751c5d844SKevin Hilman return 0; 132851c5d844SKevin Hilman 1329bb364890SRemi Pommarel err_free_irq: 1330bb364890SRemi Pommarel free_irq(host->irq, host); 1331bd911ec4SJerome Brunet err_init_clk: 1332bd911ec4SJerome Brunet clk_disable_unprepare(host->mmc_clk); 1333ce473d5bSMichał Zegan err_core_clk: 133451c5d844SKevin Hilman clk_disable_unprepare(host->core_clk); 133551c5d844SKevin Hilman return ret; 133651c5d844SKevin Hilman } 133751c5d844SKevin Hilman 133851c5d844SKevin Hilman static int meson_mmc_remove(struct platform_device *pdev) 133951c5d844SKevin Hilman { 134051c5d844SKevin Hilman struct meson_host *host = dev_get_drvdata(&pdev->dev); 134151c5d844SKevin Hilman 1342a01fc2a2SMichał Zegan mmc_remove_host(host->mmc); 1343a01fc2a2SMichał Zegan 134492763b99SHeiner Kallweit /* disable interrupts */ 134592763b99SHeiner Kallweit writel(0, host->regs + SD_EMMC_IRQ_EN); 1346bb364890SRemi Pommarel free_irq(host->irq, host); 134792763b99SHeiner Kallweit 1348bd911ec4SJerome Brunet clk_disable_unprepare(host->mmc_clk); 134951c5d844SKevin Hilman clk_disable_unprepare(host->core_clk); 135051c5d844SKevin Hilman 135151c5d844SKevin Hilman return 0; 135251c5d844SKevin Hilman } 135351c5d844SKevin Hilman 1354df069815SNan Li static const struct meson_mmc_data meson_gx_data = { 1355df069815SNan Li .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1356df069815SNan Li .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1357df069815SNan Li .always_on = CLK_V2_ALWAYS_ON, 135871645e65SJerome Brunet .adjust = SD_EMMC_ADJUST, 1359066ecde6SHeiner Kallweit .irq_sdio_sleep = CLK_V2_IRQ_SDIO_SLEEP, 1360df069815SNan Li }; 1361df069815SNan Li 1362df069815SNan Li static const struct meson_mmc_data meson_axg_data = { 1363df069815SNan Li .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1364df069815SNan Li .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1365df069815SNan Li .always_on = CLK_V3_ALWAYS_ON, 136671645e65SJerome Brunet .adjust = SD_EMMC_V3_ADJUST, 1367066ecde6SHeiner Kallweit .irq_sdio_sleep = CLK_V3_IRQ_SDIO_SLEEP, 1368df069815SNan Li }; 1369df069815SNan Li 137051c5d844SKevin Hilman static const struct of_device_id meson_mmc_of_match[] = { 1371df069815SNan Li { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1372df069815SNan Li { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1373df069815SNan Li { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1374df069815SNan Li { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1375df069815SNan Li { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 137651c5d844SKevin Hilman {} 137751c5d844SKevin Hilman }; 137851c5d844SKevin Hilman MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 137951c5d844SKevin Hilman 138051c5d844SKevin Hilman static struct platform_driver meson_mmc_driver = { 138151c5d844SKevin Hilman .probe = meson_mmc_probe, 138251c5d844SKevin Hilman .remove = meson_mmc_remove, 138351c5d844SKevin Hilman .driver = { 138451c5d844SKevin Hilman .name = DRIVER_NAME, 13857320915cSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1386e2c01e91SKrzysztof Kozlowski .of_match_table = meson_mmc_of_match, 138751c5d844SKevin Hilman }, 138851c5d844SKevin Hilman }; 138951c5d844SKevin Hilman 139051c5d844SKevin Hilman module_platform_driver(meson_mmc_driver); 139151c5d844SKevin Hilman 1392e79dc1b4SNan Li MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 139351c5d844SKevin Hilman MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 139451c5d844SKevin Hilman MODULE_LICENSE("GPL v2"); 1395