151c5d844SKevin Hilman /* 251c5d844SKevin Hilman * Amlogic SD/eMMC driver for the GX/S905 family SoCs 351c5d844SKevin Hilman * 451c5d844SKevin Hilman * Copyright (c) 2016 BayLibre, SAS. 551c5d844SKevin Hilman * Author: Kevin Hilman <khilman@baylibre.com> 651c5d844SKevin Hilman * 751c5d844SKevin Hilman * This program is free software; you can redistribute it and/or modify 851c5d844SKevin Hilman * it under the terms of version 2 of the GNU General Public License as 951c5d844SKevin Hilman * published by the Free Software Foundation. 1051c5d844SKevin Hilman * 1151c5d844SKevin Hilman * This program is distributed in the hope that it will be useful, but 1251c5d844SKevin Hilman * WITHOUT ANY WARRANTY; without even the implied warranty of 1351c5d844SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1451c5d844SKevin Hilman * General Public License for more details. 1551c5d844SKevin Hilman * 1651c5d844SKevin Hilman * You should have received a copy of the GNU General Public License 1751c5d844SKevin Hilman * along with this program; if not, see <http://www.gnu.org/licenses/>. 1851c5d844SKevin Hilman * The full GNU General Public License is included in this distribution 1951c5d844SKevin Hilman * in the file called COPYING. 2051c5d844SKevin Hilman */ 2151c5d844SKevin Hilman #include <linux/kernel.h> 2251c5d844SKevin Hilman #include <linux/module.h> 2351c5d844SKevin Hilman #include <linux/init.h> 2451c5d844SKevin Hilman #include <linux/device.h> 2551c5d844SKevin Hilman #include <linux/of_device.h> 2651c5d844SKevin Hilman #include <linux/platform_device.h> 2751c5d844SKevin Hilman #include <linux/ioport.h> 2851c5d844SKevin Hilman #include <linux/spinlock.h> 2951c5d844SKevin Hilman #include <linux/dma-mapping.h> 3051c5d844SKevin Hilman #include <linux/mmc/host.h> 3151c5d844SKevin Hilman #include <linux/mmc/mmc.h> 3251c5d844SKevin Hilman #include <linux/mmc/sdio.h> 3351c5d844SKevin Hilman #include <linux/mmc/slot-gpio.h> 3451c5d844SKevin Hilman #include <linux/io.h> 3551c5d844SKevin Hilman #include <linux/clk.h> 3651c5d844SKevin Hilman #include <linux/clk-provider.h> 3751c5d844SKevin Hilman #include <linux/regulator/consumer.h> 38b8789ec4SUlf Hansson #include <linux/interrupt.h> 391231e7ebSHeiner Kallweit #include <linux/bitfield.h> 4051c5d844SKevin Hilman 4151c5d844SKevin Hilman #define DRIVER_NAME "meson-gx-mmc" 4251c5d844SKevin Hilman 4351c5d844SKevin Hilman #define SD_EMMC_CLOCK 0x0 441231e7ebSHeiner Kallweit #define CLK_DIV_MASK GENMASK(5, 0) 4551c5d844SKevin Hilman #define CLK_DIV_MAX 63 461231e7ebSHeiner Kallweit #define CLK_SRC_MASK GENMASK(7, 6) 4751c5d844SKevin Hilman #define CLK_SRC_XTAL 0 /* external crystal */ 4851c5d844SKevin Hilman #define CLK_SRC_XTAL_RATE 24000000 4951c5d844SKevin Hilman #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ 5051c5d844SKevin Hilman #define CLK_SRC_PLL_RATE 1000000000 511231e7ebSHeiner Kallweit #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 5251c5d844SKevin Hilman #define CLK_PHASE_0 0 5351c5d844SKevin Hilman #define CLK_PHASE_90 1 5451c5d844SKevin Hilman #define CLK_PHASE_180 2 5551c5d844SKevin Hilman #define CLK_PHASE_270 3 5651c5d844SKevin Hilman #define CLK_ALWAYS_ON BIT(24) 5751c5d844SKevin Hilman 5851c5d844SKevin Hilman #define SD_EMMC_DElAY 0x4 5951c5d844SKevin Hilman #define SD_EMMC_ADJUST 0x8 6051c5d844SKevin Hilman #define SD_EMMC_CALOUT 0x10 6151c5d844SKevin Hilman #define SD_EMMC_START 0x40 6251c5d844SKevin Hilman #define START_DESC_INIT BIT(0) 6351c5d844SKevin Hilman #define START_DESC_BUSY BIT(1) 641231e7ebSHeiner Kallweit #define START_DESC_ADDR_MASK GENMASK(31, 2) 6551c5d844SKevin Hilman 6651c5d844SKevin Hilman #define SD_EMMC_CFG 0x44 671231e7ebSHeiner Kallweit #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 6851c5d844SKevin Hilman #define CFG_BUS_WIDTH_1 0x0 6951c5d844SKevin Hilman #define CFG_BUS_WIDTH_4 0x1 7051c5d844SKevin Hilman #define CFG_BUS_WIDTH_8 0x2 7151c5d844SKevin Hilman #define CFG_DDR BIT(2) 721231e7ebSHeiner Kallweit #define CFG_BLK_LEN_MASK GENMASK(7, 4) 731231e7ebSHeiner Kallweit #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 741231e7ebSHeiner Kallweit #define CFG_RC_CC_MASK GENMASK(15, 12) 7551c5d844SKevin Hilman #define CFG_STOP_CLOCK BIT(22) 7651c5d844SKevin Hilman #define CFG_CLK_ALWAYS_ON BIT(18) 77e21e6fddSHeiner Kallweit #define CFG_CHK_DS BIT(20) 7851c5d844SKevin Hilman #define CFG_AUTO_CLK BIT(23) 7951c5d844SKevin Hilman 8051c5d844SKevin Hilman #define SD_EMMC_STATUS 0x48 8151c5d844SKevin Hilman #define STATUS_BUSY BIT(31) 8251c5d844SKevin Hilman 8351c5d844SKevin Hilman #define SD_EMMC_IRQ_EN 0x4c 841231e7ebSHeiner Kallweit #define IRQ_EN_MASK GENMASK(13, 0) 851231e7ebSHeiner Kallweit #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 8651c5d844SKevin Hilman #define IRQ_TXD_ERR BIT(8) 8751c5d844SKevin Hilman #define IRQ_DESC_ERR BIT(9) 8851c5d844SKevin Hilman #define IRQ_RESP_ERR BIT(10) 8951c5d844SKevin Hilman #define IRQ_RESP_TIMEOUT BIT(11) 9051c5d844SKevin Hilman #define IRQ_DESC_TIMEOUT BIT(12) 9151c5d844SKevin Hilman #define IRQ_END_OF_CHAIN BIT(13) 9251c5d844SKevin Hilman #define IRQ_RESP_STATUS BIT(14) 9351c5d844SKevin Hilman #define IRQ_SDIO BIT(15) 9451c5d844SKevin Hilman 9551c5d844SKevin Hilman #define SD_EMMC_CMD_CFG 0x50 9651c5d844SKevin Hilman #define SD_EMMC_CMD_ARG 0x54 9751c5d844SKevin Hilman #define SD_EMMC_CMD_DAT 0x58 9851c5d844SKevin Hilman #define SD_EMMC_CMD_RSP 0x5c 9951c5d844SKevin Hilman #define SD_EMMC_CMD_RSP1 0x60 10051c5d844SKevin Hilman #define SD_EMMC_CMD_RSP2 0x64 10151c5d844SKevin Hilman #define SD_EMMC_CMD_RSP3 0x68 10251c5d844SKevin Hilman 10351c5d844SKevin Hilman #define SD_EMMC_RXD 0x94 10451c5d844SKevin Hilman #define SD_EMMC_TXD 0x94 10551c5d844SKevin Hilman #define SD_EMMC_LAST_REG SD_EMMC_TXD 10651c5d844SKevin Hilman 10751c5d844SKevin Hilman #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 10851c5d844SKevin Hilman #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 109bb11eff1SHeiner Kallweit #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 110bb11eff1SHeiner Kallweit #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 11151c5d844SKevin Hilman #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 11251c5d844SKevin Hilman #define MUX_CLK_NUM_PARENTS 2 11351c5d844SKevin Hilman 11451c5d844SKevin Hilman struct meson_host { 11551c5d844SKevin Hilman struct device *dev; 11651c5d844SKevin Hilman struct mmc_host *mmc; 11751c5d844SKevin Hilman struct mmc_command *cmd; 11851c5d844SKevin Hilman 11951c5d844SKevin Hilman spinlock_t lock; 12051c5d844SKevin Hilman void __iomem *regs; 12151c5d844SKevin Hilman struct clk *core_clk; 12251c5d844SKevin Hilman struct clk_mux mux; 12351c5d844SKevin Hilman struct clk *mux_clk; 1245da86887SHeiner Kallweit unsigned long current_clock; 12551c5d844SKevin Hilman 12651c5d844SKevin Hilman struct clk_divider cfg_div; 12751c5d844SKevin Hilman struct clk *cfg_div_clk; 12851c5d844SKevin Hilman 12951c5d844SKevin Hilman unsigned int bounce_buf_size; 13051c5d844SKevin Hilman void *bounce_buf; 13151c5d844SKevin Hilman dma_addr_t bounce_dma_addr; 13251c5d844SKevin Hilman 13351c5d844SKevin Hilman bool vqmmc_enabled; 13451c5d844SKevin Hilman }; 13551c5d844SKevin Hilman 13651c5d844SKevin Hilman struct sd_emmc_desc { 13751c5d844SKevin Hilman u32 cmd_cfg; 13851c5d844SKevin Hilman u32 cmd_arg; 13951c5d844SKevin Hilman u32 cmd_data; 14051c5d844SKevin Hilman u32 cmd_resp; 14151c5d844SKevin Hilman }; 1421231e7ebSHeiner Kallweit 1431231e7ebSHeiner Kallweit #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 14451c5d844SKevin Hilman #define CMD_CFG_BLOCK_MODE BIT(9) 14551c5d844SKevin Hilman #define CMD_CFG_R1B BIT(10) 14651c5d844SKevin Hilman #define CMD_CFG_END_OF_CHAIN BIT(11) 1471231e7ebSHeiner Kallweit #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 14851c5d844SKevin Hilman #define CMD_CFG_NO_RESP BIT(16) 14951c5d844SKevin Hilman #define CMD_CFG_NO_CMD BIT(17) 15051c5d844SKevin Hilman #define CMD_CFG_DATA_IO BIT(18) 15151c5d844SKevin Hilman #define CMD_CFG_DATA_WR BIT(19) 15251c5d844SKevin Hilman #define CMD_CFG_RESP_NOCRC BIT(20) 15351c5d844SKevin Hilman #define CMD_CFG_RESP_128 BIT(21) 15451c5d844SKevin Hilman #define CMD_CFG_RESP_NUM BIT(22) 15551c5d844SKevin Hilman #define CMD_CFG_DATA_NUM BIT(23) 1561231e7ebSHeiner Kallweit #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 15751c5d844SKevin Hilman #define CMD_CFG_ERROR BIT(30) 15851c5d844SKevin Hilman #define CMD_CFG_OWNER BIT(31) 15951c5d844SKevin Hilman 1601231e7ebSHeiner Kallweit #define CMD_DATA_MASK GENMASK(31, 2) 16151c5d844SKevin Hilman #define CMD_DATA_BIG_ENDIAN BIT(1) 16251c5d844SKevin Hilman #define CMD_DATA_SRAM BIT(0) 1631231e7ebSHeiner Kallweit #define CMD_RESP_MASK GENMASK(31, 1) 16451c5d844SKevin Hilman #define CMD_RESP_SRAM BIT(0) 16551c5d844SKevin Hilman 16651c5d844SKevin Hilman static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) 16751c5d844SKevin Hilman { 16851c5d844SKevin Hilman struct mmc_host *mmc = host->mmc; 1695da86887SHeiner Kallweit int ret; 17051c5d844SKevin Hilman u32 cfg; 17151c5d844SKevin Hilman 17251c5d844SKevin Hilman if (clk_rate) { 17351c5d844SKevin Hilman if (WARN_ON(clk_rate > mmc->f_max)) 17451c5d844SKevin Hilman clk_rate = mmc->f_max; 17551c5d844SKevin Hilman else if (WARN_ON(clk_rate < mmc->f_min)) 17651c5d844SKevin Hilman clk_rate = mmc->f_min; 17751c5d844SKevin Hilman } 17851c5d844SKevin Hilman 1795da86887SHeiner Kallweit if (clk_rate == host->current_clock) 18051c5d844SKevin Hilman return 0; 18151c5d844SKevin Hilman 18251c5d844SKevin Hilman /* stop clock */ 18351c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 18451c5d844SKevin Hilman if (!(cfg & CFG_STOP_CLOCK)) { 18551c5d844SKevin Hilman cfg |= CFG_STOP_CLOCK; 18651c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 18751c5d844SKevin Hilman } 18851c5d844SKevin Hilman 18951c5d844SKevin Hilman dev_dbg(host->dev, "change clock rate %u -> %lu\n", 19051c5d844SKevin Hilman mmc->actual_clock, clk_rate); 19151c5d844SKevin Hilman 1925da86887SHeiner Kallweit if (!clk_rate) { 19351c5d844SKevin Hilman mmc->actual_clock = 0; 1945da86887SHeiner Kallweit host->current_clock = 0; 1955da86887SHeiner Kallweit /* return with clock being stopped */ 19651c5d844SKevin Hilman return 0; 19751c5d844SKevin Hilman } 19851c5d844SKevin Hilman 19951c5d844SKevin Hilman ret = clk_set_rate(host->cfg_div_clk, clk_rate); 2005da86887SHeiner Kallweit if (ret) { 2015da86887SHeiner Kallweit dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 20251c5d844SKevin Hilman clk_rate, ret); 2035da86887SHeiner Kallweit return ret; 2045da86887SHeiner Kallweit } 20551c5d844SKevin Hilman 2065da86887SHeiner Kallweit mmc->actual_clock = clk_get_rate(host->cfg_div_clk); 2075da86887SHeiner Kallweit host->current_clock = clk_rate; 2085da86887SHeiner Kallweit 2095da86887SHeiner Kallweit if (clk_rate != mmc->actual_clock) 2105da86887SHeiner Kallweit dev_dbg(host->dev, 2115da86887SHeiner Kallweit "divider requested rate %lu != actual rate %u\n", 2125da86887SHeiner Kallweit clk_rate, mmc->actual_clock); 2135da86887SHeiner Kallweit 2145da86887SHeiner Kallweit /* (re)start clock */ 21551c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 21651c5d844SKevin Hilman cfg &= ~CFG_STOP_CLOCK; 21751c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 21851c5d844SKevin Hilman 2195da86887SHeiner Kallweit return 0; 22051c5d844SKevin Hilman } 22151c5d844SKevin Hilman 22251c5d844SKevin Hilman /* 22351c5d844SKevin Hilman * The SD/eMMC IP block has an internal mux and divider used for 22451c5d844SKevin Hilman * generating the MMC clock. Use the clock framework to create and 22551c5d844SKevin Hilman * manage these clocks. 22651c5d844SKevin Hilman */ 22751c5d844SKevin Hilman static int meson_mmc_clk_init(struct meson_host *host) 22851c5d844SKevin Hilman { 22951c5d844SKevin Hilman struct clk_init_data init; 23051c5d844SKevin Hilman char clk_name[32]; 23151c5d844SKevin Hilman int i, ret = 0; 23251c5d844SKevin Hilman const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 23351c5d844SKevin Hilman const char *clk_div_parents[1]; 23451c5d844SKevin Hilman u32 clk_reg, cfg; 23551c5d844SKevin Hilman 23651c5d844SKevin Hilman /* get the mux parents */ 23751c5d844SKevin Hilman for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 238e9883ef2SHeiner Kallweit struct clk *clk; 23951c5d844SKevin Hilman char name[16]; 24051c5d844SKevin Hilman 24151c5d844SKevin Hilman snprintf(name, sizeof(name), "clkin%d", i); 242e9883ef2SHeiner Kallweit clk = devm_clk_get(host->dev, name); 243e9883ef2SHeiner Kallweit if (IS_ERR(clk)) { 244e9883ef2SHeiner Kallweit if (clk != ERR_PTR(-EPROBE_DEFER)) 24551c5d844SKevin Hilman dev_err(host->dev, "Missing clock %s\n", name); 246e9883ef2SHeiner Kallweit return PTR_ERR(clk); 24751c5d844SKevin Hilman } 24851c5d844SKevin Hilman 249e9883ef2SHeiner Kallweit mux_parent_names[i] = __clk_get_name(clk); 25051c5d844SKevin Hilman } 25151c5d844SKevin Hilman 25251c5d844SKevin Hilman /* create the mux */ 25351c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 25451c5d844SKevin Hilman init.name = clk_name; 25551c5d844SKevin Hilman init.ops = &clk_mux_ops; 25651c5d844SKevin Hilman init.flags = 0; 25751c5d844SKevin Hilman init.parent_names = mux_parent_names; 2587558c113SHeiner Kallweit init.num_parents = MUX_CLK_NUM_PARENTS; 25951c5d844SKevin Hilman host->mux.reg = host->regs + SD_EMMC_CLOCK; 2601231e7ebSHeiner Kallweit host->mux.shift = __bf_shf(CLK_SRC_MASK); 26151c5d844SKevin Hilman host->mux.mask = CLK_SRC_MASK; 26251c5d844SKevin Hilman host->mux.flags = 0; 26351c5d844SKevin Hilman host->mux.table = NULL; 26451c5d844SKevin Hilman host->mux.hw.init = &init; 26551c5d844SKevin Hilman 26651c5d844SKevin Hilman host->mux_clk = devm_clk_register(host->dev, &host->mux.hw); 26751c5d844SKevin Hilman if (WARN_ON(IS_ERR(host->mux_clk))) 26851c5d844SKevin Hilman return PTR_ERR(host->mux_clk); 26951c5d844SKevin Hilman 27051c5d844SKevin Hilman /* create the divider */ 27151c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 2727b9ebad3SHeiner Kallweit init.name = clk_name; 27351c5d844SKevin Hilman init.ops = &clk_divider_ops; 27451c5d844SKevin Hilman init.flags = CLK_SET_RATE_PARENT; 27551c5d844SKevin Hilman clk_div_parents[0] = __clk_get_name(host->mux_clk); 27651c5d844SKevin Hilman init.parent_names = clk_div_parents; 27751c5d844SKevin Hilman init.num_parents = ARRAY_SIZE(clk_div_parents); 27851c5d844SKevin Hilman 27951c5d844SKevin Hilman host->cfg_div.reg = host->regs + SD_EMMC_CLOCK; 2801231e7ebSHeiner Kallweit host->cfg_div.shift = __bf_shf(CLK_DIV_MASK); 2811231e7ebSHeiner Kallweit host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK); 28251c5d844SKevin Hilman host->cfg_div.hw.init = &init; 28351c5d844SKevin Hilman host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | 28451c5d844SKevin Hilman CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO; 28551c5d844SKevin Hilman 28651c5d844SKevin Hilman host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); 28751c5d844SKevin Hilman if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) 28851c5d844SKevin Hilman return PTR_ERR(host->cfg_div_clk); 28951c5d844SKevin Hilman 29051c5d844SKevin Hilman /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 29151c5d844SKevin Hilman clk_reg = 0; 2921231e7ebSHeiner Kallweit clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 2931231e7ebSHeiner Kallweit clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); 2941231e7ebSHeiner Kallweit clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); 29551c5d844SKevin Hilman clk_reg &= ~CLK_ALWAYS_ON; 29651c5d844SKevin Hilman writel(clk_reg, host->regs + SD_EMMC_CLOCK); 29751c5d844SKevin Hilman 29851c5d844SKevin Hilman /* Ensure clock starts in "auto" mode, not "always on" */ 29951c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 30051c5d844SKevin Hilman cfg &= ~CFG_CLK_ALWAYS_ON; 30151c5d844SKevin Hilman cfg |= CFG_AUTO_CLK; 30251c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 30351c5d844SKevin Hilman 30451c5d844SKevin Hilman ret = clk_prepare_enable(host->cfg_div_clk); 305a4c38c8dSUlf Hansson if (ret) 306a4c38c8dSUlf Hansson return ret; 30751c5d844SKevin Hilman 308a4c38c8dSUlf Hansson /* Get the nearest minimum clock to 400KHz */ 309a4c38c8dSUlf Hansson host->mmc->f_min = clk_round_rate(host->cfg_div_clk, 400000); 310a4c38c8dSUlf Hansson 311a4c38c8dSUlf Hansson ret = meson_mmc_clk_set(host, host->mmc->f_min); 312cac3a478SHeiner Kallweit if (ret) 31351c5d844SKevin Hilman clk_disable_unprepare(host->cfg_div_clk); 31451c5d844SKevin Hilman 31551c5d844SKevin Hilman return ret; 31651c5d844SKevin Hilman } 31751c5d844SKevin Hilman 31851c5d844SKevin Hilman static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 31951c5d844SKevin Hilman { 32051c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 32151c5d844SKevin Hilman u32 bus_width; 32251c5d844SKevin Hilman u32 val, orig; 32351c5d844SKevin Hilman 32451c5d844SKevin Hilman /* 32551c5d844SKevin Hilman * GPIO regulator, only controls switching between 1v8 and 32651c5d844SKevin Hilman * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 32751c5d844SKevin Hilman */ 32851c5d844SKevin Hilman switch (ios->power_mode) { 32951c5d844SKevin Hilman case MMC_POWER_OFF: 33051c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vmmc)) 33151c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 33251c5d844SKevin Hilman 33351c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 33451c5d844SKevin Hilman regulator_disable(mmc->supply.vqmmc); 33551c5d844SKevin Hilman host->vqmmc_enabled = false; 33651c5d844SKevin Hilman } 33751c5d844SKevin Hilman 33851c5d844SKevin Hilman break; 33951c5d844SKevin Hilman 34051c5d844SKevin Hilman case MMC_POWER_UP: 34151c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vmmc)) 34251c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 34351c5d844SKevin Hilman break; 34451c5d844SKevin Hilman 34551c5d844SKevin Hilman case MMC_POWER_ON: 34651c5d844SKevin Hilman if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 34751c5d844SKevin Hilman int ret = regulator_enable(mmc->supply.vqmmc); 34851c5d844SKevin Hilman 34951c5d844SKevin Hilman if (ret < 0) 35051c5d844SKevin Hilman dev_err(mmc_dev(mmc), 35151c5d844SKevin Hilman "failed to enable vqmmc regulator\n"); 35251c5d844SKevin Hilman else 35351c5d844SKevin Hilman host->vqmmc_enabled = true; 35451c5d844SKevin Hilman } 35551c5d844SKevin Hilman 35651c5d844SKevin Hilman break; 35751c5d844SKevin Hilman } 35851c5d844SKevin Hilman 35951c5d844SKevin Hilman 36051c5d844SKevin Hilman meson_mmc_clk_set(host, ios->clock); 36151c5d844SKevin Hilman 36251c5d844SKevin Hilman /* Bus width */ 36351c5d844SKevin Hilman switch (ios->bus_width) { 36451c5d844SKevin Hilman case MMC_BUS_WIDTH_1: 36551c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_1; 36651c5d844SKevin Hilman break; 36751c5d844SKevin Hilman case MMC_BUS_WIDTH_4: 36851c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4; 36951c5d844SKevin Hilman break; 37051c5d844SKevin Hilman case MMC_BUS_WIDTH_8: 37151c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_8; 37251c5d844SKevin Hilman break; 37351c5d844SKevin Hilman default: 37451c5d844SKevin Hilman dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 37551c5d844SKevin Hilman ios->bus_width); 37651c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4; 37751c5d844SKevin Hilman } 37851c5d844SKevin Hilman 37951c5d844SKevin Hilman val = readl(host->regs + SD_EMMC_CFG); 38051c5d844SKevin Hilman orig = val; 38151c5d844SKevin Hilman 3821231e7ebSHeiner Kallweit val &= ~CFG_BUS_WIDTH_MASK; 3831231e7ebSHeiner Kallweit val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 38451c5d844SKevin Hilman 385e21e6fddSHeiner Kallweit val &= ~CFG_DDR; 386e21e6fddSHeiner Kallweit if (ios->timing == MMC_TIMING_UHS_DDR50 || 387e21e6fddSHeiner Kallweit ios->timing == MMC_TIMING_MMC_DDR52 || 388e21e6fddSHeiner Kallweit ios->timing == MMC_TIMING_MMC_HS400) 389e21e6fddSHeiner Kallweit val |= CFG_DDR; 390e21e6fddSHeiner Kallweit 391e21e6fddSHeiner Kallweit val &= ~CFG_CHK_DS; 392e21e6fddSHeiner Kallweit if (ios->timing == MMC_TIMING_MMC_HS400) 393e21e6fddSHeiner Kallweit val |= CFG_CHK_DS; 394e21e6fddSHeiner Kallweit 395c01d1219SHeiner Kallweit if (val != orig) { 39651c5d844SKevin Hilman writel(val, host->regs + SD_EMMC_CFG); 39751c5d844SKevin Hilman dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n", 39851c5d844SKevin Hilman __func__, orig, val); 39951c5d844SKevin Hilman } 400c01d1219SHeiner Kallweit } 40151c5d844SKevin Hilman 4023d6c991bSHeiner Kallweit static void meson_mmc_request_done(struct mmc_host *mmc, 4033d6c991bSHeiner Kallweit struct mmc_request *mrq) 40451c5d844SKevin Hilman { 40551c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 40651c5d844SKevin Hilman 40751c5d844SKevin Hilman host->cmd = NULL; 40851c5d844SKevin Hilman mmc_request_done(host->mmc, mrq); 40951c5d844SKevin Hilman } 41051c5d844SKevin Hilman 41151c5d844SKevin Hilman static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 41251c5d844SKevin Hilman { 41351c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 41400412ddcSHeiner Kallweit struct mmc_data *data = cmd->data; 415a322febeSHeiner Kallweit u32 cfg, cmd_cfg = 0, cmd_data = 0; 416a744c6feSHeiner Kallweit u8 blk_len; 41751c5d844SKevin Hilman unsigned int xfer_bytes = 0; 41851c5d844SKevin Hilman 41951c5d844SKevin Hilman /* Setup descriptors */ 42051c5d844SKevin Hilman dma_rmb(); 42151c5d844SKevin Hilman 4221231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 423a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 42451c5d844SKevin Hilman 42551c5d844SKevin Hilman /* Response */ 42651c5d844SKevin Hilman if (cmd->flags & MMC_RSP_PRESENT) { 42751c5d844SKevin Hilman if (cmd->flags & MMC_RSP_136) 428a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_RESP_128; 429a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_RESP_NUM; 43051c5d844SKevin Hilman 43151c5d844SKevin Hilman if (!(cmd->flags & MMC_RSP_CRC)) 432a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_RESP_NOCRC; 43351c5d844SKevin Hilman 43451c5d844SKevin Hilman if (cmd->flags & MMC_RSP_BUSY) 435a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_R1B; 43651c5d844SKevin Hilman } else { 437a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_NO_RESP; 43851c5d844SKevin Hilman } 43951c5d844SKevin Hilman 44051c5d844SKevin Hilman /* data? */ 44100412ddcSHeiner Kallweit if (data) { 442a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_IO; 4431231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 4441231e7ebSHeiner Kallweit ilog2(SD_EMMC_CMD_TIMEOUT_DATA)); 445a744c6feSHeiner Kallweit 44600412ddcSHeiner Kallweit if (data->blocks > 1) { 447a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_BLOCK_MODE; 4481231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 4491231e7ebSHeiner Kallweit data->blocks); 45051c5d844SKevin Hilman 45151c5d844SKevin Hilman /* check if block-size matches, if not update */ 45251c5d844SKevin Hilman cfg = readl(host->regs + SD_EMMC_CFG); 4531231e7ebSHeiner Kallweit blk_len = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 45400412ddcSHeiner Kallweit if (blk_len != ilog2(data->blksz)) { 455dc012058SKevin Hilman dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", 45651c5d844SKevin Hilman __func__, blk_len, 45700412ddcSHeiner Kallweit ilog2(data->blksz)); 45800412ddcSHeiner Kallweit blk_len = ilog2(data->blksz); 4591231e7ebSHeiner Kallweit cfg &= ~CFG_BLK_LEN_MASK; 4601231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blk_len); 46151c5d844SKevin Hilman writel(cfg, host->regs + SD_EMMC_CFG); 46251c5d844SKevin Hilman } 46351c5d844SKevin Hilman } else { 4641231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 46551c5d844SKevin Hilman } 46651c5d844SKevin Hilman 46700412ddcSHeiner Kallweit data->bytes_xfered = 0; 46800412ddcSHeiner Kallweit xfer_bytes = data->blksz * data->blocks; 46900412ddcSHeiner Kallweit if (data->flags & MMC_DATA_WRITE) { 470a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_WR; 47151c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size); 47200412ddcSHeiner Kallweit sg_copy_to_buffer(data->sg, data->sg_len, 47351c5d844SKevin Hilman host->bounce_buf, xfer_bytes); 47451c5d844SKevin Hilman dma_wmb(); 47551c5d844SKevin Hilman } 47651c5d844SKevin Hilman 477a322febeSHeiner Kallweit cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 47851c5d844SKevin Hilman } else { 4791231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 4801231e7ebSHeiner Kallweit ilog2(SD_EMMC_CMD_TIMEOUT)); 48151c5d844SKevin Hilman } 48251c5d844SKevin Hilman 48351c5d844SKevin Hilman host->cmd = cmd; 48451c5d844SKevin Hilman 48551c5d844SKevin Hilman /* Last descriptor */ 486a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_END_OF_CHAIN; 487a322febeSHeiner Kallweit writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 488a322febeSHeiner Kallweit writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 489a322febeSHeiner Kallweit writel(0, host->regs + SD_EMMC_CMD_RSP); 49051c5d844SKevin Hilman wmb(); /* ensure descriptor is written before kicked */ 491a322febeSHeiner Kallweit writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 49251c5d844SKevin Hilman } 49351c5d844SKevin Hilman 49451c5d844SKevin Hilman static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 49551c5d844SKevin Hilman { 49651c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 49751c5d844SKevin Hilman 49851c5d844SKevin Hilman /* Stop execution */ 49951c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START); 50051c5d844SKevin Hilman 50151c5d844SKevin Hilman if (mrq->sbc) 50251c5d844SKevin Hilman meson_mmc_start_cmd(mmc, mrq->sbc); 50351c5d844SKevin Hilman else 50451c5d844SKevin Hilman meson_mmc_start_cmd(mmc, mrq->cmd); 50551c5d844SKevin Hilman } 50651c5d844SKevin Hilman 5073d6c991bSHeiner Kallweit static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 50851c5d844SKevin Hilman { 50951c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc); 51051c5d844SKevin Hilman 51151c5d844SKevin Hilman if (cmd->flags & MMC_RSP_136) { 51251c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 51351c5d844SKevin Hilman cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 51451c5d844SKevin Hilman cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 51551c5d844SKevin Hilman cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 51651c5d844SKevin Hilman } else if (cmd->flags & MMC_RSP_PRESENT) { 51751c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 51851c5d844SKevin Hilman } 51951c5d844SKevin Hilman } 52051c5d844SKevin Hilman 52151c5d844SKevin Hilman static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 52251c5d844SKevin Hilman { 52351c5d844SKevin Hilman struct meson_host *host = dev_id; 52419a91dd4SHeinrich Schuchardt struct mmc_command *cmd; 5252c8d96a4SHeiner Kallweit struct mmc_data *data; 52651c5d844SKevin Hilman u32 irq_en, status, raw_status; 52751c5d844SKevin Hilman irqreturn_t ret = IRQ_HANDLED; 52851c5d844SKevin Hilman 52951c5d844SKevin Hilman if (WARN_ON(!host)) 53051c5d844SKevin Hilman return IRQ_NONE; 53151c5d844SKevin Hilman 53219a91dd4SHeinrich Schuchardt cmd = host->cmd; 53319a91dd4SHeinrich Schuchardt 53451c5d844SKevin Hilman if (WARN_ON(!cmd)) 53551c5d844SKevin Hilman return IRQ_NONE; 53651c5d844SKevin Hilman 5372c8d96a4SHeiner Kallweit data = cmd->data; 5382c8d96a4SHeiner Kallweit 53951c5d844SKevin Hilman spin_lock(&host->lock); 54051c5d844SKevin Hilman irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 54151c5d844SKevin Hilman raw_status = readl(host->regs + SD_EMMC_STATUS); 54251c5d844SKevin Hilman status = raw_status & irq_en; 54351c5d844SKevin Hilman 54451c5d844SKevin Hilman if (!status) { 54551c5d844SKevin Hilman dev_warn(host->dev, "Spurious IRQ! status=0x%08x, irq_en=0x%08x\n", 54651c5d844SKevin Hilman raw_status, irq_en); 54751c5d844SKevin Hilman ret = IRQ_NONE; 54851c5d844SKevin Hilman goto out; 54951c5d844SKevin Hilman } 55051c5d844SKevin Hilman 5511f8066d9SHeiner Kallweit meson_mmc_read_resp(host->mmc, cmd); 5521f8066d9SHeiner Kallweit 55351c5d844SKevin Hilman cmd->error = 0; 55451c5d844SKevin Hilman if (status & IRQ_RXD_ERR_MASK) { 55551c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: RXD error\n"); 55651c5d844SKevin Hilman cmd->error = -EILSEQ; 55751c5d844SKevin Hilman } 55851c5d844SKevin Hilman if (status & IRQ_TXD_ERR) { 55951c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: TXD error\n"); 56051c5d844SKevin Hilman cmd->error = -EILSEQ; 56151c5d844SKevin Hilman } 56251c5d844SKevin Hilman if (status & IRQ_DESC_ERR) 56351c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Descriptor error\n"); 56451c5d844SKevin Hilman if (status & IRQ_RESP_ERR) { 56551c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Response error\n"); 56651c5d844SKevin Hilman cmd->error = -EILSEQ; 56751c5d844SKevin Hilman } 56851c5d844SKevin Hilman if (status & IRQ_RESP_TIMEOUT) { 56951c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Response timeout\n"); 57051c5d844SKevin Hilman cmd->error = -ETIMEDOUT; 57151c5d844SKevin Hilman } 57251c5d844SKevin Hilman if (status & IRQ_DESC_TIMEOUT) { 57351c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: Descriptor timeout\n"); 57451c5d844SKevin Hilman cmd->error = -ETIMEDOUT; 57551c5d844SKevin Hilman } 57651c5d844SKevin Hilman if (status & IRQ_SDIO) 57751c5d844SKevin Hilman dev_dbg(host->dev, "Unhandled IRQ: SDIO.\n"); 57851c5d844SKevin Hilman 5792c8d96a4SHeiner Kallweit if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 5802c8d96a4SHeiner Kallweit if (data && !cmd->error) 5812c8d96a4SHeiner Kallweit data->bytes_xfered = data->blksz * data->blocks; 58251c5d844SKevin Hilman ret = IRQ_WAKE_THREAD; 5832c8d96a4SHeiner Kallweit } else { 58451c5d844SKevin Hilman dev_warn(host->dev, "Unknown IRQ! status=0x%04x: MMC CMD%u arg=0x%08x flags=0x%08x stop=%d\n", 58551c5d844SKevin Hilman status, cmd->opcode, cmd->arg, 5867cdcc480SHeiner Kallweit cmd->flags, cmd->mrq->stop ? 1 : 0); 58751c5d844SKevin Hilman if (cmd->data) { 58851c5d844SKevin Hilman struct mmc_data *data = cmd->data; 58951c5d844SKevin Hilman 59051c5d844SKevin Hilman dev_warn(host->dev, "\tblksz %u blocks %u flags 0x%08x (%s%s)", 59151c5d844SKevin Hilman data->blksz, data->blocks, data->flags, 59251c5d844SKevin Hilman data->flags & MMC_DATA_WRITE ? "write" : "", 59351c5d844SKevin Hilman data->flags & MMC_DATA_READ ? "read" : ""); 59451c5d844SKevin Hilman } 59551c5d844SKevin Hilman } 59651c5d844SKevin Hilman 59751c5d844SKevin Hilman out: 59851c5d844SKevin Hilman /* ack all (enabled) interrupts */ 59951c5d844SKevin Hilman writel(status, host->regs + SD_EMMC_STATUS); 60051c5d844SKevin Hilman 6011f8066d9SHeiner Kallweit if (ret == IRQ_HANDLED) 60251c5d844SKevin Hilman meson_mmc_request_done(host->mmc, cmd->mrq); 60351c5d844SKevin Hilman 60451c5d844SKevin Hilman spin_unlock(&host->lock); 60551c5d844SKevin Hilman return ret; 60651c5d844SKevin Hilman } 60751c5d844SKevin Hilman 60851c5d844SKevin Hilman static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 60951c5d844SKevin Hilman { 61051c5d844SKevin Hilman struct meson_host *host = dev_id; 61151c5d844SKevin Hilman struct mmc_command *cmd = host->cmd; 61251c5d844SKevin Hilman struct mmc_data *data; 61351c5d844SKevin Hilman unsigned int xfer_bytes; 61451c5d844SKevin Hilman 61551c5d844SKevin Hilman if (WARN_ON(!cmd)) 61619a91dd4SHeinrich Schuchardt return IRQ_NONE; 61751c5d844SKevin Hilman 61851c5d844SKevin Hilman data = cmd->data; 619690f90b6SHeiner Kallweit if (data && data->flags & MMC_DATA_READ) { 62051c5d844SKevin Hilman xfer_bytes = data->blksz * data->blocks; 62151c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size); 62251c5d844SKevin Hilman sg_copy_from_buffer(data->sg, data->sg_len, 62351c5d844SKevin Hilman host->bounce_buf, xfer_bytes); 62451c5d844SKevin Hilman } 62551c5d844SKevin Hilman 6267cdcc480SHeiner Kallweit if (!data || !data->stop || cmd->mrq->sbc) 6277cdcc480SHeiner Kallweit meson_mmc_request_done(host->mmc, cmd->mrq); 62851c5d844SKevin Hilman else 62951c5d844SKevin Hilman meson_mmc_start_cmd(host->mmc, data->stop); 63051c5d844SKevin Hilman 631690f90b6SHeiner Kallweit return IRQ_HANDLED; 63251c5d844SKevin Hilman } 63351c5d844SKevin Hilman 63451c5d844SKevin Hilman /* 63551c5d844SKevin Hilman * NOTE: we only need this until the GPIO/pinctrl driver can handle 63651c5d844SKevin Hilman * interrupts. For now, the MMC core will use this for polling. 63751c5d844SKevin Hilman */ 63851c5d844SKevin Hilman static int meson_mmc_get_cd(struct mmc_host *mmc) 63951c5d844SKevin Hilman { 64051c5d844SKevin Hilman int status = mmc_gpio_get_cd(mmc); 64151c5d844SKevin Hilman 64251c5d844SKevin Hilman if (status == -ENOSYS) 64351c5d844SKevin Hilman return 1; /* assume present */ 64451c5d844SKevin Hilman 64551c5d844SKevin Hilman return status; 64651c5d844SKevin Hilman } 64751c5d844SKevin Hilman 648c01d1219SHeiner Kallweit static void meson_mmc_cfg_init(struct meson_host *host) 649c01d1219SHeiner Kallweit { 650c01d1219SHeiner Kallweit u32 cfg = 0; 651c01d1219SHeiner Kallweit 6521231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 6531231e7ebSHeiner Kallweit ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 6541231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 6551231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 656c01d1219SHeiner Kallweit 657c01d1219SHeiner Kallweit writel(cfg, host->regs + SD_EMMC_CFG); 658c01d1219SHeiner Kallweit } 659c01d1219SHeiner Kallweit 66051c5d844SKevin Hilman static const struct mmc_host_ops meson_mmc_ops = { 66151c5d844SKevin Hilman .request = meson_mmc_request, 66251c5d844SKevin Hilman .set_ios = meson_mmc_set_ios, 66351c5d844SKevin Hilman .get_cd = meson_mmc_get_cd, 66451c5d844SKevin Hilman }; 66551c5d844SKevin Hilman 66651c5d844SKevin Hilman static int meson_mmc_probe(struct platform_device *pdev) 66751c5d844SKevin Hilman { 66851c5d844SKevin Hilman struct resource *res; 66951c5d844SKevin Hilman struct meson_host *host; 67051c5d844SKevin Hilman struct mmc_host *mmc; 6719a1da4dfSHeiner Kallweit int ret, irq; 67251c5d844SKevin Hilman 67351c5d844SKevin Hilman mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 67451c5d844SKevin Hilman if (!mmc) 67551c5d844SKevin Hilman return -ENOMEM; 67651c5d844SKevin Hilman host = mmc_priv(mmc); 67751c5d844SKevin Hilman host->mmc = mmc; 67851c5d844SKevin Hilman host->dev = &pdev->dev; 67951c5d844SKevin Hilman dev_set_drvdata(&pdev->dev, host); 68051c5d844SKevin Hilman 68151c5d844SKevin Hilman spin_lock_init(&host->lock); 68251c5d844SKevin Hilman 68351c5d844SKevin Hilman /* Get regulators and the supported OCR mask */ 68451c5d844SKevin Hilman host->vqmmc_enabled = false; 68551c5d844SKevin Hilman ret = mmc_regulator_get_supply(mmc); 68651c5d844SKevin Hilman if (ret == -EPROBE_DEFER) 68751c5d844SKevin Hilman goto free_host; 68851c5d844SKevin Hilman 68951c5d844SKevin Hilman ret = mmc_of_parse(mmc); 69051c5d844SKevin Hilman if (ret) { 691dc012058SKevin Hilman if (ret != -EPROBE_DEFER) 69251c5d844SKevin Hilman dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 69351c5d844SKevin Hilman goto free_host; 69451c5d844SKevin Hilman } 69551c5d844SKevin Hilman 69651c5d844SKevin Hilman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 69751c5d844SKevin Hilman host->regs = devm_ioremap_resource(&pdev->dev, res); 69851c5d844SKevin Hilman if (IS_ERR(host->regs)) { 69951c5d844SKevin Hilman ret = PTR_ERR(host->regs); 70051c5d844SKevin Hilman goto free_host; 70151c5d844SKevin Hilman } 70251c5d844SKevin Hilman 7039a1da4dfSHeiner Kallweit irq = platform_get_irq(pdev, 0); 7049a1da4dfSHeiner Kallweit if (!irq) { 70551c5d844SKevin Hilman dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 70651c5d844SKevin Hilman ret = -EINVAL; 70751c5d844SKevin Hilman goto free_host; 70851c5d844SKevin Hilman } 70951c5d844SKevin Hilman 71051c5d844SKevin Hilman host->core_clk = devm_clk_get(&pdev->dev, "core"); 71151c5d844SKevin Hilman if (IS_ERR(host->core_clk)) { 71251c5d844SKevin Hilman ret = PTR_ERR(host->core_clk); 71351c5d844SKevin Hilman goto free_host; 71451c5d844SKevin Hilman } 71551c5d844SKevin Hilman 71651c5d844SKevin Hilman ret = clk_prepare_enable(host->core_clk); 71751c5d844SKevin Hilman if (ret) 71851c5d844SKevin Hilman goto free_host; 71951c5d844SKevin Hilman 72051c5d844SKevin Hilman ret = meson_mmc_clk_init(host); 72151c5d844SKevin Hilman if (ret) 722ce473d5bSMichał Zegan goto err_core_clk; 72351c5d844SKevin Hilman 72451c5d844SKevin Hilman /* Stop execution */ 72551c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START); 72651c5d844SKevin Hilman 72751c5d844SKevin Hilman /* clear, ack, enable all interrupts */ 72851c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_IRQ_EN); 72951c5d844SKevin Hilman writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); 73092763b99SHeiner Kallweit writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); 73151c5d844SKevin Hilman 732c01d1219SHeiner Kallweit /* set config to sane default */ 733c01d1219SHeiner Kallweit meson_mmc_cfg_init(host); 734c01d1219SHeiner Kallweit 7359a1da4dfSHeiner Kallweit ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq, 7369a1da4dfSHeiner Kallweit meson_mmc_irq_thread, IRQF_SHARED, 7379a1da4dfSHeiner Kallweit DRIVER_NAME, host); 73851c5d844SKevin Hilman if (ret) 739cac3a478SHeiner Kallweit goto err_div_clk; 74051c5d844SKevin Hilman 741efe0b669SHeiner Kallweit mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 742efe0b669SHeiner Kallweit mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 743efe0b669SHeiner Kallweit 74451c5d844SKevin Hilman /* data bounce buffer */ 7454136fcb5SHeiner Kallweit host->bounce_buf_size = mmc->max_req_size; 74651c5d844SKevin Hilman host->bounce_buf = 74751c5d844SKevin Hilman dma_alloc_coherent(host->dev, host->bounce_buf_size, 74851c5d844SKevin Hilman &host->bounce_dma_addr, GFP_KERNEL); 74951c5d844SKevin Hilman if (host->bounce_buf == NULL) { 75051c5d844SKevin Hilman dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 75151c5d844SKevin Hilman ret = -ENOMEM; 752cac3a478SHeiner Kallweit goto err_div_clk; 75351c5d844SKevin Hilman } 75451c5d844SKevin Hilman 75551c5d844SKevin Hilman mmc->ops = &meson_mmc_ops; 75651c5d844SKevin Hilman mmc_add_host(mmc); 75751c5d844SKevin Hilman 75851c5d844SKevin Hilman return 0; 75951c5d844SKevin Hilman 760cac3a478SHeiner Kallweit err_div_clk: 76151c5d844SKevin Hilman clk_disable_unprepare(host->cfg_div_clk); 762ce473d5bSMichał Zegan err_core_clk: 76351c5d844SKevin Hilman clk_disable_unprepare(host->core_clk); 764ce473d5bSMichał Zegan free_host: 76551c5d844SKevin Hilman mmc_free_host(mmc); 76651c5d844SKevin Hilman return ret; 76751c5d844SKevin Hilman } 76851c5d844SKevin Hilman 76951c5d844SKevin Hilman static int meson_mmc_remove(struct platform_device *pdev) 77051c5d844SKevin Hilman { 77151c5d844SKevin Hilman struct meson_host *host = dev_get_drvdata(&pdev->dev); 77251c5d844SKevin Hilman 773a01fc2a2SMichał Zegan mmc_remove_host(host->mmc); 774a01fc2a2SMichał Zegan 77592763b99SHeiner Kallweit /* disable interrupts */ 77692763b99SHeiner Kallweit writel(0, host->regs + SD_EMMC_IRQ_EN); 77792763b99SHeiner Kallweit 77851c5d844SKevin Hilman dma_free_coherent(host->dev, host->bounce_buf_size, 77951c5d844SKevin Hilman host->bounce_buf, host->bounce_dma_addr); 78051c5d844SKevin Hilman 78151c5d844SKevin Hilman clk_disable_unprepare(host->cfg_div_clk); 78251c5d844SKevin Hilman clk_disable_unprepare(host->core_clk); 78351c5d844SKevin Hilman 78451c5d844SKevin Hilman mmc_free_host(host->mmc); 78551c5d844SKevin Hilman return 0; 78651c5d844SKevin Hilman } 78751c5d844SKevin Hilman 78851c5d844SKevin Hilman static const struct of_device_id meson_mmc_of_match[] = { 78951c5d844SKevin Hilman { .compatible = "amlogic,meson-gx-mmc", }, 79051c5d844SKevin Hilman { .compatible = "amlogic,meson-gxbb-mmc", }, 79151c5d844SKevin Hilman { .compatible = "amlogic,meson-gxl-mmc", }, 79251c5d844SKevin Hilman { .compatible = "amlogic,meson-gxm-mmc", }, 79351c5d844SKevin Hilman {} 79451c5d844SKevin Hilman }; 79551c5d844SKevin Hilman MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 79651c5d844SKevin Hilman 79751c5d844SKevin Hilman static struct platform_driver meson_mmc_driver = { 79851c5d844SKevin Hilman .probe = meson_mmc_probe, 79951c5d844SKevin Hilman .remove = meson_mmc_remove, 80051c5d844SKevin Hilman .driver = { 80151c5d844SKevin Hilman .name = DRIVER_NAME, 80251c5d844SKevin Hilman .of_match_table = of_match_ptr(meson_mmc_of_match), 80351c5d844SKevin Hilman }, 80451c5d844SKevin Hilman }; 80551c5d844SKevin Hilman 80651c5d844SKevin Hilman module_platform_driver(meson_mmc_driver); 80751c5d844SKevin Hilman 80851c5d844SKevin Hilman MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver"); 80951c5d844SKevin Hilman MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 81051c5d844SKevin Hilman MODULE_LICENSE("GPL v2"); 811