138cf0d46SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
251c5d844SKevin Hilman /*
351c5d844SKevin Hilman * Amlogic SD/eMMC driver for the GX/S905 family SoCs
451c5d844SKevin Hilman *
551c5d844SKevin Hilman * Copyright (c) 2016 BayLibre, SAS.
651c5d844SKevin Hilman * Author: Kevin Hilman <khilman@baylibre.com>
751c5d844SKevin Hilman */
851c5d844SKevin Hilman #include <linux/kernel.h>
951c5d844SKevin Hilman #include <linux/module.h>
1051c5d844SKevin Hilman #include <linux/init.h>
1118f92bc0SJerome Brunet #include <linux/delay.h>
1251c5d844SKevin Hilman #include <linux/device.h>
1398849da6SJerome Brunet #include <linux/iopoll.h>
14c62da8a8SRob Herring #include <linux/of.h>
1551c5d844SKevin Hilman #include <linux/platform_device.h>
1651c5d844SKevin Hilman #include <linux/ioport.h>
1751c5d844SKevin Hilman #include <linux/dma-mapping.h>
1851c5d844SKevin Hilman #include <linux/mmc/host.h>
1951c5d844SKevin Hilman #include <linux/mmc/mmc.h>
2051c5d844SKevin Hilman #include <linux/mmc/sdio.h>
2151c5d844SKevin Hilman #include <linux/mmc/slot-gpio.h>
2251c5d844SKevin Hilman #include <linux/io.h>
2351c5d844SKevin Hilman #include <linux/clk.h>
2451c5d844SKevin Hilman #include <linux/clk-provider.h>
2551c5d844SKevin Hilman #include <linux/regulator/consumer.h>
2619c6beaaSJerome Brunet #include <linux/reset.h>
27b8789ec4SUlf Hansson #include <linux/interrupt.h>
281231e7ebSHeiner Kallweit #include <linux/bitfield.h>
298fb572acSThierry Reding #include <linux/pinctrl/consumer.h>
3051c5d844SKevin Hilman
3151c5d844SKevin Hilman #define DRIVER_NAME "meson-gx-mmc"
3251c5d844SKevin Hilman
3351c5d844SKevin Hilman #define SD_EMMC_CLOCK 0x0
341231e7ebSHeiner Kallweit #define CLK_DIV_MASK GENMASK(5, 0)
351231e7ebSHeiner Kallweit #define CLK_SRC_MASK GENMASK(7, 6)
361231e7ebSHeiner Kallweit #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
37c08bcb6cSHeiner Kallweit #define CLK_TX_PHASE_MASK GENMASK(11, 10)
38c08bcb6cSHeiner Kallweit #define CLK_RX_PHASE_MASK GENMASK(13, 12)
395e6f75f4SJerome Brunet #define CLK_PHASE_0 0
405e6f75f4SJerome Brunet #define CLK_PHASE_180 2
41df069815SNan Li #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
42df069815SNan Li #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
43df069815SNan Li #define CLK_V2_ALWAYS_ON BIT(24)
44066ecde6SHeiner Kallweit #define CLK_V2_IRQ_SDIO_SLEEP BIT(25)
45df069815SNan Li
46df069815SNan Li #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
47df069815SNan Li #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
48df069815SNan Li #define CLK_V3_ALWAYS_ON BIT(28)
49066ecde6SHeiner Kallweit #define CLK_V3_IRQ_SDIO_SLEEP BIT(29)
50df069815SNan Li
51df069815SNan Li #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
52df069815SNan Li #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
53df069815SNan Li #define CLK_ALWAYS_ON(h) (h->data->always_on)
54066ecde6SHeiner Kallweit #define CLK_IRQ_SDIO_SLEEP(h) (h->data->irq_sdio_sleep)
5551c5d844SKevin Hilman
5652899b99SJerome Brunet #define SD_EMMC_DELAY 0x4
5751c5d844SKevin Hilman #define SD_EMMC_ADJUST 0x8
5871645e65SJerome Brunet #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
5971645e65SJerome Brunet #define ADJUST_DS_EN BIT(15)
6071645e65SJerome Brunet #define ADJUST_ADJ_EN BIT(13)
61df069815SNan Li
62df069815SNan Li #define SD_EMMC_DELAY1 0x4
63df069815SNan Li #define SD_EMMC_DELAY2 0x8
64df069815SNan Li #define SD_EMMC_V3_ADJUST 0xc
65df069815SNan Li
6651c5d844SKevin Hilman #define SD_EMMC_CALOUT 0x10
6751c5d844SKevin Hilman #define SD_EMMC_START 0x40
6851c5d844SKevin Hilman #define START_DESC_INIT BIT(0)
6951c5d844SKevin Hilman #define START_DESC_BUSY BIT(1)
701231e7ebSHeiner Kallweit #define START_DESC_ADDR_MASK GENMASK(31, 2)
7151c5d844SKevin Hilman
7251c5d844SKevin Hilman #define SD_EMMC_CFG 0x44
731231e7ebSHeiner Kallweit #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
7451c5d844SKevin Hilman #define CFG_BUS_WIDTH_1 0x0
7551c5d844SKevin Hilman #define CFG_BUS_WIDTH_4 0x1
7651c5d844SKevin Hilman #define CFG_BUS_WIDTH_8 0x2
7751c5d844SKevin Hilman #define CFG_DDR BIT(2)
781231e7ebSHeiner Kallweit #define CFG_BLK_LEN_MASK GENMASK(7, 4)
791231e7ebSHeiner Kallweit #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
801231e7ebSHeiner Kallweit #define CFG_RC_CC_MASK GENMASK(15, 12)
8151c5d844SKevin Hilman #define CFG_STOP_CLOCK BIT(22)
8251c5d844SKevin Hilman #define CFG_CLK_ALWAYS_ON BIT(18)
83e21e6fddSHeiner Kallweit #define CFG_CHK_DS BIT(20)
8451c5d844SKevin Hilman #define CFG_AUTO_CLK BIT(23)
8518f92bc0SJerome Brunet #define CFG_ERR_ABORT BIT(27)
8651c5d844SKevin Hilman
8751c5d844SKevin Hilman #define SD_EMMC_STATUS 0x48
8851c5d844SKevin Hilman #define STATUS_BUSY BIT(31)
8918f92bc0SJerome Brunet #define STATUS_DESC_BUSY BIT(30)
90186cd8b7SJerome Brunet #define STATUS_DATI GENMASK(23, 16)
9151c5d844SKevin Hilman
9251c5d844SKevin Hilman #define SD_EMMC_IRQ_EN 0x4c
931231e7ebSHeiner Kallweit #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
9451c5d844SKevin Hilman #define IRQ_TXD_ERR BIT(8)
9551c5d844SKevin Hilman #define IRQ_DESC_ERR BIT(9)
9651c5d844SKevin Hilman #define IRQ_RESP_ERR BIT(10)
9774858655SJerome Brunet #define IRQ_CRC_ERR \
9874858655SJerome Brunet (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
9951c5d844SKevin Hilman #define IRQ_RESP_TIMEOUT BIT(11)
10051c5d844SKevin Hilman #define IRQ_DESC_TIMEOUT BIT(12)
10174858655SJerome Brunet #define IRQ_TIMEOUTS \
10274858655SJerome Brunet (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
10351c5d844SKevin Hilman #define IRQ_END_OF_CHAIN BIT(13)
10451c5d844SKevin Hilman #define IRQ_RESP_STATUS BIT(14)
10551c5d844SKevin Hilman #define IRQ_SDIO BIT(15)
10674858655SJerome Brunet #define IRQ_EN_MASK \
1076f6fac8aSHeiner Kallweit (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN)
10851c5d844SKevin Hilman
10951c5d844SKevin Hilman #define SD_EMMC_CMD_CFG 0x50
11051c5d844SKevin Hilman #define SD_EMMC_CMD_ARG 0x54
11151c5d844SKevin Hilman #define SD_EMMC_CMD_DAT 0x58
11251c5d844SKevin Hilman #define SD_EMMC_CMD_RSP 0x5c
11351c5d844SKevin Hilman #define SD_EMMC_CMD_RSP1 0x60
11451c5d844SKevin Hilman #define SD_EMMC_CMD_RSP2 0x64
11551c5d844SKevin Hilman #define SD_EMMC_CMD_RSP3 0x68
11651c5d844SKevin Hilman
11751c5d844SKevin Hilman #define SD_EMMC_RXD 0x94
11851c5d844SKevin Hilman #define SD_EMMC_TXD 0x94
11951c5d844SKevin Hilman #define SD_EMMC_LAST_REG SD_EMMC_TXD
12051c5d844SKevin Hilman
121acdc8e71SNeil Armstrong #define SD_EMMC_SRAM_DATA_BUF_LEN 1536
122acdc8e71SNeil Armstrong #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
123acdc8e71SNeil Armstrong
12451c5d844SKevin Hilman #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
12551c5d844SKevin Hilman #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
126bb11eff1SHeiner Kallweit #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
127bb11eff1SHeiner Kallweit #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
12851c5d844SKevin Hilman #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
12979ed05e3SHeiner Kallweit #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
13079ed05e3SHeiner Kallweit
13179ed05e3SHeiner Kallweit #define SD_EMMC_PRE_REQ_DONE BIT(0)
13279ed05e3SHeiner Kallweit #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
13379ed05e3SHeiner Kallweit
13451c5d844SKevin Hilman #define MUX_CLK_NUM_PARENTS 2
13551c5d844SKevin Hilman
136df069815SNan Li struct meson_mmc_data {
137df069815SNan Li unsigned int tx_delay_mask;
138df069815SNan Li unsigned int rx_delay_mask;
139df069815SNan Li unsigned int always_on;
14071645e65SJerome Brunet unsigned int adjust;
141066ecde6SHeiner Kallweit unsigned int irq_sdio_sleep;
142df069815SNan Li };
143df069815SNan Li
14479ed05e3SHeiner Kallweit struct sd_emmc_desc {
14579ed05e3SHeiner Kallweit u32 cmd_cfg;
14679ed05e3SHeiner Kallweit u32 cmd_arg;
14779ed05e3SHeiner Kallweit u32 cmd_data;
14879ed05e3SHeiner Kallweit u32 cmd_resp;
14979ed05e3SHeiner Kallweit };
15079ed05e3SHeiner Kallweit
15151c5d844SKevin Hilman struct meson_host {
15251c5d844SKevin Hilman struct device *dev;
153c5a66dd8SHeiner Kallweit const struct meson_mmc_data *data;
15451c5d844SKevin Hilman struct mmc_host *mmc;
15551c5d844SKevin Hilman struct mmc_command *cmd;
15651c5d844SKevin Hilman
15751c5d844SKevin Hilman void __iomem *regs;
1585e6f75f4SJerome Brunet struct clk *mux_clk;
159bd911ec4SJerome Brunet struct clk *mmc_clk;
160f89f55dfSJerome Brunet unsigned long req_rate;
161dc38ac81SJerome Brunet bool ddr;
16251c5d844SKevin Hilman
163acdc8e71SNeil Armstrong bool dram_access_quirk;
164acdc8e71SNeil Armstrong
1651e03331dSJerome Brunet struct pinctrl *pinctrl;
1661e03331dSJerome Brunet struct pinctrl_state *pins_clk_gate;
1671e03331dSJerome Brunet
16851c5d844SKevin Hilman unsigned int bounce_buf_size;
16951c5d844SKevin Hilman void *bounce_buf;
170103a5348SNeil Armstrong void __iomem *bounce_iomem_buf;
17151c5d844SKevin Hilman dma_addr_t bounce_dma_addr;
17279ed05e3SHeiner Kallweit struct sd_emmc_desc *descs;
17379ed05e3SHeiner Kallweit dma_addr_t descs_dma_addr;
17451c5d844SKevin Hilman
175bb364890SRemi Pommarel int irq;
176bb364890SRemi Pommarel
177f0d2f153SRong Chen bool needs_pre_post_req;
178f0d2f153SRong Chen
179066ecde6SHeiner Kallweit spinlock_t lock;
18051c5d844SKevin Hilman };
18151c5d844SKevin Hilman
1821231e7ebSHeiner Kallweit #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
18351c5d844SKevin Hilman #define CMD_CFG_BLOCK_MODE BIT(9)
18451c5d844SKevin Hilman #define CMD_CFG_R1B BIT(10)
18551c5d844SKevin Hilman #define CMD_CFG_END_OF_CHAIN BIT(11)
1861231e7ebSHeiner Kallweit #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
18751c5d844SKevin Hilman #define CMD_CFG_NO_RESP BIT(16)
18851c5d844SKevin Hilman #define CMD_CFG_NO_CMD BIT(17)
18951c5d844SKevin Hilman #define CMD_CFG_DATA_IO BIT(18)
19051c5d844SKevin Hilman #define CMD_CFG_DATA_WR BIT(19)
19151c5d844SKevin Hilman #define CMD_CFG_RESP_NOCRC BIT(20)
19251c5d844SKevin Hilman #define CMD_CFG_RESP_128 BIT(21)
19351c5d844SKevin Hilman #define CMD_CFG_RESP_NUM BIT(22)
19451c5d844SKevin Hilman #define CMD_CFG_DATA_NUM BIT(23)
1951231e7ebSHeiner Kallweit #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
19651c5d844SKevin Hilman #define CMD_CFG_ERROR BIT(30)
19751c5d844SKevin Hilman #define CMD_CFG_OWNER BIT(31)
19851c5d844SKevin Hilman
1991231e7ebSHeiner Kallweit #define CMD_DATA_MASK GENMASK(31, 2)
20051c5d844SKevin Hilman #define CMD_DATA_BIG_ENDIAN BIT(1)
20151c5d844SKevin Hilman #define CMD_DATA_SRAM BIT(0)
2021231e7ebSHeiner Kallweit #define CMD_RESP_MASK GENMASK(31, 1)
20351c5d844SKevin Hilman #define CMD_RESP_SRAM BIT(0)
20451c5d844SKevin Hilman
meson_mmc_get_timeout_msecs(struct mmc_data * data)2054eee86c3SHeiner Kallweit static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
2064eee86c3SHeiner Kallweit {
2074eee86c3SHeiner Kallweit unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
2084eee86c3SHeiner Kallweit
2094eee86c3SHeiner Kallweit if (!timeout)
2104eee86c3SHeiner Kallweit return SD_EMMC_CMD_TIMEOUT_DATA;
2114eee86c3SHeiner Kallweit
2124eee86c3SHeiner Kallweit timeout = roundup_pow_of_two(timeout);
2134eee86c3SHeiner Kallweit
2144eee86c3SHeiner Kallweit return min(timeout, 32768U); /* max. 2^15 ms */
2154eee86c3SHeiner Kallweit }
2164eee86c3SHeiner Kallweit
meson_mmc_get_next_command(struct mmc_command * cmd)217e5e4a3ebSHeiner Kallweit static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
218e5e4a3ebSHeiner Kallweit {
219e5e4a3ebSHeiner Kallweit if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
220e5e4a3ebSHeiner Kallweit return cmd->mrq->cmd;
221e5e4a3ebSHeiner Kallweit else if (mmc_op_multi(cmd->opcode) &&
222e5e4a3ebSHeiner Kallweit (!cmd->mrq->sbc || cmd->error || cmd->data->error))
223e5e4a3ebSHeiner Kallweit return cmd->mrq->stop;
224e5e4a3ebSHeiner Kallweit else
225e5e4a3ebSHeiner Kallweit return NULL;
226e5e4a3ebSHeiner Kallweit }
227e5e4a3ebSHeiner Kallweit
meson_mmc_get_transfer_mode(struct mmc_host * mmc,struct mmc_request * mrq)22879ed05e3SHeiner Kallweit static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
22979ed05e3SHeiner Kallweit struct mmc_request *mrq)
23079ed05e3SHeiner Kallweit {
231acdc8e71SNeil Armstrong struct meson_host *host = mmc_priv(mmc);
23279ed05e3SHeiner Kallweit struct mmc_data *data = mrq->data;
23379ed05e3SHeiner Kallweit struct scatterlist *sg;
23479ed05e3SHeiner Kallweit int i;
23579ed05e3SHeiner Kallweit
23624835611SHeiner Kallweit /*
237acdc8e71SNeil Armstrong * When Controller DMA cannot directly access DDR memory, disable
238acdc8e71SNeil Armstrong * support for Chain Mode to directly use the internal SRAM using
239acdc8e71SNeil Armstrong * the bounce buffer mode.
240acdc8e71SNeil Armstrong */
241acdc8e71SNeil Armstrong if (host->dram_access_quirk)
242acdc8e71SNeil Armstrong return;
243acdc8e71SNeil Armstrong
2449b81354dSNeil Armstrong /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */
2459b81354dSNeil Armstrong if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
246acdc8e71SNeil Armstrong /*
247e085b51cSDmitry Lebed * In block mode DMA descriptor format, "length" field indicates
248e085b51cSDmitry Lebed * number of blocks and there is no way to pass DMA size that
249e085b51cSDmitry Lebed * is not multiple of SDIO block size, making it impossible to
250e085b51cSDmitry Lebed * tie more than one memory buffer with single SDIO block.
251e085b51cSDmitry Lebed * Block mode sg buffer size should be aligned with SDIO block
252e085b51cSDmitry Lebed * size, otherwise chain mode could not be used.
25324835611SHeiner Kallweit */
254e085b51cSDmitry Lebed for_each_sg(data->sg, sg, data->sg_len, i) {
255e085b51cSDmitry Lebed if (sg->length % data->blksz) {
2567412dee9SNeil Armstrong dev_warn_once(mmc_dev(mmc),
2577412dee9SNeil Armstrong "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n",
258e085b51cSDmitry Lebed sg->length, data->blksz);
25924835611SHeiner Kallweit return;
260e085b51cSDmitry Lebed }
261e085b51cSDmitry Lebed }
26279ed05e3SHeiner Kallweit }
26379ed05e3SHeiner Kallweit
264e085b51cSDmitry Lebed for_each_sg(data->sg, sg, data->sg_len, i) {
265e085b51cSDmitry Lebed /* check for 8 byte alignment */
266e085b51cSDmitry Lebed if (sg->offset % 8) {
267cabb1bb6SNeil Armstrong dev_warn_once(mmc_dev(mmc),
268cabb1bb6SNeil Armstrong "unaligned sg offset %u, disabling descriptor DMA for transfer\n",
269cabb1bb6SNeil Armstrong sg->offset);
270e085b51cSDmitry Lebed return;
271e085b51cSDmitry Lebed }
272e085b51cSDmitry Lebed }
273e085b51cSDmitry Lebed
27479ed05e3SHeiner Kallweit data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
27579ed05e3SHeiner Kallweit }
27679ed05e3SHeiner Kallweit
meson_mmc_desc_chain_mode(const struct mmc_data * data)27779ed05e3SHeiner Kallweit static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
27879ed05e3SHeiner Kallweit {
27979ed05e3SHeiner Kallweit return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
28079ed05e3SHeiner Kallweit }
28179ed05e3SHeiner Kallweit
meson_mmc_bounce_buf_read(const struct mmc_data * data)28279ed05e3SHeiner Kallweit static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
28379ed05e3SHeiner Kallweit {
28479ed05e3SHeiner Kallweit return data && data->flags & MMC_DATA_READ &&
28579ed05e3SHeiner Kallweit !meson_mmc_desc_chain_mode(data);
28679ed05e3SHeiner Kallweit }
28779ed05e3SHeiner Kallweit
meson_mmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)28879ed05e3SHeiner Kallweit static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
28979ed05e3SHeiner Kallweit {
29079ed05e3SHeiner Kallweit struct mmc_data *data = mrq->data;
29179ed05e3SHeiner Kallweit
29279ed05e3SHeiner Kallweit if (!data)
29379ed05e3SHeiner Kallweit return;
29479ed05e3SHeiner Kallweit
29579ed05e3SHeiner Kallweit meson_mmc_get_transfer_mode(mmc, mrq);
29679ed05e3SHeiner Kallweit data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
29779ed05e3SHeiner Kallweit
29879ed05e3SHeiner Kallweit if (!meson_mmc_desc_chain_mode(data))
29979ed05e3SHeiner Kallweit return;
30079ed05e3SHeiner Kallweit
30179ed05e3SHeiner Kallweit data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
30279ed05e3SHeiner Kallweit mmc_get_dma_dir(data));
30379ed05e3SHeiner Kallweit if (!data->sg_count)
30479ed05e3SHeiner Kallweit dev_err(mmc_dev(mmc), "dma_map_sg failed");
30579ed05e3SHeiner Kallweit }
30679ed05e3SHeiner Kallweit
meson_mmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)30779ed05e3SHeiner Kallweit static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
30879ed05e3SHeiner Kallweit int err)
30979ed05e3SHeiner Kallweit {
31079ed05e3SHeiner Kallweit struct mmc_data *data = mrq->data;
31179ed05e3SHeiner Kallweit
31279ed05e3SHeiner Kallweit if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
31379ed05e3SHeiner Kallweit dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
31479ed05e3SHeiner Kallweit mmc_get_dma_dir(data));
31579ed05e3SHeiner Kallweit }
31679ed05e3SHeiner Kallweit
3171e03331dSJerome Brunet /*
3181e03331dSJerome Brunet * Gating the clock on this controller is tricky. It seems the mmc clock
3191e03331dSJerome Brunet * is also used by the controller. It may crash during some operation if the
3201e03331dSJerome Brunet * clock is stopped. The safest thing to do, whenever possible, is to keep
3211e03331dSJerome Brunet * clock running at stop it at the pad using the pinmux.
3221e03331dSJerome Brunet */
meson_mmc_clk_gate(struct meson_host * host)3231e03331dSJerome Brunet static void meson_mmc_clk_gate(struct meson_host *host)
3241e03331dSJerome Brunet {
3251e03331dSJerome Brunet u32 cfg;
3261e03331dSJerome Brunet
3271e03331dSJerome Brunet if (host->pins_clk_gate) {
3281e03331dSJerome Brunet pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
3291e03331dSJerome Brunet } else {
3301e03331dSJerome Brunet /*
3311e03331dSJerome Brunet * If the pinmux is not provided - default to the classic and
3321e03331dSJerome Brunet * unsafe method
3331e03331dSJerome Brunet */
3341e03331dSJerome Brunet cfg = readl(host->regs + SD_EMMC_CFG);
3351e03331dSJerome Brunet cfg |= CFG_STOP_CLOCK;
3361e03331dSJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG);
3371e03331dSJerome Brunet }
3381e03331dSJerome Brunet }
3391e03331dSJerome Brunet
meson_mmc_clk_ungate(struct meson_host * host)3401e03331dSJerome Brunet static void meson_mmc_clk_ungate(struct meson_host *host)
3411e03331dSJerome Brunet {
3421e03331dSJerome Brunet u32 cfg;
3431e03331dSJerome Brunet
3441e03331dSJerome Brunet if (host->pins_clk_gate)
345f9be7f9cSUlf Hansson pinctrl_select_default_state(host->dev);
3461e03331dSJerome Brunet
3471e03331dSJerome Brunet /* Make sure the clock is not stopped in the controller */
3481e03331dSJerome Brunet cfg = readl(host->regs + SD_EMMC_CFG);
3491e03331dSJerome Brunet cfg &= ~CFG_STOP_CLOCK;
3501e03331dSJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG);
3511e03331dSJerome Brunet }
3521e03331dSJerome Brunet
meson_mmc_clk_set(struct meson_host * host,unsigned long rate,bool ddr)353dc38ac81SJerome Brunet static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
354dc38ac81SJerome Brunet bool ddr)
35551c5d844SKevin Hilman {
35651c5d844SKevin Hilman struct mmc_host *mmc = host->mmc;
3575da86887SHeiner Kallweit int ret;
35851c5d844SKevin Hilman u32 cfg;
35951c5d844SKevin Hilman
360f89f55dfSJerome Brunet /* Same request - bail-out */
361dc38ac81SJerome Brunet if (host->ddr == ddr && host->req_rate == rate)
36251c5d844SKevin Hilman return 0;
36351c5d844SKevin Hilman
36451c5d844SKevin Hilman /* stop clock */
3651e03331dSJerome Brunet meson_mmc_clk_gate(host);
366f89f55dfSJerome Brunet host->req_rate = 0;
36751c5d844SKevin Hilman mmc->actual_clock = 0;
368dc38ac81SJerome Brunet
3695da86887SHeiner Kallweit /* return with clock being stopped */
370dc38ac81SJerome Brunet if (!rate)
37151c5d844SKevin Hilman return 0;
37251c5d844SKevin Hilman
3731e03331dSJerome Brunet /* Stop the clock during rate change to avoid glitches */
3741e03331dSJerome Brunet cfg = readl(host->regs + SD_EMMC_CFG);
3751e03331dSJerome Brunet cfg |= CFG_STOP_CLOCK;
3761e03331dSJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG);
3771e03331dSJerome Brunet
378dc38ac81SJerome Brunet if (ddr) {
379dc38ac81SJerome Brunet /* DDR modes require higher module clock */
380dc38ac81SJerome Brunet rate <<= 1;
381dc38ac81SJerome Brunet cfg |= CFG_DDR;
382dc38ac81SJerome Brunet } else {
383dc38ac81SJerome Brunet cfg &= ~CFG_DDR;
384dc38ac81SJerome Brunet }
385dc38ac81SJerome Brunet writel(cfg, host->regs + SD_EMMC_CFG);
386dc38ac81SJerome Brunet host->ddr = ddr;
387dc38ac81SJerome Brunet
388844c8a75SJerome Brunet ret = clk_set_rate(host->mmc_clk, rate);
3895da86887SHeiner Kallweit if (ret) {
3905da86887SHeiner Kallweit dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
391844c8a75SJerome Brunet rate, ret);
3925da86887SHeiner Kallweit return ret;
3935da86887SHeiner Kallweit }
39451c5d844SKevin Hilman
395844c8a75SJerome Brunet host->req_rate = rate;
396bd911ec4SJerome Brunet mmc->actual_clock = clk_get_rate(host->mmc_clk);
3975da86887SHeiner Kallweit
398844c8a75SJerome Brunet /* We should report the real output frequency of the controller */
399dc38ac81SJerome Brunet if (ddr) {
400dc38ac81SJerome Brunet host->req_rate >>= 1;
401844c8a75SJerome Brunet mmc->actual_clock >>= 1;
402dc38ac81SJerome Brunet }
403844c8a75SJerome Brunet
404f89f55dfSJerome Brunet dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
405dc38ac81SJerome Brunet if (rate != mmc->actual_clock)
406dc38ac81SJerome Brunet dev_dbg(host->dev, "requested rate was %lu\n", rate);
4075da86887SHeiner Kallweit
4085da86887SHeiner Kallweit /* (re)start clock */
4091e03331dSJerome Brunet meson_mmc_clk_ungate(host);
41051c5d844SKevin Hilman
4115da86887SHeiner Kallweit return 0;
41251c5d844SKevin Hilman }
41351c5d844SKevin Hilman
41451c5d844SKevin Hilman /*
41551c5d844SKevin Hilman * The SD/eMMC IP block has an internal mux and divider used for
41651c5d844SKevin Hilman * generating the MMC clock. Use the clock framework to create and
41751c5d844SKevin Hilman * manage these clocks.
41851c5d844SKevin Hilman */
meson_mmc_clk_init(struct meson_host * host)41951c5d844SKevin Hilman static int meson_mmc_clk_init(struct meson_host *host)
42051c5d844SKevin Hilman {
42151c5d844SKevin Hilman struct clk_init_data init;
422bd911ec4SJerome Brunet struct clk_mux *mux;
423bd911ec4SJerome Brunet struct clk_divider *div;
42451c5d844SKevin Hilman char clk_name[32];
42551c5d844SKevin Hilman int i, ret = 0;
42651c5d844SKevin Hilman const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
427bd911ec4SJerome Brunet const char *clk_parent[1];
4283c39e2caSJerome Brunet u32 clk_reg;
42951c5d844SKevin Hilman
430ef5c4815SJerome Brunet /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
4315e6f75f4SJerome Brunet clk_reg = CLK_ALWAYS_ON(host);
432ef5c4815SJerome Brunet clk_reg |= CLK_DIV_MASK;
4335e6f75f4SJerome Brunet clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
4345e6f75f4SJerome Brunet clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
4355e6f75f4SJerome Brunet clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
4366ea6b95aSHeiner Kallweit if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
437066ecde6SHeiner Kallweit clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
438ef5c4815SJerome Brunet writel(clk_reg, host->regs + SD_EMMC_CLOCK);
439ef5c4815SJerome Brunet
44051c5d844SKevin Hilman /* get the mux parents */
44151c5d844SKevin Hilman for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
442e9883ef2SHeiner Kallweit struct clk *clk;
44351c5d844SKevin Hilman char name[16];
44451c5d844SKevin Hilman
44551c5d844SKevin Hilman snprintf(name, sizeof(name), "clkin%d", i);
446e9883ef2SHeiner Kallweit clk = devm_clk_get(host->dev, name);
44789280d09SKrzysztof Kozlowski if (IS_ERR(clk))
44889280d09SKrzysztof Kozlowski return dev_err_probe(host->dev, PTR_ERR(clk),
44989280d09SKrzysztof Kozlowski "Missing clock %s\n", name);
45051c5d844SKevin Hilman
451e9883ef2SHeiner Kallweit mux_parent_names[i] = __clk_get_name(clk);
45251c5d844SKevin Hilman }
45351c5d844SKevin Hilman
45451c5d844SKevin Hilman /* create the mux */
455bd911ec4SJerome Brunet mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
456bd911ec4SJerome Brunet if (!mux)
457bd911ec4SJerome Brunet return -ENOMEM;
458bd911ec4SJerome Brunet
45951c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
46051c5d844SKevin Hilman init.name = clk_name;
46151c5d844SKevin Hilman init.ops = &clk_mux_ops;
46251c5d844SKevin Hilman init.flags = 0;
46351c5d844SKevin Hilman init.parent_names = mux_parent_names;
4647558c113SHeiner Kallweit init.num_parents = MUX_CLK_NUM_PARENTS;
46551c5d844SKevin Hilman
466bd911ec4SJerome Brunet mux->reg = host->regs + SD_EMMC_CLOCK;
467795c633fSJerome Brunet mux->shift = __ffs(CLK_SRC_MASK);
468bd911ec4SJerome Brunet mux->mask = CLK_SRC_MASK >> mux->shift;
469bd911ec4SJerome Brunet mux->hw.init = &init;
470bd911ec4SJerome Brunet
4715e6f75f4SJerome Brunet host->mux_clk = devm_clk_register(host->dev, &mux->hw);
4725e6f75f4SJerome Brunet if (WARN_ON(IS_ERR(host->mux_clk)))
4735e6f75f4SJerome Brunet return PTR_ERR(host->mux_clk);
47451c5d844SKevin Hilman
47551c5d844SKevin Hilman /* create the divider */
476bd911ec4SJerome Brunet div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
477bd911ec4SJerome Brunet if (!div)
478bd911ec4SJerome Brunet return -ENOMEM;
479bd911ec4SJerome Brunet
48051c5d844SKevin Hilman snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
4817b9ebad3SHeiner Kallweit init.name = clk_name;
48251c5d844SKevin Hilman init.ops = &clk_divider_ops;
48351c5d844SKevin Hilman init.flags = CLK_SET_RATE_PARENT;
4845e6f75f4SJerome Brunet clk_parent[0] = __clk_get_name(host->mux_clk);
485bd911ec4SJerome Brunet init.parent_names = clk_parent;
486bd911ec4SJerome Brunet init.num_parents = 1;
48751c5d844SKevin Hilman
488bd911ec4SJerome Brunet div->reg = host->regs + SD_EMMC_CLOCK;
489795c633fSJerome Brunet div->shift = __ffs(CLK_DIV_MASK);
490bd911ec4SJerome Brunet div->width = __builtin_popcountl(CLK_DIV_MASK);
491bd911ec4SJerome Brunet div->hw.init = &init;
492ca3dcd3fSJerome Brunet div->flags = CLK_DIVIDER_ONE_BASED;
49351c5d844SKevin Hilman
4945e6f75f4SJerome Brunet host->mmc_clk = devm_clk_register(host->dev, &div->hw);
4955e6f75f4SJerome Brunet if (WARN_ON(IS_ERR(host->mmc_clk)))
496bd911ec4SJerome Brunet return PTR_ERR(host->mmc_clk);
49751c5d844SKevin Hilman
498bd911ec4SJerome Brunet /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
499bd911ec4SJerome Brunet host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
500bd911ec4SJerome Brunet ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
501a4c38c8dSUlf Hansson if (ret)
502a4c38c8dSUlf Hansson return ret;
50351c5d844SKevin Hilman
504bd911ec4SJerome Brunet return clk_prepare_enable(host->mmc_clk);
50551c5d844SKevin Hilman }
50651c5d844SKevin Hilman
meson_mmc_disable_resampling(struct meson_host * host)507f50b7ac5SJerome Brunet static void meson_mmc_disable_resampling(struct meson_host *host)
508f50b7ac5SJerome Brunet {
509f50b7ac5SJerome Brunet unsigned int val = readl(host->regs + host->data->adjust);
510f50b7ac5SJerome Brunet
511f50b7ac5SJerome Brunet val &= ~ADJUST_ADJ_EN;
512f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust);
513f50b7ac5SJerome Brunet }
514f50b7ac5SJerome Brunet
meson_mmc_reset_resampling(struct meson_host * host)515f50b7ac5SJerome Brunet static void meson_mmc_reset_resampling(struct meson_host *host)
516f50b7ac5SJerome Brunet {
517f50b7ac5SJerome Brunet unsigned int val;
518f50b7ac5SJerome Brunet
519f50b7ac5SJerome Brunet meson_mmc_disable_resampling(host);
520f50b7ac5SJerome Brunet
521f50b7ac5SJerome Brunet val = readl(host->regs + host->data->adjust);
522f50b7ac5SJerome Brunet val &= ~ADJUST_ADJ_DELAY_MASK;
523f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust);
524f50b7ac5SJerome Brunet }
525f50b7ac5SJerome Brunet
meson_mmc_resampling_tuning(struct mmc_host * mmc,u32 opcode)526f50b7ac5SJerome Brunet static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
527f50b7ac5SJerome Brunet {
528f50b7ac5SJerome Brunet struct meson_host *host = mmc_priv(mmc);
529f50b7ac5SJerome Brunet unsigned int val, dly, max_dly, i;
530f50b7ac5SJerome Brunet int ret;
531f50b7ac5SJerome Brunet
532f50b7ac5SJerome Brunet /* Resampling is done using the source clock */
533f50b7ac5SJerome Brunet max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
534f50b7ac5SJerome Brunet clk_get_rate(host->mmc_clk));
535f50b7ac5SJerome Brunet
536f50b7ac5SJerome Brunet val = readl(host->regs + host->data->adjust);
537f50b7ac5SJerome Brunet val |= ADJUST_ADJ_EN;
538f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust);
539f50b7ac5SJerome Brunet
540e0c29be6SWolfram Sang if (mmc_doing_retune(mmc))
541f50b7ac5SJerome Brunet dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
542f50b7ac5SJerome Brunet else
543f50b7ac5SJerome Brunet dly = 0;
544f50b7ac5SJerome Brunet
545f50b7ac5SJerome Brunet for (i = 0; i < max_dly; i++) {
546f50b7ac5SJerome Brunet val &= ~ADJUST_ADJ_DELAY_MASK;
547f50b7ac5SJerome Brunet val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
548f50b7ac5SJerome Brunet writel(val, host->regs + host->data->adjust);
549f50b7ac5SJerome Brunet
550f50b7ac5SJerome Brunet ret = mmc_send_tuning(mmc, opcode, NULL);
551f50b7ac5SJerome Brunet if (!ret) {
552f50b7ac5SJerome Brunet dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
553f50b7ac5SJerome Brunet (dly + i) % max_dly);
554f50b7ac5SJerome Brunet return 0;
555f50b7ac5SJerome Brunet }
556f50b7ac5SJerome Brunet }
557f50b7ac5SJerome Brunet
558f50b7ac5SJerome Brunet meson_mmc_reset_resampling(host);
559f50b7ac5SJerome Brunet return -EIO;
560f50b7ac5SJerome Brunet }
561f50b7ac5SJerome Brunet
meson_mmc_prepare_ios_clock(struct meson_host * host,struct mmc_ios * ios)562dc38ac81SJerome Brunet static int meson_mmc_prepare_ios_clock(struct meson_host *host,
563dc38ac81SJerome Brunet struct mmc_ios *ios)
564dc38ac81SJerome Brunet {
565dc38ac81SJerome Brunet bool ddr;
566dc38ac81SJerome Brunet
567dc38ac81SJerome Brunet switch (ios->timing) {
568dc38ac81SJerome Brunet case MMC_TIMING_MMC_DDR52:
569dc38ac81SJerome Brunet case MMC_TIMING_UHS_DDR50:
570dc38ac81SJerome Brunet ddr = true;
571dc38ac81SJerome Brunet break;
572dc38ac81SJerome Brunet
573dc38ac81SJerome Brunet default:
574dc38ac81SJerome Brunet ddr = false;
575dc38ac81SJerome Brunet break;
576dc38ac81SJerome Brunet }
577dc38ac81SJerome Brunet
578dc38ac81SJerome Brunet return meson_mmc_clk_set(host, ios->clock, ddr);
579dc38ac81SJerome Brunet }
580dc38ac81SJerome Brunet
meson_mmc_check_resampling(struct meson_host * host,struct mmc_ios * ios)581f50b7ac5SJerome Brunet static void meson_mmc_check_resampling(struct meson_host *host,
582f50b7ac5SJerome Brunet struct mmc_ios *ios)
583f50b7ac5SJerome Brunet {
584f50b7ac5SJerome Brunet switch (ios->timing) {
585f50b7ac5SJerome Brunet case MMC_TIMING_LEGACY:
586f50b7ac5SJerome Brunet case MMC_TIMING_MMC_HS:
587f50b7ac5SJerome Brunet case MMC_TIMING_SD_HS:
588f50b7ac5SJerome Brunet case MMC_TIMING_MMC_DDR52:
589f50b7ac5SJerome Brunet meson_mmc_disable_resampling(host);
590f50b7ac5SJerome Brunet break;
591f50b7ac5SJerome Brunet }
592f50b7ac5SJerome Brunet }
593f50b7ac5SJerome Brunet
meson_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)59451c5d844SKevin Hilman static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
59551c5d844SKevin Hilman {
59651c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc);
597c36cf125SJerome Brunet u32 bus_width, val;
598c36cf125SJerome Brunet int err;
59951c5d844SKevin Hilman
60051c5d844SKevin Hilman /*
60151c5d844SKevin Hilman * GPIO regulator, only controls switching between 1v8 and
60251c5d844SKevin Hilman * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
60351c5d844SKevin Hilman */
60451c5d844SKevin Hilman switch (ios->power_mode) {
60551c5d844SKevin Hilman case MMC_POWER_OFF:
60651c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
607e3f0d221SHeiner Kallweit mmc_regulator_disable_vqmmc(mmc);
60851c5d844SKevin Hilman
60951c5d844SKevin Hilman break;
61051c5d844SKevin Hilman
61151c5d844SKevin Hilman case MMC_POWER_UP:
61251c5d844SKevin Hilman mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
6133e2b0af4SJerome Brunet
61451c5d844SKevin Hilman break;
61551c5d844SKevin Hilman
61651c5d844SKevin Hilman case MMC_POWER_ON:
617e3f0d221SHeiner Kallweit mmc_regulator_enable_vqmmc(mmc);
61851c5d844SKevin Hilman
61951c5d844SKevin Hilman break;
62051c5d844SKevin Hilman }
62151c5d844SKevin Hilman
62251c5d844SKevin Hilman /* Bus width */
62351c5d844SKevin Hilman switch (ios->bus_width) {
62451c5d844SKevin Hilman case MMC_BUS_WIDTH_1:
62551c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_1;
62651c5d844SKevin Hilman break;
62751c5d844SKevin Hilman case MMC_BUS_WIDTH_4:
62851c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4;
62951c5d844SKevin Hilman break;
63051c5d844SKevin Hilman case MMC_BUS_WIDTH_8:
63151c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_8;
63251c5d844SKevin Hilman break;
63351c5d844SKevin Hilman default:
63451c5d844SKevin Hilman dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
63551c5d844SKevin Hilman ios->bus_width);
63651c5d844SKevin Hilman bus_width = CFG_BUS_WIDTH_4;
63751c5d844SKevin Hilman }
63851c5d844SKevin Hilman
63951c5d844SKevin Hilman val = readl(host->regs + SD_EMMC_CFG);
6401231e7ebSHeiner Kallweit val &= ~CFG_BUS_WIDTH_MASK;
6411231e7ebSHeiner Kallweit val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
642dc38ac81SJerome Brunet writel(val, host->regs + SD_EMMC_CFG);
64351c5d844SKevin Hilman
644f50b7ac5SJerome Brunet meson_mmc_check_resampling(host, ios);
645dc38ac81SJerome Brunet err = meson_mmc_prepare_ios_clock(host, ios);
646c36cf125SJerome Brunet if (err)
647c36cf125SJerome Brunet dev_err(host->dev, "Failed to set clock: %d\n,", err);
648c36cf125SJerome Brunet
649c36cf125SJerome Brunet dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
650c01d1219SHeiner Kallweit }
65151c5d844SKevin Hilman
meson_mmc_request_done(struct mmc_host * mmc,struct mmc_request * mrq)6523d6c991bSHeiner Kallweit static void meson_mmc_request_done(struct mmc_host *mmc,
6533d6c991bSHeiner Kallweit struct mmc_request *mrq)
65451c5d844SKevin Hilman {
65551c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc);
65651c5d844SKevin Hilman
65751c5d844SKevin Hilman host->cmd = NULL;
658f0d2f153SRong Chen if (host->needs_pre_post_req)
659f0d2f153SRong Chen meson_mmc_post_req(mmc, mrq, 0);
66051c5d844SKevin Hilman mmc_request_done(host->mmc, mrq);
66151c5d844SKevin Hilman }
66251c5d844SKevin Hilman
meson_mmc_set_blksz(struct mmc_host * mmc,unsigned int blksz)6633d03f6a9SHeiner Kallweit static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
6643d03f6a9SHeiner Kallweit {
6653d03f6a9SHeiner Kallweit struct meson_host *host = mmc_priv(mmc);
6663d03f6a9SHeiner Kallweit u32 cfg, blksz_old;
6673d03f6a9SHeiner Kallweit
6683d03f6a9SHeiner Kallweit cfg = readl(host->regs + SD_EMMC_CFG);
6693d03f6a9SHeiner Kallweit blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
6703d03f6a9SHeiner Kallweit
6713d03f6a9SHeiner Kallweit if (!is_power_of_2(blksz))
6723d03f6a9SHeiner Kallweit dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
6733d03f6a9SHeiner Kallweit
6743d03f6a9SHeiner Kallweit blksz = ilog2(blksz);
6753d03f6a9SHeiner Kallweit
6763d03f6a9SHeiner Kallweit /* check if block-size matches, if not update */
6773d03f6a9SHeiner Kallweit if (blksz == blksz_old)
6783d03f6a9SHeiner Kallweit return;
6793d03f6a9SHeiner Kallweit
6803d03f6a9SHeiner Kallweit dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
6813d03f6a9SHeiner Kallweit blksz_old, blksz);
6823d03f6a9SHeiner Kallweit
6833d03f6a9SHeiner Kallweit cfg &= ~CFG_BLK_LEN_MASK;
6843d03f6a9SHeiner Kallweit cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
6853d03f6a9SHeiner Kallweit writel(cfg, host->regs + SD_EMMC_CFG);
6863d03f6a9SHeiner Kallweit }
6873d03f6a9SHeiner Kallweit
meson_mmc_set_response_bits(struct mmc_command * cmd,u32 * cmd_cfg)68875c7fd96SHeiner Kallweit static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
68975c7fd96SHeiner Kallweit {
69075c7fd96SHeiner Kallweit if (cmd->flags & MMC_RSP_PRESENT) {
69175c7fd96SHeiner Kallweit if (cmd->flags & MMC_RSP_136)
69275c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_RESP_128;
69375c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_RESP_NUM;
69475c7fd96SHeiner Kallweit
69575c7fd96SHeiner Kallweit if (!(cmd->flags & MMC_RSP_CRC))
69675c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_RESP_NOCRC;
69775c7fd96SHeiner Kallweit
69875c7fd96SHeiner Kallweit if (cmd->flags & MMC_RSP_BUSY)
69975c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_R1B;
70075c7fd96SHeiner Kallweit } else {
70175c7fd96SHeiner Kallweit *cmd_cfg |= CMD_CFG_NO_RESP;
70275c7fd96SHeiner Kallweit }
70375c7fd96SHeiner Kallweit }
70475c7fd96SHeiner Kallweit
meson_mmc_desc_chain_transfer(struct mmc_host * mmc,u32 cmd_cfg)70579ed05e3SHeiner Kallweit static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
70679ed05e3SHeiner Kallweit {
70779ed05e3SHeiner Kallweit struct meson_host *host = mmc_priv(mmc);
70879ed05e3SHeiner Kallweit struct sd_emmc_desc *desc = host->descs;
70979ed05e3SHeiner Kallweit struct mmc_data *data = host->cmd->data;
71079ed05e3SHeiner Kallweit struct scatterlist *sg;
71179ed05e3SHeiner Kallweit u32 start;
71279ed05e3SHeiner Kallweit int i;
71379ed05e3SHeiner Kallweit
71479ed05e3SHeiner Kallweit if (data->flags & MMC_DATA_WRITE)
71579ed05e3SHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_WR;
71679ed05e3SHeiner Kallweit
71779ed05e3SHeiner Kallweit if (data->blocks > 1) {
71879ed05e3SHeiner Kallweit cmd_cfg |= CMD_CFG_BLOCK_MODE;
71979ed05e3SHeiner Kallweit meson_mmc_set_blksz(mmc, data->blksz);
72079ed05e3SHeiner Kallweit }
72179ed05e3SHeiner Kallweit
72279ed05e3SHeiner Kallweit for_each_sg(data->sg, sg, data->sg_count, i) {
72379ed05e3SHeiner Kallweit unsigned int len = sg_dma_len(sg);
72479ed05e3SHeiner Kallweit
72579ed05e3SHeiner Kallweit if (data->blocks > 1)
72679ed05e3SHeiner Kallweit len /= data->blksz;
72779ed05e3SHeiner Kallweit
72879ed05e3SHeiner Kallweit desc[i].cmd_cfg = cmd_cfg;
72979ed05e3SHeiner Kallweit desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
73079ed05e3SHeiner Kallweit if (i > 0)
73179ed05e3SHeiner Kallweit desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
73279ed05e3SHeiner Kallweit desc[i].cmd_arg = host->cmd->arg;
73379ed05e3SHeiner Kallweit desc[i].cmd_resp = 0;
73479ed05e3SHeiner Kallweit desc[i].cmd_data = sg_dma_address(sg);
73579ed05e3SHeiner Kallweit }
73679ed05e3SHeiner Kallweit desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
73779ed05e3SHeiner Kallweit
73879ed05e3SHeiner Kallweit dma_wmb(); /* ensure descriptor is written before kicked */
73979ed05e3SHeiner Kallweit start = host->descs_dma_addr | START_DESC_BUSY;
74079ed05e3SHeiner Kallweit writel(start, host->regs + SD_EMMC_START);
74179ed05e3SHeiner Kallweit }
74279ed05e3SHeiner Kallweit
7438a38a4d5SNeil Armstrong /* local sg copy for dram_access_quirk */
meson_mmc_copy_buffer(struct meson_host * host,struct mmc_data * data,size_t buflen,bool to_buffer)744103a5348SNeil Armstrong static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
745103a5348SNeil Armstrong size_t buflen, bool to_buffer)
746103a5348SNeil Armstrong {
747103a5348SNeil Armstrong unsigned int sg_flags = SG_MITER_ATOMIC;
748103a5348SNeil Armstrong struct scatterlist *sgl = data->sg;
749103a5348SNeil Armstrong unsigned int nents = data->sg_len;
750103a5348SNeil Armstrong struct sg_mapping_iter miter;
751103a5348SNeil Armstrong unsigned int offset = 0;
752103a5348SNeil Armstrong
753103a5348SNeil Armstrong if (to_buffer)
754103a5348SNeil Armstrong sg_flags |= SG_MITER_FROM_SG;
755103a5348SNeil Armstrong else
756103a5348SNeil Armstrong sg_flags |= SG_MITER_TO_SG;
757103a5348SNeil Armstrong
758103a5348SNeil Armstrong sg_miter_start(&miter, sgl, nents, sg_flags);
759103a5348SNeil Armstrong
760103a5348SNeil Armstrong while ((offset < buflen) && sg_miter_next(&miter)) {
7618a38a4d5SNeil Armstrong unsigned int buf_offset = 0;
7628a38a4d5SNeil Armstrong unsigned int len, left;
7638a38a4d5SNeil Armstrong u32 *buf = miter.addr;
764103a5348SNeil Armstrong
765103a5348SNeil Armstrong len = min(miter.length, buflen - offset);
7668a38a4d5SNeil Armstrong left = len;
767103a5348SNeil Armstrong
7688a38a4d5SNeil Armstrong if (to_buffer) {
7698a38a4d5SNeil Armstrong do {
7708a38a4d5SNeil Armstrong writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
7718a38a4d5SNeil Armstrong
7728a38a4d5SNeil Armstrong buf_offset += 4;
7738a38a4d5SNeil Armstrong left -= 4;
7748a38a4d5SNeil Armstrong } while (left);
775103a5348SNeil Armstrong } else {
7768a38a4d5SNeil Armstrong do {
7778a38a4d5SNeil Armstrong *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
7788a38a4d5SNeil Armstrong
7798a38a4d5SNeil Armstrong buf_offset += 4;
7808a38a4d5SNeil Armstrong left -= 4;
7818a38a4d5SNeil Armstrong } while (left);
782103a5348SNeil Armstrong }
783103a5348SNeil Armstrong
784103a5348SNeil Armstrong offset += len;
785103a5348SNeil Armstrong }
786103a5348SNeil Armstrong
787103a5348SNeil Armstrong sg_miter_stop(&miter);
788103a5348SNeil Armstrong }
789103a5348SNeil Armstrong
meson_mmc_start_cmd(struct mmc_host * mmc,struct mmc_command * cmd)79051c5d844SKevin Hilman static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
79151c5d844SKevin Hilman {
79251c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc);
79300412ddcSHeiner Kallweit struct mmc_data *data = cmd->data;
7943d03f6a9SHeiner Kallweit u32 cmd_cfg = 0, cmd_data = 0;
79551c5d844SKevin Hilman unsigned int xfer_bytes = 0;
79651c5d844SKevin Hilman
79751c5d844SKevin Hilman /* Setup descriptors */
79851c5d844SKevin Hilman dma_rmb();
79951c5d844SKevin Hilman
80079ed05e3SHeiner Kallweit host->cmd = cmd;
80179ed05e3SHeiner Kallweit
8021231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
803a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
80451c5d844SKevin Hilman
80575c7fd96SHeiner Kallweit meson_mmc_set_response_bits(cmd, &cmd_cfg);
80651c5d844SKevin Hilman
80751c5d844SKevin Hilman /* data? */
80800412ddcSHeiner Kallweit if (data) {
80979ed05e3SHeiner Kallweit data->bytes_xfered = 0;
810a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_IO;
8111231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
8124eee86c3SHeiner Kallweit ilog2(meson_mmc_get_timeout_msecs(data)));
813a744c6feSHeiner Kallweit
81479ed05e3SHeiner Kallweit if (meson_mmc_desc_chain_mode(data)) {
81579ed05e3SHeiner Kallweit meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
81679ed05e3SHeiner Kallweit return;
81779ed05e3SHeiner Kallweit }
81879ed05e3SHeiner Kallweit
81900412ddcSHeiner Kallweit if (data->blocks > 1) {
820a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_BLOCK_MODE;
8211231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
8221231e7ebSHeiner Kallweit data->blocks);
8233d03f6a9SHeiner Kallweit meson_mmc_set_blksz(mmc, data->blksz);
82451c5d844SKevin Hilman } else {
8251231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
82651c5d844SKevin Hilman }
82751c5d844SKevin Hilman
82800412ddcSHeiner Kallweit xfer_bytes = data->blksz * data->blocks;
82900412ddcSHeiner Kallweit if (data->flags & MMC_DATA_WRITE) {
830a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_DATA_WR;
83151c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size);
8328a38a4d5SNeil Armstrong if (host->dram_access_quirk)
833103a5348SNeil Armstrong meson_mmc_copy_buffer(host, data, xfer_bytes, true);
8348a38a4d5SNeil Armstrong else
8358a38a4d5SNeil Armstrong sg_copy_to_buffer(data->sg, data->sg_len,
8368a38a4d5SNeil Armstrong host->bounce_buf, xfer_bytes);
83751c5d844SKevin Hilman dma_wmb();
83851c5d844SKevin Hilman }
83951c5d844SKevin Hilman
840a322febeSHeiner Kallweit cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
84151c5d844SKevin Hilman } else {
8421231e7ebSHeiner Kallweit cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
8431231e7ebSHeiner Kallweit ilog2(SD_EMMC_CMD_TIMEOUT));
84451c5d844SKevin Hilman }
84551c5d844SKevin Hilman
84651c5d844SKevin Hilman /* Last descriptor */
847a322febeSHeiner Kallweit cmd_cfg |= CMD_CFG_END_OF_CHAIN;
848a322febeSHeiner Kallweit writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
849a322febeSHeiner Kallweit writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
850a322febeSHeiner Kallweit writel(0, host->regs + SD_EMMC_CMD_RSP);
85151c5d844SKevin Hilman wmb(); /* ensure descriptor is written before kicked */
852a322febeSHeiner Kallweit writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
85351c5d844SKevin Hilman }
85451c5d844SKevin Hilman
meson_mmc_validate_dram_access(struct mmc_host * mmc,struct mmc_data * data)8558a38a4d5SNeil Armstrong static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
8568a38a4d5SNeil Armstrong {
8578a38a4d5SNeil Armstrong struct scatterlist *sg;
8588a38a4d5SNeil Armstrong int i;
8598a38a4d5SNeil Armstrong
8608a38a4d5SNeil Armstrong /* Reject request if any element offset or size is not 32bit aligned */
8618a38a4d5SNeil Armstrong for_each_sg(data->sg, sg, data->sg_len, i) {
8628a38a4d5SNeil Armstrong if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
8638a38a4d5SNeil Armstrong !IS_ALIGNED(sg->length, sizeof(u32))) {
8648a38a4d5SNeil Armstrong dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
8658a38a4d5SNeil Armstrong data->sg->offset, data->sg->length);
8668a38a4d5SNeil Armstrong return -EINVAL;
8678a38a4d5SNeil Armstrong }
8688a38a4d5SNeil Armstrong }
8698a38a4d5SNeil Armstrong
8708a38a4d5SNeil Armstrong return 0;
8718a38a4d5SNeil Armstrong }
8728a38a4d5SNeil Armstrong
meson_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)87351c5d844SKevin Hilman static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
87451c5d844SKevin Hilman {
87551c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc);
876f0d2f153SRong Chen host->needs_pre_post_req = mrq->data &&
87779ed05e3SHeiner Kallweit !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
87879ed05e3SHeiner Kallweit
8798a38a4d5SNeil Armstrong /*
8808a38a4d5SNeil Armstrong * The memory at the end of the controller used as bounce buffer for
8818a38a4d5SNeil Armstrong * the dram_access_quirk only accepts 32bit read/write access,
8828a38a4d5SNeil Armstrong * check the aligment and length of the data before starting the request.
8838a38a4d5SNeil Armstrong */
8848a38a4d5SNeil Armstrong if (host->dram_access_quirk && mrq->data) {
8858a38a4d5SNeil Armstrong mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
8868a38a4d5SNeil Armstrong if (mrq->cmd->error) {
8878a38a4d5SNeil Armstrong mmc_request_done(mmc, mrq);
8888a38a4d5SNeil Armstrong return;
8898a38a4d5SNeil Armstrong }
8908a38a4d5SNeil Armstrong }
8918a38a4d5SNeil Armstrong
892f0d2f153SRong Chen if (host->needs_pre_post_req) {
89379ed05e3SHeiner Kallweit meson_mmc_get_transfer_mode(mmc, mrq);
89479ed05e3SHeiner Kallweit if (!meson_mmc_desc_chain_mode(mrq->data))
895f0d2f153SRong Chen host->needs_pre_post_req = false;
89679ed05e3SHeiner Kallweit }
89779ed05e3SHeiner Kallweit
898f0d2f153SRong Chen if (host->needs_pre_post_req)
89979ed05e3SHeiner Kallweit meson_mmc_pre_req(mmc, mrq);
90051c5d844SKevin Hilman
90151c5d844SKevin Hilman /* Stop execution */
90251c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START);
90351c5d844SKevin Hilman
90479ed05e3SHeiner Kallweit meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
90551c5d844SKevin Hilman }
90651c5d844SKevin Hilman
meson_mmc_read_resp(struct mmc_host * mmc,struct mmc_command * cmd)9073d6c991bSHeiner Kallweit static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
90851c5d844SKevin Hilman {
90951c5d844SKevin Hilman struct meson_host *host = mmc_priv(mmc);
91051c5d844SKevin Hilman
91151c5d844SKevin Hilman if (cmd->flags & MMC_RSP_136) {
91251c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
91351c5d844SKevin Hilman cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
91451c5d844SKevin Hilman cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
91551c5d844SKevin Hilman cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
91651c5d844SKevin Hilman } else if (cmd->flags & MMC_RSP_PRESENT) {
91751c5d844SKevin Hilman cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
91851c5d844SKevin Hilman }
91951c5d844SKevin Hilman }
92051c5d844SKevin Hilman
__meson_mmc_enable_sdio_irq(struct mmc_host * mmc,int enable)921066ecde6SHeiner Kallweit static void __meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
922066ecde6SHeiner Kallweit {
923066ecde6SHeiner Kallweit struct meson_host *host = mmc_priv(mmc);
924066ecde6SHeiner Kallweit u32 reg_irqen = IRQ_EN_MASK;
925066ecde6SHeiner Kallweit
926066ecde6SHeiner Kallweit if (enable)
927066ecde6SHeiner Kallweit reg_irqen |= IRQ_SDIO;
928066ecde6SHeiner Kallweit writel(reg_irqen, host->regs + SD_EMMC_IRQ_EN);
929066ecde6SHeiner Kallweit }
930066ecde6SHeiner Kallweit
meson_mmc_irq(int irq,void * dev_id)93151c5d844SKevin Hilman static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
93251c5d844SKevin Hilman {
93351c5d844SKevin Hilman struct meson_host *host = dev_id;
93419a91dd4SHeinrich Schuchardt struct mmc_command *cmd;
9356ea6b95aSHeiner Kallweit u32 status, raw_status, irq_mask = IRQ_EN_MASK;
93674858655SJerome Brunet irqreturn_t ret = IRQ_NONE;
93751c5d844SKevin Hilman
9386ea6b95aSHeiner Kallweit if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
9396ea6b95aSHeiner Kallweit irq_mask |= IRQ_SDIO;
94018f92bc0SJerome Brunet raw_status = readl(host->regs + SD_EMMC_STATUS);
9416ea6b95aSHeiner Kallweit status = raw_status & irq_mask;
94218f92bc0SJerome Brunet
94318f92bc0SJerome Brunet if (!status) {
94418f92bc0SJerome Brunet dev_dbg(host->dev,
9456ea6b95aSHeiner Kallweit "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
9466ea6b95aSHeiner Kallweit irq_mask, raw_status);
94718f92bc0SJerome Brunet return IRQ_NONE;
94818f92bc0SJerome Brunet }
94918f92bc0SJerome Brunet
950c2c1e63aSJerome Brunet /* ack all raised interrupts */
951c2c1e63aSJerome Brunet writel(status, host->regs + SD_EMMC_STATUS);
952c2c1e63aSJerome Brunet
95374858655SJerome Brunet cmd = host->cmd;
954066ecde6SHeiner Kallweit
955066ecde6SHeiner Kallweit if (status & IRQ_SDIO) {
956066ecde6SHeiner Kallweit spin_lock(&host->lock);
957066ecde6SHeiner Kallweit __meson_mmc_enable_sdio_irq(host->mmc, 0);
958066ecde6SHeiner Kallweit sdio_signal_irq(host->mmc);
959066ecde6SHeiner Kallweit spin_unlock(&host->lock);
960066ecde6SHeiner Kallweit status &= ~IRQ_SDIO;
961066ecde6SHeiner Kallweit if (!status)
962066ecde6SHeiner Kallweit return IRQ_HANDLED;
963066ecde6SHeiner Kallweit }
964066ecde6SHeiner Kallweit
965066ecde6SHeiner Kallweit if (WARN_ON(!cmd))
966066ecde6SHeiner Kallweit return IRQ_NONE;
967066ecde6SHeiner Kallweit
96874858655SJerome Brunet cmd->error = 0;
96974858655SJerome Brunet if (status & IRQ_CRC_ERR) {
97074858655SJerome Brunet dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
97174858655SJerome Brunet cmd->error = -EILSEQ;
97218f92bc0SJerome Brunet ret = IRQ_WAKE_THREAD;
97374858655SJerome Brunet goto out;
97474858655SJerome Brunet }
97574858655SJerome Brunet
97674858655SJerome Brunet if (status & IRQ_TIMEOUTS) {
97774858655SJerome Brunet dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
97874858655SJerome Brunet cmd->error = -ETIMEDOUT;
97918f92bc0SJerome Brunet ret = IRQ_WAKE_THREAD;
98051c5d844SKevin Hilman goto out;
98151c5d844SKevin Hilman }
98251c5d844SKevin Hilman
9831f8066d9SHeiner Kallweit meson_mmc_read_resp(host->mmc, cmd);
9841f8066d9SHeiner Kallweit
9852c8d96a4SHeiner Kallweit if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
986066ecde6SHeiner Kallweit struct mmc_data *data = cmd->data;
987066ecde6SHeiner Kallweit
9882c8d96a4SHeiner Kallweit if (data && !cmd->error)
9892c8d96a4SHeiner Kallweit data->bytes_xfered = data->blksz * data->blocks;
9903c40eb81SMartin Hundebøll
9913c40eb81SMartin Hundebøll return IRQ_WAKE_THREAD;
99251c5d844SKevin Hilman }
99351c5d844SKevin Hilman
99451c5d844SKevin Hilman out:
99518f92bc0SJerome Brunet if (cmd->error) {
99618f92bc0SJerome Brunet /* Stop desc in case of errors */
99718f92bc0SJerome Brunet u32 start = readl(host->regs + SD_EMMC_START);
99818f92bc0SJerome Brunet
99918f92bc0SJerome Brunet start &= ~START_DESC_BUSY;
100018f92bc0SJerome Brunet writel(start, host->regs + SD_EMMC_START);
100118f92bc0SJerome Brunet }
100218f92bc0SJerome Brunet
100351c5d844SKevin Hilman return ret;
100451c5d844SKevin Hilman }
100551c5d844SKevin Hilman
meson_mmc_wait_desc_stop(struct meson_host * host)100618f92bc0SJerome Brunet static int meson_mmc_wait_desc_stop(struct meson_host *host)
100718f92bc0SJerome Brunet {
100818f92bc0SJerome Brunet u32 status;
100918f92bc0SJerome Brunet
101018f92bc0SJerome Brunet /*
101118f92bc0SJerome Brunet * It may sometimes take a while for it to actually halt. Here, we
101218f92bc0SJerome Brunet * are giving it 5ms to comply
101318f92bc0SJerome Brunet *
101418f92bc0SJerome Brunet * If we don't confirm the descriptor is stopped, it might raise new
101518f92bc0SJerome Brunet * IRQs after we have called mmc_request_done() which is bad.
101618f92bc0SJerome Brunet */
101718f92bc0SJerome Brunet
101898849da6SJerome Brunet return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
101998849da6SJerome Brunet !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
102098849da6SJerome Brunet 100, 5000);
102118f92bc0SJerome Brunet }
102218f92bc0SJerome Brunet
meson_mmc_irq_thread(int irq,void * dev_id)102351c5d844SKevin Hilman static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
102451c5d844SKevin Hilman {
102551c5d844SKevin Hilman struct meson_host *host = dev_id;
1026e5e4a3ebSHeiner Kallweit struct mmc_command *next_cmd, *cmd = host->cmd;
102751c5d844SKevin Hilman struct mmc_data *data;
102851c5d844SKevin Hilman unsigned int xfer_bytes;
102951c5d844SKevin Hilman
103051c5d844SKevin Hilman if (WARN_ON(!cmd))
103119a91dd4SHeinrich Schuchardt return IRQ_NONE;
103251c5d844SKevin Hilman
103318f92bc0SJerome Brunet if (cmd->error) {
103418f92bc0SJerome Brunet meson_mmc_wait_desc_stop(host);
103518f92bc0SJerome Brunet meson_mmc_request_done(host->mmc, cmd->mrq);
103618f92bc0SJerome Brunet
103718f92bc0SJerome Brunet return IRQ_HANDLED;
103818f92bc0SJerome Brunet }
103918f92bc0SJerome Brunet
104051c5d844SKevin Hilman data = cmd->data;
104179ed05e3SHeiner Kallweit if (meson_mmc_bounce_buf_read(data)) {
104251c5d844SKevin Hilman xfer_bytes = data->blksz * data->blocks;
104351c5d844SKevin Hilman WARN_ON(xfer_bytes > host->bounce_buf_size);
10448a38a4d5SNeil Armstrong if (host->dram_access_quirk)
1045103a5348SNeil Armstrong meson_mmc_copy_buffer(host, data, xfer_bytes, false);
10468a38a4d5SNeil Armstrong else
10478a38a4d5SNeil Armstrong sg_copy_from_buffer(data->sg, data->sg_len,
10488a38a4d5SNeil Armstrong host->bounce_buf, xfer_bytes);
104951c5d844SKevin Hilman }
105051c5d844SKevin Hilman
1051e5e4a3ebSHeiner Kallweit next_cmd = meson_mmc_get_next_command(cmd);
1052e5e4a3ebSHeiner Kallweit if (next_cmd)
1053e5e4a3ebSHeiner Kallweit meson_mmc_start_cmd(host->mmc, next_cmd);
105451c5d844SKevin Hilman else
1055e5e4a3ebSHeiner Kallweit meson_mmc_request_done(host->mmc, cmd->mrq);
105651c5d844SKevin Hilman
1057690f90b6SHeiner Kallweit return IRQ_HANDLED;
105851c5d844SKevin Hilman }
105951c5d844SKevin Hilman
meson_mmc_cfg_init(struct meson_host * host)1060c01d1219SHeiner Kallweit static void meson_mmc_cfg_init(struct meson_host *host)
1061c01d1219SHeiner Kallweit {
106271e3e00cSAndreas Fenkart u32 cfg = 0;
1063c01d1219SHeiner Kallweit
10641231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
10651231e7ebSHeiner Kallweit ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
10661231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
10671231e7ebSHeiner Kallweit cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1068c01d1219SHeiner Kallweit
106918f92bc0SJerome Brunet /* abort chain on R/W errors */
107018f92bc0SJerome Brunet cfg |= CFG_ERR_ABORT;
107118f92bc0SJerome Brunet
1072c01d1219SHeiner Kallweit writel(cfg, host->regs + SD_EMMC_CFG);
1073c01d1219SHeiner Kallweit }
1074c01d1219SHeiner Kallweit
meson_mmc_card_busy(struct mmc_host * mmc)1075186cd8b7SJerome Brunet static int meson_mmc_card_busy(struct mmc_host *mmc)
1076186cd8b7SJerome Brunet {
1077186cd8b7SJerome Brunet struct meson_host *host = mmc_priv(mmc);
1078186cd8b7SJerome Brunet u32 regval;
1079186cd8b7SJerome Brunet
1080186cd8b7SJerome Brunet regval = readl(host->regs + SD_EMMC_STATUS);
1081186cd8b7SJerome Brunet
1082186cd8b7SJerome Brunet /* We are only interrested in lines 0 to 3, so mask the other ones */
1083186cd8b7SJerome Brunet return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1084186cd8b7SJerome Brunet }
1085186cd8b7SJerome Brunet
meson_mmc_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1086b1231b2fSJerome Brunet static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1087b1231b2fSJerome Brunet {
10889cbe0fc8SMarek Vasut int ret;
10899cbe0fc8SMarek Vasut
1090b1231b2fSJerome Brunet /* vqmmc regulator is available */
1091b1231b2fSJerome Brunet if (!IS_ERR(mmc->supply.vqmmc)) {
1092b1231b2fSJerome Brunet /*
1093b1231b2fSJerome Brunet * The usual amlogic setup uses a GPIO to switch from one
1094b1231b2fSJerome Brunet * regulator to the other. While the voltage ramp up is
1095b1231b2fSJerome Brunet * pretty fast, care must be taken when switching from 3.3v
1096b1231b2fSJerome Brunet * to 1.8v. Please make sure the regulator framework is aware
1097b1231b2fSJerome Brunet * of your own regulator constraints
1098b1231b2fSJerome Brunet */
10999cbe0fc8SMarek Vasut ret = mmc_regulator_set_vqmmc(mmc, ios);
11009cbe0fc8SMarek Vasut return ret < 0 ? ret : 0;
1101b1231b2fSJerome Brunet }
1102b1231b2fSJerome Brunet
1103b1231b2fSJerome Brunet /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1104b1231b2fSJerome Brunet if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1105b1231b2fSJerome Brunet return 0;
1106b1231b2fSJerome Brunet
1107b1231b2fSJerome Brunet return -EINVAL;
1108b1231b2fSJerome Brunet }
1109b1231b2fSJerome Brunet
meson_mmc_enable_sdio_irq(struct mmc_host * mmc,int enable)1110066ecde6SHeiner Kallweit static void meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1111066ecde6SHeiner Kallweit {
1112066ecde6SHeiner Kallweit struct meson_host *host = mmc_priv(mmc);
1113066ecde6SHeiner Kallweit unsigned long flags;
1114066ecde6SHeiner Kallweit
1115066ecde6SHeiner Kallweit spin_lock_irqsave(&host->lock, flags);
1116066ecde6SHeiner Kallweit __meson_mmc_enable_sdio_irq(mmc, enable);
1117066ecde6SHeiner Kallweit spin_unlock_irqrestore(&host->lock, flags);
1118066ecde6SHeiner Kallweit }
1119066ecde6SHeiner Kallweit
meson_mmc_ack_sdio_irq(struct mmc_host * mmc)1120066ecde6SHeiner Kallweit static void meson_mmc_ack_sdio_irq(struct mmc_host *mmc)
1121066ecde6SHeiner Kallweit {
1122066ecde6SHeiner Kallweit meson_mmc_enable_sdio_irq(mmc, 1);
1123066ecde6SHeiner Kallweit }
1124066ecde6SHeiner Kallweit
112551c5d844SKevin Hilman static const struct mmc_host_ops meson_mmc_ops = {
112651c5d844SKevin Hilman .request = meson_mmc_request,
112751c5d844SKevin Hilman .set_ios = meson_mmc_set_ios,
112891a3cba7SHeiner Kallweit .get_cd = mmc_gpio_get_cd,
112979ed05e3SHeiner Kallweit .pre_req = meson_mmc_pre_req,
113079ed05e3SHeiner Kallweit .post_req = meson_mmc_post_req,
1131f50b7ac5SJerome Brunet .execute_tuning = meson_mmc_resampling_tuning,
1132186cd8b7SJerome Brunet .card_busy = meson_mmc_card_busy,
1133b1231b2fSJerome Brunet .start_signal_voltage_switch = meson_mmc_voltage_switch,
1134066ecde6SHeiner Kallweit .enable_sdio_irq = meson_mmc_enable_sdio_irq,
1135066ecde6SHeiner Kallweit .ack_sdio_irq = meson_mmc_ack_sdio_irq,
113651c5d844SKevin Hilman };
113751c5d844SKevin Hilman
meson_mmc_probe(struct platform_device * pdev)113851c5d844SKevin Hilman static int meson_mmc_probe(struct platform_device *pdev)
113951c5d844SKevin Hilman {
114051c5d844SKevin Hilman struct resource *res;
114151c5d844SKevin Hilman struct meson_host *host;
114251c5d844SKevin Hilman struct mmc_host *mmc;
11434c4fe4f0SHeiner Kallweit struct clk *core_clk;
1144a543f702SHeiner Kallweit int cd_irq, ret;
114551c5d844SKevin Hilman
1146418f7c2dSHeiner Kallweit mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct meson_host));
114751c5d844SKevin Hilman if (!mmc)
114851c5d844SKevin Hilman return -ENOMEM;
114951c5d844SKevin Hilman host = mmc_priv(mmc);
115051c5d844SKevin Hilman host->mmc = mmc;
115151c5d844SKevin Hilman host->dev = &pdev->dev;
115251c5d844SKevin Hilman dev_set_drvdata(&pdev->dev, host);
115351c5d844SKevin Hilman
1154acdc8e71SNeil Armstrong /* The G12A SDIO Controller needs an SRAM bounce buffer */
1155acdc8e71SNeil Armstrong host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1156acdc8e71SNeil Armstrong "amlogic,dram-access-quirk");
1157acdc8e71SNeil Armstrong
115851c5d844SKevin Hilman /* Get regulators and the supported OCR mask */
115951c5d844SKevin Hilman ret = mmc_regulator_get_supply(mmc);
1160fa54f3e3SWolfram Sang if (ret)
1161418f7c2dSHeiner Kallweit return ret;
116251c5d844SKevin Hilman
116351c5d844SKevin Hilman ret = mmc_of_parse(mmc);
1164418f7c2dSHeiner Kallweit if (ret)
1165418f7c2dSHeiner Kallweit return dev_err_probe(&pdev->dev, ret, "error parsing DT\n");
116651c5d844SKevin Hilman
11676ea6b95aSHeiner Kallweit mmc->caps |= MMC_CAP_CMD23;
11686ea6b95aSHeiner Kallweit
11696ea6b95aSHeiner Kallweit if (mmc->caps & MMC_CAP_SDIO_IRQ)
11706ea6b95aSHeiner Kallweit mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
11716ea6b95aSHeiner Kallweit
1172c5a66dd8SHeiner Kallweit host->data = of_device_get_match_data(&pdev->dev);
1173418f7c2dSHeiner Kallweit if (!host->data)
1174418f7c2dSHeiner Kallweit return -EINVAL;
1175df069815SNan Li
117619c6beaaSJerome Brunet ret = device_reset_optional(&pdev->dev);
1177418f7c2dSHeiner Kallweit if (ret)
1178418f7c2dSHeiner Kallweit return dev_err_probe(&pdev->dev, ret, "device reset failed\n");
117919c6beaaSJerome Brunet
1180571f2351SYang Li host->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1181418f7c2dSHeiner Kallweit if (IS_ERR(host->regs))
1182418f7c2dSHeiner Kallweit return PTR_ERR(host->regs);
118351c5d844SKevin Hilman
1184bb364890SRemi Pommarel host->irq = platform_get_irq(pdev, 0);
1185b8ada54fSSergey Shtylyov if (host->irq < 0)
1186b8ada54fSSergey Shtylyov return host->irq;
118751c5d844SKevin Hilman
1188a543f702SHeiner Kallweit cd_irq = platform_get_irq_optional(pdev, 1);
1189a543f702SHeiner Kallweit mmc_gpio_set_cd_irq(mmc, cd_irq);
1190a543f702SHeiner Kallweit
11911e03331dSJerome Brunet host->pinctrl = devm_pinctrl_get(&pdev->dev);
1192418f7c2dSHeiner Kallweit if (IS_ERR(host->pinctrl))
1193418f7c2dSHeiner Kallweit return PTR_ERR(host->pinctrl);
11941e03331dSJerome Brunet
11951e03331dSJerome Brunet host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
11961e03331dSJerome Brunet "clk-gate");
11971e03331dSJerome Brunet if (IS_ERR(host->pins_clk_gate)) {
11981e03331dSJerome Brunet dev_warn(&pdev->dev,
11991e03331dSJerome Brunet "can't get clk-gate pinctrl, using clk_stop bit\n");
12001e03331dSJerome Brunet host->pins_clk_gate = NULL;
12011e03331dSJerome Brunet }
12021e03331dSJerome Brunet
12034c4fe4f0SHeiner Kallweit core_clk = devm_clk_get_enabled(&pdev->dev, "core");
12044c4fe4f0SHeiner Kallweit if (IS_ERR(core_clk))
12054c4fe4f0SHeiner Kallweit return PTR_ERR(core_clk);
120651c5d844SKevin Hilman
120751c5d844SKevin Hilman ret = meson_mmc_clk_init(host);
120851c5d844SKevin Hilman if (ret)
12094c4fe4f0SHeiner Kallweit return ret;
121051c5d844SKevin Hilman
12113c39e2caSJerome Brunet /* set config to sane default */
12123c39e2caSJerome Brunet meson_mmc_cfg_init(host);
12133c39e2caSJerome Brunet
121451c5d844SKevin Hilman /* Stop execution */
121551c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_START);
121651c5d844SKevin Hilman
121774858655SJerome Brunet /* clear, ack and enable interrupts */
121851c5d844SKevin Hilman writel(0, host->regs + SD_EMMC_IRQ_EN);
12196f6fac8aSHeiner Kallweit writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
12206f6fac8aSHeiner Kallweit writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);
122151c5d844SKevin Hilman
1222bb364890SRemi Pommarel ret = request_threaded_irq(host->irq, meson_mmc_irq,
1223eb4d8112SJerome Brunet meson_mmc_irq_thread, IRQF_ONESHOT,
122483e418a8SMartin Blumenstingl dev_name(&pdev->dev), host);
122551c5d844SKevin Hilman if (ret)
1226bd911ec4SJerome Brunet goto err_init_clk;
122751c5d844SKevin Hilman
1228066ecde6SHeiner Kallweit spin_lock_init(&host->lock);
1229066ecde6SHeiner Kallweit
1230acdc8e71SNeil Armstrong if (host->dram_access_quirk) {
123127a5e7d3SNeil Armstrong /* Limit segments to 1 due to low available sram memory */
123227a5e7d3SNeil Armstrong mmc->max_segs = 1;
1233acdc8e71SNeil Armstrong /* Limit to the available sram memory */
123427a5e7d3SNeil Armstrong mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
123527a5e7d3SNeil Armstrong mmc->max_blk_size;
1236acdc8e71SNeil Armstrong } else {
1237efe0b669SHeiner Kallweit mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1238acdc8e71SNeil Armstrong mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1239acdc8e71SNeil Armstrong sizeof(struct sd_emmc_desc);
1240acdc8e71SNeil Armstrong }
1241efe0b669SHeiner Kallweit mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
124279ed05e3SHeiner Kallweit mmc->max_seg_size = mmc->max_req_size;
1243efe0b669SHeiner Kallweit
1244d5f758f2SJerome Brunet /*
1245d5f758f2SJerome Brunet * At the moment, we don't know how to reliably enable HS400.
1246d5f758f2SJerome Brunet * From the different datasheets, it is not even clear if this mode
1247d5f758f2SJerome Brunet * is officially supported by any of the SoCs
1248d5f758f2SJerome Brunet */
1249d5f758f2SJerome Brunet mmc->caps2 &= ~MMC_CAP2_HS400;
1250d5f758f2SJerome Brunet
1251acdc8e71SNeil Armstrong if (host->dram_access_quirk) {
1252acdc8e71SNeil Armstrong /*
1253acdc8e71SNeil Armstrong * The MMC Controller embeds 1,5KiB of internal SRAM
1254acdc8e71SNeil Armstrong * that can be used to be used as bounce buffer.
1255acdc8e71SNeil Armstrong * In the case of the G12A SDIO controller, use these
1256acdc8e71SNeil Armstrong * instead of the DDR memory
1257acdc8e71SNeil Armstrong */
1258acdc8e71SNeil Armstrong host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1259103a5348SNeil Armstrong host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1260acdc8e71SNeil Armstrong host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1261acdc8e71SNeil Armstrong } else {
126251c5d844SKevin Hilman /* data bounce buffer */
12634136fcb5SHeiner Kallweit host->bounce_buf_size = mmc->max_req_size;
126451c5d844SKevin Hilman host->bounce_buf =
1265238b638bSHeiner Kallweit dmam_alloc_coherent(host->dev, host->bounce_buf_size,
126651c5d844SKevin Hilman &host->bounce_dma_addr, GFP_KERNEL);
126751c5d844SKevin Hilman if (host->bounce_buf == NULL) {
126851c5d844SKevin Hilman dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
126951c5d844SKevin Hilman ret = -ENOMEM;
1270bb364890SRemi Pommarel goto err_free_irq;
127151c5d844SKevin Hilman }
1272acdc8e71SNeil Armstrong }
127351c5d844SKevin Hilman
1274238b638bSHeiner Kallweit host->descs = dmam_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
127579ed05e3SHeiner Kallweit &host->descs_dma_addr, GFP_KERNEL);
127679ed05e3SHeiner Kallweit if (!host->descs) {
127779ed05e3SHeiner Kallweit dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
127879ed05e3SHeiner Kallweit ret = -ENOMEM;
1279238b638bSHeiner Kallweit goto err_free_irq;
128079ed05e3SHeiner Kallweit }
128179ed05e3SHeiner Kallweit
128251c5d844SKevin Hilman mmc->ops = &meson_mmc_ops;
128390935f16SYang Yingliang ret = mmc_add_host(mmc);
128490935f16SYang Yingliang if (ret)
128590935f16SYang Yingliang goto err_free_irq;
128651c5d844SKevin Hilman
128751c5d844SKevin Hilman return 0;
128851c5d844SKevin Hilman
1289bb364890SRemi Pommarel err_free_irq:
1290bb364890SRemi Pommarel free_irq(host->irq, host);
1291bd911ec4SJerome Brunet err_init_clk:
1292bd911ec4SJerome Brunet clk_disable_unprepare(host->mmc_clk);
129351c5d844SKevin Hilman return ret;
129451c5d844SKevin Hilman }
129551c5d844SKevin Hilman
meson_mmc_remove(struct platform_device * pdev)1296*e50aed55SYangtao Li static void meson_mmc_remove(struct platform_device *pdev)
129751c5d844SKevin Hilman {
129851c5d844SKevin Hilman struct meson_host *host = dev_get_drvdata(&pdev->dev);
129951c5d844SKevin Hilman
1300a01fc2a2SMichał Zegan mmc_remove_host(host->mmc);
1301a01fc2a2SMichał Zegan
130292763b99SHeiner Kallweit /* disable interrupts */
130392763b99SHeiner Kallweit writel(0, host->regs + SD_EMMC_IRQ_EN);
1304bb364890SRemi Pommarel free_irq(host->irq, host);
130592763b99SHeiner Kallweit
1306bd911ec4SJerome Brunet clk_disable_unprepare(host->mmc_clk);
130751c5d844SKevin Hilman }
130851c5d844SKevin Hilman
1309df069815SNan Li static const struct meson_mmc_data meson_gx_data = {
1310df069815SNan Li .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1311df069815SNan Li .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1312df069815SNan Li .always_on = CLK_V2_ALWAYS_ON,
131371645e65SJerome Brunet .adjust = SD_EMMC_ADJUST,
1314066ecde6SHeiner Kallweit .irq_sdio_sleep = CLK_V2_IRQ_SDIO_SLEEP,
1315df069815SNan Li };
1316df069815SNan Li
1317df069815SNan Li static const struct meson_mmc_data meson_axg_data = {
1318df069815SNan Li .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1319df069815SNan Li .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1320df069815SNan Li .always_on = CLK_V3_ALWAYS_ON,
132171645e65SJerome Brunet .adjust = SD_EMMC_V3_ADJUST,
1322066ecde6SHeiner Kallweit .irq_sdio_sleep = CLK_V3_IRQ_SDIO_SLEEP,
1323df069815SNan Li };
1324df069815SNan Li
132551c5d844SKevin Hilman static const struct of_device_id meson_mmc_of_match[] = {
1326df069815SNan Li { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1327df069815SNan Li { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1328df069815SNan Li { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1329df069815SNan Li { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1330df069815SNan Li { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
133151c5d844SKevin Hilman {}
133251c5d844SKevin Hilman };
133351c5d844SKevin Hilman MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
133451c5d844SKevin Hilman
133551c5d844SKevin Hilman static struct platform_driver meson_mmc_driver = {
133651c5d844SKevin Hilman .probe = meson_mmc_probe,
1337*e50aed55SYangtao Li .remove_new = meson_mmc_remove,
133851c5d844SKevin Hilman .driver = {
133951c5d844SKevin Hilman .name = DRIVER_NAME,
13407320915cSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1341e2c01e91SKrzysztof Kozlowski .of_match_table = meson_mmc_of_match,
134251c5d844SKevin Hilman },
134351c5d844SKevin Hilman };
134451c5d844SKevin Hilman
134551c5d844SKevin Hilman module_platform_driver(meson_mmc_driver);
134651c5d844SKevin Hilman
1347e79dc1b4SNan Li MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
134851c5d844SKevin Hilman MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
134951c5d844SKevin Hilman MODULE_LICENSE("GPL v2");
1350