1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 4 * Copyright (C) 2013, Imagination Technologies 5 * 6 * JZ4740 SD/MMC controller driver 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/slot-gpio.h> 20 #include <linux/module.h> 21 #include <linux/of_device.h> 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/platform_device.h> 24 #include <linux/scatterlist.h> 25 26 #include <asm/cacheflush.h> 27 28 #define JZ_REG_MMC_STRPCL 0x00 29 #define JZ_REG_MMC_STATUS 0x04 30 #define JZ_REG_MMC_CLKRT 0x08 31 #define JZ_REG_MMC_CMDAT 0x0C 32 #define JZ_REG_MMC_RESTO 0x10 33 #define JZ_REG_MMC_RDTO 0x14 34 #define JZ_REG_MMC_BLKLEN 0x18 35 #define JZ_REG_MMC_NOB 0x1C 36 #define JZ_REG_MMC_SNOB 0x20 37 #define JZ_REG_MMC_IMASK 0x24 38 #define JZ_REG_MMC_IREG 0x28 39 #define JZ_REG_MMC_CMD 0x2C 40 #define JZ_REG_MMC_ARG 0x30 41 #define JZ_REG_MMC_RESP_FIFO 0x34 42 #define JZ_REG_MMC_RXFIFO 0x38 43 #define JZ_REG_MMC_TXFIFO 0x3C 44 #define JZ_REG_MMC_DMAC 0x44 45 46 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) 47 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) 48 #define JZ_MMC_STRPCL_START_READWAIT BIT(5) 49 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) 50 #define JZ_MMC_STRPCL_RESET BIT(3) 51 #define JZ_MMC_STRPCL_START_OP BIT(2) 52 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) 53 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) 54 #define JZ_MMC_STRPCL_CLOCK_START BIT(1) 55 56 57 #define JZ_MMC_STATUS_IS_RESETTING BIT(15) 58 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) 59 #define JZ_MMC_STATUS_PRG_DONE BIT(13) 60 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) 61 #define JZ_MMC_STATUS_END_CMD_RES BIT(11) 62 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) 63 #define JZ_MMC_STATUS_IS_READWAIT BIT(9) 64 #define JZ_MMC_STATUS_CLK_EN BIT(8) 65 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) 66 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) 67 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) 68 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) 69 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) 70 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) 71 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) 72 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) 73 74 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) 75 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) 76 77 78 #define JZ_MMC_CMDAT_IO_ABORT BIT(11) 79 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) 80 #define JZ_MMC_CMDAT_BUS_WIDTH_8BIT (BIT(10) | BIT(9)) 81 #define JZ_MMC_CMDAT_BUS_WIDTH_MASK (BIT(10) | BIT(9)) 82 #define JZ_MMC_CMDAT_DMA_EN BIT(8) 83 #define JZ_MMC_CMDAT_INIT BIT(7) 84 #define JZ_MMC_CMDAT_BUSY BIT(6) 85 #define JZ_MMC_CMDAT_STREAM BIT(5) 86 #define JZ_MMC_CMDAT_WRITE BIT(4) 87 #define JZ_MMC_CMDAT_DATA_EN BIT(3) 88 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) 89 #define JZ_MMC_CMDAT_RSP_R1 1 90 #define JZ_MMC_CMDAT_RSP_R2 2 91 #define JZ_MMC_CMDAT_RSP_R3 3 92 93 #define JZ_MMC_IRQ_SDIO BIT(7) 94 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) 95 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) 96 #define JZ_MMC_IRQ_END_CMD_RES BIT(2) 97 #define JZ_MMC_IRQ_PRG_DONE BIT(1) 98 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) 99 100 #define JZ_MMC_DMAC_DMA_SEL BIT(1) 101 #define JZ_MMC_DMAC_DMA_EN BIT(0) 102 103 #define JZ_MMC_CLK_RATE 24000000 104 105 enum jz4740_mmc_version { 106 JZ_MMC_JZ4740, 107 JZ_MMC_JZ4725B, 108 JZ_MMC_JZ4760, 109 JZ_MMC_JZ4780, 110 }; 111 112 enum jz4740_mmc_state { 113 JZ4740_MMC_STATE_READ_RESPONSE, 114 JZ4740_MMC_STATE_TRANSFER_DATA, 115 JZ4740_MMC_STATE_SEND_STOP, 116 JZ4740_MMC_STATE_DONE, 117 }; 118 119 /* 120 * The MMC core allows to prepare a mmc_request while another mmc_request 121 * is in-flight. This is used via the pre_req/post_req hooks. 122 * This driver uses the pre_req/post_req hooks to map/unmap the mmc_request. 123 * Following what other drivers do (sdhci, dw_mmc) we use the following cookie 124 * flags to keep track of the mmc_request mapping state. 125 * 126 * COOKIE_UNMAPPED: the request is not mapped. 127 * COOKIE_PREMAPPED: the request was mapped in pre_req, 128 * and should be unmapped in post_req. 129 * COOKIE_MAPPED: the request was mapped in the irq handler, 130 * and should be unmapped before mmc_request_done is called.. 131 */ 132 enum jz4780_cookie { 133 COOKIE_UNMAPPED = 0, 134 COOKIE_PREMAPPED, 135 COOKIE_MAPPED, 136 }; 137 138 struct jz4740_mmc_host { 139 struct mmc_host *mmc; 140 struct platform_device *pdev; 141 struct clk *clk; 142 143 enum jz4740_mmc_version version; 144 145 int irq; 146 int card_detect_irq; 147 148 void __iomem *base; 149 struct resource *mem_res; 150 struct mmc_request *req; 151 struct mmc_command *cmd; 152 153 unsigned long waiting; 154 155 uint32_t cmdat; 156 157 uint32_t irq_mask; 158 159 spinlock_t lock; 160 161 struct timer_list timeout_timer; 162 struct sg_mapping_iter miter; 163 enum jz4740_mmc_state state; 164 165 /* DMA support */ 166 struct dma_chan *dma_rx; 167 struct dma_chan *dma_tx; 168 bool use_dma; 169 170 /* The DMA trigger level is 8 words, that is to say, the DMA read 171 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write 172 * trigger is when data words in MSC_TXFIFO is < 8. 173 */ 174 #define JZ4740_MMC_FIFO_HALF_SIZE 8 175 }; 176 177 static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host, 178 uint32_t val) 179 { 180 if (host->version >= JZ_MMC_JZ4725B) 181 return writel(val, host->base + JZ_REG_MMC_IMASK); 182 else 183 return writew(val, host->base + JZ_REG_MMC_IMASK); 184 } 185 186 static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host, 187 uint32_t val) 188 { 189 if (host->version >= JZ_MMC_JZ4780) 190 writel(val, host->base + JZ_REG_MMC_IREG); 191 else 192 writew(val, host->base + JZ_REG_MMC_IREG); 193 } 194 195 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host) 196 { 197 if (host->version >= JZ_MMC_JZ4780) 198 return readl(host->base + JZ_REG_MMC_IREG); 199 else 200 return readw(host->base + JZ_REG_MMC_IREG); 201 } 202 203 /*----------------------------------------------------------------------------*/ 204 /* DMA infrastructure */ 205 206 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host) 207 { 208 if (!host->use_dma) 209 return; 210 211 dma_release_channel(host->dma_tx); 212 dma_release_channel(host->dma_rx); 213 } 214 215 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host) 216 { 217 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); 218 if (IS_ERR(host->dma_tx)) { 219 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n"); 220 return PTR_ERR(host->dma_tx); 221 } 222 223 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); 224 if (IS_ERR(host->dma_rx)) { 225 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n"); 226 dma_release_channel(host->dma_tx); 227 return PTR_ERR(host->dma_rx); 228 } 229 230 return 0; 231 } 232 233 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host, 234 struct mmc_data *data) 235 { 236 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx; 237 } 238 239 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host, 240 struct mmc_data *data) 241 { 242 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 243 enum dma_data_direction dir = mmc_get_dma_dir(data); 244 245 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 246 data->host_cookie = COOKIE_UNMAPPED; 247 } 248 249 /* Prepares DMA data for current or next transfer. 250 * A request can be in-flight when this is called. 251 */ 252 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host, 253 struct mmc_data *data, 254 int cookie) 255 { 256 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 257 enum dma_data_direction dir = mmc_get_dma_dir(data); 258 int sg_count; 259 260 if (data->host_cookie == COOKIE_PREMAPPED) 261 return data->sg_count; 262 263 sg_count = dma_map_sg(chan->device->dev, 264 data->sg, 265 data->sg_len, 266 dir); 267 268 if (sg_count <= 0) { 269 dev_err(mmc_dev(host->mmc), 270 "Failed to map scatterlist for DMA operation\n"); 271 return -EINVAL; 272 } 273 274 data->sg_count = sg_count; 275 data->host_cookie = cookie; 276 277 return data->sg_count; 278 } 279 280 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host, 281 struct mmc_data *data) 282 { 283 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 284 struct dma_async_tx_descriptor *desc; 285 struct dma_slave_config conf = { 286 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 287 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 288 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, 289 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, 290 }; 291 int sg_count; 292 293 if (data->flags & MMC_DATA_WRITE) { 294 conf.direction = DMA_MEM_TO_DEV; 295 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO; 296 } else { 297 conf.direction = DMA_DEV_TO_MEM; 298 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO; 299 } 300 301 sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED); 302 if (sg_count < 0) 303 return sg_count; 304 305 dmaengine_slave_config(chan, &conf); 306 desc = dmaengine_prep_slave_sg(chan, data->sg, sg_count, 307 conf.direction, 308 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 309 if (!desc) { 310 dev_err(mmc_dev(host->mmc), 311 "Failed to allocate DMA %s descriptor", 312 conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX"); 313 goto dma_unmap; 314 } 315 316 dmaengine_submit(desc); 317 dma_async_issue_pending(chan); 318 319 return 0; 320 321 dma_unmap: 322 if (data->host_cookie == COOKIE_MAPPED) 323 jz4740_mmc_dma_unmap(host, data); 324 return -ENOMEM; 325 } 326 327 static void jz4740_mmc_pre_request(struct mmc_host *mmc, 328 struct mmc_request *mrq) 329 { 330 struct jz4740_mmc_host *host = mmc_priv(mmc); 331 struct mmc_data *data = mrq->data; 332 333 if (!host->use_dma) 334 return; 335 336 data->host_cookie = COOKIE_UNMAPPED; 337 if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0) 338 data->host_cookie = COOKIE_UNMAPPED; 339 } 340 341 static void jz4740_mmc_post_request(struct mmc_host *mmc, 342 struct mmc_request *mrq, 343 int err) 344 { 345 struct jz4740_mmc_host *host = mmc_priv(mmc); 346 struct mmc_data *data = mrq->data; 347 348 if (data && data->host_cookie != COOKIE_UNMAPPED) 349 jz4740_mmc_dma_unmap(host, data); 350 351 if (err) { 352 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 353 354 dmaengine_terminate_all(chan); 355 } 356 } 357 358 /*----------------------------------------------------------------------------*/ 359 360 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, 361 unsigned int irq, bool enabled) 362 { 363 unsigned long flags; 364 365 spin_lock_irqsave(&host->lock, flags); 366 if (enabled) 367 host->irq_mask &= ~irq; 368 else 369 host->irq_mask |= irq; 370 371 jz4740_mmc_write_irq_mask(host, host->irq_mask); 372 spin_unlock_irqrestore(&host->lock, flags); 373 } 374 375 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, 376 bool start_transfer) 377 { 378 uint16_t val = JZ_MMC_STRPCL_CLOCK_START; 379 380 if (start_transfer) 381 val |= JZ_MMC_STRPCL_START_OP; 382 383 writew(val, host->base + JZ_REG_MMC_STRPCL); 384 } 385 386 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) 387 { 388 uint32_t status; 389 unsigned int timeout = 1000; 390 391 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); 392 do { 393 status = readl(host->base + JZ_REG_MMC_STATUS); 394 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); 395 } 396 397 static void jz4740_mmc_reset(struct jz4740_mmc_host *host) 398 { 399 uint32_t status; 400 unsigned int timeout = 1000; 401 402 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); 403 udelay(10); 404 do { 405 status = readl(host->base + JZ_REG_MMC_STATUS); 406 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); 407 } 408 409 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) 410 { 411 struct mmc_request *req; 412 struct mmc_data *data; 413 414 req = host->req; 415 data = req->data; 416 host->req = NULL; 417 418 if (data && data->host_cookie == COOKIE_MAPPED) 419 jz4740_mmc_dma_unmap(host, data); 420 mmc_request_done(host->mmc, req); 421 } 422 423 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, 424 unsigned int irq) 425 { 426 unsigned int timeout = 0x800; 427 uint32_t status; 428 429 do { 430 status = jz4740_mmc_read_irq_reg(host); 431 } while (!(status & irq) && --timeout); 432 433 if (timeout == 0) { 434 set_bit(0, &host->waiting); 435 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 436 jz4740_mmc_set_irq_enabled(host, irq, true); 437 return true; 438 } 439 440 return false; 441 } 442 443 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, 444 struct mmc_data *data) 445 { 446 int status; 447 448 status = readl(host->base + JZ_REG_MMC_STATUS); 449 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { 450 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { 451 host->req->cmd->error = -ETIMEDOUT; 452 data->error = -ETIMEDOUT; 453 } else { 454 host->req->cmd->error = -EIO; 455 data->error = -EIO; 456 } 457 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) { 458 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) { 459 host->req->cmd->error = -ETIMEDOUT; 460 data->error = -ETIMEDOUT; 461 } else { 462 host->req->cmd->error = -EIO; 463 data->error = -EIO; 464 } 465 } 466 } 467 468 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, 469 struct mmc_data *data) 470 { 471 struct sg_mapping_iter *miter = &host->miter; 472 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; 473 uint32_t *buf; 474 bool timeout; 475 size_t i, j; 476 477 while (sg_miter_next(miter)) { 478 buf = miter->addr; 479 i = miter->length / 4; 480 j = i / 8; 481 i = i & 0x7; 482 while (j) { 483 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 484 if (unlikely(timeout)) 485 goto poll_timeout; 486 487 writel(buf[0], fifo_addr); 488 writel(buf[1], fifo_addr); 489 writel(buf[2], fifo_addr); 490 writel(buf[3], fifo_addr); 491 writel(buf[4], fifo_addr); 492 writel(buf[5], fifo_addr); 493 writel(buf[6], fifo_addr); 494 writel(buf[7], fifo_addr); 495 buf += 8; 496 --j; 497 } 498 if (unlikely(i)) { 499 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 500 if (unlikely(timeout)) 501 goto poll_timeout; 502 503 while (i) { 504 writel(*buf, fifo_addr); 505 ++buf; 506 --i; 507 } 508 } 509 data->bytes_xfered += miter->length; 510 } 511 sg_miter_stop(miter); 512 513 return false; 514 515 poll_timeout: 516 miter->consumed = (void *)buf - miter->addr; 517 data->bytes_xfered += miter->consumed; 518 sg_miter_stop(miter); 519 520 return true; 521 } 522 523 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, 524 struct mmc_data *data) 525 { 526 struct sg_mapping_iter *miter = &host->miter; 527 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; 528 uint32_t *buf; 529 uint32_t d; 530 uint32_t status; 531 size_t i, j; 532 unsigned int timeout; 533 534 while (sg_miter_next(miter)) { 535 buf = miter->addr; 536 i = miter->length; 537 j = i / 32; 538 i = i & 0x1f; 539 while (j) { 540 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 541 if (unlikely(timeout)) 542 goto poll_timeout; 543 544 buf[0] = readl(fifo_addr); 545 buf[1] = readl(fifo_addr); 546 buf[2] = readl(fifo_addr); 547 buf[3] = readl(fifo_addr); 548 buf[4] = readl(fifo_addr); 549 buf[5] = readl(fifo_addr); 550 buf[6] = readl(fifo_addr); 551 buf[7] = readl(fifo_addr); 552 553 buf += 8; 554 --j; 555 } 556 557 if (unlikely(i)) { 558 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 559 if (unlikely(timeout)) 560 goto poll_timeout; 561 562 while (i >= 4) { 563 *buf++ = readl(fifo_addr); 564 i -= 4; 565 } 566 if (unlikely(i > 0)) { 567 d = readl(fifo_addr); 568 memcpy(buf, &d, i); 569 } 570 } 571 data->bytes_xfered += miter->length; 572 573 /* This can go away once MIPS implements 574 * flush_kernel_dcache_page */ 575 flush_dcache_page(miter->page); 576 } 577 sg_miter_stop(miter); 578 579 /* For whatever reason there is sometime one word more in the fifo then 580 * requested */ 581 timeout = 1000; 582 status = readl(host->base + JZ_REG_MMC_STATUS); 583 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { 584 d = readl(fifo_addr); 585 status = readl(host->base + JZ_REG_MMC_STATUS); 586 } 587 588 return false; 589 590 poll_timeout: 591 miter->consumed = (void *)buf - miter->addr; 592 data->bytes_xfered += miter->consumed; 593 sg_miter_stop(miter); 594 595 return true; 596 } 597 598 static void jz4740_mmc_timeout(struct timer_list *t) 599 { 600 struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer); 601 602 if (!test_and_clear_bit(0, &host->waiting)) 603 return; 604 605 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); 606 607 host->req->cmd->error = -ETIMEDOUT; 608 jz4740_mmc_request_done(host); 609 } 610 611 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, 612 struct mmc_command *cmd) 613 { 614 int i; 615 uint16_t tmp; 616 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; 617 618 if (cmd->flags & MMC_RSP_136) { 619 tmp = readw(fifo_addr); 620 for (i = 0; i < 4; ++i) { 621 cmd->resp[i] = tmp << 24; 622 tmp = readw(fifo_addr); 623 cmd->resp[i] |= tmp << 8; 624 tmp = readw(fifo_addr); 625 cmd->resp[i] |= tmp >> 8; 626 } 627 } else { 628 cmd->resp[0] = readw(fifo_addr) << 24; 629 cmd->resp[0] |= readw(fifo_addr) << 8; 630 cmd->resp[0] |= readw(fifo_addr) & 0xff; 631 } 632 } 633 634 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, 635 struct mmc_command *cmd) 636 { 637 uint32_t cmdat = host->cmdat; 638 639 host->cmdat &= ~JZ_MMC_CMDAT_INIT; 640 jz4740_mmc_clock_disable(host); 641 642 host->cmd = cmd; 643 644 if (cmd->flags & MMC_RSP_BUSY) 645 cmdat |= JZ_MMC_CMDAT_BUSY; 646 647 switch (mmc_resp_type(cmd)) { 648 case MMC_RSP_R1B: 649 case MMC_RSP_R1: 650 cmdat |= JZ_MMC_CMDAT_RSP_R1; 651 break; 652 case MMC_RSP_R2: 653 cmdat |= JZ_MMC_CMDAT_RSP_R2; 654 break; 655 case MMC_RSP_R3: 656 cmdat |= JZ_MMC_CMDAT_RSP_R3; 657 break; 658 default: 659 break; 660 } 661 662 if (cmd->data) { 663 cmdat |= JZ_MMC_CMDAT_DATA_EN; 664 if (cmd->data->flags & MMC_DATA_WRITE) 665 cmdat |= JZ_MMC_CMDAT_WRITE; 666 if (host->use_dma) { 667 /* 668 * The 4780's MMC controller has integrated DMA ability 669 * in addition to being able to use the external DMA 670 * controller. It moves DMA control bits to a separate 671 * register. The DMA_SEL bit chooses the external 672 * controller over the integrated one. Earlier SoCs 673 * can only use the external controller, and have a 674 * single DMA enable bit in CMDAT. 675 */ 676 if (host->version >= JZ_MMC_JZ4780) { 677 writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL, 678 host->base + JZ_REG_MMC_DMAC); 679 } else { 680 cmdat |= JZ_MMC_CMDAT_DMA_EN; 681 } 682 } else if (host->version >= JZ_MMC_JZ4780) { 683 writel(0, host->base + JZ_REG_MMC_DMAC); 684 } 685 686 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); 687 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); 688 } 689 690 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); 691 writel(cmd->arg, host->base + JZ_REG_MMC_ARG); 692 writel(cmdat, host->base + JZ_REG_MMC_CMDAT); 693 694 jz4740_mmc_clock_enable(host, 1); 695 } 696 697 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) 698 { 699 struct mmc_command *cmd = host->req->cmd; 700 struct mmc_data *data = cmd->data; 701 int direction; 702 703 if (data->flags & MMC_DATA_READ) 704 direction = SG_MITER_TO_SG; 705 else 706 direction = SG_MITER_FROM_SG; 707 708 sg_miter_start(&host->miter, data->sg, data->sg_len, direction); 709 } 710 711 712 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) 713 { 714 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; 715 struct mmc_command *cmd = host->req->cmd; 716 struct mmc_request *req = host->req; 717 struct mmc_data *data = cmd->data; 718 bool timeout = false; 719 720 if (cmd->error) 721 host->state = JZ4740_MMC_STATE_DONE; 722 723 switch (host->state) { 724 case JZ4740_MMC_STATE_READ_RESPONSE: 725 if (cmd->flags & MMC_RSP_PRESENT) 726 jz4740_mmc_read_response(host, cmd); 727 728 if (!data) 729 break; 730 731 jz_mmc_prepare_data_transfer(host); 732 /* fall through */ 733 734 case JZ4740_MMC_STATE_TRANSFER_DATA: 735 if (host->use_dma) { 736 /* Use DMA if enabled. 737 * Data transfer direction is defined later by 738 * relying on data flags in 739 * jz4740_mmc_prepare_dma_data() and 740 * jz4740_mmc_start_dma_transfer(). 741 */ 742 timeout = jz4740_mmc_start_dma_transfer(host, data); 743 data->bytes_xfered = data->blocks * data->blksz; 744 } else if (data->flags & MMC_DATA_READ) 745 /* Use PIO if DMA is not enabled. 746 * Data transfer direction was defined before 747 * by relying on data flags in 748 * jz_mmc_prepare_data_transfer(). 749 */ 750 timeout = jz4740_mmc_read_data(host, data); 751 else 752 timeout = jz4740_mmc_write_data(host, data); 753 754 if (unlikely(timeout)) { 755 host->state = JZ4740_MMC_STATE_TRANSFER_DATA; 756 break; 757 } 758 759 jz4740_mmc_transfer_check_state(host, data); 760 761 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); 762 if (unlikely(timeout)) { 763 host->state = JZ4740_MMC_STATE_SEND_STOP; 764 break; 765 } 766 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE); 767 /* fall through */ 768 769 case JZ4740_MMC_STATE_SEND_STOP: 770 if (!req->stop) 771 break; 772 773 jz4740_mmc_send_command(host, req->stop); 774 775 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) { 776 timeout = jz4740_mmc_poll_irq(host, 777 JZ_MMC_IRQ_PRG_DONE); 778 if (timeout) { 779 host->state = JZ4740_MMC_STATE_DONE; 780 break; 781 } 782 } 783 case JZ4740_MMC_STATE_DONE: 784 break; 785 } 786 787 if (!timeout) 788 jz4740_mmc_request_done(host); 789 790 return IRQ_HANDLED; 791 } 792 793 static irqreturn_t jz_mmc_irq(int irq, void *devid) 794 { 795 struct jz4740_mmc_host *host = devid; 796 struct mmc_command *cmd = host->cmd; 797 uint32_t irq_reg, status, tmp; 798 799 status = readl(host->base + JZ_REG_MMC_STATUS); 800 irq_reg = jz4740_mmc_read_irq_reg(host); 801 802 tmp = irq_reg; 803 irq_reg &= ~host->irq_mask; 804 805 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | 806 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); 807 808 if (tmp != irq_reg) 809 jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg); 810 811 if (irq_reg & JZ_MMC_IRQ_SDIO) { 812 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO); 813 mmc_signal_sdio_irq(host->mmc); 814 irq_reg &= ~JZ_MMC_IRQ_SDIO; 815 } 816 817 if (host->req && cmd && irq_reg) { 818 if (test_and_clear_bit(0, &host->waiting)) { 819 del_timer(&host->timeout_timer); 820 821 if (status & JZ_MMC_STATUS_TIMEOUT_RES) { 822 cmd->error = -ETIMEDOUT; 823 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { 824 cmd->error = -EIO; 825 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | 826 JZ_MMC_STATUS_CRC_WRITE_ERROR)) { 827 if (cmd->data) 828 cmd->data->error = -EIO; 829 cmd->error = -EIO; 830 } 831 832 jz4740_mmc_set_irq_enabled(host, irq_reg, false); 833 jz4740_mmc_write_irq_reg(host, irq_reg); 834 835 return IRQ_WAKE_THREAD; 836 } 837 } 838 839 return IRQ_HANDLED; 840 } 841 842 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) 843 { 844 int div = 0; 845 int real_rate; 846 847 jz4740_mmc_clock_disable(host); 848 clk_set_rate(host->clk, host->mmc->f_max); 849 850 real_rate = clk_get_rate(host->clk); 851 852 while (real_rate > rate && div < 7) { 853 ++div; 854 real_rate >>= 1; 855 } 856 857 writew(div, host->base + JZ_REG_MMC_CLKRT); 858 return real_rate; 859 } 860 861 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) 862 { 863 struct jz4740_mmc_host *host = mmc_priv(mmc); 864 865 host->req = req; 866 867 jz4740_mmc_write_irq_reg(host, ~0); 868 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); 869 870 host->state = JZ4740_MMC_STATE_READ_RESPONSE; 871 set_bit(0, &host->waiting); 872 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 873 jz4740_mmc_send_command(host, req->cmd); 874 } 875 876 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 877 { 878 struct jz4740_mmc_host *host = mmc_priv(mmc); 879 if (ios->clock) 880 jz4740_mmc_set_clock_rate(host, ios->clock); 881 882 switch (ios->power_mode) { 883 case MMC_POWER_UP: 884 jz4740_mmc_reset(host); 885 if (!IS_ERR(mmc->supply.vmmc)) 886 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 887 host->cmdat |= JZ_MMC_CMDAT_INIT; 888 clk_prepare_enable(host->clk); 889 break; 890 case MMC_POWER_ON: 891 break; 892 default: 893 if (!IS_ERR(mmc->supply.vmmc)) 894 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 895 clk_disable_unprepare(host->clk); 896 break; 897 } 898 899 switch (ios->bus_width) { 900 case MMC_BUS_WIDTH_1: 901 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; 902 break; 903 case MMC_BUS_WIDTH_4: 904 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; 905 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; 906 break; 907 case MMC_BUS_WIDTH_8: 908 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; 909 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_8BIT; 910 break; 911 default: 912 break; 913 } 914 } 915 916 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 917 { 918 struct jz4740_mmc_host *host = mmc_priv(mmc); 919 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); 920 } 921 922 static const struct mmc_host_ops jz4740_mmc_ops = { 923 .request = jz4740_mmc_request, 924 .pre_req = jz4740_mmc_pre_request, 925 .post_req = jz4740_mmc_post_request, 926 .set_ios = jz4740_mmc_set_ios, 927 .get_ro = mmc_gpio_get_ro, 928 .get_cd = mmc_gpio_get_cd, 929 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, 930 }; 931 932 static const struct of_device_id jz4740_mmc_of_match[] = { 933 { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 }, 934 { .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B }, 935 { .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 }, 936 { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 }, 937 {}, 938 }; 939 MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match); 940 941 static int jz4740_mmc_probe(struct platform_device* pdev) 942 { 943 int ret; 944 struct mmc_host *mmc; 945 struct jz4740_mmc_host *host; 946 const struct of_device_id *match; 947 948 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); 949 if (!mmc) { 950 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); 951 return -ENOMEM; 952 } 953 954 host = mmc_priv(mmc); 955 956 match = of_match_device(jz4740_mmc_of_match, &pdev->dev); 957 if (match) { 958 host->version = (enum jz4740_mmc_version)match->data; 959 } else { 960 /* JZ4740 should be the only one using legacy probe */ 961 host->version = JZ_MMC_JZ4740; 962 } 963 964 ret = mmc_of_parse(mmc); 965 if (ret) { 966 if (ret != -EPROBE_DEFER) 967 dev_err(&pdev->dev, 968 "could not parse device properties: %d\n", ret); 969 goto err_free_host; 970 } 971 972 mmc_regulator_get_supply(mmc); 973 974 host->irq = platform_get_irq(pdev, 0); 975 if (host->irq < 0) { 976 ret = host->irq; 977 goto err_free_host; 978 } 979 980 host->clk = devm_clk_get(&pdev->dev, "mmc"); 981 if (IS_ERR(host->clk)) { 982 ret = PTR_ERR(host->clk); 983 dev_err(&pdev->dev, "Failed to get mmc clock\n"); 984 goto err_free_host; 985 } 986 987 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 988 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res); 989 if (IS_ERR(host->base)) { 990 ret = PTR_ERR(host->base); 991 dev_err(&pdev->dev, "Failed to ioremap base memory\n"); 992 goto err_free_host; 993 } 994 995 mmc->ops = &jz4740_mmc_ops; 996 if (!mmc->f_max) 997 mmc->f_max = JZ_MMC_CLK_RATE; 998 mmc->f_min = mmc->f_max / 128; 999 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1000 1001 mmc->max_blk_size = (1 << 10) - 1; 1002 mmc->max_blk_count = (1 << 15) - 1; 1003 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1004 1005 mmc->max_segs = 128; 1006 mmc->max_seg_size = mmc->max_req_size; 1007 1008 host->mmc = mmc; 1009 host->pdev = pdev; 1010 spin_lock_init(&host->lock); 1011 host->irq_mask = ~0; 1012 1013 jz4740_mmc_reset(host); 1014 1015 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, 1016 dev_name(&pdev->dev), host); 1017 if (ret) { 1018 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); 1019 goto err_free_host; 1020 } 1021 1022 jz4740_mmc_clock_disable(host); 1023 timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0); 1024 1025 ret = jz4740_mmc_acquire_dma_channels(host); 1026 if (ret == -EPROBE_DEFER) 1027 goto err_free_irq; 1028 host->use_dma = !ret; 1029 1030 platform_set_drvdata(pdev, host); 1031 ret = mmc_add_host(mmc); 1032 1033 if (ret) { 1034 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); 1035 goto err_release_dma; 1036 } 1037 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); 1038 1039 dev_info(&pdev->dev, "Using %s, %d-bit mode\n", 1040 host->use_dma ? "DMA" : "PIO", 1041 (mmc->caps & MMC_CAP_8_BIT_DATA) ? 8 : 1042 ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1)); 1043 1044 return 0; 1045 1046 err_release_dma: 1047 if (host->use_dma) 1048 jz4740_mmc_release_dma_channels(host); 1049 err_free_irq: 1050 free_irq(host->irq, host); 1051 err_free_host: 1052 mmc_free_host(mmc); 1053 1054 return ret; 1055 } 1056 1057 static int jz4740_mmc_remove(struct platform_device *pdev) 1058 { 1059 struct jz4740_mmc_host *host = platform_get_drvdata(pdev); 1060 1061 del_timer_sync(&host->timeout_timer); 1062 jz4740_mmc_set_irq_enabled(host, 0xff, false); 1063 jz4740_mmc_reset(host); 1064 1065 mmc_remove_host(host->mmc); 1066 1067 free_irq(host->irq, host); 1068 1069 if (host->use_dma) 1070 jz4740_mmc_release_dma_channels(host); 1071 1072 mmc_free_host(host->mmc); 1073 1074 return 0; 1075 } 1076 1077 #ifdef CONFIG_PM_SLEEP 1078 1079 static int jz4740_mmc_suspend(struct device *dev) 1080 { 1081 return pinctrl_pm_select_sleep_state(dev); 1082 } 1083 1084 static int jz4740_mmc_resume(struct device *dev) 1085 { 1086 return pinctrl_pm_select_default_state(dev); 1087 } 1088 1089 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend, 1090 jz4740_mmc_resume); 1091 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) 1092 #else 1093 #define JZ4740_MMC_PM_OPS NULL 1094 #endif 1095 1096 static struct platform_driver jz4740_mmc_driver = { 1097 .probe = jz4740_mmc_probe, 1098 .remove = jz4740_mmc_remove, 1099 .driver = { 1100 .name = "jz4740-mmc", 1101 .of_match_table = of_match_ptr(jz4740_mmc_of_match), 1102 .pm = JZ4740_MMC_PM_OPS, 1103 }, 1104 }; 1105 1106 module_platform_driver(jz4740_mmc_driver); 1107 1108 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); 1109 MODULE_LICENSE("GPL"); 1110 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1111