1 /* 2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 3 * Copyright (C) 2013, Imagination Technologies 4 * 5 * JZ4740 SD/MMC controller driver 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * You should have received a copy of the GNU General Public License along 13 * with this program; if not, write to the Free Software Foundation, Inc., 14 * 675 Mass Ave, Cambridge, MA 02139, USA. 15 * 16 */ 17 18 #include <linux/bitops.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/dmaengine.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/err.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/irq.h> 27 #include <linux/mmc/host.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/module.h> 30 #include <linux/of_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/platform_device.h> 33 #include <linux/scatterlist.h> 34 35 #include <asm/cacheflush.h> 36 37 #include <asm/mach-jz4740/dma.h> 38 39 #define JZ_REG_MMC_STRPCL 0x00 40 #define JZ_REG_MMC_STATUS 0x04 41 #define JZ_REG_MMC_CLKRT 0x08 42 #define JZ_REG_MMC_CMDAT 0x0C 43 #define JZ_REG_MMC_RESTO 0x10 44 #define JZ_REG_MMC_RDTO 0x14 45 #define JZ_REG_MMC_BLKLEN 0x18 46 #define JZ_REG_MMC_NOB 0x1C 47 #define JZ_REG_MMC_SNOB 0x20 48 #define JZ_REG_MMC_IMASK 0x24 49 #define JZ_REG_MMC_IREG 0x28 50 #define JZ_REG_MMC_CMD 0x2C 51 #define JZ_REG_MMC_ARG 0x30 52 #define JZ_REG_MMC_RESP_FIFO 0x34 53 #define JZ_REG_MMC_RXFIFO 0x38 54 #define JZ_REG_MMC_TXFIFO 0x3C 55 #define JZ_REG_MMC_DMAC 0x44 56 57 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) 58 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) 59 #define JZ_MMC_STRPCL_START_READWAIT BIT(5) 60 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) 61 #define JZ_MMC_STRPCL_RESET BIT(3) 62 #define JZ_MMC_STRPCL_START_OP BIT(2) 63 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) 64 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) 65 #define JZ_MMC_STRPCL_CLOCK_START BIT(1) 66 67 68 #define JZ_MMC_STATUS_IS_RESETTING BIT(15) 69 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) 70 #define JZ_MMC_STATUS_PRG_DONE BIT(13) 71 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) 72 #define JZ_MMC_STATUS_END_CMD_RES BIT(11) 73 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) 74 #define JZ_MMC_STATUS_IS_READWAIT BIT(9) 75 #define JZ_MMC_STATUS_CLK_EN BIT(8) 76 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) 77 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) 78 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) 79 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) 80 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) 81 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) 82 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) 83 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) 84 85 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) 86 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) 87 88 89 #define JZ_MMC_CMDAT_IO_ABORT BIT(11) 90 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) 91 #define JZ_MMC_CMDAT_DMA_EN BIT(8) 92 #define JZ_MMC_CMDAT_INIT BIT(7) 93 #define JZ_MMC_CMDAT_BUSY BIT(6) 94 #define JZ_MMC_CMDAT_STREAM BIT(5) 95 #define JZ_MMC_CMDAT_WRITE BIT(4) 96 #define JZ_MMC_CMDAT_DATA_EN BIT(3) 97 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) 98 #define JZ_MMC_CMDAT_RSP_R1 1 99 #define JZ_MMC_CMDAT_RSP_R2 2 100 #define JZ_MMC_CMDAT_RSP_R3 3 101 102 #define JZ_MMC_IRQ_SDIO BIT(7) 103 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) 104 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) 105 #define JZ_MMC_IRQ_END_CMD_RES BIT(2) 106 #define JZ_MMC_IRQ_PRG_DONE BIT(1) 107 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) 108 109 #define JZ_MMC_DMAC_DMA_SEL BIT(1) 110 #define JZ_MMC_DMAC_DMA_EN BIT(0) 111 112 #define JZ_MMC_CLK_RATE 24000000 113 114 enum jz4740_mmc_version { 115 JZ_MMC_JZ4740, 116 JZ_MMC_JZ4725B, 117 JZ_MMC_JZ4780, 118 }; 119 120 enum jz4740_mmc_state { 121 JZ4740_MMC_STATE_READ_RESPONSE, 122 JZ4740_MMC_STATE_TRANSFER_DATA, 123 JZ4740_MMC_STATE_SEND_STOP, 124 JZ4740_MMC_STATE_DONE, 125 }; 126 127 /* 128 * The MMC core allows to prepare a mmc_request while another mmc_request 129 * is in-flight. This is used via the pre_req/post_req hooks. 130 * This driver uses the pre_req/post_req hooks to map/unmap the mmc_request. 131 * Following what other drivers do (sdhci, dw_mmc) we use the following cookie 132 * flags to keep track of the mmc_request mapping state. 133 * 134 * COOKIE_UNMAPPED: the request is not mapped. 135 * COOKIE_PREMAPPED: the request was mapped in pre_req, 136 * and should be unmapped in post_req. 137 * COOKIE_MAPPED: the request was mapped in the irq handler, 138 * and should be unmapped before mmc_request_done is called.. 139 */ 140 enum jz4780_cookie { 141 COOKIE_UNMAPPED = 0, 142 COOKIE_PREMAPPED, 143 COOKIE_MAPPED, 144 }; 145 146 struct jz4740_mmc_host { 147 struct mmc_host *mmc; 148 struct platform_device *pdev; 149 struct clk *clk; 150 151 enum jz4740_mmc_version version; 152 153 int irq; 154 int card_detect_irq; 155 156 void __iomem *base; 157 struct resource *mem_res; 158 struct mmc_request *req; 159 struct mmc_command *cmd; 160 161 unsigned long waiting; 162 163 uint32_t cmdat; 164 165 uint32_t irq_mask; 166 167 spinlock_t lock; 168 169 struct timer_list timeout_timer; 170 struct sg_mapping_iter miter; 171 enum jz4740_mmc_state state; 172 173 /* DMA support */ 174 struct dma_chan *dma_rx; 175 struct dma_chan *dma_tx; 176 bool use_dma; 177 178 /* The DMA trigger level is 8 words, that is to say, the DMA read 179 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write 180 * trigger is when data words in MSC_TXFIFO is < 8. 181 */ 182 #define JZ4740_MMC_FIFO_HALF_SIZE 8 183 }; 184 185 static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host, 186 uint32_t val) 187 { 188 if (host->version >= JZ_MMC_JZ4725B) 189 return writel(val, host->base + JZ_REG_MMC_IMASK); 190 else 191 return writew(val, host->base + JZ_REG_MMC_IMASK); 192 } 193 194 static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host, 195 uint32_t val) 196 { 197 if (host->version >= JZ_MMC_JZ4780) 198 return writel(val, host->base + JZ_REG_MMC_IREG); 199 else 200 return writew(val, host->base + JZ_REG_MMC_IREG); 201 } 202 203 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host) 204 { 205 if (host->version >= JZ_MMC_JZ4780) 206 return readl(host->base + JZ_REG_MMC_IREG); 207 else 208 return readw(host->base + JZ_REG_MMC_IREG); 209 } 210 211 /*----------------------------------------------------------------------------*/ 212 /* DMA infrastructure */ 213 214 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host) 215 { 216 if (!host->use_dma) 217 return; 218 219 dma_release_channel(host->dma_tx); 220 dma_release_channel(host->dma_rx); 221 } 222 223 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host) 224 { 225 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); 226 if (IS_ERR(host->dma_tx)) { 227 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n"); 228 return PTR_ERR(host->dma_tx); 229 } 230 231 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); 232 if (IS_ERR(host->dma_rx)) { 233 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n"); 234 dma_release_channel(host->dma_tx); 235 return PTR_ERR(host->dma_rx); 236 } 237 238 return 0; 239 } 240 241 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host, 242 struct mmc_data *data) 243 { 244 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx; 245 } 246 247 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host, 248 struct mmc_data *data) 249 { 250 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 251 enum dma_data_direction dir = mmc_get_dma_dir(data); 252 253 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 254 data->host_cookie = COOKIE_UNMAPPED; 255 } 256 257 /* Prepares DMA data for current or next transfer. 258 * A request can be in-flight when this is called. 259 */ 260 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host, 261 struct mmc_data *data, 262 int cookie) 263 { 264 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 265 enum dma_data_direction dir = mmc_get_dma_dir(data); 266 int sg_count; 267 268 if (data->host_cookie == COOKIE_PREMAPPED) 269 return data->sg_count; 270 271 sg_count = dma_map_sg(chan->device->dev, 272 data->sg, 273 data->sg_len, 274 dir); 275 276 if (sg_count <= 0) { 277 dev_err(mmc_dev(host->mmc), 278 "Failed to map scatterlist for DMA operation\n"); 279 return -EINVAL; 280 } 281 282 data->sg_count = sg_count; 283 data->host_cookie = cookie; 284 285 return data->sg_count; 286 } 287 288 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host, 289 struct mmc_data *data) 290 { 291 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 292 struct dma_async_tx_descriptor *desc; 293 struct dma_slave_config conf = { 294 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 295 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 296 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, 297 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, 298 }; 299 int sg_count; 300 301 if (data->flags & MMC_DATA_WRITE) { 302 conf.direction = DMA_MEM_TO_DEV; 303 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO; 304 conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT; 305 } else { 306 conf.direction = DMA_DEV_TO_MEM; 307 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO; 308 conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE; 309 } 310 311 sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED); 312 if (sg_count < 0) 313 return sg_count; 314 315 dmaengine_slave_config(chan, &conf); 316 desc = dmaengine_prep_slave_sg(chan, data->sg, sg_count, 317 conf.direction, 318 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 319 if (!desc) { 320 dev_err(mmc_dev(host->mmc), 321 "Failed to allocate DMA %s descriptor", 322 conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX"); 323 goto dma_unmap; 324 } 325 326 dmaengine_submit(desc); 327 dma_async_issue_pending(chan); 328 329 return 0; 330 331 dma_unmap: 332 if (data->host_cookie == COOKIE_MAPPED) 333 jz4740_mmc_dma_unmap(host, data); 334 return -ENOMEM; 335 } 336 337 static void jz4740_mmc_pre_request(struct mmc_host *mmc, 338 struct mmc_request *mrq) 339 { 340 struct jz4740_mmc_host *host = mmc_priv(mmc); 341 struct mmc_data *data = mrq->data; 342 343 if (!host->use_dma) 344 return; 345 346 data->host_cookie = COOKIE_UNMAPPED; 347 if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0) 348 data->host_cookie = COOKIE_UNMAPPED; 349 } 350 351 static void jz4740_mmc_post_request(struct mmc_host *mmc, 352 struct mmc_request *mrq, 353 int err) 354 { 355 struct jz4740_mmc_host *host = mmc_priv(mmc); 356 struct mmc_data *data = mrq->data; 357 358 if (data && data->host_cookie != COOKIE_UNMAPPED) 359 jz4740_mmc_dma_unmap(host, data); 360 361 if (err) { 362 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); 363 364 dmaengine_terminate_all(chan); 365 } 366 } 367 368 /*----------------------------------------------------------------------------*/ 369 370 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, 371 unsigned int irq, bool enabled) 372 { 373 unsigned long flags; 374 375 spin_lock_irqsave(&host->lock, flags); 376 if (enabled) 377 host->irq_mask &= ~irq; 378 else 379 host->irq_mask |= irq; 380 381 jz4740_mmc_write_irq_mask(host, host->irq_mask); 382 spin_unlock_irqrestore(&host->lock, flags); 383 } 384 385 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, 386 bool start_transfer) 387 { 388 uint16_t val = JZ_MMC_STRPCL_CLOCK_START; 389 390 if (start_transfer) 391 val |= JZ_MMC_STRPCL_START_OP; 392 393 writew(val, host->base + JZ_REG_MMC_STRPCL); 394 } 395 396 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) 397 { 398 uint32_t status; 399 unsigned int timeout = 1000; 400 401 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); 402 do { 403 status = readl(host->base + JZ_REG_MMC_STATUS); 404 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); 405 } 406 407 static void jz4740_mmc_reset(struct jz4740_mmc_host *host) 408 { 409 uint32_t status; 410 unsigned int timeout = 1000; 411 412 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); 413 udelay(10); 414 do { 415 status = readl(host->base + JZ_REG_MMC_STATUS); 416 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); 417 } 418 419 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) 420 { 421 struct mmc_request *req; 422 struct mmc_data *data; 423 424 req = host->req; 425 data = req->data; 426 host->req = NULL; 427 428 if (data && data->host_cookie == COOKIE_MAPPED) 429 jz4740_mmc_dma_unmap(host, data); 430 mmc_request_done(host->mmc, req); 431 } 432 433 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, 434 unsigned int irq) 435 { 436 unsigned int timeout = 0x800; 437 uint32_t status; 438 439 do { 440 status = jz4740_mmc_read_irq_reg(host); 441 } while (!(status & irq) && --timeout); 442 443 if (timeout == 0) { 444 set_bit(0, &host->waiting); 445 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 446 jz4740_mmc_set_irq_enabled(host, irq, true); 447 return true; 448 } 449 450 return false; 451 } 452 453 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, 454 struct mmc_data *data) 455 { 456 int status; 457 458 status = readl(host->base + JZ_REG_MMC_STATUS); 459 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { 460 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { 461 host->req->cmd->error = -ETIMEDOUT; 462 data->error = -ETIMEDOUT; 463 } else { 464 host->req->cmd->error = -EIO; 465 data->error = -EIO; 466 } 467 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) { 468 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) { 469 host->req->cmd->error = -ETIMEDOUT; 470 data->error = -ETIMEDOUT; 471 } else { 472 host->req->cmd->error = -EIO; 473 data->error = -EIO; 474 } 475 } 476 } 477 478 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, 479 struct mmc_data *data) 480 { 481 struct sg_mapping_iter *miter = &host->miter; 482 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; 483 uint32_t *buf; 484 bool timeout; 485 size_t i, j; 486 487 while (sg_miter_next(miter)) { 488 buf = miter->addr; 489 i = miter->length / 4; 490 j = i / 8; 491 i = i & 0x7; 492 while (j) { 493 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 494 if (unlikely(timeout)) 495 goto poll_timeout; 496 497 writel(buf[0], fifo_addr); 498 writel(buf[1], fifo_addr); 499 writel(buf[2], fifo_addr); 500 writel(buf[3], fifo_addr); 501 writel(buf[4], fifo_addr); 502 writel(buf[5], fifo_addr); 503 writel(buf[6], fifo_addr); 504 writel(buf[7], fifo_addr); 505 buf += 8; 506 --j; 507 } 508 if (unlikely(i)) { 509 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 510 if (unlikely(timeout)) 511 goto poll_timeout; 512 513 while (i) { 514 writel(*buf, fifo_addr); 515 ++buf; 516 --i; 517 } 518 } 519 data->bytes_xfered += miter->length; 520 } 521 sg_miter_stop(miter); 522 523 return false; 524 525 poll_timeout: 526 miter->consumed = (void *)buf - miter->addr; 527 data->bytes_xfered += miter->consumed; 528 sg_miter_stop(miter); 529 530 return true; 531 } 532 533 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, 534 struct mmc_data *data) 535 { 536 struct sg_mapping_iter *miter = &host->miter; 537 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; 538 uint32_t *buf; 539 uint32_t d; 540 uint32_t status; 541 size_t i, j; 542 unsigned int timeout; 543 544 while (sg_miter_next(miter)) { 545 buf = miter->addr; 546 i = miter->length; 547 j = i / 32; 548 i = i & 0x1f; 549 while (j) { 550 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 551 if (unlikely(timeout)) 552 goto poll_timeout; 553 554 buf[0] = readl(fifo_addr); 555 buf[1] = readl(fifo_addr); 556 buf[2] = readl(fifo_addr); 557 buf[3] = readl(fifo_addr); 558 buf[4] = readl(fifo_addr); 559 buf[5] = readl(fifo_addr); 560 buf[6] = readl(fifo_addr); 561 buf[7] = readl(fifo_addr); 562 563 buf += 8; 564 --j; 565 } 566 567 if (unlikely(i)) { 568 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 569 if (unlikely(timeout)) 570 goto poll_timeout; 571 572 while (i >= 4) { 573 *buf++ = readl(fifo_addr); 574 i -= 4; 575 } 576 if (unlikely(i > 0)) { 577 d = readl(fifo_addr); 578 memcpy(buf, &d, i); 579 } 580 } 581 data->bytes_xfered += miter->length; 582 583 /* This can go away once MIPS implements 584 * flush_kernel_dcache_page */ 585 flush_dcache_page(miter->page); 586 } 587 sg_miter_stop(miter); 588 589 /* For whatever reason there is sometime one word more in the fifo then 590 * requested */ 591 timeout = 1000; 592 status = readl(host->base + JZ_REG_MMC_STATUS); 593 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { 594 d = readl(fifo_addr); 595 status = readl(host->base + JZ_REG_MMC_STATUS); 596 } 597 598 return false; 599 600 poll_timeout: 601 miter->consumed = (void *)buf - miter->addr; 602 data->bytes_xfered += miter->consumed; 603 sg_miter_stop(miter); 604 605 return true; 606 } 607 608 static void jz4740_mmc_timeout(struct timer_list *t) 609 { 610 struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer); 611 612 if (!test_and_clear_bit(0, &host->waiting)) 613 return; 614 615 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); 616 617 host->req->cmd->error = -ETIMEDOUT; 618 jz4740_mmc_request_done(host); 619 } 620 621 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, 622 struct mmc_command *cmd) 623 { 624 int i; 625 uint16_t tmp; 626 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; 627 628 if (cmd->flags & MMC_RSP_136) { 629 tmp = readw(fifo_addr); 630 for (i = 0; i < 4; ++i) { 631 cmd->resp[i] = tmp << 24; 632 tmp = readw(fifo_addr); 633 cmd->resp[i] |= tmp << 8; 634 tmp = readw(fifo_addr); 635 cmd->resp[i] |= tmp >> 8; 636 } 637 } else { 638 cmd->resp[0] = readw(fifo_addr) << 24; 639 cmd->resp[0] |= readw(fifo_addr) << 8; 640 cmd->resp[0] |= readw(fifo_addr) & 0xff; 641 } 642 } 643 644 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, 645 struct mmc_command *cmd) 646 { 647 uint32_t cmdat = host->cmdat; 648 649 host->cmdat &= ~JZ_MMC_CMDAT_INIT; 650 jz4740_mmc_clock_disable(host); 651 652 host->cmd = cmd; 653 654 if (cmd->flags & MMC_RSP_BUSY) 655 cmdat |= JZ_MMC_CMDAT_BUSY; 656 657 switch (mmc_resp_type(cmd)) { 658 case MMC_RSP_R1B: 659 case MMC_RSP_R1: 660 cmdat |= JZ_MMC_CMDAT_RSP_R1; 661 break; 662 case MMC_RSP_R2: 663 cmdat |= JZ_MMC_CMDAT_RSP_R2; 664 break; 665 case MMC_RSP_R3: 666 cmdat |= JZ_MMC_CMDAT_RSP_R3; 667 break; 668 default: 669 break; 670 } 671 672 if (cmd->data) { 673 cmdat |= JZ_MMC_CMDAT_DATA_EN; 674 if (cmd->data->flags & MMC_DATA_WRITE) 675 cmdat |= JZ_MMC_CMDAT_WRITE; 676 if (host->use_dma) { 677 /* 678 * The 4780's MMC controller has integrated DMA ability 679 * in addition to being able to use the external DMA 680 * controller. It moves DMA control bits to a separate 681 * register. The DMA_SEL bit chooses the external 682 * controller over the integrated one. Earlier SoCs 683 * can only use the external controller, and have a 684 * single DMA enable bit in CMDAT. 685 */ 686 if (host->version >= JZ_MMC_JZ4780) { 687 writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL, 688 host->base + JZ_REG_MMC_DMAC); 689 } else { 690 cmdat |= JZ_MMC_CMDAT_DMA_EN; 691 } 692 } else if (host->version >= JZ_MMC_JZ4780) { 693 writel(0, host->base + JZ_REG_MMC_DMAC); 694 } 695 696 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); 697 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); 698 } 699 700 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); 701 writel(cmd->arg, host->base + JZ_REG_MMC_ARG); 702 writel(cmdat, host->base + JZ_REG_MMC_CMDAT); 703 704 jz4740_mmc_clock_enable(host, 1); 705 } 706 707 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) 708 { 709 struct mmc_command *cmd = host->req->cmd; 710 struct mmc_data *data = cmd->data; 711 int direction; 712 713 if (data->flags & MMC_DATA_READ) 714 direction = SG_MITER_TO_SG; 715 else 716 direction = SG_MITER_FROM_SG; 717 718 sg_miter_start(&host->miter, data->sg, data->sg_len, direction); 719 } 720 721 722 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) 723 { 724 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; 725 struct mmc_command *cmd = host->req->cmd; 726 struct mmc_request *req = host->req; 727 struct mmc_data *data = cmd->data; 728 bool timeout = false; 729 730 if (cmd->error) 731 host->state = JZ4740_MMC_STATE_DONE; 732 733 switch (host->state) { 734 case JZ4740_MMC_STATE_READ_RESPONSE: 735 if (cmd->flags & MMC_RSP_PRESENT) 736 jz4740_mmc_read_response(host, cmd); 737 738 if (!data) 739 break; 740 741 jz_mmc_prepare_data_transfer(host); 742 /* fall through */ 743 744 case JZ4740_MMC_STATE_TRANSFER_DATA: 745 if (host->use_dma) { 746 /* Use DMA if enabled. 747 * Data transfer direction is defined later by 748 * relying on data flags in 749 * jz4740_mmc_prepare_dma_data() and 750 * jz4740_mmc_start_dma_transfer(). 751 */ 752 timeout = jz4740_mmc_start_dma_transfer(host, data); 753 data->bytes_xfered = data->blocks * data->blksz; 754 } else if (data->flags & MMC_DATA_READ) 755 /* Use PIO if DMA is not enabled. 756 * Data transfer direction was defined before 757 * by relying on data flags in 758 * jz_mmc_prepare_data_transfer(). 759 */ 760 timeout = jz4740_mmc_read_data(host, data); 761 else 762 timeout = jz4740_mmc_write_data(host, data); 763 764 if (unlikely(timeout)) { 765 host->state = JZ4740_MMC_STATE_TRANSFER_DATA; 766 break; 767 } 768 769 jz4740_mmc_transfer_check_state(host, data); 770 771 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); 772 if (unlikely(timeout)) { 773 host->state = JZ4740_MMC_STATE_SEND_STOP; 774 break; 775 } 776 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE); 777 /* fall through */ 778 779 case JZ4740_MMC_STATE_SEND_STOP: 780 if (!req->stop) 781 break; 782 783 jz4740_mmc_send_command(host, req->stop); 784 785 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) { 786 timeout = jz4740_mmc_poll_irq(host, 787 JZ_MMC_IRQ_PRG_DONE); 788 if (timeout) { 789 host->state = JZ4740_MMC_STATE_DONE; 790 break; 791 } 792 } 793 case JZ4740_MMC_STATE_DONE: 794 break; 795 } 796 797 if (!timeout) 798 jz4740_mmc_request_done(host); 799 800 return IRQ_HANDLED; 801 } 802 803 static irqreturn_t jz_mmc_irq(int irq, void *devid) 804 { 805 struct jz4740_mmc_host *host = devid; 806 struct mmc_command *cmd = host->cmd; 807 uint32_t irq_reg, status, tmp; 808 809 status = readl(host->base + JZ_REG_MMC_STATUS); 810 irq_reg = jz4740_mmc_read_irq_reg(host); 811 812 tmp = irq_reg; 813 irq_reg &= ~host->irq_mask; 814 815 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | 816 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); 817 818 if (tmp != irq_reg) 819 jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg); 820 821 if (irq_reg & JZ_MMC_IRQ_SDIO) { 822 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO); 823 mmc_signal_sdio_irq(host->mmc); 824 irq_reg &= ~JZ_MMC_IRQ_SDIO; 825 } 826 827 if (host->req && cmd && irq_reg) { 828 if (test_and_clear_bit(0, &host->waiting)) { 829 del_timer(&host->timeout_timer); 830 831 if (status & JZ_MMC_STATUS_TIMEOUT_RES) { 832 cmd->error = -ETIMEDOUT; 833 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { 834 cmd->error = -EIO; 835 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | 836 JZ_MMC_STATUS_CRC_WRITE_ERROR)) { 837 if (cmd->data) 838 cmd->data->error = -EIO; 839 cmd->error = -EIO; 840 } 841 842 jz4740_mmc_set_irq_enabled(host, irq_reg, false); 843 jz4740_mmc_write_irq_reg(host, irq_reg); 844 845 return IRQ_WAKE_THREAD; 846 } 847 } 848 849 return IRQ_HANDLED; 850 } 851 852 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) 853 { 854 int div = 0; 855 int real_rate; 856 857 jz4740_mmc_clock_disable(host); 858 clk_set_rate(host->clk, host->mmc->f_max); 859 860 real_rate = clk_get_rate(host->clk); 861 862 while (real_rate > rate && div < 7) { 863 ++div; 864 real_rate >>= 1; 865 } 866 867 writew(div, host->base + JZ_REG_MMC_CLKRT); 868 return real_rate; 869 } 870 871 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) 872 { 873 struct jz4740_mmc_host *host = mmc_priv(mmc); 874 875 host->req = req; 876 877 jz4740_mmc_write_irq_reg(host, ~0); 878 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); 879 880 host->state = JZ4740_MMC_STATE_READ_RESPONSE; 881 set_bit(0, &host->waiting); 882 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 883 jz4740_mmc_send_command(host, req->cmd); 884 } 885 886 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 887 { 888 struct jz4740_mmc_host *host = mmc_priv(mmc); 889 if (ios->clock) 890 jz4740_mmc_set_clock_rate(host, ios->clock); 891 892 switch (ios->power_mode) { 893 case MMC_POWER_UP: 894 jz4740_mmc_reset(host); 895 if (!IS_ERR(mmc->supply.vmmc)) 896 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 897 host->cmdat |= JZ_MMC_CMDAT_INIT; 898 clk_prepare_enable(host->clk); 899 break; 900 case MMC_POWER_ON: 901 break; 902 default: 903 if (!IS_ERR(mmc->supply.vmmc)) 904 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 905 clk_disable_unprepare(host->clk); 906 break; 907 } 908 909 switch (ios->bus_width) { 910 case MMC_BUS_WIDTH_1: 911 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; 912 break; 913 case MMC_BUS_WIDTH_4: 914 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; 915 break; 916 default: 917 break; 918 } 919 } 920 921 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 922 { 923 struct jz4740_mmc_host *host = mmc_priv(mmc); 924 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); 925 } 926 927 static const struct mmc_host_ops jz4740_mmc_ops = { 928 .request = jz4740_mmc_request, 929 .pre_req = jz4740_mmc_pre_request, 930 .post_req = jz4740_mmc_post_request, 931 .set_ios = jz4740_mmc_set_ios, 932 .get_ro = mmc_gpio_get_ro, 933 .get_cd = mmc_gpio_get_cd, 934 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, 935 }; 936 937 static const struct of_device_id jz4740_mmc_of_match[] = { 938 { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 }, 939 { .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B }, 940 { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 }, 941 {}, 942 }; 943 MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match); 944 945 static int jz4740_mmc_probe(struct platform_device* pdev) 946 { 947 int ret; 948 struct mmc_host *mmc; 949 struct jz4740_mmc_host *host; 950 const struct of_device_id *match; 951 952 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); 953 if (!mmc) { 954 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); 955 return -ENOMEM; 956 } 957 958 host = mmc_priv(mmc); 959 960 match = of_match_device(jz4740_mmc_of_match, &pdev->dev); 961 if (match) { 962 host->version = (enum jz4740_mmc_version)match->data; 963 } else { 964 /* JZ4740 should be the only one using legacy probe */ 965 host->version = JZ_MMC_JZ4740; 966 } 967 968 ret = mmc_of_parse(mmc); 969 if (ret) { 970 if (ret != -EPROBE_DEFER) 971 dev_err(&pdev->dev, 972 "could not parse device properties: %d\n", ret); 973 goto err_free_host; 974 } 975 976 mmc_regulator_get_supply(mmc); 977 978 host->irq = platform_get_irq(pdev, 0); 979 if (host->irq < 0) { 980 ret = host->irq; 981 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); 982 goto err_free_host; 983 } 984 985 host->clk = devm_clk_get(&pdev->dev, "mmc"); 986 if (IS_ERR(host->clk)) { 987 ret = PTR_ERR(host->clk); 988 dev_err(&pdev->dev, "Failed to get mmc clock\n"); 989 goto err_free_host; 990 } 991 992 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 993 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res); 994 if (IS_ERR(host->base)) { 995 ret = PTR_ERR(host->base); 996 dev_err(&pdev->dev, "Failed to ioremap base memory\n"); 997 goto err_free_host; 998 } 999 1000 mmc->ops = &jz4740_mmc_ops; 1001 if (!mmc->f_max) 1002 mmc->f_max = JZ_MMC_CLK_RATE; 1003 mmc->f_min = mmc->f_max / 128; 1004 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1005 1006 mmc->max_blk_size = (1 << 10) - 1; 1007 mmc->max_blk_count = (1 << 15) - 1; 1008 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1009 1010 mmc->max_segs = 128; 1011 mmc->max_seg_size = mmc->max_req_size; 1012 1013 host->mmc = mmc; 1014 host->pdev = pdev; 1015 spin_lock_init(&host->lock); 1016 host->irq_mask = ~0; 1017 1018 jz4740_mmc_reset(host); 1019 1020 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, 1021 dev_name(&pdev->dev), host); 1022 if (ret) { 1023 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); 1024 goto err_free_host; 1025 } 1026 1027 jz4740_mmc_clock_disable(host); 1028 timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0); 1029 1030 ret = jz4740_mmc_acquire_dma_channels(host); 1031 if (ret == -EPROBE_DEFER) 1032 goto err_free_irq; 1033 host->use_dma = !ret; 1034 1035 platform_set_drvdata(pdev, host); 1036 ret = mmc_add_host(mmc); 1037 1038 if (ret) { 1039 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); 1040 goto err_release_dma; 1041 } 1042 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); 1043 1044 dev_info(&pdev->dev, "Using %s, %d-bit mode\n", 1045 host->use_dma ? "DMA" : "PIO", 1046 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1047 1048 return 0; 1049 1050 err_release_dma: 1051 if (host->use_dma) 1052 jz4740_mmc_release_dma_channels(host); 1053 err_free_irq: 1054 free_irq(host->irq, host); 1055 err_free_host: 1056 mmc_free_host(mmc); 1057 1058 return ret; 1059 } 1060 1061 static int jz4740_mmc_remove(struct platform_device *pdev) 1062 { 1063 struct jz4740_mmc_host *host = platform_get_drvdata(pdev); 1064 1065 del_timer_sync(&host->timeout_timer); 1066 jz4740_mmc_set_irq_enabled(host, 0xff, false); 1067 jz4740_mmc_reset(host); 1068 1069 mmc_remove_host(host->mmc); 1070 1071 free_irq(host->irq, host); 1072 1073 if (host->use_dma) 1074 jz4740_mmc_release_dma_channels(host); 1075 1076 mmc_free_host(host->mmc); 1077 1078 return 0; 1079 } 1080 1081 #ifdef CONFIG_PM_SLEEP 1082 1083 static int jz4740_mmc_suspend(struct device *dev) 1084 { 1085 return pinctrl_pm_select_sleep_state(dev); 1086 } 1087 1088 static int jz4740_mmc_resume(struct device *dev) 1089 { 1090 return pinctrl_pm_select_default_state(dev); 1091 } 1092 1093 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend, 1094 jz4740_mmc_resume); 1095 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) 1096 #else 1097 #define JZ4740_MMC_PM_OPS NULL 1098 #endif 1099 1100 static struct platform_driver jz4740_mmc_driver = { 1101 .probe = jz4740_mmc_probe, 1102 .remove = jz4740_mmc_remove, 1103 .driver = { 1104 .name = "jz4740-mmc", 1105 .of_match_table = of_match_ptr(jz4740_mmc_of_match), 1106 .pm = JZ4740_MMC_PM_OPS, 1107 }, 1108 }; 1109 1110 module_platform_driver(jz4740_mmc_driver); 1111 1112 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); 1113 MODULE_LICENSE("GPL"); 1114 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1115