1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef _DW_MMC_H_ 15 #define _DW_MMC_H_ 16 17 #include <linux/scatterlist.h> 18 #include <linux/mmc/core.h> 19 #include <linux/dmaengine.h> 20 #include <linux/reset.h> 21 #include <linux/interrupt.h> 22 23 enum dw_mci_state { 24 STATE_IDLE = 0, 25 STATE_SENDING_CMD, 26 STATE_SENDING_DATA, 27 STATE_DATA_BUSY, 28 STATE_SENDING_STOP, 29 STATE_DATA_ERROR, 30 STATE_SENDING_CMD11, 31 STATE_WAITING_CMD11_DONE, 32 }; 33 34 enum { 35 EVENT_CMD_COMPLETE = 0, 36 EVENT_XFER_COMPLETE, 37 EVENT_DATA_COMPLETE, 38 EVENT_DATA_ERROR, 39 }; 40 41 enum dw_mci_cookie { 42 COOKIE_UNMAPPED, 43 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ 44 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ 45 }; 46 47 struct mmc_data; 48 49 enum { 50 TRANS_MODE_PIO = 0, 51 TRANS_MODE_IDMAC, 52 TRANS_MODE_EDMAC 53 }; 54 55 struct dw_mci_dma_slave { 56 struct dma_chan *ch; 57 enum dma_transfer_direction direction; 58 }; 59 60 /** 61 * struct dw_mci - MMC controller state shared between all slots 62 * @lock: Spinlock protecting the queue and associated data. 63 * @irq_lock: Spinlock protecting the INTMASK setting. 64 * @regs: Pointer to MMIO registers. 65 * @fifo_reg: Pointer to MMIO registers for data FIFO 66 * @sg: Scatterlist entry currently being processed by PIO code, if any. 67 * @sg_miter: PIO mapping scatterlist iterator. 68 * @cur_slot: The slot which is currently using the controller. 69 * @mrq: The request currently being processed on @cur_slot, 70 * or NULL if the controller is idle. 71 * @cmd: The command currently being sent to the card, or NULL. 72 * @data: The data currently being transferred, or NULL if no data 73 * transfer is in progress. 74 * @stop_abort: The command currently prepared for stoping transfer. 75 * @prev_blksz: The former transfer blksz record. 76 * @timing: Record of current ios timing. 77 * @use_dma: Whether DMA channel is initialized or not. 78 * @using_dma: Whether DMA is in use for the current transfer. 79 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 80 * @sg_dma: Bus address of DMA buffer. 81 * @sg_cpu: Virtual address of DMA buffer. 82 * @dma_ops: Pointer to platform-specific DMA callbacks. 83 * @cmd_status: Snapshot of SR taken upon completion of the current 84 * @ring_size: Buffer size for idma descriptors. 85 * command. Only valid when EVENT_CMD_COMPLETE is pending. 86 * @dms: structure of slave-dma private data. 87 * @phy_regs: physical address of controller's register map 88 * @data_status: Snapshot of SR taken upon completion of the current 89 * data transfer. Only valid when EVENT_DATA_COMPLETE or 90 * EVENT_DATA_ERROR is pending. 91 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 92 * to be sent. 93 * @dir_status: Direction of current transfer. 94 * @tasklet: Tasklet running the request state machine. 95 * @pending_events: Bitmask of events flagged by the interrupt handler 96 * to be processed by the tasklet. 97 * @completed_events: Bitmask of events which the state machine has 98 * processed. 99 * @state: Tasklet state. 100 * @queue: List of slots waiting for access to the controller. 101 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 102 * rate and timeout calculations. 103 * @current_speed: Configured rate of the controller. 104 * @num_slots: Number of slots available. 105 * @fifoth_val: The value of FIFOTH register. 106 * @verid: Denote Version ID. 107 * @dev: Device associated with the MMC controller. 108 * @pdata: Platform data associated with the MMC controller. 109 * @drv_data: Driver specific data for identified variant of the controller 110 * @priv: Implementation defined private data. 111 * @biu_clk: Pointer to bus interface unit clock instance. 112 * @ciu_clk: Pointer to card interface unit clock instance. 113 * @slot: Slots sharing this MMC controller. 114 * @fifo_depth: depth of FIFO. 115 * @data_addr_override: override fifo reg offset with this value. 116 * @wm_aligned: force fifo watermark equal with data length in PIO mode. 117 * Set as true if alignment is needed. 118 * @data_shift: log2 of FIFO item size. 119 * @part_buf_start: Start index in part_buf. 120 * @part_buf_count: Bytes of partial data in part_buf. 121 * @part_buf: Simple buffer for partial fifo reads/writes. 122 * @push_data: Pointer to FIFO push function. 123 * @pull_data: Pointer to FIFO pull function. 124 * @vqmmc_enabled: Status of vqmmc, should be true or false. 125 * @irq_flags: The flags to be passed to request_irq. 126 * @irq: The irq value to be passed to request_irq. 127 * @sdio_id0: Number of slot0 in the SDIO interrupt registers. 128 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. 129 * @dto_timer: Timer for broken data transfer over scheme. 130 * 131 * Locking 132 * ======= 133 * 134 * @lock is a softirq-safe spinlock protecting @queue as well as 135 * @cur_slot, @mrq and @state. These must always be updated 136 * at the same time while holding @lock. 137 * 138 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 139 * to allow the interrupt handler to modify it directly. Held for only long 140 * enough to read-modify-write INTMASK and no other locks are grabbed when 141 * holding this one. 142 * 143 * The @mrq field of struct dw_mci_slot is also protected by @lock, 144 * and must always be written at the same time as the slot is added to 145 * @queue. 146 * 147 * @pending_events and @completed_events are accessed using atomic bit 148 * operations, so they don't need any locking. 149 * 150 * None of the fields touched by the interrupt handler need any 151 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 152 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 153 * interrupts must be disabled and @data_status updated with a 154 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 155 * CMDRDY interrupt must be disabled and @cmd_status updated with a 156 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 157 * bytes_xfered field of @data must be written. This is ensured by 158 * using barriers. 159 */ 160 struct dw_mci { 161 spinlock_t lock; 162 spinlock_t irq_lock; 163 void __iomem *regs; 164 void __iomem *fifo_reg; 165 u32 data_addr_override; 166 bool wm_aligned; 167 168 struct scatterlist *sg; 169 struct sg_mapping_iter sg_miter; 170 171 struct dw_mci_slot *cur_slot; 172 struct mmc_request *mrq; 173 struct mmc_command *cmd; 174 struct mmc_data *data; 175 struct mmc_command stop_abort; 176 unsigned int prev_blksz; 177 unsigned char timing; 178 179 /* DMA interface members*/ 180 int use_dma; 181 int using_dma; 182 int dma_64bit_address; 183 184 dma_addr_t sg_dma; 185 void *sg_cpu; 186 const struct dw_mci_dma_ops *dma_ops; 187 /* For idmac */ 188 unsigned int ring_size; 189 190 /* For edmac */ 191 struct dw_mci_dma_slave *dms; 192 /* Registers's physical base address */ 193 resource_size_t phy_regs; 194 195 u32 cmd_status; 196 u32 data_status; 197 u32 stop_cmdr; 198 u32 dir_status; 199 struct tasklet_struct tasklet; 200 unsigned long pending_events; 201 unsigned long completed_events; 202 enum dw_mci_state state; 203 struct list_head queue; 204 205 u32 bus_hz; 206 u32 current_speed; 207 u32 num_slots; 208 u32 fifoth_val; 209 u16 verid; 210 struct device *dev; 211 struct dw_mci_board *pdata; 212 const struct dw_mci_drv_data *drv_data; 213 void *priv; 214 struct clk *biu_clk; 215 struct clk *ciu_clk; 216 struct dw_mci_slot *slot; 217 218 /* FIFO push and pull */ 219 int fifo_depth; 220 int data_shift; 221 u8 part_buf_start; 222 u8 part_buf_count; 223 union { 224 u16 part_buf16; 225 u32 part_buf32; 226 u64 part_buf; 227 }; 228 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 229 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 230 231 bool vqmmc_enabled; 232 unsigned long irq_flags; /* IRQ flags */ 233 int irq; 234 235 int sdio_id0; 236 237 struct timer_list cmd11_timer; 238 struct timer_list dto_timer; 239 }; 240 241 /* DMA ops for Internal/External DMAC interface */ 242 struct dw_mci_dma_ops { 243 /* DMA Ops */ 244 int (*init)(struct dw_mci *host); 245 int (*start)(struct dw_mci *host, unsigned int sg_len); 246 void (*complete)(void *host); 247 void (*stop)(struct dw_mci *host); 248 void (*cleanup)(struct dw_mci *host); 249 void (*exit)(struct dw_mci *host); 250 }; 251 252 struct dma_pdata; 253 254 /* Board platform data */ 255 struct dw_mci_board { 256 u32 num_slots; 257 258 unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 259 260 u32 caps; /* Capabilities */ 261 u32 caps2; /* More capabilities */ 262 u32 pm_caps; /* PM capabilities */ 263 /* 264 * Override fifo depth. If 0, autodetect it from the FIFOTH register, 265 * but note that this may not be reliable after a bootloader has used 266 * it. 267 */ 268 unsigned int fifo_depth; 269 270 /* delay in mS before detecting cards after interrupt */ 271 u32 detect_delay_ms; 272 273 struct reset_control *rstc; 274 struct dw_mci_dma_ops *dma_ops; 275 struct dma_pdata *data; 276 }; 277 278 #define DW_MMC_240A 0x240a 279 #define DW_MMC_280A 0x280a 280 281 #define SDMMC_CTRL 0x000 282 #define SDMMC_PWREN 0x004 283 #define SDMMC_CLKDIV 0x008 284 #define SDMMC_CLKSRC 0x00c 285 #define SDMMC_CLKENA 0x010 286 #define SDMMC_TMOUT 0x014 287 #define SDMMC_CTYPE 0x018 288 #define SDMMC_BLKSIZ 0x01c 289 #define SDMMC_BYTCNT 0x020 290 #define SDMMC_INTMASK 0x024 291 #define SDMMC_CMDARG 0x028 292 #define SDMMC_CMD 0x02c 293 #define SDMMC_RESP0 0x030 294 #define SDMMC_RESP1 0x034 295 #define SDMMC_RESP2 0x038 296 #define SDMMC_RESP3 0x03c 297 #define SDMMC_MINTSTS 0x040 298 #define SDMMC_RINTSTS 0x044 299 #define SDMMC_STATUS 0x048 300 #define SDMMC_FIFOTH 0x04c 301 #define SDMMC_CDETECT 0x050 302 #define SDMMC_WRTPRT 0x054 303 #define SDMMC_GPIO 0x058 304 #define SDMMC_TCBCNT 0x05c 305 #define SDMMC_TBBCNT 0x060 306 #define SDMMC_DEBNCE 0x064 307 #define SDMMC_USRID 0x068 308 #define SDMMC_VERID 0x06c 309 #define SDMMC_HCON 0x070 310 #define SDMMC_UHS_REG 0x074 311 #define SDMMC_RST_N 0x078 312 #define SDMMC_BMOD 0x080 313 #define SDMMC_PLDMND 0x084 314 #define SDMMC_DBADDR 0x088 315 #define SDMMC_IDSTS 0x08c 316 #define SDMMC_IDINTEN 0x090 317 #define SDMMC_DSCADDR 0x094 318 #define SDMMC_BUFADDR 0x098 319 #define SDMMC_CDTHRCTL 0x100 320 #define SDMMC_DATA(x) (x) 321 /* 322 * Registers to support idmac 64-bit address mode 323 */ 324 #define SDMMC_DBADDRL 0x088 325 #define SDMMC_DBADDRU 0x08c 326 #define SDMMC_IDSTS64 0x090 327 #define SDMMC_IDINTEN64 0x094 328 #define SDMMC_DSCADDRL 0x098 329 #define SDMMC_DSCADDRU 0x09c 330 #define SDMMC_BUFADDRL 0x0A0 331 #define SDMMC_BUFADDRU 0x0A4 332 333 /* 334 * Data offset is difference according to Version 335 * Lower than 2.40a : data register offest is 0x100 336 */ 337 #define DATA_OFFSET 0x100 338 #define DATA_240A_OFFSET 0x200 339 340 /* shift bit field */ 341 #define _SBF(f, v) ((v) << (f)) 342 343 /* Control register defines */ 344 #define SDMMC_CTRL_USE_IDMAC BIT(25) 345 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 346 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 347 #define SDMMC_CTRL_SEND_CCSD BIT(9) 348 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 349 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 350 #define SDMMC_CTRL_READ_WAIT BIT(6) 351 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 352 #define SDMMC_CTRL_INT_ENABLE BIT(4) 353 #define SDMMC_CTRL_DMA_RESET BIT(2) 354 #define SDMMC_CTRL_FIFO_RESET BIT(1) 355 #define SDMMC_CTRL_RESET BIT(0) 356 /* Clock Enable register defines */ 357 #define SDMMC_CLKEN_LOW_PWR BIT(16) 358 #define SDMMC_CLKEN_ENABLE BIT(0) 359 /* time-out register defines */ 360 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 361 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 362 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 363 #define SDMMC_TMOUT_RESP_MSK 0xFF 364 /* card-type register defines */ 365 #define SDMMC_CTYPE_8BIT BIT(16) 366 #define SDMMC_CTYPE_4BIT BIT(0) 367 #define SDMMC_CTYPE_1BIT 0 368 /* Interrupt status & mask register defines */ 369 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 370 #define SDMMC_INT_EBE BIT(15) 371 #define SDMMC_INT_ACD BIT(14) 372 #define SDMMC_INT_SBE BIT(13) 373 #define SDMMC_INT_HLE BIT(12) 374 #define SDMMC_INT_FRUN BIT(11) 375 #define SDMMC_INT_HTO BIT(10) 376 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 377 #define SDMMC_INT_DRTO BIT(9) 378 #define SDMMC_INT_RTO BIT(8) 379 #define SDMMC_INT_DCRC BIT(7) 380 #define SDMMC_INT_RCRC BIT(6) 381 #define SDMMC_INT_RXDR BIT(5) 382 #define SDMMC_INT_TXDR BIT(4) 383 #define SDMMC_INT_DATA_OVER BIT(3) 384 #define SDMMC_INT_CMD_DONE BIT(2) 385 #define SDMMC_INT_RESP_ERR BIT(1) 386 #define SDMMC_INT_CD BIT(0) 387 #define SDMMC_INT_ERROR 0xbfc2 388 /* Command register defines */ 389 #define SDMMC_CMD_START BIT(31) 390 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 391 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 392 #define SDMMC_CMD_CCS_EXP BIT(23) 393 #define SDMMC_CMD_CEATA_RD BIT(22) 394 #define SDMMC_CMD_UPD_CLK BIT(21) 395 #define SDMMC_CMD_INIT BIT(15) 396 #define SDMMC_CMD_STOP BIT(14) 397 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 398 #define SDMMC_CMD_SEND_STOP BIT(12) 399 #define SDMMC_CMD_STRM_MODE BIT(11) 400 #define SDMMC_CMD_DAT_WR BIT(10) 401 #define SDMMC_CMD_DAT_EXP BIT(9) 402 #define SDMMC_CMD_RESP_CRC BIT(8) 403 #define SDMMC_CMD_RESP_LONG BIT(7) 404 #define SDMMC_CMD_RESP_EXP BIT(6) 405 #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 406 /* Status register defines */ 407 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 408 #define SDMMC_STATUS_DMA_REQ BIT(31) 409 #define SDMMC_STATUS_BUSY BIT(9) 410 /* FIFOTH register defines */ 411 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 412 ((r) & 0xFFF) << 16 | \ 413 ((t) & 0xFFF)) 414 /* HCON register defines */ 415 #define DMA_INTERFACE_IDMA (0x0) 416 #define DMA_INTERFACE_DWDMA (0x1) 417 #define DMA_INTERFACE_GDMA (0x2) 418 #define DMA_INTERFACE_NODMA (0x3) 419 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 420 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 421 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 422 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 423 /* Internal DMAC interrupt defines */ 424 #define SDMMC_IDMAC_INT_AI BIT(9) 425 #define SDMMC_IDMAC_INT_NI BIT(8) 426 #define SDMMC_IDMAC_INT_CES BIT(5) 427 #define SDMMC_IDMAC_INT_DU BIT(4) 428 #define SDMMC_IDMAC_INT_FBE BIT(2) 429 #define SDMMC_IDMAC_INT_RI BIT(1) 430 #define SDMMC_IDMAC_INT_TI BIT(0) 431 /* Internal DMAC bus mode bits */ 432 #define SDMMC_IDMAC_ENABLE BIT(7) 433 #define SDMMC_IDMAC_FB BIT(1) 434 #define SDMMC_IDMAC_SWRESET BIT(0) 435 /* H/W reset */ 436 #define SDMMC_RST_HWACTIVE 0x1 437 /* Version ID register define */ 438 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 439 /* Card read threshold */ 440 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 441 #define SDMMC_CARD_WR_THR_EN BIT(2) 442 #define SDMMC_CARD_RD_THR_EN BIT(0) 443 /* UHS-1 register defines */ 444 #define SDMMC_UHS_18V BIT(0) 445 /* All ctrl reset bits */ 446 #define SDMMC_CTRL_ALL_RESET_FLAGS \ 447 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 448 449 /* FIFO register access macros. These should not change the data endian-ness 450 * as they are written to memory to be dealt with by the upper layers */ 451 #define mci_fifo_readw(__reg) __raw_readw(__reg) 452 #define mci_fifo_readl(__reg) __raw_readl(__reg) 453 #define mci_fifo_readq(__reg) __raw_readq(__reg) 454 455 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 456 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 457 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 458 459 /* Register access macros */ 460 #define mci_readl(dev, reg) \ 461 readl_relaxed((dev)->regs + SDMMC_##reg) 462 #define mci_writel(dev, reg, value) \ 463 writel_relaxed((value), (dev)->regs + SDMMC_##reg) 464 465 /* 16-bit FIFO access macros */ 466 #define mci_readw(dev, reg) \ 467 readw_relaxed((dev)->regs + SDMMC_##reg) 468 #define mci_writew(dev, reg, value) \ 469 writew_relaxed((value), (dev)->regs + SDMMC_##reg) 470 471 /* 64-bit FIFO access macros */ 472 #ifdef readq 473 #define mci_readq(dev, reg) \ 474 readq_relaxed((dev)->regs + SDMMC_##reg) 475 #define mci_writeq(dev, reg, value) \ 476 writeq_relaxed((value), (dev)->regs + SDMMC_##reg) 477 #else 478 /* 479 * Dummy readq implementation for architectures that don't define it. 480 * 481 * We would assume that none of these architectures would configure 482 * the IP block with a 64bit FIFO width, so this code will never be 483 * executed on those machines. Defining these macros here keeps the 484 * rest of the code free from ifdefs. 485 */ 486 #define mci_readq(dev, reg) \ 487 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 488 #define mci_writeq(dev, reg, value) \ 489 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 490 491 #define __raw_writeq(__value, __reg) \ 492 (*(volatile u64 __force *)(__reg) = (__value)) 493 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 494 #endif 495 496 extern int dw_mci_probe(struct dw_mci *host); 497 extern void dw_mci_remove(struct dw_mci *host); 498 #ifdef CONFIG_PM 499 extern int dw_mci_runtime_suspend(struct device *device); 500 extern int dw_mci_runtime_resume(struct device *device); 501 #endif 502 503 /** 504 * struct dw_mci_slot - MMC slot state 505 * @mmc: The mmc_host representing this slot. 506 * @host: The MMC controller this slot is using. 507 * @ctype: Card type for this slot. 508 * @mrq: mmc_request currently being processed or waiting to be 509 * processed, or NULL when the slot is idle. 510 * @queue_node: List node for placing this node in the @queue list of 511 * &struct dw_mci. 512 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 513 * @__clk_old: The last clock value that was requested from core. 514 * Keeping track of this helps us to avoid spamming the console. 515 * @flags: Random state bits associated with the slot. 516 * @id: Number of this slot. 517 * @sdio_id: Number of this slot in the SDIO interrupt registers. 518 */ 519 struct dw_mci_slot { 520 struct mmc_host *mmc; 521 struct dw_mci *host; 522 523 u32 ctype; 524 525 struct mmc_request *mrq; 526 struct list_head queue_node; 527 528 unsigned int clock; 529 unsigned int __clk_old; 530 531 unsigned long flags; 532 #define DW_MMC_CARD_PRESENT 0 533 #define DW_MMC_CARD_NEED_INIT 1 534 #define DW_MMC_CARD_NO_LOW_PWR 2 535 #define DW_MMC_CARD_NO_USE_HOLD 3 536 #define DW_MMC_CARD_NEEDS_POLL 4 537 int id; 538 int sdio_id; 539 }; 540 541 /** 542 * dw_mci driver data - dw-mshc implementation specific driver data. 543 * @caps: mmc subsystem specified capabilities of the controller(s). 544 * @init: early implementation specific initialization. 545 * @set_ios: handle bus specific extensions. 546 * @parse_dt: parse implementation specific device tree properties. 547 * @execute_tuning: implementation specific tuning procedure. 548 * 549 * Provide controller implementation specific extensions. The usage of this 550 * data structure is fully optional and usage of each member in this structure 551 * is optional as well. 552 */ 553 struct dw_mci_drv_data { 554 unsigned long *caps; 555 int (*init)(struct dw_mci *host); 556 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 557 int (*parse_dt)(struct dw_mci *host); 558 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); 559 int (*prepare_hs400_tuning)(struct dw_mci *host, 560 struct mmc_ios *ios); 561 int (*switch_voltage)(struct mmc_host *mmc, 562 struct mmc_ios *ios); 563 }; 564 #endif /* _DW_MMC_H_ */ 565