1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare Multimedia Card Interface driver 4 * (Based on NXP driver for lpc 31xx) 5 * 6 * Copyright (C) 2009 NXP Semiconductors 7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8 */ 9 10 #ifndef _DW_MMC_H_ 11 #define _DW_MMC_H_ 12 13 #include <linux/scatterlist.h> 14 #include <linux/mmc/core.h> 15 #include <linux/dmaengine.h> 16 #include <linux/reset.h> 17 #include <linux/fault-inject.h> 18 #include <linux/hrtimer.h> 19 #include <linux/interrupt.h> 20 21 enum dw_mci_state { 22 STATE_IDLE = 0, 23 STATE_SENDING_CMD, 24 STATE_SENDING_DATA, 25 STATE_DATA_BUSY, 26 STATE_SENDING_STOP, 27 STATE_DATA_ERROR, 28 STATE_SENDING_CMD11, 29 STATE_WAITING_CMD11_DONE, 30 }; 31 32 enum { 33 EVENT_CMD_COMPLETE = 0, 34 EVENT_XFER_COMPLETE, 35 EVENT_DATA_COMPLETE, 36 EVENT_DATA_ERROR, 37 }; 38 39 enum dw_mci_cookie { 40 COOKIE_UNMAPPED, 41 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ 42 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ 43 }; 44 45 struct mmc_data; 46 47 enum { 48 TRANS_MODE_PIO = 0, 49 TRANS_MODE_IDMAC, 50 TRANS_MODE_EDMAC 51 }; 52 53 struct dw_mci_dma_slave { 54 struct dma_chan *ch; 55 enum dma_transfer_direction direction; 56 }; 57 58 /** 59 * struct dw_mci - MMC controller state shared between all slots 60 * @lock: Spinlock protecting the queue and associated data. 61 * @irq_lock: Spinlock protecting the INTMASK setting. 62 * @regs: Pointer to MMIO registers. 63 * @fifo_reg: Pointer to MMIO registers for data FIFO 64 * @sg: Scatterlist entry currently being processed by PIO code, if any. 65 * @sg_miter: PIO mapping scatterlist iterator. 66 * @mrq: The request currently being processed on @slot, 67 * or NULL if the controller is idle. 68 * @cmd: The command currently being sent to the card, or NULL. 69 * @data: The data currently being transferred, or NULL if no data 70 * transfer is in progress. 71 * @stop_abort: The command currently prepared for stoping transfer. 72 * @prev_blksz: The former transfer blksz record. 73 * @timing: Record of current ios timing. 74 * @use_dma: Which DMA channel is in use for the current transfer, zero 75 * denotes PIO mode. 76 * @using_dma: Whether DMA is in use for the current transfer. 77 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 78 * @sg_dma: Bus address of DMA buffer. 79 * @sg_cpu: Virtual address of DMA buffer. 80 * @dma_ops: Pointer to platform-specific DMA callbacks. 81 * @cmd_status: Snapshot of SR taken upon completion of the current 82 * @ring_size: Buffer size for idma descriptors. 83 * command. Only valid when EVENT_CMD_COMPLETE is pending. 84 * @dms: structure of slave-dma private data. 85 * @phy_regs: physical address of controller's register map 86 * @data_status: Snapshot of SR taken upon completion of the current 87 * data transfer. Only valid when EVENT_DATA_COMPLETE or 88 * EVENT_DATA_ERROR is pending. 89 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 90 * to be sent. 91 * @dir_status: Direction of current transfer. 92 * @tasklet: Tasklet running the request state machine. 93 * @pending_events: Bitmask of events flagged by the interrupt handler 94 * to be processed by the tasklet. 95 * @completed_events: Bitmask of events which the state machine has 96 * processed. 97 * @state: Tasklet state. 98 * @queue: List of slots waiting for access to the controller. 99 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 100 * rate and timeout calculations. 101 * @current_speed: Configured rate of the controller. 102 * @fifoth_val: The value of FIFOTH register. 103 * @verid: Denote Version ID. 104 * @dev: Device associated with the MMC controller. 105 * @pdata: Platform data associated with the MMC controller. 106 * @drv_data: Driver specific data for identified variant of the controller 107 * @priv: Implementation defined private data. 108 * @biu_clk: Pointer to bus interface unit clock instance. 109 * @ciu_clk: Pointer to card interface unit clock instance. 110 * @slot: Slots sharing this MMC controller. 111 * @fifo_depth: depth of FIFO. 112 * @data_addr_override: override fifo reg offset with this value. 113 * @wm_aligned: force fifo watermark equal with data length in PIO mode. 114 * Set as true if alignment is needed. 115 * @data_shift: log2 of FIFO item size. 116 * @part_buf_start: Start index in part_buf. 117 * @part_buf_count: Bytes of partial data in part_buf. 118 * @part_buf: Simple buffer for partial fifo reads/writes. 119 * @push_data: Pointer to FIFO push function. 120 * @pull_data: Pointer to FIFO pull function. 121 * @quirks: Set of quirks that apply to specific versions of the IP. 122 * @vqmmc_enabled: Status of vqmmc, should be true or false. 123 * @irq_flags: The flags to be passed to request_irq. 124 * @irq: The irq value to be passed to request_irq. 125 * @sdio_id0: Number of slot0 in the SDIO interrupt registers. 126 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. 127 * @cto_timer: Timer for broken command transfer over scheme. 128 * @dto_timer: Timer for broken data transfer over scheme. 129 * 130 * Locking 131 * ======= 132 * 133 * @lock is a softirq-safe spinlock protecting @queue as well as 134 * @slot, @mrq and @state. These must always be updated 135 * at the same time while holding @lock. 136 * The @mrq field of struct dw_mci_slot is also protected by @lock, 137 * and must always be written at the same time as the slot is added to 138 * @queue. 139 * 140 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 141 * to allow the interrupt handler to modify it directly. Held for only long 142 * enough to read-modify-write INTMASK and no other locks are grabbed when 143 * holding this one. 144 * 145 * @pending_events and @completed_events are accessed using atomic bit 146 * operations, so they don't need any locking. 147 * 148 * None of the fields touched by the interrupt handler need any 149 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 150 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 151 * interrupts must be disabled and @data_status updated with a 152 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 153 * CMDRDY interrupt must be disabled and @cmd_status updated with a 154 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 155 * bytes_xfered field of @data must be written. This is ensured by 156 * using barriers. 157 */ 158 struct dw_mci { 159 spinlock_t lock; 160 spinlock_t irq_lock; 161 void __iomem *regs; 162 void __iomem *fifo_reg; 163 u32 data_addr_override; 164 bool wm_aligned; 165 166 struct scatterlist *sg; 167 struct sg_mapping_iter sg_miter; 168 169 struct mmc_request *mrq; 170 struct mmc_command *cmd; 171 struct mmc_data *data; 172 struct mmc_command stop_abort; 173 unsigned int prev_blksz; 174 unsigned char timing; 175 176 /* DMA interface members*/ 177 int use_dma; 178 int using_dma; 179 int dma_64bit_address; 180 181 dma_addr_t sg_dma; 182 void *sg_cpu; 183 const struct dw_mci_dma_ops *dma_ops; 184 /* For idmac */ 185 unsigned int ring_size; 186 187 /* For edmac */ 188 struct dw_mci_dma_slave *dms; 189 /* Registers's physical base address */ 190 resource_size_t phy_regs; 191 192 u32 cmd_status; 193 u32 data_status; 194 u32 stop_cmdr; 195 u32 dir_status; 196 struct tasklet_struct tasklet; 197 unsigned long pending_events; 198 unsigned long completed_events; 199 enum dw_mci_state state; 200 struct list_head queue; 201 202 u32 bus_hz; 203 u32 current_speed; 204 u32 fifoth_val; 205 u16 verid; 206 struct device *dev; 207 struct dw_mci_board *pdata; 208 const struct dw_mci_drv_data *drv_data; 209 void *priv; 210 struct clk *biu_clk; 211 struct clk *ciu_clk; 212 struct dw_mci_slot *slot; 213 214 /* FIFO push and pull */ 215 int fifo_depth; 216 int data_shift; 217 u8 part_buf_start; 218 u8 part_buf_count; 219 union { 220 u16 part_buf16; 221 u32 part_buf32; 222 u64 part_buf; 223 }; 224 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 225 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 226 227 u32 quirks; 228 bool vqmmc_enabled; 229 unsigned long irq_flags; /* IRQ flags */ 230 int irq; 231 232 int sdio_id0; 233 234 struct timer_list cmd11_timer; 235 struct timer_list cto_timer; 236 struct timer_list dto_timer; 237 238 #ifdef CONFIG_FAULT_INJECTION 239 struct fault_attr fail_data_crc; 240 struct hrtimer fault_timer; 241 #endif 242 }; 243 244 /* DMA ops for Internal/External DMAC interface */ 245 struct dw_mci_dma_ops { 246 /* DMA Ops */ 247 int (*init)(struct dw_mci *host); 248 int (*start)(struct dw_mci *host, unsigned int sg_len); 249 void (*complete)(void *host); 250 void (*stop)(struct dw_mci *host); 251 void (*cleanup)(struct dw_mci *host); 252 void (*exit)(struct dw_mci *host); 253 }; 254 255 struct dma_pdata; 256 257 /* Board platform data */ 258 struct dw_mci_board { 259 unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 260 261 u32 caps; /* Capabilities */ 262 u32 caps2; /* More capabilities */ 263 u32 pm_caps; /* PM capabilities */ 264 /* 265 * Override fifo depth. If 0, autodetect it from the FIFOTH register, 266 * but note that this may not be reliable after a bootloader has used 267 * it. 268 */ 269 unsigned int fifo_depth; 270 271 /* delay in mS before detecting cards after interrupt */ 272 u32 detect_delay_ms; 273 274 struct reset_control *rstc; 275 struct dw_mci_dma_ops *dma_ops; 276 struct dma_pdata *data; 277 }; 278 279 /* Support for longer data read timeout */ 280 #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) 281 282 #define DW_MMC_240A 0x240a 283 #define DW_MMC_280A 0x280a 284 285 #define SDMMC_CTRL 0x000 286 #define SDMMC_PWREN 0x004 287 #define SDMMC_CLKDIV 0x008 288 #define SDMMC_CLKSRC 0x00c 289 #define SDMMC_CLKENA 0x010 290 #define SDMMC_TMOUT 0x014 291 #define SDMMC_CTYPE 0x018 292 #define SDMMC_BLKSIZ 0x01c 293 #define SDMMC_BYTCNT 0x020 294 #define SDMMC_INTMASK 0x024 295 #define SDMMC_CMDARG 0x028 296 #define SDMMC_CMD 0x02c 297 #define SDMMC_RESP0 0x030 298 #define SDMMC_RESP1 0x034 299 #define SDMMC_RESP2 0x038 300 #define SDMMC_RESP3 0x03c 301 #define SDMMC_MINTSTS 0x040 302 #define SDMMC_RINTSTS 0x044 303 #define SDMMC_STATUS 0x048 304 #define SDMMC_FIFOTH 0x04c 305 #define SDMMC_CDETECT 0x050 306 #define SDMMC_WRTPRT 0x054 307 #define SDMMC_GPIO 0x058 308 #define SDMMC_TCBCNT 0x05c 309 #define SDMMC_TBBCNT 0x060 310 #define SDMMC_DEBNCE 0x064 311 #define SDMMC_USRID 0x068 312 #define SDMMC_VERID 0x06c 313 #define SDMMC_HCON 0x070 314 #define SDMMC_UHS_REG 0x074 315 #define SDMMC_RST_N 0x078 316 #define SDMMC_BMOD 0x080 317 #define SDMMC_PLDMND 0x084 318 #define SDMMC_DBADDR 0x088 319 #define SDMMC_IDSTS 0x08c 320 #define SDMMC_IDINTEN 0x090 321 #define SDMMC_DSCADDR 0x094 322 #define SDMMC_BUFADDR 0x098 323 #define SDMMC_CDTHRCTL 0x100 324 #define SDMMC_UHS_REG_EXT 0x108 325 #define SDMMC_DDR_REG 0x10c 326 #define SDMMC_ENABLE_SHIFT 0x110 327 #define SDMMC_DATA(x) (x) 328 /* 329 * Registers to support idmac 64-bit address mode 330 */ 331 #define SDMMC_DBADDRL 0x088 332 #define SDMMC_DBADDRU 0x08c 333 #define SDMMC_IDSTS64 0x090 334 #define SDMMC_IDINTEN64 0x094 335 #define SDMMC_DSCADDRL 0x098 336 #define SDMMC_DSCADDRU 0x09c 337 #define SDMMC_BUFADDRL 0x0A0 338 #define SDMMC_BUFADDRU 0x0A4 339 340 /* 341 * Data offset is difference according to Version 342 * Lower than 2.40a : data register offest is 0x100 343 */ 344 #define DATA_OFFSET 0x100 345 #define DATA_240A_OFFSET 0x200 346 347 /* shift bit field */ 348 #define _SBF(f, v) ((v) << (f)) 349 350 /* Control register defines */ 351 #define SDMMC_CTRL_USE_IDMAC BIT(25) 352 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 353 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 354 #define SDMMC_CTRL_SEND_CCSD BIT(9) 355 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 356 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 357 #define SDMMC_CTRL_READ_WAIT BIT(6) 358 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 359 #define SDMMC_CTRL_INT_ENABLE BIT(4) 360 #define SDMMC_CTRL_DMA_RESET BIT(2) 361 #define SDMMC_CTRL_FIFO_RESET BIT(1) 362 #define SDMMC_CTRL_RESET BIT(0) 363 /* Clock Enable register defines */ 364 #define SDMMC_CLKEN_LOW_PWR BIT(16) 365 #define SDMMC_CLKEN_ENABLE BIT(0) 366 /* time-out register defines */ 367 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 368 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 369 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 370 #define SDMMC_TMOUT_RESP_MSK 0xFF 371 /* card-type register defines */ 372 #define SDMMC_CTYPE_8BIT BIT(16) 373 #define SDMMC_CTYPE_4BIT BIT(0) 374 #define SDMMC_CTYPE_1BIT 0 375 /* Interrupt status & mask register defines */ 376 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 377 #define SDMMC_INT_EBE BIT(15) 378 #define SDMMC_INT_ACD BIT(14) 379 #define SDMMC_INT_SBE BIT(13) 380 #define SDMMC_INT_HLE BIT(12) 381 #define SDMMC_INT_FRUN BIT(11) 382 #define SDMMC_INT_HTO BIT(10) 383 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 384 #define SDMMC_INT_DRTO BIT(9) 385 #define SDMMC_INT_RTO BIT(8) 386 #define SDMMC_INT_DCRC BIT(7) 387 #define SDMMC_INT_RCRC BIT(6) 388 #define SDMMC_INT_RXDR BIT(5) 389 #define SDMMC_INT_TXDR BIT(4) 390 #define SDMMC_INT_DATA_OVER BIT(3) 391 #define SDMMC_INT_CMD_DONE BIT(2) 392 #define SDMMC_INT_RESP_ERR BIT(1) 393 #define SDMMC_INT_CD BIT(0) 394 #define SDMMC_INT_ERROR 0xbfc2 395 /* Command register defines */ 396 #define SDMMC_CMD_START BIT(31) 397 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 398 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 399 #define SDMMC_CMD_CCS_EXP BIT(23) 400 #define SDMMC_CMD_CEATA_RD BIT(22) 401 #define SDMMC_CMD_UPD_CLK BIT(21) 402 #define SDMMC_CMD_INIT BIT(15) 403 #define SDMMC_CMD_STOP BIT(14) 404 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 405 #define SDMMC_CMD_SEND_STOP BIT(12) 406 #define SDMMC_CMD_STRM_MODE BIT(11) 407 #define SDMMC_CMD_DAT_WR BIT(10) 408 #define SDMMC_CMD_DAT_EXP BIT(9) 409 #define SDMMC_CMD_RESP_CRC BIT(8) 410 #define SDMMC_CMD_RESP_LONG BIT(7) 411 #define SDMMC_CMD_RESP_EXP BIT(6) 412 #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 413 /* Status register defines */ 414 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 415 #define SDMMC_STATUS_DMA_REQ BIT(31) 416 #define SDMMC_STATUS_BUSY BIT(9) 417 /* FIFOTH register defines */ 418 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 419 ((r) & 0xFFF) << 16 | \ 420 ((t) & 0xFFF)) 421 /* HCON register defines */ 422 #define DMA_INTERFACE_IDMA (0x0) 423 #define DMA_INTERFACE_DWDMA (0x1) 424 #define DMA_INTERFACE_GDMA (0x2) 425 #define DMA_INTERFACE_NODMA (0x3) 426 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 427 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 428 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 429 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 430 /* Internal DMAC interrupt defines */ 431 #define SDMMC_IDMAC_INT_AI BIT(9) 432 #define SDMMC_IDMAC_INT_NI BIT(8) 433 #define SDMMC_IDMAC_INT_CES BIT(5) 434 #define SDMMC_IDMAC_INT_DU BIT(4) 435 #define SDMMC_IDMAC_INT_FBE BIT(2) 436 #define SDMMC_IDMAC_INT_RI BIT(1) 437 #define SDMMC_IDMAC_INT_TI BIT(0) 438 /* Internal DMAC bus mode bits */ 439 #define SDMMC_IDMAC_ENABLE BIT(7) 440 #define SDMMC_IDMAC_FB BIT(1) 441 #define SDMMC_IDMAC_SWRESET BIT(0) 442 /* H/W reset */ 443 #define SDMMC_RST_HWACTIVE 0x1 444 /* Version ID register define */ 445 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 446 /* Card read threshold */ 447 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 448 #define SDMMC_CARD_WR_THR_EN BIT(2) 449 #define SDMMC_CARD_RD_THR_EN BIT(0) 450 /* UHS-1 register defines */ 451 #define SDMMC_UHS_DDR BIT(16) 452 #define SDMMC_UHS_18V BIT(0) 453 /* DDR register defines */ 454 #define SDMMC_DDR_HS400 BIT(31) 455 /* Enable shift register defines */ 456 #define SDMMC_ENABLE_PHASE BIT(0) 457 /* All ctrl reset bits */ 458 #define SDMMC_CTRL_ALL_RESET_FLAGS \ 459 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 460 461 /* FIFO register access macros. These should not change the data endian-ness 462 * as they are written to memory to be dealt with by the upper layers 463 */ 464 #define mci_fifo_readw(__reg) __raw_readw(__reg) 465 #define mci_fifo_readl(__reg) __raw_readl(__reg) 466 #define mci_fifo_readq(__reg) __raw_readq(__reg) 467 468 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 469 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 470 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 471 472 /* Register access macros */ 473 #define mci_readl(dev, reg) \ 474 readl_relaxed((dev)->regs + SDMMC_##reg) 475 #define mci_writel(dev, reg, value) \ 476 writel_relaxed((value), (dev)->regs + SDMMC_##reg) 477 478 /* 16-bit FIFO access macros */ 479 #define mci_readw(dev, reg) \ 480 readw_relaxed((dev)->regs + SDMMC_##reg) 481 #define mci_writew(dev, reg, value) \ 482 writew_relaxed((value), (dev)->regs + SDMMC_##reg) 483 484 /* 64-bit FIFO access macros */ 485 #ifdef readq 486 #define mci_readq(dev, reg) \ 487 readq_relaxed((dev)->regs + SDMMC_##reg) 488 #define mci_writeq(dev, reg, value) \ 489 writeq_relaxed((value), (dev)->regs + SDMMC_##reg) 490 #else 491 /* 492 * Dummy readq implementation for architectures that don't define it. 493 * 494 * We would assume that none of these architectures would configure 495 * the IP block with a 64bit FIFO width, so this code will never be 496 * executed on those machines. Defining these macros here keeps the 497 * rest of the code free from ifdefs. 498 */ 499 #define mci_readq(dev, reg) \ 500 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 501 #define mci_writeq(dev, reg, value) \ 502 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 503 504 #define __raw_writeq(__value, __reg) \ 505 (*(volatile u64 __force *)(__reg) = (__value)) 506 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 507 #endif 508 509 extern int dw_mci_probe(struct dw_mci *host); 510 extern void dw_mci_remove(struct dw_mci *host); 511 #ifdef CONFIG_PM 512 extern int dw_mci_runtime_suspend(struct device *device); 513 extern int dw_mci_runtime_resume(struct device *device); 514 #endif 515 516 /** 517 * struct dw_mci_slot - MMC slot state 518 * @mmc: The mmc_host representing this slot. 519 * @host: The MMC controller this slot is using. 520 * @ctype: Card type for this slot. 521 * @mrq: mmc_request currently being processed or waiting to be 522 * processed, or NULL when the slot is idle. 523 * @queue_node: List node for placing this node in the @queue list of 524 * &struct dw_mci. 525 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 526 * @__clk_old: The last clock value that was requested from core. 527 * Keeping track of this helps us to avoid spamming the console. 528 * @flags: Random state bits associated with the slot. 529 * @id: Number of this slot. 530 * @sdio_id: Number of this slot in the SDIO interrupt registers. 531 */ 532 struct dw_mci_slot { 533 struct mmc_host *mmc; 534 struct dw_mci *host; 535 536 u32 ctype; 537 538 struct mmc_request *mrq; 539 struct list_head queue_node; 540 541 unsigned int clock; 542 unsigned int __clk_old; 543 544 unsigned long flags; 545 #define DW_MMC_CARD_PRESENT 0 546 #define DW_MMC_CARD_NEED_INIT 1 547 #define DW_MMC_CARD_NO_LOW_PWR 2 548 #define DW_MMC_CARD_NO_USE_HOLD 3 549 #define DW_MMC_CARD_NEEDS_POLL 4 550 int id; 551 int sdio_id; 552 }; 553 554 /** 555 * dw_mci driver data - dw-mshc implementation specific driver data. 556 * @caps: mmc subsystem specified capabilities of the controller(s). 557 * @num_caps: number of capabilities specified by @caps. 558 * @common_caps: mmc subsystem specified capabilities applicable to all of 559 * the controllers 560 * @init: early implementation specific initialization. 561 * @set_ios: handle bus specific extensions. 562 * @parse_dt: parse implementation specific device tree properties. 563 * @execute_tuning: implementation specific tuning procedure. 564 * @set_data_timeout: implementation specific timeout. 565 * @get_drto_clks: implementation specific cycle count for data read timeout. 566 * 567 * Provide controller implementation specific extensions. The usage of this 568 * data structure is fully optional and usage of each member in this structure 569 * is optional as well. 570 */ 571 struct dw_mci_drv_data { 572 unsigned long *caps; 573 u32 num_caps; 574 u32 common_caps; 575 int (*init)(struct dw_mci *host); 576 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 577 int (*parse_dt)(struct dw_mci *host); 578 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); 579 int (*prepare_hs400_tuning)(struct dw_mci *host, 580 struct mmc_ios *ios); 581 int (*switch_voltage)(struct mmc_host *mmc, 582 struct mmc_ios *ios); 583 void (*set_data_timeout)(struct dw_mci *host, 584 unsigned int timeout_ns); 585 u32 (*get_drto_clks)(struct dw_mci *host); 586 }; 587 #endif /* _DW_MMC_H_ */ 588