1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef _DW_MMC_H_ 15 #define _DW_MMC_H_ 16 17 #include <linux/scatterlist.h> 18 #include <linux/mmc/core.h> 19 #include <linux/dmaengine.h> 20 #include <linux/reset.h> 21 22 #define MAX_MCI_SLOTS 2 23 24 enum dw_mci_state { 25 STATE_IDLE = 0, 26 STATE_SENDING_CMD, 27 STATE_SENDING_DATA, 28 STATE_DATA_BUSY, 29 STATE_SENDING_STOP, 30 STATE_DATA_ERROR, 31 STATE_SENDING_CMD11, 32 STATE_WAITING_CMD11_DONE, 33 }; 34 35 enum { 36 EVENT_CMD_COMPLETE = 0, 37 EVENT_XFER_COMPLETE, 38 EVENT_DATA_COMPLETE, 39 EVENT_DATA_ERROR, 40 }; 41 42 enum dw_mci_cookie { 43 COOKIE_UNMAPPED, 44 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ 45 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ 46 }; 47 48 struct mmc_data; 49 50 enum { 51 TRANS_MODE_PIO = 0, 52 TRANS_MODE_IDMAC, 53 TRANS_MODE_EDMAC 54 }; 55 56 struct dw_mci_dma_slave { 57 struct dma_chan *ch; 58 enum dma_transfer_direction direction; 59 }; 60 61 /** 62 * struct dw_mci - MMC controller state shared between all slots 63 * @lock: Spinlock protecting the queue and associated data. 64 * @irq_lock: Spinlock protecting the INTMASK setting. 65 * @regs: Pointer to MMIO registers. 66 * @fifo_reg: Pointer to MMIO registers for data FIFO 67 * @sg: Scatterlist entry currently being processed by PIO code, if any. 68 * @sg_miter: PIO mapping scatterlist iterator. 69 * @cur_slot: The slot which is currently using the controller. 70 * @mrq: The request currently being processed on @cur_slot, 71 * or NULL if the controller is idle. 72 * @cmd: The command currently being sent to the card, or NULL. 73 * @data: The data currently being transferred, or NULL if no data 74 * transfer is in progress. 75 * @stop_abort: The command currently prepared for stoping transfer. 76 * @prev_blksz: The former transfer blksz record. 77 * @timing: Record of current ios timing. 78 * @use_dma: Whether DMA channel is initialized or not. 79 * @using_dma: Whether DMA is in use for the current transfer. 80 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 81 * @sg_dma: Bus address of DMA buffer. 82 * @sg_cpu: Virtual address of DMA buffer. 83 * @dma_ops: Pointer to platform-specific DMA callbacks. 84 * @cmd_status: Snapshot of SR taken upon completion of the current 85 * @ring_size: Buffer size for idma descriptors. 86 * command. Only valid when EVENT_CMD_COMPLETE is pending. 87 * @dms: structure of slave-dma private data. 88 * @phy_regs: physical address of controller's register map 89 * @data_status: Snapshot of SR taken upon completion of the current 90 * data transfer. Only valid when EVENT_DATA_COMPLETE or 91 * EVENT_DATA_ERROR is pending. 92 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 93 * to be sent. 94 * @dir_status: Direction of current transfer. 95 * @tasklet: Tasklet running the request state machine. 96 * @pending_events: Bitmask of events flagged by the interrupt handler 97 * to be processed by the tasklet. 98 * @completed_events: Bitmask of events which the state machine has 99 * processed. 100 * @state: Tasklet state. 101 * @queue: List of slots waiting for access to the controller. 102 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 103 * rate and timeout calculations. 104 * @current_speed: Configured rate of the controller. 105 * @num_slots: Number of slots available. 106 * @fifoth_val: The value of FIFOTH register. 107 * @verid: Denote Version ID. 108 * @dev: Device associated with the MMC controller. 109 * @pdata: Platform data associated with the MMC controller. 110 * @drv_data: Driver specific data for identified variant of the controller 111 * @priv: Implementation defined private data. 112 * @biu_clk: Pointer to bus interface unit clock instance. 113 * @ciu_clk: Pointer to card interface unit clock instance. 114 * @slot: Slots sharing this MMC controller. 115 * @fifo_depth: depth of FIFO. 116 * @data_shift: log2 of FIFO item size. 117 * @part_buf_start: Start index in part_buf. 118 * @part_buf_count: Bytes of partial data in part_buf. 119 * @part_buf: Simple buffer for partial fifo reads/writes. 120 * @push_data: Pointer to FIFO push function. 121 * @pull_data: Pointer to FIFO pull function. 122 * @vqmmc_enabled: Status of vqmmc, should be true or false. 123 * @irq_flags: The flags to be passed to request_irq. 124 * @irq: The irq value to be passed to request_irq. 125 * @sdio_id0: Number of slot0 in the SDIO interrupt registers. 126 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. 127 * @dto_timer: Timer for broken data transfer over scheme. 128 * 129 * Locking 130 * ======= 131 * 132 * @lock is a softirq-safe spinlock protecting @queue as well as 133 * @cur_slot, @mrq and @state. These must always be updated 134 * at the same time while holding @lock. 135 * 136 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 137 * to allow the interrupt handler to modify it directly. Held for only long 138 * enough to read-modify-write INTMASK and no other locks are grabbed when 139 * holding this one. 140 * 141 * The @mrq field of struct dw_mci_slot is also protected by @lock, 142 * and must always be written at the same time as the slot is added to 143 * @queue. 144 * 145 * @pending_events and @completed_events are accessed using atomic bit 146 * operations, so they don't need any locking. 147 * 148 * None of the fields touched by the interrupt handler need any 149 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 150 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 151 * interrupts must be disabled and @data_status updated with a 152 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 153 * CMDRDY interrupt must be disabled and @cmd_status updated with a 154 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 155 * bytes_xfered field of @data must be written. This is ensured by 156 * using barriers. 157 */ 158 struct dw_mci { 159 spinlock_t lock; 160 spinlock_t irq_lock; 161 void __iomem *regs; 162 void __iomem *fifo_reg; 163 164 struct scatterlist *sg; 165 struct sg_mapping_iter sg_miter; 166 167 struct dw_mci_slot *cur_slot; 168 struct mmc_request *mrq; 169 struct mmc_command *cmd; 170 struct mmc_data *data; 171 struct mmc_command stop_abort; 172 unsigned int prev_blksz; 173 unsigned char timing; 174 175 /* DMA interface members*/ 176 int use_dma; 177 int using_dma; 178 int dma_64bit_address; 179 180 dma_addr_t sg_dma; 181 void *sg_cpu; 182 const struct dw_mci_dma_ops *dma_ops; 183 /* For idmac */ 184 unsigned int ring_size; 185 186 /* For edmac */ 187 struct dw_mci_dma_slave *dms; 188 /* Registers's physical base address */ 189 resource_size_t phy_regs; 190 191 u32 cmd_status; 192 u32 data_status; 193 u32 stop_cmdr; 194 u32 dir_status; 195 struct tasklet_struct tasklet; 196 unsigned long pending_events; 197 unsigned long completed_events; 198 enum dw_mci_state state; 199 struct list_head queue; 200 201 u32 bus_hz; 202 u32 current_speed; 203 u32 num_slots; 204 u32 fifoth_val; 205 u16 verid; 206 struct device *dev; 207 struct dw_mci_board *pdata; 208 const struct dw_mci_drv_data *drv_data; 209 void *priv; 210 struct clk *biu_clk; 211 struct clk *ciu_clk; 212 struct dw_mci_slot *slot[MAX_MCI_SLOTS]; 213 214 /* FIFO push and pull */ 215 int fifo_depth; 216 int data_shift; 217 u8 part_buf_start; 218 u8 part_buf_count; 219 union { 220 u16 part_buf16; 221 u32 part_buf32; 222 u64 part_buf; 223 }; 224 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 225 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 226 227 bool vqmmc_enabled; 228 unsigned long irq_flags; /* IRQ flags */ 229 int irq; 230 231 int sdio_id0; 232 233 struct timer_list cmd11_timer; 234 struct timer_list dto_timer; 235 }; 236 237 /* DMA ops for Internal/External DMAC interface */ 238 struct dw_mci_dma_ops { 239 /* DMA Ops */ 240 int (*init)(struct dw_mci *host); 241 int (*start)(struct dw_mci *host, unsigned int sg_len); 242 void (*complete)(void *host); 243 void (*stop)(struct dw_mci *host); 244 void (*cleanup)(struct dw_mci *host); 245 void (*exit)(struct dw_mci *host); 246 }; 247 248 struct dma_pdata; 249 250 /* Board platform data */ 251 struct dw_mci_board { 252 u32 num_slots; 253 254 unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 255 256 u32 caps; /* Capabilities */ 257 u32 caps2; /* More capabilities */ 258 u32 pm_caps; /* PM capabilities */ 259 /* 260 * Override fifo depth. If 0, autodetect it from the FIFOTH register, 261 * but note that this may not be reliable after a bootloader has used 262 * it. 263 */ 264 unsigned int fifo_depth; 265 266 /* delay in mS before detecting cards after interrupt */ 267 u32 detect_delay_ms; 268 269 struct reset_control *rstc; 270 struct dw_mci_dma_ops *dma_ops; 271 struct dma_pdata *data; 272 }; 273 274 #define DW_MMC_240A 0x240a 275 #define DW_MMC_280A 0x280a 276 277 #define SDMMC_CTRL 0x000 278 #define SDMMC_PWREN 0x004 279 #define SDMMC_CLKDIV 0x008 280 #define SDMMC_CLKSRC 0x00c 281 #define SDMMC_CLKENA 0x010 282 #define SDMMC_TMOUT 0x014 283 #define SDMMC_CTYPE 0x018 284 #define SDMMC_BLKSIZ 0x01c 285 #define SDMMC_BYTCNT 0x020 286 #define SDMMC_INTMASK 0x024 287 #define SDMMC_CMDARG 0x028 288 #define SDMMC_CMD 0x02c 289 #define SDMMC_RESP0 0x030 290 #define SDMMC_RESP1 0x034 291 #define SDMMC_RESP2 0x038 292 #define SDMMC_RESP3 0x03c 293 #define SDMMC_MINTSTS 0x040 294 #define SDMMC_RINTSTS 0x044 295 #define SDMMC_STATUS 0x048 296 #define SDMMC_FIFOTH 0x04c 297 #define SDMMC_CDETECT 0x050 298 #define SDMMC_WRTPRT 0x054 299 #define SDMMC_GPIO 0x058 300 #define SDMMC_TCBCNT 0x05c 301 #define SDMMC_TBBCNT 0x060 302 #define SDMMC_DEBNCE 0x064 303 #define SDMMC_USRID 0x068 304 #define SDMMC_VERID 0x06c 305 #define SDMMC_HCON 0x070 306 #define SDMMC_UHS_REG 0x074 307 #define SDMMC_RST_N 0x078 308 #define SDMMC_BMOD 0x080 309 #define SDMMC_PLDMND 0x084 310 #define SDMMC_DBADDR 0x088 311 #define SDMMC_IDSTS 0x08c 312 #define SDMMC_IDINTEN 0x090 313 #define SDMMC_DSCADDR 0x094 314 #define SDMMC_BUFADDR 0x098 315 #define SDMMC_CDTHRCTL 0x100 316 #define SDMMC_DATA(x) (x) 317 /* 318 * Registers to support idmac 64-bit address mode 319 */ 320 #define SDMMC_DBADDRL 0x088 321 #define SDMMC_DBADDRU 0x08c 322 #define SDMMC_IDSTS64 0x090 323 #define SDMMC_IDINTEN64 0x094 324 #define SDMMC_DSCADDRL 0x098 325 #define SDMMC_DSCADDRU 0x09c 326 #define SDMMC_BUFADDRL 0x0A0 327 #define SDMMC_BUFADDRU 0x0A4 328 329 /* 330 * Data offset is difference according to Version 331 * Lower than 2.40a : data register offest is 0x100 332 */ 333 #define DATA_OFFSET 0x100 334 #define DATA_240A_OFFSET 0x200 335 336 /* shift bit field */ 337 #define _SBF(f, v) ((v) << (f)) 338 339 /* Control register defines */ 340 #define SDMMC_CTRL_USE_IDMAC BIT(25) 341 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 342 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 343 #define SDMMC_CTRL_SEND_CCSD BIT(9) 344 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 345 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 346 #define SDMMC_CTRL_READ_WAIT BIT(6) 347 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 348 #define SDMMC_CTRL_INT_ENABLE BIT(4) 349 #define SDMMC_CTRL_DMA_RESET BIT(2) 350 #define SDMMC_CTRL_FIFO_RESET BIT(1) 351 #define SDMMC_CTRL_RESET BIT(0) 352 /* Clock Enable register defines */ 353 #define SDMMC_CLKEN_LOW_PWR BIT(16) 354 #define SDMMC_CLKEN_ENABLE BIT(0) 355 /* time-out register defines */ 356 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 357 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 358 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 359 #define SDMMC_TMOUT_RESP_MSK 0xFF 360 /* card-type register defines */ 361 #define SDMMC_CTYPE_8BIT BIT(16) 362 #define SDMMC_CTYPE_4BIT BIT(0) 363 #define SDMMC_CTYPE_1BIT 0 364 /* Interrupt status & mask register defines */ 365 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 366 #define SDMMC_INT_EBE BIT(15) 367 #define SDMMC_INT_ACD BIT(14) 368 #define SDMMC_INT_SBE BIT(13) 369 #define SDMMC_INT_HLE BIT(12) 370 #define SDMMC_INT_FRUN BIT(11) 371 #define SDMMC_INT_HTO BIT(10) 372 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 373 #define SDMMC_INT_DRTO BIT(9) 374 #define SDMMC_INT_RTO BIT(8) 375 #define SDMMC_INT_DCRC BIT(7) 376 #define SDMMC_INT_RCRC BIT(6) 377 #define SDMMC_INT_RXDR BIT(5) 378 #define SDMMC_INT_TXDR BIT(4) 379 #define SDMMC_INT_DATA_OVER BIT(3) 380 #define SDMMC_INT_CMD_DONE BIT(2) 381 #define SDMMC_INT_RESP_ERR BIT(1) 382 #define SDMMC_INT_CD BIT(0) 383 #define SDMMC_INT_ERROR 0xbfc2 384 /* Command register defines */ 385 #define SDMMC_CMD_START BIT(31) 386 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 387 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 388 #define SDMMC_CMD_CCS_EXP BIT(23) 389 #define SDMMC_CMD_CEATA_RD BIT(22) 390 #define SDMMC_CMD_UPD_CLK BIT(21) 391 #define SDMMC_CMD_INIT BIT(15) 392 #define SDMMC_CMD_STOP BIT(14) 393 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 394 #define SDMMC_CMD_SEND_STOP BIT(12) 395 #define SDMMC_CMD_STRM_MODE BIT(11) 396 #define SDMMC_CMD_DAT_WR BIT(10) 397 #define SDMMC_CMD_DAT_EXP BIT(9) 398 #define SDMMC_CMD_RESP_CRC BIT(8) 399 #define SDMMC_CMD_RESP_LONG BIT(7) 400 #define SDMMC_CMD_RESP_EXP BIT(6) 401 #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 402 /* Status register defines */ 403 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 404 #define SDMMC_STATUS_DMA_REQ BIT(31) 405 #define SDMMC_STATUS_BUSY BIT(9) 406 /* FIFOTH register defines */ 407 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 408 ((r) & 0xFFF) << 16 | \ 409 ((t) & 0xFFF)) 410 /* HCON register defines */ 411 #define DMA_INTERFACE_IDMA (0x0) 412 #define DMA_INTERFACE_DWDMA (0x1) 413 #define DMA_INTERFACE_GDMA (0x2) 414 #define DMA_INTERFACE_NODMA (0x3) 415 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 416 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 417 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 418 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 419 /* Internal DMAC interrupt defines */ 420 #define SDMMC_IDMAC_INT_AI BIT(9) 421 #define SDMMC_IDMAC_INT_NI BIT(8) 422 #define SDMMC_IDMAC_INT_CES BIT(5) 423 #define SDMMC_IDMAC_INT_DU BIT(4) 424 #define SDMMC_IDMAC_INT_FBE BIT(2) 425 #define SDMMC_IDMAC_INT_RI BIT(1) 426 #define SDMMC_IDMAC_INT_TI BIT(0) 427 /* Internal DMAC bus mode bits */ 428 #define SDMMC_IDMAC_ENABLE BIT(7) 429 #define SDMMC_IDMAC_FB BIT(1) 430 #define SDMMC_IDMAC_SWRESET BIT(0) 431 /* H/W reset */ 432 #define SDMMC_RST_HWACTIVE 0x1 433 /* Version ID register define */ 434 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 435 /* Card read threshold */ 436 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 437 #define SDMMC_CARD_WR_THR_EN BIT(2) 438 #define SDMMC_CARD_RD_THR_EN BIT(0) 439 /* UHS-1 register defines */ 440 #define SDMMC_UHS_18V BIT(0) 441 /* All ctrl reset bits */ 442 #define SDMMC_CTRL_ALL_RESET_FLAGS \ 443 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 444 445 /* FIFO register access macros. These should not change the data endian-ness 446 * as they are written to memory to be dealt with by the upper layers */ 447 #define mci_fifo_readw(__reg) __raw_readw(__reg) 448 #define mci_fifo_readl(__reg) __raw_readl(__reg) 449 #define mci_fifo_readq(__reg) __raw_readq(__reg) 450 451 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 452 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 453 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 454 455 /* Register access macros */ 456 #define mci_readl(dev, reg) \ 457 readl_relaxed((dev)->regs + SDMMC_##reg) 458 #define mci_writel(dev, reg, value) \ 459 writel_relaxed((value), (dev)->regs + SDMMC_##reg) 460 461 /* 16-bit FIFO access macros */ 462 #define mci_readw(dev, reg) \ 463 readw_relaxed((dev)->regs + SDMMC_##reg) 464 #define mci_writew(dev, reg, value) \ 465 writew_relaxed((value), (dev)->regs + SDMMC_##reg) 466 467 /* 64-bit FIFO access macros */ 468 #ifdef readq 469 #define mci_readq(dev, reg) \ 470 readq_relaxed((dev)->regs + SDMMC_##reg) 471 #define mci_writeq(dev, reg, value) \ 472 writeq_relaxed((value), (dev)->regs + SDMMC_##reg) 473 #else 474 /* 475 * Dummy readq implementation for architectures that don't define it. 476 * 477 * We would assume that none of these architectures would configure 478 * the IP block with a 64bit FIFO width, so this code will never be 479 * executed on those machines. Defining these macros here keeps the 480 * rest of the code free from ifdefs. 481 */ 482 #define mci_readq(dev, reg) \ 483 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 484 #define mci_writeq(dev, reg, value) \ 485 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 486 487 #define __raw_writeq(__value, __reg) \ 488 (*(volatile u64 __force *)(__reg) = (__value)) 489 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 490 #endif 491 492 extern int dw_mci_probe(struct dw_mci *host); 493 extern void dw_mci_remove(struct dw_mci *host); 494 #ifdef CONFIG_PM 495 extern int dw_mci_runtime_suspend(struct device *device); 496 extern int dw_mci_runtime_resume(struct device *device); 497 #endif 498 499 /** 500 * struct dw_mci_slot - MMC slot state 501 * @mmc: The mmc_host representing this slot. 502 * @host: The MMC controller this slot is using. 503 * @ctype: Card type for this slot. 504 * @mrq: mmc_request currently being processed or waiting to be 505 * processed, or NULL when the slot is idle. 506 * @queue_node: List node for placing this node in the @queue list of 507 * &struct dw_mci. 508 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 509 * @__clk_old: The last clock value that was requested from core. 510 * Keeping track of this helps us to avoid spamming the console. 511 * @flags: Random state bits associated with the slot. 512 * @id: Number of this slot. 513 * @sdio_id: Number of this slot in the SDIO interrupt registers. 514 */ 515 struct dw_mci_slot { 516 struct mmc_host *mmc; 517 struct dw_mci *host; 518 519 u32 ctype; 520 521 struct mmc_request *mrq; 522 struct list_head queue_node; 523 524 unsigned int clock; 525 unsigned int __clk_old; 526 527 unsigned long flags; 528 #define DW_MMC_CARD_PRESENT 0 529 #define DW_MMC_CARD_NEED_INIT 1 530 #define DW_MMC_CARD_NO_LOW_PWR 2 531 #define DW_MMC_CARD_NO_USE_HOLD 3 532 #define DW_MMC_CARD_NEEDS_POLL 4 533 int id; 534 int sdio_id; 535 }; 536 537 /** 538 * dw_mci driver data - dw-mshc implementation specific driver data. 539 * @caps: mmc subsystem specified capabilities of the controller(s). 540 * @init: early implementation specific initialization. 541 * @set_ios: handle bus specific extensions. 542 * @parse_dt: parse implementation specific device tree properties. 543 * @execute_tuning: implementation specific tuning procedure. 544 * 545 * Provide controller implementation specific extensions. The usage of this 546 * data structure is fully optional and usage of each member in this structure 547 * is optional as well. 548 */ 549 struct dw_mci_drv_data { 550 unsigned long *caps; 551 int (*init)(struct dw_mci *host); 552 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 553 int (*parse_dt)(struct dw_mci *host); 554 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); 555 int (*prepare_hs400_tuning)(struct dw_mci *host, 556 struct mmc_ios *ios); 557 int (*switch_voltage)(struct mmc_host *mmc, 558 struct mmc_ios *ios); 559 }; 560 #endif /* _DW_MMC_H_ */ 561