1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #ifndef _DW_MMC_H_ 15f95f3850SWill Newton #define _DW_MMC_H_ 16f95f3850SWill Newton 174e0a5adfSJaehoon Chung #define DW_MMC_240A 0x240a 187e4bf1bcSJaehoon Chung #define DW_MMC_280A 0x280a 194e0a5adfSJaehoon Chung 20f95f3850SWill Newton #define SDMMC_CTRL 0x000 21f95f3850SWill Newton #define SDMMC_PWREN 0x004 22f95f3850SWill Newton #define SDMMC_CLKDIV 0x008 23f95f3850SWill Newton #define SDMMC_CLKSRC 0x00c 24f95f3850SWill Newton #define SDMMC_CLKENA 0x010 25f95f3850SWill Newton #define SDMMC_TMOUT 0x014 26f95f3850SWill Newton #define SDMMC_CTYPE 0x018 27f95f3850SWill Newton #define SDMMC_BLKSIZ 0x01c 28f95f3850SWill Newton #define SDMMC_BYTCNT 0x020 29f95f3850SWill Newton #define SDMMC_INTMASK 0x024 30f95f3850SWill Newton #define SDMMC_CMDARG 0x028 31f95f3850SWill Newton #define SDMMC_CMD 0x02c 32f95f3850SWill Newton #define SDMMC_RESP0 0x030 33f95f3850SWill Newton #define SDMMC_RESP1 0x034 34f95f3850SWill Newton #define SDMMC_RESP2 0x038 35f95f3850SWill Newton #define SDMMC_RESP3 0x03c 36f95f3850SWill Newton #define SDMMC_MINTSTS 0x040 37f95f3850SWill Newton #define SDMMC_RINTSTS 0x044 38f95f3850SWill Newton #define SDMMC_STATUS 0x048 39f95f3850SWill Newton #define SDMMC_FIFOTH 0x04c 40f95f3850SWill Newton #define SDMMC_CDETECT 0x050 41f95f3850SWill Newton #define SDMMC_WRTPRT 0x054 42f95f3850SWill Newton #define SDMMC_GPIO 0x058 43f95f3850SWill Newton #define SDMMC_TCBCNT 0x05c 44f95f3850SWill Newton #define SDMMC_TBBCNT 0x060 45f95f3850SWill Newton #define SDMMC_DEBNCE 0x064 46f95f3850SWill Newton #define SDMMC_USRID 0x068 47f95f3850SWill Newton #define SDMMC_VERID 0x06c 48f95f3850SWill Newton #define SDMMC_HCON 0x070 4941babf75SJaehoon Chung #define SDMMC_UHS_REG 0x074 50935a665eSShawn Lin #define SDMMC_RST_N 0x078 51f95f3850SWill Newton #define SDMMC_BMOD 0x080 52f95f3850SWill Newton #define SDMMC_PLDMND 0x084 53f95f3850SWill Newton #define SDMMC_DBADDR 0x088 54f95f3850SWill Newton #define SDMMC_IDSTS 0x08c 55f95f3850SWill Newton #define SDMMC_IDINTEN 0x090 56f95f3850SWill Newton #define SDMMC_DSCADDR 0x094 57f95f3850SWill Newton #define SDMMC_BUFADDR 0x098 58f1d2736cSSeungwon Jeon #define SDMMC_CDTHRCTL 0x100 594e0a5adfSJaehoon Chung #define SDMMC_DATA(x) (x) 6069d99fdcSPrabu Thangamuthu /* 6169d99fdcSPrabu Thangamuthu * Registers to support idmac 64-bit address mode 6269d99fdcSPrabu Thangamuthu */ 6369d99fdcSPrabu Thangamuthu #define SDMMC_DBADDRL 0x088 6469d99fdcSPrabu Thangamuthu #define SDMMC_DBADDRU 0x08c 6569d99fdcSPrabu Thangamuthu #define SDMMC_IDSTS64 0x090 6669d99fdcSPrabu Thangamuthu #define SDMMC_IDINTEN64 0x094 6769d99fdcSPrabu Thangamuthu #define SDMMC_DSCADDRL 0x098 6869d99fdcSPrabu Thangamuthu #define SDMMC_DSCADDRU 0x09c 6969d99fdcSPrabu Thangamuthu #define SDMMC_BUFADDRL 0x0A0 7069d99fdcSPrabu Thangamuthu #define SDMMC_BUFADDRU 0x0A4 714e0a5adfSJaehoon Chung 724e0a5adfSJaehoon Chung /* 734e0a5adfSJaehoon Chung * Data offset is difference according to Version 744e0a5adfSJaehoon Chung * Lower than 2.40a : data register offest is 0x100 754e0a5adfSJaehoon Chung */ 764e0a5adfSJaehoon Chung #define DATA_OFFSET 0x100 774e0a5adfSJaehoon Chung #define DATA_240A_OFFSET 0x200 78f95f3850SWill Newton 79f95f3850SWill Newton /* shift bit field */ 80f95f3850SWill Newton #define _SBF(f, v) ((v) << (f)) 81f95f3850SWill Newton 82f95f3850SWill Newton /* Control register defines */ 83f95f3850SWill Newton #define SDMMC_CTRL_USE_IDMAC BIT(25) 84f95f3850SWill Newton #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 85f95f3850SWill Newton #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 86f95f3850SWill Newton #define SDMMC_CTRL_SEND_CCSD BIT(9) 87f95f3850SWill Newton #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 88f95f3850SWill Newton #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 89f95f3850SWill Newton #define SDMMC_CTRL_READ_WAIT BIT(6) 90f95f3850SWill Newton #define SDMMC_CTRL_DMA_ENABLE BIT(5) 91f95f3850SWill Newton #define SDMMC_CTRL_INT_ENABLE BIT(4) 92f95f3850SWill Newton #define SDMMC_CTRL_DMA_RESET BIT(2) 93f95f3850SWill Newton #define SDMMC_CTRL_FIFO_RESET BIT(1) 94f95f3850SWill Newton #define SDMMC_CTRL_RESET BIT(0) 95f95f3850SWill Newton /* Clock Enable register defines */ 96f95f3850SWill Newton #define SDMMC_CLKEN_LOW_PWR BIT(16) 97f95f3850SWill Newton #define SDMMC_CLKEN_ENABLE BIT(0) 98f95f3850SWill Newton /* time-out register defines */ 99f95f3850SWill Newton #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 100f95f3850SWill Newton #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 101f95f3850SWill Newton #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 102f95f3850SWill Newton #define SDMMC_TMOUT_RESP_MSK 0xFF 103f95f3850SWill Newton /* card-type register defines */ 104f95f3850SWill Newton #define SDMMC_CTYPE_8BIT BIT(16) 105f95f3850SWill Newton #define SDMMC_CTYPE_4BIT BIT(0) 106f95f3850SWill Newton #define SDMMC_CTYPE_1BIT 0 107f95f3850SWill Newton /* Interrupt status & mask register defines */ 1081a5c8e1fSShashidhar Hiremath #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 109f95f3850SWill Newton #define SDMMC_INT_EBE BIT(15) 110f95f3850SWill Newton #define SDMMC_INT_ACD BIT(14) 111f95f3850SWill Newton #define SDMMC_INT_SBE BIT(13) 112f95f3850SWill Newton #define SDMMC_INT_HLE BIT(12) 113f95f3850SWill Newton #define SDMMC_INT_FRUN BIT(11) 114f95f3850SWill Newton #define SDMMC_INT_HTO BIT(10) 11501730558SDoug Anderson #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 1163f7eec62SJaehoon Chung #define SDMMC_INT_DRTO BIT(9) 117f95f3850SWill Newton #define SDMMC_INT_RTO BIT(8) 118f95f3850SWill Newton #define SDMMC_INT_DCRC BIT(7) 119f95f3850SWill Newton #define SDMMC_INT_RCRC BIT(6) 120f95f3850SWill Newton #define SDMMC_INT_RXDR BIT(5) 121f95f3850SWill Newton #define SDMMC_INT_TXDR BIT(4) 122f95f3850SWill Newton #define SDMMC_INT_DATA_OVER BIT(3) 123f95f3850SWill Newton #define SDMMC_INT_CMD_DONE BIT(2) 124f95f3850SWill Newton #define SDMMC_INT_RESP_ERR BIT(1) 125f95f3850SWill Newton #define SDMMC_INT_CD BIT(0) 126f95f3850SWill Newton #define SDMMC_INT_ERROR 0xbfc2 127f95f3850SWill Newton /* Command register defines */ 128f95f3850SWill Newton #define SDMMC_CMD_START BIT(31) 129eede2111SDinh Nguyen #define SDMMC_CMD_USE_HOLD_REG BIT(29) 13001730558SDoug Anderson #define SDMMC_CMD_VOLT_SWITCH BIT(28) 131f95f3850SWill Newton #define SDMMC_CMD_CCS_EXP BIT(23) 132f95f3850SWill Newton #define SDMMC_CMD_CEATA_RD BIT(22) 133f95f3850SWill Newton #define SDMMC_CMD_UPD_CLK BIT(21) 134f95f3850SWill Newton #define SDMMC_CMD_INIT BIT(15) 135f95f3850SWill Newton #define SDMMC_CMD_STOP BIT(14) 136f95f3850SWill Newton #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 137f95f3850SWill Newton #define SDMMC_CMD_SEND_STOP BIT(12) 138f95f3850SWill Newton #define SDMMC_CMD_STRM_MODE BIT(11) 139f95f3850SWill Newton #define SDMMC_CMD_DAT_WR BIT(10) 140f95f3850SWill Newton #define SDMMC_CMD_DAT_EXP BIT(9) 141f95f3850SWill Newton #define SDMMC_CMD_RESP_CRC BIT(8) 142f95f3850SWill Newton #define SDMMC_CMD_RESP_LONG BIT(7) 143f95f3850SWill Newton #define SDMMC_CMD_RESP_EXP BIT(6) 144f95f3850SWill Newton #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 145f95f3850SWill Newton /* Status register defines */ 146ee5d19b2SJaehoon Chung #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 1473a33a94cSSonny Rao #define SDMMC_STATUS_DMA_REQ BIT(31) 14801730558SDoug Anderson #define SDMMC_STATUS_BUSY BIT(9) 14952426899SSeungwon Jeon /* FIFOTH register defines */ 15052426899SSeungwon Jeon #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 15152426899SSeungwon Jeon ((r) & 0xFFF) << 16 | \ 15252426899SSeungwon Jeon ((t) & 0xFFF)) 1533fc7eaefSShawn Lin /* HCON register defines */ 1543fc7eaefSShawn Lin #define DMA_INTERFACE_IDMA (0x0) 1553fc7eaefSShawn Lin #define DMA_INTERFACE_DWDMA (0x1) 1563fc7eaefSShawn Lin #define DMA_INTERFACE_GDMA (0x2) 1573fc7eaefSShawn Lin #define DMA_INTERFACE_NODMA (0x3) 1583fc7eaefSShawn Lin #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 15970692752SShawn Lin #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 16070692752SShawn Lin #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 16170692752SShawn Lin #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 162f95f3850SWill Newton /* Internal DMAC interrupt defines */ 163f95f3850SWill Newton #define SDMMC_IDMAC_INT_AI BIT(9) 164f95f3850SWill Newton #define SDMMC_IDMAC_INT_NI BIT(8) 165f95f3850SWill Newton #define SDMMC_IDMAC_INT_CES BIT(5) 166f95f3850SWill Newton #define SDMMC_IDMAC_INT_DU BIT(4) 167f95f3850SWill Newton #define SDMMC_IDMAC_INT_FBE BIT(2) 168f95f3850SWill Newton #define SDMMC_IDMAC_INT_RI BIT(1) 169f95f3850SWill Newton #define SDMMC_IDMAC_INT_TI BIT(0) 170f95f3850SWill Newton /* Internal DMAC bus mode bits */ 171f95f3850SWill Newton #define SDMMC_IDMAC_ENABLE BIT(7) 172f95f3850SWill Newton #define SDMMC_IDMAC_FB BIT(1) 173f95f3850SWill Newton #define SDMMC_IDMAC_SWRESET BIT(0) 174935a665eSShawn Lin /* H/W reset */ 175935a665eSShawn Lin #define SDMMC_RST_HWACTIVE 0x1 1764e0a5adfSJaehoon Chung /* Version ID register define */ 1774e0a5adfSJaehoon Chung #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 178f1d2736cSSeungwon Jeon /* Card read threshold */ 1797e4bf1bcSJaehoon Chung #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 1807e4bf1bcSJaehoon Chung #define SDMMC_CARD_WR_THR_EN BIT(2) 1817e4bf1bcSJaehoon Chung #define SDMMC_CARD_RD_THR_EN BIT(0) 1827e4bf1bcSJaehoon Chung /* UHS-1 register defines */ 18301730558SDoug Anderson #define SDMMC_UHS_18V BIT(0) 1843a33a94cSSonny Rao /* All ctrl reset bits */ 1853a33a94cSSonny Rao #define SDMMC_CTRL_ALL_RESET_FLAGS \ 1863a33a94cSSonny Rao (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 1873a33a94cSSonny Rao 18876184ac1SBen Dooks /* FIFO register access macros. These should not change the data endian-ness 18976184ac1SBen Dooks * as they are written to memory to be dealt with by the upper layers */ 19076184ac1SBen Dooks #define mci_fifo_readw(__reg) __raw_readw(__reg) 19176184ac1SBen Dooks #define mci_fifo_readl(__reg) __raw_readl(__reg) 19276184ac1SBen Dooks #define mci_fifo_readq(__reg) __raw_readq(__reg) 19376184ac1SBen Dooks 19476184ac1SBen Dooks #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 19576184ac1SBen Dooks #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 19676184ac1SBen Dooks #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 19776184ac1SBen Dooks 198f95f3850SWill Newton /* Register access macros */ 199f95f3850SWill Newton #define mci_readl(dev, reg) \ 200a2f17680SBen Dooks readl_relaxed((dev)->regs + SDMMC_##reg) 201f95f3850SWill Newton #define mci_writel(dev, reg, value) \ 202a2f17680SBen Dooks writel_relaxed((value), (dev)->regs + SDMMC_##reg) 203f95f3850SWill Newton 204f95f3850SWill Newton /* 16-bit FIFO access macros */ 205f95f3850SWill Newton #define mci_readw(dev, reg) \ 206a2f17680SBen Dooks readw_relaxed((dev)->regs + SDMMC_##reg) 207f95f3850SWill Newton #define mci_writew(dev, reg, value) \ 208a2f17680SBen Dooks writew_relaxed((value), (dev)->regs + SDMMC_##reg) 209f95f3850SWill Newton 210f95f3850SWill Newton /* 64-bit FIFO access macros */ 211f95f3850SWill Newton #ifdef readq 212f95f3850SWill Newton #define mci_readq(dev, reg) \ 213a2f17680SBen Dooks readq_relaxed((dev)->regs + SDMMC_##reg) 214f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 215a2f17680SBen Dooks writeq_relaxed((value), (dev)->regs + SDMMC_##reg) 216f95f3850SWill Newton #else 217f95f3850SWill Newton /* 218f95f3850SWill Newton * Dummy readq implementation for architectures that don't define it. 219f95f3850SWill Newton * 220f95f3850SWill Newton * We would assume that none of these architectures would configure 221f95f3850SWill Newton * the IP block with a 64bit FIFO width, so this code will never be 222f95f3850SWill Newton * executed on those machines. Defining these macros here keeps the 223f95f3850SWill Newton * rest of the code free from ifdefs. 224f95f3850SWill Newton */ 225f95f3850SWill Newton #define mci_readq(dev, reg) \ 226892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 227f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 228892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 22976184ac1SBen Dooks 23076184ac1SBen Dooks #define __raw_writeq(__value, __reg) \ 23176184ac1SBen Dooks (*(volatile u64 __force *)(__reg) = (__value)) 23276184ac1SBen Dooks #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 233f95f3850SWill Newton #endif 234f95f3850SWill Newton 23562ca8034SShashidhar Hiremath extern int dw_mci_probe(struct dw_mci *host); 23662ca8034SShashidhar Hiremath extern void dw_mci_remove(struct dw_mci *host); 237e9ed8835SShawn Lin #ifdef CONFIG_PM 238e9ed8835SShawn Lin extern int dw_mci_runtime_suspend(struct device *device); 239e9ed8835SShawn Lin extern int dw_mci_runtime_resume(struct device *device); 24062ca8034SShashidhar Hiremath #endif 24162ca8034SShashidhar Hiremath 242800d78bfSThomas Abraham /** 2430976f16dSSeungwon Jeon * struct dw_mci_slot - MMC slot state 2440976f16dSSeungwon Jeon * @mmc: The mmc_host representing this slot. 2450976f16dSSeungwon Jeon * @host: The MMC controller this slot is using. 2460976f16dSSeungwon Jeon * @ctype: Card type for this slot. 2470976f16dSSeungwon Jeon * @mrq: mmc_request currently being processed or waiting to be 2480976f16dSSeungwon Jeon * processed, or NULL when the slot is idle. 2490976f16dSSeungwon Jeon * @queue_node: List node for placing this node in the @queue list of 2500976f16dSSeungwon Jeon * &struct dw_mci. 2510976f16dSSeungwon Jeon * @clock: Clock rate configured by set_ios(). Protected by host->lock. 252005d675aSJaehoon Chung * @__clk_old: The last clock value that was requested from core. 253005d675aSJaehoon Chung * Keeping track of this helps us to avoid spamming the console. 2540976f16dSSeungwon Jeon * @flags: Random state bits associated with the slot. 2550976f16dSSeungwon Jeon * @id: Number of this slot. 25676756234SAddy Ke * @sdio_id: Number of this slot in the SDIO interrupt registers. 2570976f16dSSeungwon Jeon */ 2580976f16dSSeungwon Jeon struct dw_mci_slot { 2590976f16dSSeungwon Jeon struct mmc_host *mmc; 2600976f16dSSeungwon Jeon struct dw_mci *host; 2610976f16dSSeungwon Jeon 2620976f16dSSeungwon Jeon u32 ctype; 2630976f16dSSeungwon Jeon 2640976f16dSSeungwon Jeon struct mmc_request *mrq; 2650976f16dSSeungwon Jeon struct list_head queue_node; 2660976f16dSSeungwon Jeon 2670976f16dSSeungwon Jeon unsigned int clock; 268005d675aSJaehoon Chung unsigned int __clk_old; 2690976f16dSSeungwon Jeon 2700976f16dSSeungwon Jeon unsigned long flags; 2710976f16dSSeungwon Jeon #define DW_MMC_CARD_PRESENT 0 2720976f16dSSeungwon Jeon #define DW_MMC_CARD_NEED_INIT 1 273b24c8b26SDoug Anderson #define DW_MMC_CARD_NO_LOW_PWR 2 274aaaaeb7aSJaehoon Chung #define DW_MMC_CARD_NO_USE_HOLD 3 275e6cd7a8eSJaehoon Chung #define DW_MMC_CARD_NEEDS_POLL 4 2760976f16dSSeungwon Jeon int id; 27776756234SAddy Ke int sdio_id; 2780976f16dSSeungwon Jeon }; 2790976f16dSSeungwon Jeon 2800976f16dSSeungwon Jeon /** 281800d78bfSThomas Abraham * dw_mci driver data - dw-mshc implementation specific driver data. 282800d78bfSThomas Abraham * @caps: mmc subsystem specified capabilities of the controller(s). 283800d78bfSThomas Abraham * @init: early implementation specific initialization. 284800d78bfSThomas Abraham * @set_ios: handle bus specific extensions. 285800d78bfSThomas Abraham * @parse_dt: parse implementation specific device tree properties. 2865532ec51SSachin Kamat * @execute_tuning: implementation specific tuning procedure. 287800d78bfSThomas Abraham * 288800d78bfSThomas Abraham * Provide controller implementation specific extensions. The usage of this 289800d78bfSThomas Abraham * data structure is fully optional and usage of each member in this structure 290800d78bfSThomas Abraham * is optional as well. 291800d78bfSThomas Abraham */ 292800d78bfSThomas Abraham struct dw_mci_drv_data { 293800d78bfSThomas Abraham unsigned long *caps; 294800d78bfSThomas Abraham int (*init)(struct dw_mci *host); 295800d78bfSThomas Abraham void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 296800d78bfSThomas Abraham int (*parse_dt)(struct dw_mci *host); 2979979dbe5SChaotian Jing int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); 29880113132SSeungwon Jeon int (*prepare_hs400_tuning)(struct dw_mci *host, 29980113132SSeungwon Jeon struct mmc_ios *ios); 3008f7849c4SZhangfei Gao int (*switch_voltage)(struct mmc_host *mmc, 3018f7849c4SZhangfei Gao struct mmc_ios *ios); 302800d78bfSThomas Abraham }; 303f95f3850SWill Newton #endif /* _DW_MMC_H_ */ 304