1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #ifndef _DW_MMC_H_ 15f95f3850SWill Newton #define _DW_MMC_H_ 16f95f3850SWill Newton 17f95f3850SWill Newton #define SDMMC_CTRL 0x000 18f95f3850SWill Newton #define SDMMC_PWREN 0x004 19f95f3850SWill Newton #define SDMMC_CLKDIV 0x008 20f95f3850SWill Newton #define SDMMC_CLKSRC 0x00c 21f95f3850SWill Newton #define SDMMC_CLKENA 0x010 22f95f3850SWill Newton #define SDMMC_TMOUT 0x014 23f95f3850SWill Newton #define SDMMC_CTYPE 0x018 24f95f3850SWill Newton #define SDMMC_BLKSIZ 0x01c 25f95f3850SWill Newton #define SDMMC_BYTCNT 0x020 26f95f3850SWill Newton #define SDMMC_INTMASK 0x024 27f95f3850SWill Newton #define SDMMC_CMDARG 0x028 28f95f3850SWill Newton #define SDMMC_CMD 0x02c 29f95f3850SWill Newton #define SDMMC_RESP0 0x030 30f95f3850SWill Newton #define SDMMC_RESP1 0x034 31f95f3850SWill Newton #define SDMMC_RESP2 0x038 32f95f3850SWill Newton #define SDMMC_RESP3 0x03c 33f95f3850SWill Newton #define SDMMC_MINTSTS 0x040 34f95f3850SWill Newton #define SDMMC_RINTSTS 0x044 35f95f3850SWill Newton #define SDMMC_STATUS 0x048 36f95f3850SWill Newton #define SDMMC_FIFOTH 0x04c 37f95f3850SWill Newton #define SDMMC_CDETECT 0x050 38f95f3850SWill Newton #define SDMMC_WRTPRT 0x054 39f95f3850SWill Newton #define SDMMC_GPIO 0x058 40f95f3850SWill Newton #define SDMMC_TCBCNT 0x05c 41f95f3850SWill Newton #define SDMMC_TBBCNT 0x060 42f95f3850SWill Newton #define SDMMC_DEBNCE 0x064 43f95f3850SWill Newton #define SDMMC_USRID 0x068 44f95f3850SWill Newton #define SDMMC_VERID 0x06c 45f95f3850SWill Newton #define SDMMC_HCON 0x070 4641babf75SJaehoon Chung #define SDMMC_UHS_REG 0x074 47f95f3850SWill Newton #define SDMMC_BMOD 0x080 48f95f3850SWill Newton #define SDMMC_PLDMND 0x084 49f95f3850SWill Newton #define SDMMC_DBADDR 0x088 50f95f3850SWill Newton #define SDMMC_IDSTS 0x08c 51f95f3850SWill Newton #define SDMMC_IDINTEN 0x090 52f95f3850SWill Newton #define SDMMC_DSCADDR 0x094 53f95f3850SWill Newton #define SDMMC_BUFADDR 0x098 54f95f3850SWill Newton #define SDMMC_DATA 0x100 55f95f3850SWill Newton 56f95f3850SWill Newton /* shift bit field */ 57f95f3850SWill Newton #define _SBF(f, v) ((v) << (f)) 58f95f3850SWill Newton 59f95f3850SWill Newton /* Control register defines */ 60f95f3850SWill Newton #define SDMMC_CTRL_USE_IDMAC BIT(25) 61f95f3850SWill Newton #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 62f95f3850SWill Newton #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 63f95f3850SWill Newton #define SDMMC_CTRL_SEND_CCSD BIT(9) 64f95f3850SWill Newton #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 65f95f3850SWill Newton #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 66f95f3850SWill Newton #define SDMMC_CTRL_READ_WAIT BIT(6) 67f95f3850SWill Newton #define SDMMC_CTRL_DMA_ENABLE BIT(5) 68f95f3850SWill Newton #define SDMMC_CTRL_INT_ENABLE BIT(4) 69f95f3850SWill Newton #define SDMMC_CTRL_DMA_RESET BIT(2) 70f95f3850SWill Newton #define SDMMC_CTRL_FIFO_RESET BIT(1) 71f95f3850SWill Newton #define SDMMC_CTRL_RESET BIT(0) 72f95f3850SWill Newton /* Clock Enable register defines */ 73f95f3850SWill Newton #define SDMMC_CLKEN_LOW_PWR BIT(16) 74f95f3850SWill Newton #define SDMMC_CLKEN_ENABLE BIT(0) 75f95f3850SWill Newton /* time-out register defines */ 76f95f3850SWill Newton #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 77f95f3850SWill Newton #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 78f95f3850SWill Newton #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 79f95f3850SWill Newton #define SDMMC_TMOUT_RESP_MSK 0xFF 80f95f3850SWill Newton /* card-type register defines */ 81f95f3850SWill Newton #define SDMMC_CTYPE_8BIT BIT(16) 82f95f3850SWill Newton #define SDMMC_CTYPE_4BIT BIT(0) 83f95f3850SWill Newton #define SDMMC_CTYPE_1BIT 0 84f95f3850SWill Newton /* Interrupt status & mask register defines */ 85f95f3850SWill Newton #define SDMMC_INT_SDIO BIT(16) 86f95f3850SWill Newton #define SDMMC_INT_EBE BIT(15) 87f95f3850SWill Newton #define SDMMC_INT_ACD BIT(14) 88f95f3850SWill Newton #define SDMMC_INT_SBE BIT(13) 89f95f3850SWill Newton #define SDMMC_INT_HLE BIT(12) 90f95f3850SWill Newton #define SDMMC_INT_FRUN BIT(11) 91f95f3850SWill Newton #define SDMMC_INT_HTO BIT(10) 92f95f3850SWill Newton #define SDMMC_INT_DTO BIT(9) 93f95f3850SWill Newton #define SDMMC_INT_RTO BIT(8) 94f95f3850SWill Newton #define SDMMC_INT_DCRC BIT(7) 95f95f3850SWill Newton #define SDMMC_INT_RCRC BIT(6) 96f95f3850SWill Newton #define SDMMC_INT_RXDR BIT(5) 97f95f3850SWill Newton #define SDMMC_INT_TXDR BIT(4) 98f95f3850SWill Newton #define SDMMC_INT_DATA_OVER BIT(3) 99f95f3850SWill Newton #define SDMMC_INT_CMD_DONE BIT(2) 100f95f3850SWill Newton #define SDMMC_INT_RESP_ERR BIT(1) 101f95f3850SWill Newton #define SDMMC_INT_CD BIT(0) 102f95f3850SWill Newton #define SDMMC_INT_ERROR 0xbfc2 103f95f3850SWill Newton /* Command register defines */ 104f95f3850SWill Newton #define SDMMC_CMD_START BIT(31) 105f95f3850SWill Newton #define SDMMC_CMD_CCS_EXP BIT(23) 106f95f3850SWill Newton #define SDMMC_CMD_CEATA_RD BIT(22) 107f95f3850SWill Newton #define SDMMC_CMD_UPD_CLK BIT(21) 108f95f3850SWill Newton #define SDMMC_CMD_INIT BIT(15) 109f95f3850SWill Newton #define SDMMC_CMD_STOP BIT(14) 110f95f3850SWill Newton #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 111f95f3850SWill Newton #define SDMMC_CMD_SEND_STOP BIT(12) 112f95f3850SWill Newton #define SDMMC_CMD_STRM_MODE BIT(11) 113f95f3850SWill Newton #define SDMMC_CMD_DAT_WR BIT(10) 114f95f3850SWill Newton #define SDMMC_CMD_DAT_EXP BIT(9) 115f95f3850SWill Newton #define SDMMC_CMD_RESP_CRC BIT(8) 116f95f3850SWill Newton #define SDMMC_CMD_RESP_LONG BIT(7) 117f95f3850SWill Newton #define SDMMC_CMD_RESP_EXP BIT(6) 118f95f3850SWill Newton #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 119f95f3850SWill Newton /* Status register defines */ 120f95f3850SWill Newton #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FF) 121f95f3850SWill Newton #define SDMMC_FIFO_SZ 32 122f95f3850SWill Newton /* Internal DMAC interrupt defines */ 123f95f3850SWill Newton #define SDMMC_IDMAC_INT_AI BIT(9) 124f95f3850SWill Newton #define SDMMC_IDMAC_INT_NI BIT(8) 125f95f3850SWill Newton #define SDMMC_IDMAC_INT_CES BIT(5) 126f95f3850SWill Newton #define SDMMC_IDMAC_INT_DU BIT(4) 127f95f3850SWill Newton #define SDMMC_IDMAC_INT_FBE BIT(2) 128f95f3850SWill Newton #define SDMMC_IDMAC_INT_RI BIT(1) 129f95f3850SWill Newton #define SDMMC_IDMAC_INT_TI BIT(0) 130f95f3850SWill Newton /* Internal DMAC bus mode bits */ 131f95f3850SWill Newton #define SDMMC_IDMAC_ENABLE BIT(7) 132f95f3850SWill Newton #define SDMMC_IDMAC_FB BIT(1) 133f95f3850SWill Newton #define SDMMC_IDMAC_SWRESET BIT(0) 134f95f3850SWill Newton 135f95f3850SWill Newton /* Register access macros */ 136f95f3850SWill Newton #define mci_readl(dev, reg) \ 137892b1e31SJames Hogan __raw_readl((dev)->regs + SDMMC_##reg) 138f95f3850SWill Newton #define mci_writel(dev, reg, value) \ 139892b1e31SJames Hogan __raw_writel((value), (dev)->regs + SDMMC_##reg) 140f95f3850SWill Newton 141f95f3850SWill Newton /* 16-bit FIFO access macros */ 142f95f3850SWill Newton #define mci_readw(dev, reg) \ 143892b1e31SJames Hogan __raw_readw((dev)->regs + SDMMC_##reg) 144f95f3850SWill Newton #define mci_writew(dev, reg, value) \ 145892b1e31SJames Hogan __raw_writew((value), (dev)->regs + SDMMC_##reg) 146f95f3850SWill Newton 147f95f3850SWill Newton /* 64-bit FIFO access macros */ 148f95f3850SWill Newton #ifdef readq 149f95f3850SWill Newton #define mci_readq(dev, reg) \ 150892b1e31SJames Hogan __raw_readq((dev)->regs + SDMMC_##reg) 151f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 152892b1e31SJames Hogan __raw_writeq((value), (dev)->regs + SDMMC_##reg) 153f95f3850SWill Newton #else 154f95f3850SWill Newton /* 155f95f3850SWill Newton * Dummy readq implementation for architectures that don't define it. 156f95f3850SWill Newton * 157f95f3850SWill Newton * We would assume that none of these architectures would configure 158f95f3850SWill Newton * the IP block with a 64bit FIFO width, so this code will never be 159f95f3850SWill Newton * executed on those machines. Defining these macros here keeps the 160f95f3850SWill Newton * rest of the code free from ifdefs. 161f95f3850SWill Newton */ 162f95f3850SWill Newton #define mci_readq(dev, reg) \ 163892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 164f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 165892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 166f95f3850SWill Newton #endif 167f95f3850SWill Newton 168f95f3850SWill Newton #endif /* _DW_MMC_H_ */ 169