1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #ifndef _DW_MMC_H_ 15f95f3850SWill Newton #define _DW_MMC_H_ 16f95f3850SWill Newton 174e0a5adfSJaehoon Chung #define DW_MMC_240A 0x240a 184e0a5adfSJaehoon Chung 19f95f3850SWill Newton #define SDMMC_CTRL 0x000 20f95f3850SWill Newton #define SDMMC_PWREN 0x004 21f95f3850SWill Newton #define SDMMC_CLKDIV 0x008 22f95f3850SWill Newton #define SDMMC_CLKSRC 0x00c 23f95f3850SWill Newton #define SDMMC_CLKENA 0x010 24f95f3850SWill Newton #define SDMMC_TMOUT 0x014 25f95f3850SWill Newton #define SDMMC_CTYPE 0x018 26f95f3850SWill Newton #define SDMMC_BLKSIZ 0x01c 27f95f3850SWill Newton #define SDMMC_BYTCNT 0x020 28f95f3850SWill Newton #define SDMMC_INTMASK 0x024 29f95f3850SWill Newton #define SDMMC_CMDARG 0x028 30f95f3850SWill Newton #define SDMMC_CMD 0x02c 31f95f3850SWill Newton #define SDMMC_RESP0 0x030 32f95f3850SWill Newton #define SDMMC_RESP1 0x034 33f95f3850SWill Newton #define SDMMC_RESP2 0x038 34f95f3850SWill Newton #define SDMMC_RESP3 0x03c 35f95f3850SWill Newton #define SDMMC_MINTSTS 0x040 36f95f3850SWill Newton #define SDMMC_RINTSTS 0x044 37f95f3850SWill Newton #define SDMMC_STATUS 0x048 38f95f3850SWill Newton #define SDMMC_FIFOTH 0x04c 39f95f3850SWill Newton #define SDMMC_CDETECT 0x050 40f95f3850SWill Newton #define SDMMC_WRTPRT 0x054 41f95f3850SWill Newton #define SDMMC_GPIO 0x058 42f95f3850SWill Newton #define SDMMC_TCBCNT 0x05c 43f95f3850SWill Newton #define SDMMC_TBBCNT 0x060 44f95f3850SWill Newton #define SDMMC_DEBNCE 0x064 45f95f3850SWill Newton #define SDMMC_USRID 0x068 46f95f3850SWill Newton #define SDMMC_VERID 0x06c 47f95f3850SWill Newton #define SDMMC_HCON 0x070 4841babf75SJaehoon Chung #define SDMMC_UHS_REG 0x074 49f95f3850SWill Newton #define SDMMC_BMOD 0x080 50f95f3850SWill Newton #define SDMMC_PLDMND 0x084 51f95f3850SWill Newton #define SDMMC_DBADDR 0x088 52f95f3850SWill Newton #define SDMMC_IDSTS 0x08c 53f95f3850SWill Newton #define SDMMC_IDINTEN 0x090 54f95f3850SWill Newton #define SDMMC_DSCADDR 0x094 55f95f3850SWill Newton #define SDMMC_BUFADDR 0x098 56f1d2736cSSeungwon Jeon #define SDMMC_CDTHRCTL 0x100 574e0a5adfSJaehoon Chung #define SDMMC_DATA(x) (x) 5869d99fdcSPrabu Thangamuthu /* 5969d99fdcSPrabu Thangamuthu * Registers to support idmac 64-bit address mode 6069d99fdcSPrabu Thangamuthu */ 6169d99fdcSPrabu Thangamuthu #define SDMMC_DBADDRL 0x088 6269d99fdcSPrabu Thangamuthu #define SDMMC_DBADDRU 0x08c 6369d99fdcSPrabu Thangamuthu #define SDMMC_IDSTS64 0x090 6469d99fdcSPrabu Thangamuthu #define SDMMC_IDINTEN64 0x094 6569d99fdcSPrabu Thangamuthu #define SDMMC_DSCADDRL 0x098 6669d99fdcSPrabu Thangamuthu #define SDMMC_DSCADDRU 0x09c 6769d99fdcSPrabu Thangamuthu #define SDMMC_BUFADDRL 0x0A0 6869d99fdcSPrabu Thangamuthu #define SDMMC_BUFADDRU 0x0A4 694e0a5adfSJaehoon Chung 704e0a5adfSJaehoon Chung /* 714e0a5adfSJaehoon Chung * Data offset is difference according to Version 724e0a5adfSJaehoon Chung * Lower than 2.40a : data register offest is 0x100 734e0a5adfSJaehoon Chung */ 744e0a5adfSJaehoon Chung #define DATA_OFFSET 0x100 754e0a5adfSJaehoon Chung #define DATA_240A_OFFSET 0x200 76f95f3850SWill Newton 77f95f3850SWill Newton /* shift bit field */ 78f95f3850SWill Newton #define _SBF(f, v) ((v) << (f)) 79f95f3850SWill Newton 80f95f3850SWill Newton /* Control register defines */ 81f95f3850SWill Newton #define SDMMC_CTRL_USE_IDMAC BIT(25) 82f95f3850SWill Newton #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 83f95f3850SWill Newton #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 84f95f3850SWill Newton #define SDMMC_CTRL_SEND_CCSD BIT(9) 85f95f3850SWill Newton #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 86f95f3850SWill Newton #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 87f95f3850SWill Newton #define SDMMC_CTRL_READ_WAIT BIT(6) 88f95f3850SWill Newton #define SDMMC_CTRL_DMA_ENABLE BIT(5) 89f95f3850SWill Newton #define SDMMC_CTRL_INT_ENABLE BIT(4) 90f95f3850SWill Newton #define SDMMC_CTRL_DMA_RESET BIT(2) 91f95f3850SWill Newton #define SDMMC_CTRL_FIFO_RESET BIT(1) 92f95f3850SWill Newton #define SDMMC_CTRL_RESET BIT(0) 93f95f3850SWill Newton /* Clock Enable register defines */ 94f95f3850SWill Newton #define SDMMC_CLKEN_LOW_PWR BIT(16) 95f95f3850SWill Newton #define SDMMC_CLKEN_ENABLE BIT(0) 96f95f3850SWill Newton /* time-out register defines */ 97f95f3850SWill Newton #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 98f95f3850SWill Newton #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 99f95f3850SWill Newton #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 100f95f3850SWill Newton #define SDMMC_TMOUT_RESP_MSK 0xFF 101f95f3850SWill Newton /* card-type register defines */ 102f95f3850SWill Newton #define SDMMC_CTYPE_8BIT BIT(16) 103f95f3850SWill Newton #define SDMMC_CTYPE_4BIT BIT(0) 104f95f3850SWill Newton #define SDMMC_CTYPE_1BIT 0 105f95f3850SWill Newton /* Interrupt status & mask register defines */ 1061a5c8e1fSShashidhar Hiremath #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 107f95f3850SWill Newton #define SDMMC_INT_EBE BIT(15) 108f95f3850SWill Newton #define SDMMC_INT_ACD BIT(14) 109f95f3850SWill Newton #define SDMMC_INT_SBE BIT(13) 110f95f3850SWill Newton #define SDMMC_INT_HLE BIT(12) 111f95f3850SWill Newton #define SDMMC_INT_FRUN BIT(11) 112f95f3850SWill Newton #define SDMMC_INT_HTO BIT(10) 11301730558SDoug Anderson #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 1143f7eec62SJaehoon Chung #define SDMMC_INT_DRTO BIT(9) 115f95f3850SWill Newton #define SDMMC_INT_RTO BIT(8) 116f95f3850SWill Newton #define SDMMC_INT_DCRC BIT(7) 117f95f3850SWill Newton #define SDMMC_INT_RCRC BIT(6) 118f95f3850SWill Newton #define SDMMC_INT_RXDR BIT(5) 119f95f3850SWill Newton #define SDMMC_INT_TXDR BIT(4) 120f95f3850SWill Newton #define SDMMC_INT_DATA_OVER BIT(3) 121f95f3850SWill Newton #define SDMMC_INT_CMD_DONE BIT(2) 122f95f3850SWill Newton #define SDMMC_INT_RESP_ERR BIT(1) 123f95f3850SWill Newton #define SDMMC_INT_CD BIT(0) 124f95f3850SWill Newton #define SDMMC_INT_ERROR 0xbfc2 125f95f3850SWill Newton /* Command register defines */ 126f95f3850SWill Newton #define SDMMC_CMD_START BIT(31) 127eede2111SDinh Nguyen #define SDMMC_CMD_USE_HOLD_REG BIT(29) 12801730558SDoug Anderson #define SDMMC_CMD_VOLT_SWITCH BIT(28) 129f95f3850SWill Newton #define SDMMC_CMD_CCS_EXP BIT(23) 130f95f3850SWill Newton #define SDMMC_CMD_CEATA_RD BIT(22) 131f95f3850SWill Newton #define SDMMC_CMD_UPD_CLK BIT(21) 132f95f3850SWill Newton #define SDMMC_CMD_INIT BIT(15) 133f95f3850SWill Newton #define SDMMC_CMD_STOP BIT(14) 134f95f3850SWill Newton #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 135f95f3850SWill Newton #define SDMMC_CMD_SEND_STOP BIT(12) 136f95f3850SWill Newton #define SDMMC_CMD_STRM_MODE BIT(11) 137f95f3850SWill Newton #define SDMMC_CMD_DAT_WR BIT(10) 138f95f3850SWill Newton #define SDMMC_CMD_DAT_EXP BIT(9) 139f95f3850SWill Newton #define SDMMC_CMD_RESP_CRC BIT(8) 140f95f3850SWill Newton #define SDMMC_CMD_RESP_LONG BIT(7) 141f95f3850SWill Newton #define SDMMC_CMD_RESP_EXP BIT(6) 142f95f3850SWill Newton #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 143f95f3850SWill Newton /* Status register defines */ 144ee5d19b2SJaehoon Chung #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 1453a33a94cSSonny Rao #define SDMMC_STATUS_DMA_REQ BIT(31) 14601730558SDoug Anderson #define SDMMC_STATUS_BUSY BIT(9) 14752426899SSeungwon Jeon /* FIFOTH register defines */ 14852426899SSeungwon Jeon #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 14952426899SSeungwon Jeon ((r) & 0xFFF) << 16 | \ 15052426899SSeungwon Jeon ((t) & 0xFFF)) 1513fc7eaefSShawn Lin /* HCON register defines */ 1523fc7eaefSShawn Lin #define DMA_INTERFACE_IDMA (0x0) 1533fc7eaefSShawn Lin #define DMA_INTERFACE_DWDMA (0x1) 1543fc7eaefSShawn Lin #define DMA_INTERFACE_GDMA (0x2) 1553fc7eaefSShawn Lin #define DMA_INTERFACE_NODMA (0x3) 1563fc7eaefSShawn Lin #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 15770692752SShawn Lin #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 15870692752SShawn Lin #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 15970692752SShawn Lin #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 160f95f3850SWill Newton /* Internal DMAC interrupt defines */ 161f95f3850SWill Newton #define SDMMC_IDMAC_INT_AI BIT(9) 162f95f3850SWill Newton #define SDMMC_IDMAC_INT_NI BIT(8) 163f95f3850SWill Newton #define SDMMC_IDMAC_INT_CES BIT(5) 164f95f3850SWill Newton #define SDMMC_IDMAC_INT_DU BIT(4) 165f95f3850SWill Newton #define SDMMC_IDMAC_INT_FBE BIT(2) 166f95f3850SWill Newton #define SDMMC_IDMAC_INT_RI BIT(1) 167f95f3850SWill Newton #define SDMMC_IDMAC_INT_TI BIT(0) 168f95f3850SWill Newton /* Internal DMAC bus mode bits */ 169f95f3850SWill Newton #define SDMMC_IDMAC_ENABLE BIT(7) 170f95f3850SWill Newton #define SDMMC_IDMAC_FB BIT(1) 171f95f3850SWill Newton #define SDMMC_IDMAC_SWRESET BIT(0) 1724e0a5adfSJaehoon Chung /* Version ID register define */ 1734e0a5adfSJaehoon Chung #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 174f1d2736cSSeungwon Jeon /* Card read threshold */ 175f1d2736cSSeungwon Jeon #define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x)) 17601730558SDoug Anderson #define SDMMC_UHS_18V BIT(0) 1773a33a94cSSonny Rao /* All ctrl reset bits */ 1783a33a94cSSonny Rao #define SDMMC_CTRL_ALL_RESET_FLAGS \ 1793a33a94cSSonny Rao (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 1803a33a94cSSonny Rao 18176184ac1SBen Dooks /* FIFO register access macros. These should not change the data endian-ness 18276184ac1SBen Dooks * as they are written to memory to be dealt with by the upper layers */ 18376184ac1SBen Dooks #define mci_fifo_readw(__reg) __raw_readw(__reg) 18476184ac1SBen Dooks #define mci_fifo_readl(__reg) __raw_readl(__reg) 18576184ac1SBen Dooks #define mci_fifo_readq(__reg) __raw_readq(__reg) 18676184ac1SBen Dooks 18776184ac1SBen Dooks #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 18876184ac1SBen Dooks #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 18976184ac1SBen Dooks #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 19076184ac1SBen Dooks 191f95f3850SWill Newton /* Register access macros */ 192f95f3850SWill Newton #define mci_readl(dev, reg) \ 193a2f17680SBen Dooks readl_relaxed((dev)->regs + SDMMC_##reg) 194f95f3850SWill Newton #define mci_writel(dev, reg, value) \ 195a2f17680SBen Dooks writel_relaxed((value), (dev)->regs + SDMMC_##reg) 196f95f3850SWill Newton 197f95f3850SWill Newton /* 16-bit FIFO access macros */ 198f95f3850SWill Newton #define mci_readw(dev, reg) \ 199a2f17680SBen Dooks readw_relaxed((dev)->regs + SDMMC_##reg) 200f95f3850SWill Newton #define mci_writew(dev, reg, value) \ 201a2f17680SBen Dooks writew_relaxed((value), (dev)->regs + SDMMC_##reg) 202f95f3850SWill Newton 203f95f3850SWill Newton /* 64-bit FIFO access macros */ 204f95f3850SWill Newton #ifdef readq 205f95f3850SWill Newton #define mci_readq(dev, reg) \ 206a2f17680SBen Dooks readq_relaxed((dev)->regs + SDMMC_##reg) 207f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 208a2f17680SBen Dooks writeq_relaxed((value), (dev)->regs + SDMMC_##reg) 209f95f3850SWill Newton #else 210f95f3850SWill Newton /* 211f95f3850SWill Newton * Dummy readq implementation for architectures that don't define it. 212f95f3850SWill Newton * 213f95f3850SWill Newton * We would assume that none of these architectures would configure 214f95f3850SWill Newton * the IP block with a 64bit FIFO width, so this code will never be 215f95f3850SWill Newton * executed on those machines. Defining these macros here keeps the 216f95f3850SWill Newton * rest of the code free from ifdefs. 217f95f3850SWill Newton */ 218f95f3850SWill Newton #define mci_readq(dev, reg) \ 219892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 220f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 221892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 22276184ac1SBen Dooks 22376184ac1SBen Dooks #define __raw_writeq(__value, __reg) \ 22476184ac1SBen Dooks (*(volatile u64 __force *)(__reg) = (__value)) 22576184ac1SBen Dooks #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 226f95f3850SWill Newton #endif 227f95f3850SWill Newton 22862ca8034SShashidhar Hiremath extern int dw_mci_probe(struct dw_mci *host); 22962ca8034SShashidhar Hiremath extern void dw_mci_remove(struct dw_mci *host); 230370aede6SFelipe Balbi #ifdef CONFIG_PM_SLEEP 23162ca8034SShashidhar Hiremath extern int dw_mci_suspend(struct dw_mci *host); 23262ca8034SShashidhar Hiremath extern int dw_mci_resume(struct dw_mci *host); 23362ca8034SShashidhar Hiremath #endif 23462ca8034SShashidhar Hiremath 235800d78bfSThomas Abraham /** 2360976f16dSSeungwon Jeon * struct dw_mci_slot - MMC slot state 2370976f16dSSeungwon Jeon * @mmc: The mmc_host representing this slot. 2380976f16dSSeungwon Jeon * @host: The MMC controller this slot is using. 2390976f16dSSeungwon Jeon * @ctype: Card type for this slot. 2400976f16dSSeungwon Jeon * @mrq: mmc_request currently being processed or waiting to be 2410976f16dSSeungwon Jeon * processed, or NULL when the slot is idle. 2420976f16dSSeungwon Jeon * @queue_node: List node for placing this node in the @queue list of 2430976f16dSSeungwon Jeon * &struct dw_mci. 2440976f16dSSeungwon Jeon * @clock: Clock rate configured by set_ios(). Protected by host->lock. 2450976f16dSSeungwon Jeon * @__clk_old: The last updated clock with reflecting clock divider. 2460976f16dSSeungwon Jeon * Keeping track of this helps us to avoid spamming the console 2470976f16dSSeungwon Jeon * with CONFIG_MMC_CLKGATE. 2480976f16dSSeungwon Jeon * @flags: Random state bits associated with the slot. 2490976f16dSSeungwon Jeon * @id: Number of this slot. 25076756234SAddy Ke * @sdio_id: Number of this slot in the SDIO interrupt registers. 2510976f16dSSeungwon Jeon */ 2520976f16dSSeungwon Jeon struct dw_mci_slot { 2530976f16dSSeungwon Jeon struct mmc_host *mmc; 2540976f16dSSeungwon Jeon struct dw_mci *host; 2550976f16dSSeungwon Jeon 2560976f16dSSeungwon Jeon u32 ctype; 2570976f16dSSeungwon Jeon 2580976f16dSSeungwon Jeon struct mmc_request *mrq; 2590976f16dSSeungwon Jeon struct list_head queue_node; 2600976f16dSSeungwon Jeon 2610976f16dSSeungwon Jeon unsigned int clock; 2620976f16dSSeungwon Jeon unsigned int __clk_old; 2630976f16dSSeungwon Jeon 2640976f16dSSeungwon Jeon unsigned long flags; 2650976f16dSSeungwon Jeon #define DW_MMC_CARD_PRESENT 0 2660976f16dSSeungwon Jeon #define DW_MMC_CARD_NEED_INIT 1 267b24c8b26SDoug Anderson #define DW_MMC_CARD_NO_LOW_PWR 2 2680976f16dSSeungwon Jeon int id; 26976756234SAddy Ke int sdio_id; 2700976f16dSSeungwon Jeon }; 2710976f16dSSeungwon Jeon 2720976f16dSSeungwon Jeon /** 273800d78bfSThomas Abraham * dw_mci driver data - dw-mshc implementation specific driver data. 274800d78bfSThomas Abraham * @caps: mmc subsystem specified capabilities of the controller(s). 275800d78bfSThomas Abraham * @init: early implementation specific initialization. 276800d78bfSThomas Abraham * @setup_clock: implementation specific clock configuration. 277800d78bfSThomas Abraham * @prepare_command: handle CMD register extensions. 278800d78bfSThomas Abraham * @set_ios: handle bus specific extensions. 279800d78bfSThomas Abraham * @parse_dt: parse implementation specific device tree properties. 2805532ec51SSachin Kamat * @execute_tuning: implementation specific tuning procedure. 281800d78bfSThomas Abraham * 282800d78bfSThomas Abraham * Provide controller implementation specific extensions. The usage of this 283800d78bfSThomas Abraham * data structure is fully optional and usage of each member in this structure 284800d78bfSThomas Abraham * is optional as well. 285800d78bfSThomas Abraham */ 286800d78bfSThomas Abraham struct dw_mci_drv_data { 287800d78bfSThomas Abraham unsigned long *caps; 288800d78bfSThomas Abraham int (*init)(struct dw_mci *host); 289800d78bfSThomas Abraham int (*setup_clock)(struct dw_mci *host); 290800d78bfSThomas Abraham void (*prepare_command)(struct dw_mci *host, u32 *cmdr); 291800d78bfSThomas Abraham void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 292800d78bfSThomas Abraham int (*parse_dt)(struct dw_mci *host); 2936c2c6506SUlf Hansson int (*execute_tuning)(struct dw_mci_slot *slot); 29480113132SSeungwon Jeon int (*prepare_hs400_tuning)(struct dw_mci *host, 29580113132SSeungwon Jeon struct mmc_ios *ios); 2968f7849c4SZhangfei Gao int (*switch_voltage)(struct mmc_host *mmc, 2978f7849c4SZhangfei Gao struct mmc_ios *ios); 298800d78bfSThomas Abraham }; 299f95f3850SWill Newton #endif /* _DW_MMC_H_ */ 300