1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #ifndef _DW_MMC_H_ 15f95f3850SWill Newton #define _DW_MMC_H_ 16f95f3850SWill Newton 174e0a5adfSJaehoon Chung #define DW_MMC_240A 0x240a 184e0a5adfSJaehoon Chung 19f95f3850SWill Newton #define SDMMC_CTRL 0x000 20f95f3850SWill Newton #define SDMMC_PWREN 0x004 21f95f3850SWill Newton #define SDMMC_CLKDIV 0x008 22f95f3850SWill Newton #define SDMMC_CLKSRC 0x00c 23f95f3850SWill Newton #define SDMMC_CLKENA 0x010 24f95f3850SWill Newton #define SDMMC_TMOUT 0x014 25f95f3850SWill Newton #define SDMMC_CTYPE 0x018 26f95f3850SWill Newton #define SDMMC_BLKSIZ 0x01c 27f95f3850SWill Newton #define SDMMC_BYTCNT 0x020 28f95f3850SWill Newton #define SDMMC_INTMASK 0x024 29f95f3850SWill Newton #define SDMMC_CMDARG 0x028 30f95f3850SWill Newton #define SDMMC_CMD 0x02c 31f95f3850SWill Newton #define SDMMC_RESP0 0x030 32f95f3850SWill Newton #define SDMMC_RESP1 0x034 33f95f3850SWill Newton #define SDMMC_RESP2 0x038 34f95f3850SWill Newton #define SDMMC_RESP3 0x03c 35f95f3850SWill Newton #define SDMMC_MINTSTS 0x040 36f95f3850SWill Newton #define SDMMC_RINTSTS 0x044 37f95f3850SWill Newton #define SDMMC_STATUS 0x048 38f95f3850SWill Newton #define SDMMC_FIFOTH 0x04c 39f95f3850SWill Newton #define SDMMC_CDETECT 0x050 40f95f3850SWill Newton #define SDMMC_WRTPRT 0x054 41f95f3850SWill Newton #define SDMMC_GPIO 0x058 42f95f3850SWill Newton #define SDMMC_TCBCNT 0x05c 43f95f3850SWill Newton #define SDMMC_TBBCNT 0x060 44f95f3850SWill Newton #define SDMMC_DEBNCE 0x064 45f95f3850SWill Newton #define SDMMC_USRID 0x068 46f95f3850SWill Newton #define SDMMC_VERID 0x06c 47f95f3850SWill Newton #define SDMMC_HCON 0x070 4841babf75SJaehoon Chung #define SDMMC_UHS_REG 0x074 49f95f3850SWill Newton #define SDMMC_BMOD 0x080 50f95f3850SWill Newton #define SDMMC_PLDMND 0x084 51f95f3850SWill Newton #define SDMMC_DBADDR 0x088 52f95f3850SWill Newton #define SDMMC_IDSTS 0x08c 53f95f3850SWill Newton #define SDMMC_IDINTEN 0x090 54f95f3850SWill Newton #define SDMMC_DSCADDR 0x094 55f95f3850SWill Newton #define SDMMC_BUFADDR 0x098 564e0a5adfSJaehoon Chung #define SDMMC_DATA(x) (x) 574e0a5adfSJaehoon Chung 584e0a5adfSJaehoon Chung /* 594e0a5adfSJaehoon Chung * Data offset is difference according to Version 604e0a5adfSJaehoon Chung * Lower than 2.40a : data register offest is 0x100 614e0a5adfSJaehoon Chung */ 624e0a5adfSJaehoon Chung #define DATA_OFFSET 0x100 634e0a5adfSJaehoon Chung #define DATA_240A_OFFSET 0x200 64f95f3850SWill Newton 65f95f3850SWill Newton /* shift bit field */ 66f95f3850SWill Newton #define _SBF(f, v) ((v) << (f)) 67f95f3850SWill Newton 68f95f3850SWill Newton /* Control register defines */ 69f95f3850SWill Newton #define SDMMC_CTRL_USE_IDMAC BIT(25) 70f95f3850SWill Newton #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 71f95f3850SWill Newton #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 72f95f3850SWill Newton #define SDMMC_CTRL_SEND_CCSD BIT(9) 73f95f3850SWill Newton #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 74f95f3850SWill Newton #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 75f95f3850SWill Newton #define SDMMC_CTRL_READ_WAIT BIT(6) 76f95f3850SWill Newton #define SDMMC_CTRL_DMA_ENABLE BIT(5) 77f95f3850SWill Newton #define SDMMC_CTRL_INT_ENABLE BIT(4) 78f95f3850SWill Newton #define SDMMC_CTRL_DMA_RESET BIT(2) 79f95f3850SWill Newton #define SDMMC_CTRL_FIFO_RESET BIT(1) 80f95f3850SWill Newton #define SDMMC_CTRL_RESET BIT(0) 81f95f3850SWill Newton /* Clock Enable register defines */ 82f95f3850SWill Newton #define SDMMC_CLKEN_LOW_PWR BIT(16) 83f95f3850SWill Newton #define SDMMC_CLKEN_ENABLE BIT(0) 84f95f3850SWill Newton /* time-out register defines */ 85f95f3850SWill Newton #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 86f95f3850SWill Newton #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 87f95f3850SWill Newton #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 88f95f3850SWill Newton #define SDMMC_TMOUT_RESP_MSK 0xFF 89f95f3850SWill Newton /* card-type register defines */ 90f95f3850SWill Newton #define SDMMC_CTYPE_8BIT BIT(16) 91f95f3850SWill Newton #define SDMMC_CTYPE_4BIT BIT(0) 92f95f3850SWill Newton #define SDMMC_CTYPE_1BIT 0 93f95f3850SWill Newton /* Interrupt status & mask register defines */ 941a5c8e1fSShashidhar Hiremath #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 95f95f3850SWill Newton #define SDMMC_INT_EBE BIT(15) 96f95f3850SWill Newton #define SDMMC_INT_ACD BIT(14) 97f95f3850SWill Newton #define SDMMC_INT_SBE BIT(13) 98f95f3850SWill Newton #define SDMMC_INT_HLE BIT(12) 99f95f3850SWill Newton #define SDMMC_INT_FRUN BIT(11) 100f95f3850SWill Newton #define SDMMC_INT_HTO BIT(10) 101f95f3850SWill Newton #define SDMMC_INT_DTO BIT(9) 102f95f3850SWill Newton #define SDMMC_INT_RTO BIT(8) 103f95f3850SWill Newton #define SDMMC_INT_DCRC BIT(7) 104f95f3850SWill Newton #define SDMMC_INT_RCRC BIT(6) 105f95f3850SWill Newton #define SDMMC_INT_RXDR BIT(5) 106f95f3850SWill Newton #define SDMMC_INT_TXDR BIT(4) 107f95f3850SWill Newton #define SDMMC_INT_DATA_OVER BIT(3) 108f95f3850SWill Newton #define SDMMC_INT_CMD_DONE BIT(2) 109f95f3850SWill Newton #define SDMMC_INT_RESP_ERR BIT(1) 110f95f3850SWill Newton #define SDMMC_INT_CD BIT(0) 111f95f3850SWill Newton #define SDMMC_INT_ERROR 0xbfc2 112f95f3850SWill Newton /* Command register defines */ 113f95f3850SWill Newton #define SDMMC_CMD_START BIT(31) 114f95f3850SWill Newton #define SDMMC_CMD_CCS_EXP BIT(23) 115f95f3850SWill Newton #define SDMMC_CMD_CEATA_RD BIT(22) 116f95f3850SWill Newton #define SDMMC_CMD_UPD_CLK BIT(21) 117f95f3850SWill Newton #define SDMMC_CMD_INIT BIT(15) 118f95f3850SWill Newton #define SDMMC_CMD_STOP BIT(14) 119f95f3850SWill Newton #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 120f95f3850SWill Newton #define SDMMC_CMD_SEND_STOP BIT(12) 121f95f3850SWill Newton #define SDMMC_CMD_STRM_MODE BIT(11) 122f95f3850SWill Newton #define SDMMC_CMD_DAT_WR BIT(10) 123f95f3850SWill Newton #define SDMMC_CMD_DAT_EXP BIT(9) 124f95f3850SWill Newton #define SDMMC_CMD_RESP_CRC BIT(8) 125f95f3850SWill Newton #define SDMMC_CMD_RESP_LONG BIT(7) 126f95f3850SWill Newton #define SDMMC_CMD_RESP_EXP BIT(6) 127f95f3850SWill Newton #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 128f95f3850SWill Newton /* Status register defines */ 129f95f3850SWill Newton #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FF) 130f95f3850SWill Newton /* Internal DMAC interrupt defines */ 131f95f3850SWill Newton #define SDMMC_IDMAC_INT_AI BIT(9) 132f95f3850SWill Newton #define SDMMC_IDMAC_INT_NI BIT(8) 133f95f3850SWill Newton #define SDMMC_IDMAC_INT_CES BIT(5) 134f95f3850SWill Newton #define SDMMC_IDMAC_INT_DU BIT(4) 135f95f3850SWill Newton #define SDMMC_IDMAC_INT_FBE BIT(2) 136f95f3850SWill Newton #define SDMMC_IDMAC_INT_RI BIT(1) 137f95f3850SWill Newton #define SDMMC_IDMAC_INT_TI BIT(0) 138f95f3850SWill Newton /* Internal DMAC bus mode bits */ 139f95f3850SWill Newton #define SDMMC_IDMAC_ENABLE BIT(7) 140f95f3850SWill Newton #define SDMMC_IDMAC_FB BIT(1) 141f95f3850SWill Newton #define SDMMC_IDMAC_SWRESET BIT(0) 1424e0a5adfSJaehoon Chung /* Version ID register define */ 1434e0a5adfSJaehoon Chung #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 144f95f3850SWill Newton 145f95f3850SWill Newton /* Register access macros */ 146f95f3850SWill Newton #define mci_readl(dev, reg) \ 147892b1e31SJames Hogan __raw_readl((dev)->regs + SDMMC_##reg) 148f95f3850SWill Newton #define mci_writel(dev, reg, value) \ 149892b1e31SJames Hogan __raw_writel((value), (dev)->regs + SDMMC_##reg) 150f95f3850SWill Newton 151f95f3850SWill Newton /* 16-bit FIFO access macros */ 152f95f3850SWill Newton #define mci_readw(dev, reg) \ 153892b1e31SJames Hogan __raw_readw((dev)->regs + SDMMC_##reg) 154f95f3850SWill Newton #define mci_writew(dev, reg, value) \ 155892b1e31SJames Hogan __raw_writew((value), (dev)->regs + SDMMC_##reg) 156f95f3850SWill Newton 157f95f3850SWill Newton /* 64-bit FIFO access macros */ 158f95f3850SWill Newton #ifdef readq 159f95f3850SWill Newton #define mci_readq(dev, reg) \ 160892b1e31SJames Hogan __raw_readq((dev)->regs + SDMMC_##reg) 161f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 162892b1e31SJames Hogan __raw_writeq((value), (dev)->regs + SDMMC_##reg) 163f95f3850SWill Newton #else 164f95f3850SWill Newton /* 165f95f3850SWill Newton * Dummy readq implementation for architectures that don't define it. 166f95f3850SWill Newton * 167f95f3850SWill Newton * We would assume that none of these architectures would configure 168f95f3850SWill Newton * the IP block with a 64bit FIFO width, so this code will never be 169f95f3850SWill Newton * executed on those machines. Defining these macros here keeps the 170f95f3850SWill Newton * rest of the code free from ifdefs. 171f95f3850SWill Newton */ 172f95f3850SWill Newton #define mci_readq(dev, reg) \ 173892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 174f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 175892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 176f95f3850SWill Newton #endif 177f95f3850SWill Newton 178f95f3850SWill Newton #endif /* _DW_MMC_H_ */ 179