1f95f3850SWill Newton /* 2f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 3f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 4f95f3850SWill Newton * 5f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 6f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7f95f3850SWill Newton * 8f95f3850SWill Newton * This program is free software; you can redistribute it and/or modify 9f95f3850SWill Newton * it under the terms of the GNU General Public License as published by 10f95f3850SWill Newton * the Free Software Foundation; either version 2 of the License, or 11f95f3850SWill Newton * (at your option) any later version. 12f95f3850SWill Newton */ 13f95f3850SWill Newton 14f95f3850SWill Newton #ifndef _DW_MMC_H_ 15f95f3850SWill Newton #define _DW_MMC_H_ 16f95f3850SWill Newton 174e0a5adfSJaehoon Chung #define DW_MMC_240A 0x240a 184e0a5adfSJaehoon Chung 19f95f3850SWill Newton #define SDMMC_CTRL 0x000 20f95f3850SWill Newton #define SDMMC_PWREN 0x004 21f95f3850SWill Newton #define SDMMC_CLKDIV 0x008 22f95f3850SWill Newton #define SDMMC_CLKSRC 0x00c 23f95f3850SWill Newton #define SDMMC_CLKENA 0x010 24f95f3850SWill Newton #define SDMMC_TMOUT 0x014 25f95f3850SWill Newton #define SDMMC_CTYPE 0x018 26f95f3850SWill Newton #define SDMMC_BLKSIZ 0x01c 27f95f3850SWill Newton #define SDMMC_BYTCNT 0x020 28f95f3850SWill Newton #define SDMMC_INTMASK 0x024 29f95f3850SWill Newton #define SDMMC_CMDARG 0x028 30f95f3850SWill Newton #define SDMMC_CMD 0x02c 31f95f3850SWill Newton #define SDMMC_RESP0 0x030 32f95f3850SWill Newton #define SDMMC_RESP1 0x034 33f95f3850SWill Newton #define SDMMC_RESP2 0x038 34f95f3850SWill Newton #define SDMMC_RESP3 0x03c 35f95f3850SWill Newton #define SDMMC_MINTSTS 0x040 36f95f3850SWill Newton #define SDMMC_RINTSTS 0x044 37f95f3850SWill Newton #define SDMMC_STATUS 0x048 38f95f3850SWill Newton #define SDMMC_FIFOTH 0x04c 39f95f3850SWill Newton #define SDMMC_CDETECT 0x050 40f95f3850SWill Newton #define SDMMC_WRTPRT 0x054 41f95f3850SWill Newton #define SDMMC_GPIO 0x058 42f95f3850SWill Newton #define SDMMC_TCBCNT 0x05c 43f95f3850SWill Newton #define SDMMC_TBBCNT 0x060 44f95f3850SWill Newton #define SDMMC_DEBNCE 0x064 45f95f3850SWill Newton #define SDMMC_USRID 0x068 46f95f3850SWill Newton #define SDMMC_VERID 0x06c 47f95f3850SWill Newton #define SDMMC_HCON 0x070 4841babf75SJaehoon Chung #define SDMMC_UHS_REG 0x074 49f95f3850SWill Newton #define SDMMC_BMOD 0x080 50f95f3850SWill Newton #define SDMMC_PLDMND 0x084 51f95f3850SWill Newton #define SDMMC_DBADDR 0x088 52f95f3850SWill Newton #define SDMMC_IDSTS 0x08c 53f95f3850SWill Newton #define SDMMC_IDINTEN 0x090 54f95f3850SWill Newton #define SDMMC_DSCADDR 0x094 55f95f3850SWill Newton #define SDMMC_BUFADDR 0x098 56f1d2736cSSeungwon Jeon #define SDMMC_CDTHRCTL 0x100 574e0a5adfSJaehoon Chung #define SDMMC_DATA(x) (x) 584e0a5adfSJaehoon Chung 594e0a5adfSJaehoon Chung /* 604e0a5adfSJaehoon Chung * Data offset is difference according to Version 614e0a5adfSJaehoon Chung * Lower than 2.40a : data register offest is 0x100 624e0a5adfSJaehoon Chung */ 634e0a5adfSJaehoon Chung #define DATA_OFFSET 0x100 644e0a5adfSJaehoon Chung #define DATA_240A_OFFSET 0x200 65f95f3850SWill Newton 66f95f3850SWill Newton /* shift bit field */ 67f95f3850SWill Newton #define _SBF(f, v) ((v) << (f)) 68f95f3850SWill Newton 69f95f3850SWill Newton /* Control register defines */ 70f95f3850SWill Newton #define SDMMC_CTRL_USE_IDMAC BIT(25) 71f95f3850SWill Newton #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 72f95f3850SWill Newton #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 73f95f3850SWill Newton #define SDMMC_CTRL_SEND_CCSD BIT(9) 74f95f3850SWill Newton #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 75f95f3850SWill Newton #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 76f95f3850SWill Newton #define SDMMC_CTRL_READ_WAIT BIT(6) 77f95f3850SWill Newton #define SDMMC_CTRL_DMA_ENABLE BIT(5) 78f95f3850SWill Newton #define SDMMC_CTRL_INT_ENABLE BIT(4) 79f95f3850SWill Newton #define SDMMC_CTRL_DMA_RESET BIT(2) 80f95f3850SWill Newton #define SDMMC_CTRL_FIFO_RESET BIT(1) 81f95f3850SWill Newton #define SDMMC_CTRL_RESET BIT(0) 82f95f3850SWill Newton /* Clock Enable register defines */ 83f95f3850SWill Newton #define SDMMC_CLKEN_LOW_PWR BIT(16) 84f95f3850SWill Newton #define SDMMC_CLKEN_ENABLE BIT(0) 85f95f3850SWill Newton /* time-out register defines */ 86f95f3850SWill Newton #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 87f95f3850SWill Newton #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 88f95f3850SWill Newton #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 89f95f3850SWill Newton #define SDMMC_TMOUT_RESP_MSK 0xFF 90f95f3850SWill Newton /* card-type register defines */ 91f95f3850SWill Newton #define SDMMC_CTYPE_8BIT BIT(16) 92f95f3850SWill Newton #define SDMMC_CTYPE_4BIT BIT(0) 93f95f3850SWill Newton #define SDMMC_CTYPE_1BIT 0 94f95f3850SWill Newton /* Interrupt status & mask register defines */ 951a5c8e1fSShashidhar Hiremath #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 96f95f3850SWill Newton #define SDMMC_INT_EBE BIT(15) 97f95f3850SWill Newton #define SDMMC_INT_ACD BIT(14) 98f95f3850SWill Newton #define SDMMC_INT_SBE BIT(13) 99f95f3850SWill Newton #define SDMMC_INT_HLE BIT(12) 100f95f3850SWill Newton #define SDMMC_INT_FRUN BIT(11) 101f95f3850SWill Newton #define SDMMC_INT_HTO BIT(10) 1023f7eec62SJaehoon Chung #define SDMMC_INT_DRTO BIT(9) 103f95f3850SWill Newton #define SDMMC_INT_RTO BIT(8) 104f95f3850SWill Newton #define SDMMC_INT_DCRC BIT(7) 105f95f3850SWill Newton #define SDMMC_INT_RCRC BIT(6) 106f95f3850SWill Newton #define SDMMC_INT_RXDR BIT(5) 107f95f3850SWill Newton #define SDMMC_INT_TXDR BIT(4) 108f95f3850SWill Newton #define SDMMC_INT_DATA_OVER BIT(3) 109f95f3850SWill Newton #define SDMMC_INT_CMD_DONE BIT(2) 110f95f3850SWill Newton #define SDMMC_INT_RESP_ERR BIT(1) 111f95f3850SWill Newton #define SDMMC_INT_CD BIT(0) 112f95f3850SWill Newton #define SDMMC_INT_ERROR 0xbfc2 113f95f3850SWill Newton /* Command register defines */ 114f95f3850SWill Newton #define SDMMC_CMD_START BIT(31) 115eede2111SDinh Nguyen #define SDMMC_CMD_USE_HOLD_REG BIT(29) 116f95f3850SWill Newton #define SDMMC_CMD_CCS_EXP BIT(23) 117f95f3850SWill Newton #define SDMMC_CMD_CEATA_RD BIT(22) 118f95f3850SWill Newton #define SDMMC_CMD_UPD_CLK BIT(21) 119f95f3850SWill Newton #define SDMMC_CMD_INIT BIT(15) 120f95f3850SWill Newton #define SDMMC_CMD_STOP BIT(14) 121f95f3850SWill Newton #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 122f95f3850SWill Newton #define SDMMC_CMD_SEND_STOP BIT(12) 123f95f3850SWill Newton #define SDMMC_CMD_STRM_MODE BIT(11) 124f95f3850SWill Newton #define SDMMC_CMD_DAT_WR BIT(10) 125f95f3850SWill Newton #define SDMMC_CMD_DAT_EXP BIT(9) 126f95f3850SWill Newton #define SDMMC_CMD_RESP_CRC BIT(8) 127f95f3850SWill Newton #define SDMMC_CMD_RESP_LONG BIT(7) 128f95f3850SWill Newton #define SDMMC_CMD_RESP_EXP BIT(6) 129f95f3850SWill Newton #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 130f95f3850SWill Newton /* Status register defines */ 131ee5d19b2SJaehoon Chung #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 1323a33a94cSSonny Rao #define SDMMC_STATUS_DMA_REQ BIT(31) 13352426899SSeungwon Jeon /* FIFOTH register defines */ 13452426899SSeungwon Jeon #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 13552426899SSeungwon Jeon ((r) & 0xFFF) << 16 | \ 13652426899SSeungwon Jeon ((t) & 0xFFF)) 137f95f3850SWill Newton /* Internal DMAC interrupt defines */ 138f95f3850SWill Newton #define SDMMC_IDMAC_INT_AI BIT(9) 139f95f3850SWill Newton #define SDMMC_IDMAC_INT_NI BIT(8) 140f95f3850SWill Newton #define SDMMC_IDMAC_INT_CES BIT(5) 141f95f3850SWill Newton #define SDMMC_IDMAC_INT_DU BIT(4) 142f95f3850SWill Newton #define SDMMC_IDMAC_INT_FBE BIT(2) 143f95f3850SWill Newton #define SDMMC_IDMAC_INT_RI BIT(1) 144f95f3850SWill Newton #define SDMMC_IDMAC_INT_TI BIT(0) 145f95f3850SWill Newton /* Internal DMAC bus mode bits */ 146f95f3850SWill Newton #define SDMMC_IDMAC_ENABLE BIT(7) 147f95f3850SWill Newton #define SDMMC_IDMAC_FB BIT(1) 148f95f3850SWill Newton #define SDMMC_IDMAC_SWRESET BIT(0) 1494e0a5adfSJaehoon Chung /* Version ID register define */ 1504e0a5adfSJaehoon Chung #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 151f1d2736cSSeungwon Jeon /* Card read threshold */ 152f1d2736cSSeungwon Jeon #define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x)) 153f95f3850SWill Newton 1543a33a94cSSonny Rao /* All ctrl reset bits */ 1553a33a94cSSonny Rao #define SDMMC_CTRL_ALL_RESET_FLAGS \ 1563a33a94cSSonny Rao (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 1573a33a94cSSonny Rao 158f95f3850SWill Newton /* Register access macros */ 159f95f3850SWill Newton #define mci_readl(dev, reg) \ 160892b1e31SJames Hogan __raw_readl((dev)->regs + SDMMC_##reg) 161f95f3850SWill Newton #define mci_writel(dev, reg, value) \ 162892b1e31SJames Hogan __raw_writel((value), (dev)->regs + SDMMC_##reg) 163f95f3850SWill Newton 164f95f3850SWill Newton /* 16-bit FIFO access macros */ 165f95f3850SWill Newton #define mci_readw(dev, reg) \ 166892b1e31SJames Hogan __raw_readw((dev)->regs + SDMMC_##reg) 167f95f3850SWill Newton #define mci_writew(dev, reg, value) \ 168892b1e31SJames Hogan __raw_writew((value), (dev)->regs + SDMMC_##reg) 169f95f3850SWill Newton 170f95f3850SWill Newton /* 64-bit FIFO access macros */ 171f95f3850SWill Newton #ifdef readq 172f95f3850SWill Newton #define mci_readq(dev, reg) \ 173892b1e31SJames Hogan __raw_readq((dev)->regs + SDMMC_##reg) 174f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 175892b1e31SJames Hogan __raw_writeq((value), (dev)->regs + SDMMC_##reg) 176f95f3850SWill Newton #else 177f95f3850SWill Newton /* 178f95f3850SWill Newton * Dummy readq implementation for architectures that don't define it. 179f95f3850SWill Newton * 180f95f3850SWill Newton * We would assume that none of these architectures would configure 181f95f3850SWill Newton * the IP block with a 64bit FIFO width, so this code will never be 182f95f3850SWill Newton * executed on those machines. Defining these macros here keeps the 183f95f3850SWill Newton * rest of the code free from ifdefs. 184f95f3850SWill Newton */ 185f95f3850SWill Newton #define mci_readq(dev, reg) \ 186892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 187f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 188892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 189f95f3850SWill Newton #endif 190f95f3850SWill Newton 19162ca8034SShashidhar Hiremath extern int dw_mci_probe(struct dw_mci *host); 19262ca8034SShashidhar Hiremath extern void dw_mci_remove(struct dw_mci *host); 193370aede6SFelipe Balbi #ifdef CONFIG_PM_SLEEP 19462ca8034SShashidhar Hiremath extern int dw_mci_suspend(struct dw_mci *host); 19562ca8034SShashidhar Hiremath extern int dw_mci_resume(struct dw_mci *host); 19662ca8034SShashidhar Hiremath #endif 19762ca8034SShashidhar Hiremath 198800d78bfSThomas Abraham /** 1990976f16dSSeungwon Jeon * struct dw_mci_slot - MMC slot state 2000976f16dSSeungwon Jeon * @mmc: The mmc_host representing this slot. 2010976f16dSSeungwon Jeon * @host: The MMC controller this slot is using. 2020976f16dSSeungwon Jeon * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) 2030976f16dSSeungwon Jeon * @ctype: Card type for this slot. 2040976f16dSSeungwon Jeon * @mrq: mmc_request currently being processed or waiting to be 2050976f16dSSeungwon Jeon * processed, or NULL when the slot is idle. 2060976f16dSSeungwon Jeon * @queue_node: List node for placing this node in the @queue list of 2070976f16dSSeungwon Jeon * &struct dw_mci. 2080976f16dSSeungwon Jeon * @clock: Clock rate configured by set_ios(). Protected by host->lock. 2090976f16dSSeungwon Jeon * @__clk_old: The last updated clock with reflecting clock divider. 2100976f16dSSeungwon Jeon * Keeping track of this helps us to avoid spamming the console 2110976f16dSSeungwon Jeon * with CONFIG_MMC_CLKGATE. 2120976f16dSSeungwon Jeon * @flags: Random state bits associated with the slot. 2130976f16dSSeungwon Jeon * @id: Number of this slot. 2140976f16dSSeungwon Jeon * @last_detect_state: Most recently observed card detect state. 2150976f16dSSeungwon Jeon */ 2160976f16dSSeungwon Jeon struct dw_mci_slot { 2170976f16dSSeungwon Jeon struct mmc_host *mmc; 2180976f16dSSeungwon Jeon struct dw_mci *host; 2190976f16dSSeungwon Jeon 2200976f16dSSeungwon Jeon int quirks; 2210976f16dSSeungwon Jeon 2220976f16dSSeungwon Jeon u32 ctype; 2230976f16dSSeungwon Jeon 2240976f16dSSeungwon Jeon struct mmc_request *mrq; 2250976f16dSSeungwon Jeon struct list_head queue_node; 2260976f16dSSeungwon Jeon 2270976f16dSSeungwon Jeon unsigned int clock; 2280976f16dSSeungwon Jeon unsigned int __clk_old; 2290976f16dSSeungwon Jeon 2300976f16dSSeungwon Jeon unsigned long flags; 2310976f16dSSeungwon Jeon #define DW_MMC_CARD_PRESENT 0 2320976f16dSSeungwon Jeon #define DW_MMC_CARD_NEED_INIT 1 2330976f16dSSeungwon Jeon int id; 2340976f16dSSeungwon Jeon int last_detect_state; 2350976f16dSSeungwon Jeon }; 2360976f16dSSeungwon Jeon 2370976f16dSSeungwon Jeon struct dw_mci_tuning_data { 2380976f16dSSeungwon Jeon const u8 *blk_pattern; 2390976f16dSSeungwon Jeon unsigned int blksz; 2400976f16dSSeungwon Jeon }; 2410976f16dSSeungwon Jeon 2420976f16dSSeungwon Jeon /** 243800d78bfSThomas Abraham * dw_mci driver data - dw-mshc implementation specific driver data. 244800d78bfSThomas Abraham * @caps: mmc subsystem specified capabilities of the controller(s). 245800d78bfSThomas Abraham * @init: early implementation specific initialization. 246800d78bfSThomas Abraham * @setup_clock: implementation specific clock configuration. 247800d78bfSThomas Abraham * @prepare_command: handle CMD register extensions. 248800d78bfSThomas Abraham * @set_ios: handle bus specific extensions. 249800d78bfSThomas Abraham * @parse_dt: parse implementation specific device tree properties. 2505532ec51SSachin Kamat * @execute_tuning: implementation specific tuning procedure. 251800d78bfSThomas Abraham * 252800d78bfSThomas Abraham * Provide controller implementation specific extensions. The usage of this 253800d78bfSThomas Abraham * data structure is fully optional and usage of each member in this structure 254800d78bfSThomas Abraham * is optional as well. 255800d78bfSThomas Abraham */ 256800d78bfSThomas Abraham struct dw_mci_drv_data { 257800d78bfSThomas Abraham unsigned long *caps; 258800d78bfSThomas Abraham int (*init)(struct dw_mci *host); 259800d78bfSThomas Abraham int (*setup_clock)(struct dw_mci *host); 260800d78bfSThomas Abraham void (*prepare_command)(struct dw_mci *host, u32 *cmdr); 261800d78bfSThomas Abraham void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 262800d78bfSThomas Abraham int (*parse_dt)(struct dw_mci *host); 2630976f16dSSeungwon Jeon int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode, 2640976f16dSSeungwon Jeon struct dw_mci_tuning_data *tuning_data); 265800d78bfSThomas Abraham }; 266f95f3850SWill Newton #endif /* _DW_MMC_H_ */ 267