12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2f95f3850SWill Newton /* 3f95f3850SWill Newton * Synopsys DesignWare Multimedia Card Interface driver 4f95f3850SWill Newton * (Based on NXP driver for lpc 31xx) 5f95f3850SWill Newton * 6f95f3850SWill Newton * Copyright (C) 2009 NXP Semiconductors 7f95f3850SWill Newton * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8f95f3850SWill Newton */ 9f95f3850SWill Newton 10f95f3850SWill Newton #ifndef _DW_MMC_H_ 11f95f3850SWill Newton #define _DW_MMC_H_ 12f95f3850SWill Newton 130f21c58cSUlf Hansson #include <linux/scatterlist.h> 140f21c58cSUlf Hansson #include <linux/mmc/core.h> 150f21c58cSUlf Hansson #include <linux/dmaengine.h> 160f21c58cSUlf Hansson #include <linux/reset.h> 17*2b8ac062SVincent Whitchurch #include <linux/fault-inject.h> 18*2b8ac062SVincent Whitchurch #include <linux/hrtimer.h> 19b8789ec4SUlf Hansson #include <linux/interrupt.h> 200f21c58cSUlf Hansson 210f21c58cSUlf Hansson enum dw_mci_state { 220f21c58cSUlf Hansson STATE_IDLE = 0, 230f21c58cSUlf Hansson STATE_SENDING_CMD, 240f21c58cSUlf Hansson STATE_SENDING_DATA, 250f21c58cSUlf Hansson STATE_DATA_BUSY, 260f21c58cSUlf Hansson STATE_SENDING_STOP, 270f21c58cSUlf Hansson STATE_DATA_ERROR, 280f21c58cSUlf Hansson STATE_SENDING_CMD11, 290f21c58cSUlf Hansson STATE_WAITING_CMD11_DONE, 300f21c58cSUlf Hansson }; 310f21c58cSUlf Hansson 320f21c58cSUlf Hansson enum { 330f21c58cSUlf Hansson EVENT_CMD_COMPLETE = 0, 340f21c58cSUlf Hansson EVENT_XFER_COMPLETE, 350f21c58cSUlf Hansson EVENT_DATA_COMPLETE, 360f21c58cSUlf Hansson EVENT_DATA_ERROR, 370f21c58cSUlf Hansson }; 380f21c58cSUlf Hansson 390f21c58cSUlf Hansson enum dw_mci_cookie { 400f21c58cSUlf Hansson COOKIE_UNMAPPED, 410f21c58cSUlf Hansson COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ 420f21c58cSUlf Hansson COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ 430f21c58cSUlf Hansson }; 440f21c58cSUlf Hansson 450f21c58cSUlf Hansson struct mmc_data; 460f21c58cSUlf Hansson 470f21c58cSUlf Hansson enum { 480f21c58cSUlf Hansson TRANS_MODE_PIO = 0, 490f21c58cSUlf Hansson TRANS_MODE_IDMAC, 500f21c58cSUlf Hansson TRANS_MODE_EDMAC 510f21c58cSUlf Hansson }; 520f21c58cSUlf Hansson 530f21c58cSUlf Hansson struct dw_mci_dma_slave { 540f21c58cSUlf Hansson struct dma_chan *ch; 550f21c58cSUlf Hansson enum dma_transfer_direction direction; 560f21c58cSUlf Hansson }; 570f21c58cSUlf Hansson 580f21c58cSUlf Hansson /** 590f21c58cSUlf Hansson * struct dw_mci - MMC controller state shared between all slots 600f21c58cSUlf Hansson * @lock: Spinlock protecting the queue and associated data. 610f21c58cSUlf Hansson * @irq_lock: Spinlock protecting the INTMASK setting. 620f21c58cSUlf Hansson * @regs: Pointer to MMIO registers. 630f21c58cSUlf Hansson * @fifo_reg: Pointer to MMIO registers for data FIFO 640f21c58cSUlf Hansson * @sg: Scatterlist entry currently being processed by PIO code, if any. 650f21c58cSUlf Hansson * @sg_miter: PIO mapping scatterlist iterator. 664b514fa2SAlexey Roslyakov * @mrq: The request currently being processed on @slot, 670f21c58cSUlf Hansson * or NULL if the controller is idle. 680f21c58cSUlf Hansson * @cmd: The command currently being sent to the card, or NULL. 690f21c58cSUlf Hansson * @data: The data currently being transferred, or NULL if no data 700f21c58cSUlf Hansson * transfer is in progress. 710f21c58cSUlf Hansson * @stop_abort: The command currently prepared for stoping transfer. 720f21c58cSUlf Hansson * @prev_blksz: The former transfer blksz record. 730f21c58cSUlf Hansson * @timing: Record of current ios timing. 742afcbdb0SZiyuan * @use_dma: Which DMA channel is in use for the current transfer, zero 752afcbdb0SZiyuan * denotes PIO mode. 760f21c58cSUlf Hansson * @using_dma: Whether DMA is in use for the current transfer. 770f21c58cSUlf Hansson * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 780f21c58cSUlf Hansson * @sg_dma: Bus address of DMA buffer. 790f21c58cSUlf Hansson * @sg_cpu: Virtual address of DMA buffer. 800f21c58cSUlf Hansson * @dma_ops: Pointer to platform-specific DMA callbacks. 810f21c58cSUlf Hansson * @cmd_status: Snapshot of SR taken upon completion of the current 820f21c58cSUlf Hansson * @ring_size: Buffer size for idma descriptors. 830f21c58cSUlf Hansson * command. Only valid when EVENT_CMD_COMPLETE is pending. 840f21c58cSUlf Hansson * @dms: structure of slave-dma private data. 850f21c58cSUlf Hansson * @phy_regs: physical address of controller's register map 860f21c58cSUlf Hansson * @data_status: Snapshot of SR taken upon completion of the current 870f21c58cSUlf Hansson * data transfer. Only valid when EVENT_DATA_COMPLETE or 880f21c58cSUlf Hansson * EVENT_DATA_ERROR is pending. 890f21c58cSUlf Hansson * @stop_cmdr: Value to be loaded into CMDR when the stop command is 900f21c58cSUlf Hansson * to be sent. 910f21c58cSUlf Hansson * @dir_status: Direction of current transfer. 920f21c58cSUlf Hansson * @tasklet: Tasklet running the request state machine. 930f21c58cSUlf Hansson * @pending_events: Bitmask of events flagged by the interrupt handler 940f21c58cSUlf Hansson * to be processed by the tasklet. 950f21c58cSUlf Hansson * @completed_events: Bitmask of events which the state machine has 960f21c58cSUlf Hansson * processed. 970f21c58cSUlf Hansson * @state: Tasklet state. 980f21c58cSUlf Hansson * @queue: List of slots waiting for access to the controller. 990f21c58cSUlf Hansson * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 1000f21c58cSUlf Hansson * rate and timeout calculations. 1010f21c58cSUlf Hansson * @current_speed: Configured rate of the controller. 1020f21c58cSUlf Hansson * @fifoth_val: The value of FIFOTH register. 1030f21c58cSUlf Hansson * @verid: Denote Version ID. 1040f21c58cSUlf Hansson * @dev: Device associated with the MMC controller. 1050f21c58cSUlf Hansson * @pdata: Platform data associated with the MMC controller. 1060f21c58cSUlf Hansson * @drv_data: Driver specific data for identified variant of the controller 1070f21c58cSUlf Hansson * @priv: Implementation defined private data. 1080f21c58cSUlf Hansson * @biu_clk: Pointer to bus interface unit clock instance. 1090f21c58cSUlf Hansson * @ciu_clk: Pointer to card interface unit clock instance. 1100f21c58cSUlf Hansson * @slot: Slots sharing this MMC controller. 1110f21c58cSUlf Hansson * @fifo_depth: depth of FIFO. 112a0361c1aSJun Nie * @data_addr_override: override fifo reg offset with this value. 113d6fced83SJun Nie * @wm_aligned: force fifo watermark equal with data length in PIO mode. 114d6fced83SJun Nie * Set as true if alignment is needed. 1150f21c58cSUlf Hansson * @data_shift: log2 of FIFO item size. 1160f21c58cSUlf Hansson * @part_buf_start: Start index in part_buf. 1170f21c58cSUlf Hansson * @part_buf_count: Bytes of partial data in part_buf. 1180f21c58cSUlf Hansson * @part_buf: Simple buffer for partial fifo reads/writes. 1190f21c58cSUlf Hansson * @push_data: Pointer to FIFO push function. 1200f21c58cSUlf Hansson * @pull_data: Pointer to FIFO pull function. 1210f21c58cSUlf Hansson * @vqmmc_enabled: Status of vqmmc, should be true or false. 1220f21c58cSUlf Hansson * @irq_flags: The flags to be passed to request_irq. 1230f21c58cSUlf Hansson * @irq: The irq value to be passed to request_irq. 1240f21c58cSUlf Hansson * @sdio_id0: Number of slot0 in the SDIO interrupt registers. 1250f21c58cSUlf Hansson * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. 12603de1921SAddy Ke * @cto_timer: Timer for broken command transfer over scheme. 1270f21c58cSUlf Hansson * @dto_timer: Timer for broken data transfer over scheme. 1280f21c58cSUlf Hansson * 1290f21c58cSUlf Hansson * Locking 1300f21c58cSUlf Hansson * ======= 1310f21c58cSUlf Hansson * 1320f21c58cSUlf Hansson * @lock is a softirq-safe spinlock protecting @queue as well as 1334b514fa2SAlexey Roslyakov * @slot, @mrq and @state. These must always be updated 1340f21c58cSUlf Hansson * at the same time while holding @lock. 1354b514fa2SAlexey Roslyakov * The @mrq field of struct dw_mci_slot is also protected by @lock, 1364b514fa2SAlexey Roslyakov * and must always be written at the same time as the slot is added to 1374b514fa2SAlexey Roslyakov * @queue. 1380f21c58cSUlf Hansson * 1390f21c58cSUlf Hansson * @irq_lock is an irq-safe spinlock protecting the INTMASK register 1400f21c58cSUlf Hansson * to allow the interrupt handler to modify it directly. Held for only long 1410f21c58cSUlf Hansson * enough to read-modify-write INTMASK and no other locks are grabbed when 1420f21c58cSUlf Hansson * holding this one. 1430f21c58cSUlf Hansson * 1440f21c58cSUlf Hansson * @pending_events and @completed_events are accessed using atomic bit 1450f21c58cSUlf Hansson * operations, so they don't need any locking. 1460f21c58cSUlf Hansson * 1470f21c58cSUlf Hansson * None of the fields touched by the interrupt handler need any 1480f21c58cSUlf Hansson * locking. However, ordering is important: Before EVENT_DATA_ERROR or 1490f21c58cSUlf Hansson * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 1500f21c58cSUlf Hansson * interrupts must be disabled and @data_status updated with a 1510f21c58cSUlf Hansson * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 1520f21c58cSUlf Hansson * CMDRDY interrupt must be disabled and @cmd_status updated with a 1530f21c58cSUlf Hansson * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 1540f21c58cSUlf Hansson * bytes_xfered field of @data must be written. This is ensured by 1550f21c58cSUlf Hansson * using barriers. 1560f21c58cSUlf Hansson */ 1570f21c58cSUlf Hansson struct dw_mci { 1580f21c58cSUlf Hansson spinlock_t lock; 1590f21c58cSUlf Hansson spinlock_t irq_lock; 1600f21c58cSUlf Hansson void __iomem *regs; 1610f21c58cSUlf Hansson void __iomem *fifo_reg; 162a0361c1aSJun Nie u32 data_addr_override; 163d6fced83SJun Nie bool wm_aligned; 1640f21c58cSUlf Hansson 1650f21c58cSUlf Hansson struct scatterlist *sg; 1660f21c58cSUlf Hansson struct sg_mapping_iter sg_miter; 1670f21c58cSUlf Hansson 1680f21c58cSUlf Hansson struct mmc_request *mrq; 1690f21c58cSUlf Hansson struct mmc_command *cmd; 1700f21c58cSUlf Hansson struct mmc_data *data; 1710f21c58cSUlf Hansson struct mmc_command stop_abort; 1720f21c58cSUlf Hansson unsigned int prev_blksz; 1730f21c58cSUlf Hansson unsigned char timing; 1740f21c58cSUlf Hansson 1750f21c58cSUlf Hansson /* DMA interface members*/ 1760f21c58cSUlf Hansson int use_dma; 1770f21c58cSUlf Hansson int using_dma; 1780f21c58cSUlf Hansson int dma_64bit_address; 1790f21c58cSUlf Hansson 1800f21c58cSUlf Hansson dma_addr_t sg_dma; 1810f21c58cSUlf Hansson void *sg_cpu; 1820f21c58cSUlf Hansson const struct dw_mci_dma_ops *dma_ops; 1830f21c58cSUlf Hansson /* For idmac */ 1840f21c58cSUlf Hansson unsigned int ring_size; 1850f21c58cSUlf Hansson 1860f21c58cSUlf Hansson /* For edmac */ 1870f21c58cSUlf Hansson struct dw_mci_dma_slave *dms; 1880f21c58cSUlf Hansson /* Registers's physical base address */ 1890f21c58cSUlf Hansson resource_size_t phy_regs; 1900f21c58cSUlf Hansson 1910f21c58cSUlf Hansson u32 cmd_status; 1920f21c58cSUlf Hansson u32 data_status; 1930f21c58cSUlf Hansson u32 stop_cmdr; 1940f21c58cSUlf Hansson u32 dir_status; 1950f21c58cSUlf Hansson struct tasklet_struct tasklet; 1960f21c58cSUlf Hansson unsigned long pending_events; 1970f21c58cSUlf Hansson unsigned long completed_events; 1980f21c58cSUlf Hansson enum dw_mci_state state; 1990f21c58cSUlf Hansson struct list_head queue; 2000f21c58cSUlf Hansson 2010f21c58cSUlf Hansson u32 bus_hz; 2020f21c58cSUlf Hansson u32 current_speed; 2030f21c58cSUlf Hansson u32 fifoth_val; 2040f21c58cSUlf Hansson u16 verid; 2050f21c58cSUlf Hansson struct device *dev; 2060f21c58cSUlf Hansson struct dw_mci_board *pdata; 2070f21c58cSUlf Hansson const struct dw_mci_drv_data *drv_data; 2080f21c58cSUlf Hansson void *priv; 2090f21c58cSUlf Hansson struct clk *biu_clk; 2100f21c58cSUlf Hansson struct clk *ciu_clk; 211b23475faSJaehoon Chung struct dw_mci_slot *slot; 2120f21c58cSUlf Hansson 2130f21c58cSUlf Hansson /* FIFO push and pull */ 2140f21c58cSUlf Hansson int fifo_depth; 2150f21c58cSUlf Hansson int data_shift; 2160f21c58cSUlf Hansson u8 part_buf_start; 2170f21c58cSUlf Hansson u8 part_buf_count; 2180f21c58cSUlf Hansson union { 2190f21c58cSUlf Hansson u16 part_buf16; 2200f21c58cSUlf Hansson u32 part_buf32; 2210f21c58cSUlf Hansson u64 part_buf; 2220f21c58cSUlf Hansson }; 2230f21c58cSUlf Hansson void (*push_data)(struct dw_mci *host, void *buf, int cnt); 2240f21c58cSUlf Hansson void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 2250f21c58cSUlf Hansson 2260f21c58cSUlf Hansson bool vqmmc_enabled; 2270f21c58cSUlf Hansson unsigned long irq_flags; /* IRQ flags */ 2280f21c58cSUlf Hansson int irq; 2290f21c58cSUlf Hansson 2300f21c58cSUlf Hansson int sdio_id0; 2310f21c58cSUlf Hansson 2320f21c58cSUlf Hansson struct timer_list cmd11_timer; 23303de1921SAddy Ke struct timer_list cto_timer; 2340f21c58cSUlf Hansson struct timer_list dto_timer; 235*2b8ac062SVincent Whitchurch 236*2b8ac062SVincent Whitchurch #ifdef CONFIG_FAULT_INJECTION 237*2b8ac062SVincent Whitchurch struct fault_attr fail_data_crc; 238*2b8ac062SVincent Whitchurch struct hrtimer fault_timer; 239*2b8ac062SVincent Whitchurch #endif 2400f21c58cSUlf Hansson }; 2410f21c58cSUlf Hansson 2420f21c58cSUlf Hansson /* DMA ops for Internal/External DMAC interface */ 2430f21c58cSUlf Hansson struct dw_mci_dma_ops { 2440f21c58cSUlf Hansson /* DMA Ops */ 2450f21c58cSUlf Hansson int (*init)(struct dw_mci *host); 2460f21c58cSUlf Hansson int (*start)(struct dw_mci *host, unsigned int sg_len); 2470f21c58cSUlf Hansson void (*complete)(void *host); 2480f21c58cSUlf Hansson void (*stop)(struct dw_mci *host); 2490f21c58cSUlf Hansson void (*cleanup)(struct dw_mci *host); 2500f21c58cSUlf Hansson void (*exit)(struct dw_mci *host); 2510f21c58cSUlf Hansson }; 2520f21c58cSUlf Hansson 2530f21c58cSUlf Hansson struct dma_pdata; 2540f21c58cSUlf Hansson 2550f21c58cSUlf Hansson /* Board platform data */ 2560f21c58cSUlf Hansson struct dw_mci_board { 2570f21c58cSUlf Hansson unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 2580f21c58cSUlf Hansson 2590f21c58cSUlf Hansson u32 caps; /* Capabilities */ 2600f21c58cSUlf Hansson u32 caps2; /* More capabilities */ 2610f21c58cSUlf Hansson u32 pm_caps; /* PM capabilities */ 2620f21c58cSUlf Hansson /* 2630f21c58cSUlf Hansson * Override fifo depth. If 0, autodetect it from the FIFOTH register, 2640f21c58cSUlf Hansson * but note that this may not be reliable after a bootloader has used 2650f21c58cSUlf Hansson * it. 2660f21c58cSUlf Hansson */ 2670f21c58cSUlf Hansson unsigned int fifo_depth; 2680f21c58cSUlf Hansson 2690f21c58cSUlf Hansson /* delay in mS before detecting cards after interrupt */ 2700f21c58cSUlf Hansson u32 detect_delay_ms; 2710f21c58cSUlf Hansson 2720f21c58cSUlf Hansson struct reset_control *rstc; 2730f21c58cSUlf Hansson struct dw_mci_dma_ops *dma_ops; 2740f21c58cSUlf Hansson struct dma_pdata *data; 2750f21c58cSUlf Hansson }; 2760f21c58cSUlf Hansson 2774e0a5adfSJaehoon Chung #define DW_MMC_240A 0x240a 2787e4bf1bcSJaehoon Chung #define DW_MMC_280A 0x280a 2794e0a5adfSJaehoon Chung 280f95f3850SWill Newton #define SDMMC_CTRL 0x000 281f95f3850SWill Newton #define SDMMC_PWREN 0x004 282f95f3850SWill Newton #define SDMMC_CLKDIV 0x008 283f95f3850SWill Newton #define SDMMC_CLKSRC 0x00c 284f95f3850SWill Newton #define SDMMC_CLKENA 0x010 285f95f3850SWill Newton #define SDMMC_TMOUT 0x014 286f95f3850SWill Newton #define SDMMC_CTYPE 0x018 287f95f3850SWill Newton #define SDMMC_BLKSIZ 0x01c 288f95f3850SWill Newton #define SDMMC_BYTCNT 0x020 289f95f3850SWill Newton #define SDMMC_INTMASK 0x024 290f95f3850SWill Newton #define SDMMC_CMDARG 0x028 291f95f3850SWill Newton #define SDMMC_CMD 0x02c 292f95f3850SWill Newton #define SDMMC_RESP0 0x030 293f95f3850SWill Newton #define SDMMC_RESP1 0x034 294f95f3850SWill Newton #define SDMMC_RESP2 0x038 295f95f3850SWill Newton #define SDMMC_RESP3 0x03c 296f95f3850SWill Newton #define SDMMC_MINTSTS 0x040 297f95f3850SWill Newton #define SDMMC_RINTSTS 0x044 298f95f3850SWill Newton #define SDMMC_STATUS 0x048 299f95f3850SWill Newton #define SDMMC_FIFOTH 0x04c 300f95f3850SWill Newton #define SDMMC_CDETECT 0x050 301f95f3850SWill Newton #define SDMMC_WRTPRT 0x054 302f95f3850SWill Newton #define SDMMC_GPIO 0x058 303f95f3850SWill Newton #define SDMMC_TCBCNT 0x05c 304f95f3850SWill Newton #define SDMMC_TBBCNT 0x060 305f95f3850SWill Newton #define SDMMC_DEBNCE 0x064 306f95f3850SWill Newton #define SDMMC_USRID 0x068 307f95f3850SWill Newton #define SDMMC_VERID 0x06c 308f95f3850SWill Newton #define SDMMC_HCON 0x070 30941babf75SJaehoon Chung #define SDMMC_UHS_REG 0x074 310935a665eSShawn Lin #define SDMMC_RST_N 0x078 311f95f3850SWill Newton #define SDMMC_BMOD 0x080 312f95f3850SWill Newton #define SDMMC_PLDMND 0x084 313f95f3850SWill Newton #define SDMMC_DBADDR 0x088 314f95f3850SWill Newton #define SDMMC_IDSTS 0x08c 315f95f3850SWill Newton #define SDMMC_IDINTEN 0x090 316f95f3850SWill Newton #define SDMMC_DSCADDR 0x094 317f95f3850SWill Newton #define SDMMC_BUFADDR 0x098 318f1d2736cSSeungwon Jeon #define SDMMC_CDTHRCTL 0x100 319361c7fe9Sliwei #define SDMMC_UHS_REG_EXT 0x108 320e382ab74Stianshuliang #define SDMMC_DDR_REG 0x10c 321361c7fe9Sliwei #define SDMMC_ENABLE_SHIFT 0x110 3224e0a5adfSJaehoon Chung #define SDMMC_DATA(x) (x) 32369d99fdcSPrabu Thangamuthu /* 32469d99fdcSPrabu Thangamuthu * Registers to support idmac 64-bit address mode 32569d99fdcSPrabu Thangamuthu */ 32669d99fdcSPrabu Thangamuthu #define SDMMC_DBADDRL 0x088 32769d99fdcSPrabu Thangamuthu #define SDMMC_DBADDRU 0x08c 32869d99fdcSPrabu Thangamuthu #define SDMMC_IDSTS64 0x090 32969d99fdcSPrabu Thangamuthu #define SDMMC_IDINTEN64 0x094 33069d99fdcSPrabu Thangamuthu #define SDMMC_DSCADDRL 0x098 33169d99fdcSPrabu Thangamuthu #define SDMMC_DSCADDRU 0x09c 33269d99fdcSPrabu Thangamuthu #define SDMMC_BUFADDRL 0x0A0 33369d99fdcSPrabu Thangamuthu #define SDMMC_BUFADDRU 0x0A4 3344e0a5adfSJaehoon Chung 3354e0a5adfSJaehoon Chung /* 3364e0a5adfSJaehoon Chung * Data offset is difference according to Version 3374e0a5adfSJaehoon Chung * Lower than 2.40a : data register offest is 0x100 3384e0a5adfSJaehoon Chung */ 3394e0a5adfSJaehoon Chung #define DATA_OFFSET 0x100 3404e0a5adfSJaehoon Chung #define DATA_240A_OFFSET 0x200 341f95f3850SWill Newton 342f95f3850SWill Newton /* shift bit field */ 343f95f3850SWill Newton #define _SBF(f, v) ((v) << (f)) 344f95f3850SWill Newton 345f95f3850SWill Newton /* Control register defines */ 346f95f3850SWill Newton #define SDMMC_CTRL_USE_IDMAC BIT(25) 347f95f3850SWill Newton #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 348f95f3850SWill Newton #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 349f95f3850SWill Newton #define SDMMC_CTRL_SEND_CCSD BIT(9) 350f95f3850SWill Newton #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 351f95f3850SWill Newton #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 352f95f3850SWill Newton #define SDMMC_CTRL_READ_WAIT BIT(6) 353f95f3850SWill Newton #define SDMMC_CTRL_DMA_ENABLE BIT(5) 354f95f3850SWill Newton #define SDMMC_CTRL_INT_ENABLE BIT(4) 355f95f3850SWill Newton #define SDMMC_CTRL_DMA_RESET BIT(2) 356f95f3850SWill Newton #define SDMMC_CTRL_FIFO_RESET BIT(1) 357f95f3850SWill Newton #define SDMMC_CTRL_RESET BIT(0) 358f95f3850SWill Newton /* Clock Enable register defines */ 359f95f3850SWill Newton #define SDMMC_CLKEN_LOW_PWR BIT(16) 360f95f3850SWill Newton #define SDMMC_CLKEN_ENABLE BIT(0) 361f95f3850SWill Newton /* time-out register defines */ 362f95f3850SWill Newton #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 363f95f3850SWill Newton #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 364f95f3850SWill Newton #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 365f95f3850SWill Newton #define SDMMC_TMOUT_RESP_MSK 0xFF 366f95f3850SWill Newton /* card-type register defines */ 367f95f3850SWill Newton #define SDMMC_CTYPE_8BIT BIT(16) 368f95f3850SWill Newton #define SDMMC_CTYPE_4BIT BIT(0) 369f95f3850SWill Newton #define SDMMC_CTYPE_1BIT 0 370f95f3850SWill Newton /* Interrupt status & mask register defines */ 3711a5c8e1fSShashidhar Hiremath #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 372f95f3850SWill Newton #define SDMMC_INT_EBE BIT(15) 373f95f3850SWill Newton #define SDMMC_INT_ACD BIT(14) 374f95f3850SWill Newton #define SDMMC_INT_SBE BIT(13) 375f95f3850SWill Newton #define SDMMC_INT_HLE BIT(12) 376f95f3850SWill Newton #define SDMMC_INT_FRUN BIT(11) 377f95f3850SWill Newton #define SDMMC_INT_HTO BIT(10) 37801730558SDoug Anderson #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 3793f7eec62SJaehoon Chung #define SDMMC_INT_DRTO BIT(9) 380f95f3850SWill Newton #define SDMMC_INT_RTO BIT(8) 381f95f3850SWill Newton #define SDMMC_INT_DCRC BIT(7) 382f95f3850SWill Newton #define SDMMC_INT_RCRC BIT(6) 383f95f3850SWill Newton #define SDMMC_INT_RXDR BIT(5) 384f95f3850SWill Newton #define SDMMC_INT_TXDR BIT(4) 385f95f3850SWill Newton #define SDMMC_INT_DATA_OVER BIT(3) 386f95f3850SWill Newton #define SDMMC_INT_CMD_DONE BIT(2) 387f95f3850SWill Newton #define SDMMC_INT_RESP_ERR BIT(1) 388f95f3850SWill Newton #define SDMMC_INT_CD BIT(0) 389f95f3850SWill Newton #define SDMMC_INT_ERROR 0xbfc2 390f95f3850SWill Newton /* Command register defines */ 391f95f3850SWill Newton #define SDMMC_CMD_START BIT(31) 392eede2111SDinh Nguyen #define SDMMC_CMD_USE_HOLD_REG BIT(29) 39301730558SDoug Anderson #define SDMMC_CMD_VOLT_SWITCH BIT(28) 394f95f3850SWill Newton #define SDMMC_CMD_CCS_EXP BIT(23) 395f95f3850SWill Newton #define SDMMC_CMD_CEATA_RD BIT(22) 396f95f3850SWill Newton #define SDMMC_CMD_UPD_CLK BIT(21) 397f95f3850SWill Newton #define SDMMC_CMD_INIT BIT(15) 398f95f3850SWill Newton #define SDMMC_CMD_STOP BIT(14) 399f95f3850SWill Newton #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 400f95f3850SWill Newton #define SDMMC_CMD_SEND_STOP BIT(12) 401f95f3850SWill Newton #define SDMMC_CMD_STRM_MODE BIT(11) 402f95f3850SWill Newton #define SDMMC_CMD_DAT_WR BIT(10) 403f95f3850SWill Newton #define SDMMC_CMD_DAT_EXP BIT(9) 404f95f3850SWill Newton #define SDMMC_CMD_RESP_CRC BIT(8) 405f95f3850SWill Newton #define SDMMC_CMD_RESP_LONG BIT(7) 406f95f3850SWill Newton #define SDMMC_CMD_RESP_EXP BIT(6) 407f95f3850SWill Newton #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 408f95f3850SWill Newton /* Status register defines */ 409ee5d19b2SJaehoon Chung #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 4103a33a94cSSonny Rao #define SDMMC_STATUS_DMA_REQ BIT(31) 41101730558SDoug Anderson #define SDMMC_STATUS_BUSY BIT(9) 41252426899SSeungwon Jeon /* FIFOTH register defines */ 41352426899SSeungwon Jeon #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 41452426899SSeungwon Jeon ((r) & 0xFFF) << 16 | \ 41552426899SSeungwon Jeon ((t) & 0xFFF)) 4163fc7eaefSShawn Lin /* HCON register defines */ 4173fc7eaefSShawn Lin #define DMA_INTERFACE_IDMA (0x0) 4183fc7eaefSShawn Lin #define DMA_INTERFACE_DWDMA (0x1) 4193fc7eaefSShawn Lin #define DMA_INTERFACE_GDMA (0x2) 4203fc7eaefSShawn Lin #define DMA_INTERFACE_NODMA (0x3) 4213fc7eaefSShawn Lin #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 42270692752SShawn Lin #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 42370692752SShawn Lin #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 42470692752SShawn Lin #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 425f95f3850SWill Newton /* Internal DMAC interrupt defines */ 426f95f3850SWill Newton #define SDMMC_IDMAC_INT_AI BIT(9) 427f95f3850SWill Newton #define SDMMC_IDMAC_INT_NI BIT(8) 428f95f3850SWill Newton #define SDMMC_IDMAC_INT_CES BIT(5) 429f95f3850SWill Newton #define SDMMC_IDMAC_INT_DU BIT(4) 430f95f3850SWill Newton #define SDMMC_IDMAC_INT_FBE BIT(2) 431f95f3850SWill Newton #define SDMMC_IDMAC_INT_RI BIT(1) 432f95f3850SWill Newton #define SDMMC_IDMAC_INT_TI BIT(0) 433f95f3850SWill Newton /* Internal DMAC bus mode bits */ 434f95f3850SWill Newton #define SDMMC_IDMAC_ENABLE BIT(7) 435f95f3850SWill Newton #define SDMMC_IDMAC_FB BIT(1) 436f95f3850SWill Newton #define SDMMC_IDMAC_SWRESET BIT(0) 437935a665eSShawn Lin /* H/W reset */ 438935a665eSShawn Lin #define SDMMC_RST_HWACTIVE 0x1 4394e0a5adfSJaehoon Chung /* Version ID register define */ 4404e0a5adfSJaehoon Chung #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 441f1d2736cSSeungwon Jeon /* Card read threshold */ 4427e4bf1bcSJaehoon Chung #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 4437e4bf1bcSJaehoon Chung #define SDMMC_CARD_WR_THR_EN BIT(2) 4447e4bf1bcSJaehoon Chung #define SDMMC_CARD_RD_THR_EN BIT(0) 4457e4bf1bcSJaehoon Chung /* UHS-1 register defines */ 446e382ab74Stianshuliang #define SDMMC_UHS_DDR BIT(16) 44701730558SDoug Anderson #define SDMMC_UHS_18V BIT(0) 448e382ab74Stianshuliang /* DDR register defines */ 449e382ab74Stianshuliang #define SDMMC_DDR_HS400 BIT(31) 450e382ab74Stianshuliang /* Enable shift register defines */ 451e382ab74Stianshuliang #define SDMMC_ENABLE_PHASE BIT(0) 4523a33a94cSSonny Rao /* All ctrl reset bits */ 4533a33a94cSSonny Rao #define SDMMC_CTRL_ALL_RESET_FLAGS \ 4543a33a94cSSonny Rao (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 4553a33a94cSSonny Rao 45676184ac1SBen Dooks /* FIFO register access macros. These should not change the data endian-ness 4574b514fa2SAlexey Roslyakov * as they are written to memory to be dealt with by the upper layers 4584b514fa2SAlexey Roslyakov */ 45976184ac1SBen Dooks #define mci_fifo_readw(__reg) __raw_readw(__reg) 46076184ac1SBen Dooks #define mci_fifo_readl(__reg) __raw_readl(__reg) 46176184ac1SBen Dooks #define mci_fifo_readq(__reg) __raw_readq(__reg) 46276184ac1SBen Dooks 46376184ac1SBen Dooks #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 46476184ac1SBen Dooks #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 46576184ac1SBen Dooks #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 46676184ac1SBen Dooks 467f95f3850SWill Newton /* Register access macros */ 468f95f3850SWill Newton #define mci_readl(dev, reg) \ 469a2f17680SBen Dooks readl_relaxed((dev)->regs + SDMMC_##reg) 470f95f3850SWill Newton #define mci_writel(dev, reg, value) \ 471a2f17680SBen Dooks writel_relaxed((value), (dev)->regs + SDMMC_##reg) 472f95f3850SWill Newton 473f95f3850SWill Newton /* 16-bit FIFO access macros */ 474f95f3850SWill Newton #define mci_readw(dev, reg) \ 475a2f17680SBen Dooks readw_relaxed((dev)->regs + SDMMC_##reg) 476f95f3850SWill Newton #define mci_writew(dev, reg, value) \ 477a2f17680SBen Dooks writew_relaxed((value), (dev)->regs + SDMMC_##reg) 478f95f3850SWill Newton 479f95f3850SWill Newton /* 64-bit FIFO access macros */ 480f95f3850SWill Newton #ifdef readq 481f95f3850SWill Newton #define mci_readq(dev, reg) \ 482a2f17680SBen Dooks readq_relaxed((dev)->regs + SDMMC_##reg) 483f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 484a2f17680SBen Dooks writeq_relaxed((value), (dev)->regs + SDMMC_##reg) 485f95f3850SWill Newton #else 486f95f3850SWill Newton /* 487f95f3850SWill Newton * Dummy readq implementation for architectures that don't define it. 488f95f3850SWill Newton * 489f95f3850SWill Newton * We would assume that none of these architectures would configure 490f95f3850SWill Newton * the IP block with a 64bit FIFO width, so this code will never be 491f95f3850SWill Newton * executed on those machines. Defining these macros here keeps the 492f95f3850SWill Newton * rest of the code free from ifdefs. 493f95f3850SWill Newton */ 494f95f3850SWill Newton #define mci_readq(dev, reg) \ 495892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 496f95f3850SWill Newton #define mci_writeq(dev, reg, value) \ 497892b1e31SJames Hogan (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 49876184ac1SBen Dooks 49976184ac1SBen Dooks #define __raw_writeq(__value, __reg) \ 50076184ac1SBen Dooks (*(volatile u64 __force *)(__reg) = (__value)) 50176184ac1SBen Dooks #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 502f95f3850SWill Newton #endif 503f95f3850SWill Newton 50462ca8034SShashidhar Hiremath extern int dw_mci_probe(struct dw_mci *host); 50562ca8034SShashidhar Hiremath extern void dw_mci_remove(struct dw_mci *host); 506e9ed8835SShawn Lin #ifdef CONFIG_PM 507e9ed8835SShawn Lin extern int dw_mci_runtime_suspend(struct device *device); 508e9ed8835SShawn Lin extern int dw_mci_runtime_resume(struct device *device); 50962ca8034SShashidhar Hiremath #endif 51062ca8034SShashidhar Hiremath 511800d78bfSThomas Abraham /** 5120976f16dSSeungwon Jeon * struct dw_mci_slot - MMC slot state 5130976f16dSSeungwon Jeon * @mmc: The mmc_host representing this slot. 5140976f16dSSeungwon Jeon * @host: The MMC controller this slot is using. 5150976f16dSSeungwon Jeon * @ctype: Card type for this slot. 5160976f16dSSeungwon Jeon * @mrq: mmc_request currently being processed or waiting to be 5170976f16dSSeungwon Jeon * processed, or NULL when the slot is idle. 5180976f16dSSeungwon Jeon * @queue_node: List node for placing this node in the @queue list of 5190976f16dSSeungwon Jeon * &struct dw_mci. 5200976f16dSSeungwon Jeon * @clock: Clock rate configured by set_ios(). Protected by host->lock. 521005d675aSJaehoon Chung * @__clk_old: The last clock value that was requested from core. 522005d675aSJaehoon Chung * Keeping track of this helps us to avoid spamming the console. 5230976f16dSSeungwon Jeon * @flags: Random state bits associated with the slot. 5240976f16dSSeungwon Jeon * @id: Number of this slot. 52576756234SAddy Ke * @sdio_id: Number of this slot in the SDIO interrupt registers. 5260976f16dSSeungwon Jeon */ 5270976f16dSSeungwon Jeon struct dw_mci_slot { 5280976f16dSSeungwon Jeon struct mmc_host *mmc; 5290976f16dSSeungwon Jeon struct dw_mci *host; 5300976f16dSSeungwon Jeon 5310976f16dSSeungwon Jeon u32 ctype; 5320976f16dSSeungwon Jeon 5330976f16dSSeungwon Jeon struct mmc_request *mrq; 5340976f16dSSeungwon Jeon struct list_head queue_node; 5350976f16dSSeungwon Jeon 5360976f16dSSeungwon Jeon unsigned int clock; 537005d675aSJaehoon Chung unsigned int __clk_old; 5380976f16dSSeungwon Jeon 5390976f16dSSeungwon Jeon unsigned long flags; 5400976f16dSSeungwon Jeon #define DW_MMC_CARD_PRESENT 0 5410976f16dSSeungwon Jeon #define DW_MMC_CARD_NEED_INIT 1 542b24c8b26SDoug Anderson #define DW_MMC_CARD_NO_LOW_PWR 2 543aaaaeb7aSJaehoon Chung #define DW_MMC_CARD_NO_USE_HOLD 3 544e6cd7a8eSJaehoon Chung #define DW_MMC_CARD_NEEDS_POLL 4 5450976f16dSSeungwon Jeon int id; 54676756234SAddy Ke int sdio_id; 5470976f16dSSeungwon Jeon }; 5480976f16dSSeungwon Jeon 5490976f16dSSeungwon Jeon /** 550800d78bfSThomas Abraham * dw_mci driver data - dw-mshc implementation specific driver data. 551800d78bfSThomas Abraham * @caps: mmc subsystem specified capabilities of the controller(s). 5520d84b9e5SShawn Lin * @num_caps: number of capabilities specified by @caps. 553800d78bfSThomas Abraham * @init: early implementation specific initialization. 554800d78bfSThomas Abraham * @set_ios: handle bus specific extensions. 555800d78bfSThomas Abraham * @parse_dt: parse implementation specific device tree properties. 5565532ec51SSachin Kamat * @execute_tuning: implementation specific tuning procedure. 557800d78bfSThomas Abraham * 558800d78bfSThomas Abraham * Provide controller implementation specific extensions. The usage of this 559800d78bfSThomas Abraham * data structure is fully optional and usage of each member in this structure 560800d78bfSThomas Abraham * is optional as well. 561800d78bfSThomas Abraham */ 562800d78bfSThomas Abraham struct dw_mci_drv_data { 563800d78bfSThomas Abraham unsigned long *caps; 5640d84b9e5SShawn Lin u32 num_caps; 565800d78bfSThomas Abraham int (*init)(struct dw_mci *host); 566800d78bfSThomas Abraham void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 567800d78bfSThomas Abraham int (*parse_dt)(struct dw_mci *host); 5689979dbe5SChaotian Jing int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); 56980113132SSeungwon Jeon int (*prepare_hs400_tuning)(struct dw_mci *host, 57080113132SSeungwon Jeon struct mmc_ios *ios); 5718f7849c4SZhangfei Gao int (*switch_voltage)(struct mmc_host *mmc, 5728f7849c4SZhangfei Gao struct mmc_ios *ios); 573800d78bfSThomas Abraham }; 574f95f3850SWill Newton #endif /* _DW_MMC_H_ */ 575