1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/ioport.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/stat.h> 28 #include <linux/delay.h> 29 #include <linux/irq.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/dw_mmc.h> 33 #include <linux/bitops.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/workqueue.h> 36 #include <linux/of.h> 37 #include <linux/of_gpio.h> 38 39 #include "dw_mmc.h" 40 41 /* Common flag combinations */ 42 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \ 43 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 44 SDMMC_INT_EBE) 45 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 46 SDMMC_INT_RESP_ERR) 47 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 48 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 49 #define DW_MCI_SEND_STATUS 1 50 #define DW_MCI_RECV_STATUS 2 51 #define DW_MCI_DMA_THRESHOLD 16 52 53 #ifdef CONFIG_MMC_DW_IDMAC 54 struct idmac_desc { 55 u32 des0; /* Control Descriptor */ 56 #define IDMAC_DES0_DIC BIT(1) 57 #define IDMAC_DES0_LD BIT(2) 58 #define IDMAC_DES0_FD BIT(3) 59 #define IDMAC_DES0_CH BIT(4) 60 #define IDMAC_DES0_ER BIT(5) 61 #define IDMAC_DES0_CES BIT(30) 62 #define IDMAC_DES0_OWN BIT(31) 63 64 u32 des1; /* Buffer sizes */ 65 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 66 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 67 68 u32 des2; /* buffer 1 physical address */ 69 70 u32 des3; /* buffer 2 physical address */ 71 }; 72 #endif /* CONFIG_MMC_DW_IDMAC */ 73 74 /** 75 * struct dw_mci_slot - MMC slot state 76 * @mmc: The mmc_host representing this slot. 77 * @host: The MMC controller this slot is using. 78 * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) 79 * @wp_gpio: If gpio_is_valid() we'll use this to read write protect. 80 * @ctype: Card type for this slot. 81 * @mrq: mmc_request currently being processed or waiting to be 82 * processed, or NULL when the slot is idle. 83 * @queue_node: List node for placing this node in the @queue list of 84 * &struct dw_mci. 85 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 86 * @flags: Random state bits associated with the slot. 87 * @id: Number of this slot. 88 * @last_detect_state: Most recently observed card detect state. 89 */ 90 struct dw_mci_slot { 91 struct mmc_host *mmc; 92 struct dw_mci *host; 93 94 int quirks; 95 int wp_gpio; 96 97 u32 ctype; 98 99 struct mmc_request *mrq; 100 struct list_head queue_node; 101 102 unsigned int clock; 103 unsigned long flags; 104 #define DW_MMC_CARD_PRESENT 0 105 #define DW_MMC_CARD_NEED_INIT 1 106 int id; 107 int last_detect_state; 108 }; 109 110 #if defined(CONFIG_DEBUG_FS) 111 static int dw_mci_req_show(struct seq_file *s, void *v) 112 { 113 struct dw_mci_slot *slot = s->private; 114 struct mmc_request *mrq; 115 struct mmc_command *cmd; 116 struct mmc_command *stop; 117 struct mmc_data *data; 118 119 /* Make sure we get a consistent snapshot */ 120 spin_lock_bh(&slot->host->lock); 121 mrq = slot->mrq; 122 123 if (mrq) { 124 cmd = mrq->cmd; 125 data = mrq->data; 126 stop = mrq->stop; 127 128 if (cmd) 129 seq_printf(s, 130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131 cmd->opcode, cmd->arg, cmd->flags, 132 cmd->resp[0], cmd->resp[1], cmd->resp[2], 133 cmd->resp[2], cmd->error); 134 if (data) 135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136 data->bytes_xfered, data->blocks, 137 data->blksz, data->flags, data->error); 138 if (stop) 139 seq_printf(s, 140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141 stop->opcode, stop->arg, stop->flags, 142 stop->resp[0], stop->resp[1], stop->resp[2], 143 stop->resp[2], stop->error); 144 } 145 146 spin_unlock_bh(&slot->host->lock); 147 148 return 0; 149 } 150 151 static int dw_mci_req_open(struct inode *inode, struct file *file) 152 { 153 return single_open(file, dw_mci_req_show, inode->i_private); 154 } 155 156 static const struct file_operations dw_mci_req_fops = { 157 .owner = THIS_MODULE, 158 .open = dw_mci_req_open, 159 .read = seq_read, 160 .llseek = seq_lseek, 161 .release = single_release, 162 }; 163 164 static int dw_mci_regs_show(struct seq_file *s, void *v) 165 { 166 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 167 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 168 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 169 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 170 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 171 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 172 173 return 0; 174 } 175 176 static int dw_mci_regs_open(struct inode *inode, struct file *file) 177 { 178 return single_open(file, dw_mci_regs_show, inode->i_private); 179 } 180 181 static const struct file_operations dw_mci_regs_fops = { 182 .owner = THIS_MODULE, 183 .open = dw_mci_regs_open, 184 .read = seq_read, 185 .llseek = seq_lseek, 186 .release = single_release, 187 }; 188 189 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 190 { 191 struct mmc_host *mmc = slot->mmc; 192 struct dw_mci *host = slot->host; 193 struct dentry *root; 194 struct dentry *node; 195 196 root = mmc->debugfs_root; 197 if (!root) 198 return; 199 200 node = debugfs_create_file("regs", S_IRUSR, root, host, 201 &dw_mci_regs_fops); 202 if (!node) 203 goto err; 204 205 node = debugfs_create_file("req", S_IRUSR, root, slot, 206 &dw_mci_req_fops); 207 if (!node) 208 goto err; 209 210 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 211 if (!node) 212 goto err; 213 214 node = debugfs_create_x32("pending_events", S_IRUSR, root, 215 (u32 *)&host->pending_events); 216 if (!node) 217 goto err; 218 219 node = debugfs_create_x32("completed_events", S_IRUSR, root, 220 (u32 *)&host->completed_events); 221 if (!node) 222 goto err; 223 224 return; 225 226 err: 227 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 228 } 229 #endif /* defined(CONFIG_DEBUG_FS) */ 230 231 static void dw_mci_set_timeout(struct dw_mci *host) 232 { 233 /* timeout (maximum) */ 234 mci_writel(host, TMOUT, 0xffffffff); 235 } 236 237 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 238 { 239 struct mmc_data *data; 240 struct dw_mci_slot *slot = mmc_priv(mmc); 241 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 242 u32 cmdr; 243 cmd->error = -EINPROGRESS; 244 245 cmdr = cmd->opcode; 246 247 if (cmdr == MMC_STOP_TRANSMISSION) 248 cmdr |= SDMMC_CMD_STOP; 249 else 250 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 251 252 if (cmd->flags & MMC_RSP_PRESENT) { 253 /* We expect a response, so set this bit */ 254 cmdr |= SDMMC_CMD_RESP_EXP; 255 if (cmd->flags & MMC_RSP_136) 256 cmdr |= SDMMC_CMD_RESP_LONG; 257 } 258 259 if (cmd->flags & MMC_RSP_CRC) 260 cmdr |= SDMMC_CMD_RESP_CRC; 261 262 data = cmd->data; 263 if (data) { 264 cmdr |= SDMMC_CMD_DAT_EXP; 265 if (data->flags & MMC_DATA_STREAM) 266 cmdr |= SDMMC_CMD_STRM_MODE; 267 if (data->flags & MMC_DATA_WRITE) 268 cmdr |= SDMMC_CMD_DAT_WR; 269 } 270 271 if (drv_data && drv_data->prepare_command) 272 drv_data->prepare_command(slot->host, &cmdr); 273 274 return cmdr; 275 } 276 277 static void dw_mci_start_command(struct dw_mci *host, 278 struct mmc_command *cmd, u32 cmd_flags) 279 { 280 host->cmd = cmd; 281 dev_vdbg(host->dev, 282 "start command: ARGR=0x%08x CMDR=0x%08x\n", 283 cmd->arg, cmd_flags); 284 285 mci_writel(host, CMDARG, cmd->arg); 286 wmb(); 287 288 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 289 } 290 291 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data) 292 { 293 dw_mci_start_command(host, data->stop, host->stop_cmdr); 294 } 295 296 /* DMA interface functions */ 297 static void dw_mci_stop_dma(struct dw_mci *host) 298 { 299 if (host->using_dma) { 300 host->dma_ops->stop(host); 301 host->dma_ops->cleanup(host); 302 } else { 303 /* Data transfer was stopped by the interrupt handler */ 304 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 305 } 306 } 307 308 static int dw_mci_get_dma_dir(struct mmc_data *data) 309 { 310 if (data->flags & MMC_DATA_WRITE) 311 return DMA_TO_DEVICE; 312 else 313 return DMA_FROM_DEVICE; 314 } 315 316 #ifdef CONFIG_MMC_DW_IDMAC 317 static void dw_mci_dma_cleanup(struct dw_mci *host) 318 { 319 struct mmc_data *data = host->data; 320 321 if (data) 322 if (!data->host_cookie) 323 dma_unmap_sg(host->dev, 324 data->sg, 325 data->sg_len, 326 dw_mci_get_dma_dir(data)); 327 } 328 329 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 330 { 331 u32 temp; 332 333 /* Disable and reset the IDMAC interface */ 334 temp = mci_readl(host, CTRL); 335 temp &= ~SDMMC_CTRL_USE_IDMAC; 336 temp |= SDMMC_CTRL_DMA_RESET; 337 mci_writel(host, CTRL, temp); 338 339 /* Stop the IDMAC running */ 340 temp = mci_readl(host, BMOD); 341 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 342 mci_writel(host, BMOD, temp); 343 } 344 345 static void dw_mci_idmac_complete_dma(struct dw_mci *host) 346 { 347 struct mmc_data *data = host->data; 348 349 dev_vdbg(host->dev, "DMA complete\n"); 350 351 host->dma_ops->cleanup(host); 352 353 /* 354 * If the card was removed, data will be NULL. No point in trying to 355 * send the stop command or waiting for NBUSY in this case. 356 */ 357 if (data) { 358 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 359 tasklet_schedule(&host->tasklet); 360 } 361 } 362 363 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 364 unsigned int sg_len) 365 { 366 int i; 367 struct idmac_desc *desc = host->sg_cpu; 368 369 for (i = 0; i < sg_len; i++, desc++) { 370 unsigned int length = sg_dma_len(&data->sg[i]); 371 u32 mem_addr = sg_dma_address(&data->sg[i]); 372 373 /* Set the OWN bit and disable interrupts for this descriptor */ 374 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; 375 376 /* Buffer length */ 377 IDMAC_SET_BUFFER1_SIZE(desc, length); 378 379 /* Physical address to DMA to/from */ 380 desc->des2 = mem_addr; 381 } 382 383 /* Set first descriptor */ 384 desc = host->sg_cpu; 385 desc->des0 |= IDMAC_DES0_FD; 386 387 /* Set last descriptor */ 388 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 389 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 390 desc->des0 |= IDMAC_DES0_LD; 391 392 wmb(); 393 } 394 395 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 396 { 397 u32 temp; 398 399 dw_mci_translate_sglist(host, host->data, sg_len); 400 401 /* Select IDMAC interface */ 402 temp = mci_readl(host, CTRL); 403 temp |= SDMMC_CTRL_USE_IDMAC; 404 mci_writel(host, CTRL, temp); 405 406 wmb(); 407 408 /* Enable the IDMAC */ 409 temp = mci_readl(host, BMOD); 410 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 411 mci_writel(host, BMOD, temp); 412 413 /* Start it running */ 414 mci_writel(host, PLDMND, 1); 415 } 416 417 static int dw_mci_idmac_init(struct dw_mci *host) 418 { 419 struct idmac_desc *p; 420 int i; 421 422 /* Number of descriptors in the ring buffer */ 423 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 424 425 /* Forward link the descriptor list */ 426 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 427 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1)); 428 429 /* Set the last descriptor as the end-of-ring descriptor */ 430 p->des3 = host->sg_dma; 431 p->des0 = IDMAC_DES0_ER; 432 433 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET); 434 435 /* Mask out interrupts - get Tx & Rx complete only */ 436 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI | 437 SDMMC_IDMAC_INT_TI); 438 439 /* Set the descriptor base address */ 440 mci_writel(host, DBADDR, host->sg_dma); 441 return 0; 442 } 443 444 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 445 .init = dw_mci_idmac_init, 446 .start = dw_mci_idmac_start_dma, 447 .stop = dw_mci_idmac_stop_dma, 448 .complete = dw_mci_idmac_complete_dma, 449 .cleanup = dw_mci_dma_cleanup, 450 }; 451 #endif /* CONFIG_MMC_DW_IDMAC */ 452 453 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 454 struct mmc_data *data, 455 bool next) 456 { 457 struct scatterlist *sg; 458 unsigned int i, sg_len; 459 460 if (!next && data->host_cookie) 461 return data->host_cookie; 462 463 /* 464 * We don't do DMA on "complex" transfers, i.e. with 465 * non-word-aligned buffers or lengths. Also, we don't bother 466 * with all the DMA setup overhead for short transfers. 467 */ 468 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 469 return -EINVAL; 470 471 if (data->blksz & 3) 472 return -EINVAL; 473 474 for_each_sg(data->sg, sg, data->sg_len, i) { 475 if (sg->offset & 3 || sg->length & 3) 476 return -EINVAL; 477 } 478 479 sg_len = dma_map_sg(host->dev, 480 data->sg, 481 data->sg_len, 482 dw_mci_get_dma_dir(data)); 483 if (sg_len == 0) 484 return -EINVAL; 485 486 if (next) 487 data->host_cookie = sg_len; 488 489 return sg_len; 490 } 491 492 static void dw_mci_pre_req(struct mmc_host *mmc, 493 struct mmc_request *mrq, 494 bool is_first_req) 495 { 496 struct dw_mci_slot *slot = mmc_priv(mmc); 497 struct mmc_data *data = mrq->data; 498 499 if (!slot->host->use_dma || !data) 500 return; 501 502 if (data->host_cookie) { 503 data->host_cookie = 0; 504 return; 505 } 506 507 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 508 data->host_cookie = 0; 509 } 510 511 static void dw_mci_post_req(struct mmc_host *mmc, 512 struct mmc_request *mrq, 513 int err) 514 { 515 struct dw_mci_slot *slot = mmc_priv(mmc); 516 struct mmc_data *data = mrq->data; 517 518 if (!slot->host->use_dma || !data) 519 return; 520 521 if (data->host_cookie) 522 dma_unmap_sg(slot->host->dev, 523 data->sg, 524 data->sg_len, 525 dw_mci_get_dma_dir(data)); 526 data->host_cookie = 0; 527 } 528 529 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 530 { 531 int sg_len; 532 u32 temp; 533 534 host->using_dma = 0; 535 536 /* If we don't have a channel, we can't do DMA */ 537 if (!host->use_dma) 538 return -ENODEV; 539 540 sg_len = dw_mci_pre_dma_transfer(host, data, 0); 541 if (sg_len < 0) { 542 host->dma_ops->stop(host); 543 return sg_len; 544 } 545 546 host->using_dma = 1; 547 548 dev_vdbg(host->dev, 549 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 550 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 551 sg_len); 552 553 /* Enable the DMA interface */ 554 temp = mci_readl(host, CTRL); 555 temp |= SDMMC_CTRL_DMA_ENABLE; 556 mci_writel(host, CTRL, temp); 557 558 /* Disable RX/TX IRQs, let DMA handle it */ 559 temp = mci_readl(host, INTMASK); 560 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 561 mci_writel(host, INTMASK, temp); 562 563 host->dma_ops->start(host, sg_len); 564 565 return 0; 566 } 567 568 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 569 { 570 u32 temp; 571 572 data->error = -EINPROGRESS; 573 574 WARN_ON(host->data); 575 host->sg = NULL; 576 host->data = data; 577 578 if (data->flags & MMC_DATA_READ) 579 host->dir_status = DW_MCI_RECV_STATUS; 580 else 581 host->dir_status = DW_MCI_SEND_STATUS; 582 583 if (dw_mci_submit_data_dma(host, data)) { 584 int flags = SG_MITER_ATOMIC; 585 if (host->data->flags & MMC_DATA_READ) 586 flags |= SG_MITER_TO_SG; 587 else 588 flags |= SG_MITER_FROM_SG; 589 590 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 591 host->sg = data->sg; 592 host->part_buf_start = 0; 593 host->part_buf_count = 0; 594 595 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 596 temp = mci_readl(host, INTMASK); 597 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 598 mci_writel(host, INTMASK, temp); 599 600 temp = mci_readl(host, CTRL); 601 temp &= ~SDMMC_CTRL_DMA_ENABLE; 602 mci_writel(host, CTRL, temp); 603 } 604 } 605 606 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 607 { 608 struct dw_mci *host = slot->host; 609 unsigned long timeout = jiffies + msecs_to_jiffies(500); 610 unsigned int cmd_status = 0; 611 612 mci_writel(host, CMDARG, arg); 613 wmb(); 614 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 615 616 while (time_before(jiffies, timeout)) { 617 cmd_status = mci_readl(host, CMD); 618 if (!(cmd_status & SDMMC_CMD_START)) 619 return; 620 } 621 dev_err(&slot->mmc->class_dev, 622 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 623 cmd, arg, cmd_status); 624 } 625 626 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 627 { 628 struct dw_mci *host = slot->host; 629 u32 div; 630 u32 clk_en_a; 631 632 if (slot->clock != host->current_speed || force_clkinit) { 633 div = host->bus_hz / slot->clock; 634 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock) 635 /* 636 * move the + 1 after the divide to prevent 637 * over-clocking the card. 638 */ 639 div += 1; 640 641 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0; 642 643 dev_info(&slot->mmc->class_dev, 644 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ" 645 " div = %d)\n", slot->id, host->bus_hz, slot->clock, 646 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div); 647 648 /* disable clock */ 649 mci_writel(host, CLKENA, 0); 650 mci_writel(host, CLKSRC, 0); 651 652 /* inform CIU */ 653 mci_send_cmd(slot, 654 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 655 656 /* set clock to desired speed */ 657 mci_writel(host, CLKDIV, div); 658 659 /* inform CIU */ 660 mci_send_cmd(slot, 661 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 662 663 /* enable clock; only low power if no SDIO */ 664 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 665 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id))) 666 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 667 mci_writel(host, CLKENA, clk_en_a); 668 669 /* inform CIU */ 670 mci_send_cmd(slot, 671 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 672 673 host->current_speed = slot->clock; 674 } 675 676 /* Set the current slot bus width */ 677 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 678 } 679 680 static void __dw_mci_start_request(struct dw_mci *host, 681 struct dw_mci_slot *slot, 682 struct mmc_command *cmd) 683 { 684 struct mmc_request *mrq; 685 struct mmc_data *data; 686 u32 cmdflags; 687 688 mrq = slot->mrq; 689 if (host->pdata->select_slot) 690 host->pdata->select_slot(slot->id); 691 692 host->cur_slot = slot; 693 host->mrq = mrq; 694 695 host->pending_events = 0; 696 host->completed_events = 0; 697 host->data_status = 0; 698 699 data = cmd->data; 700 if (data) { 701 dw_mci_set_timeout(host); 702 mci_writel(host, BYTCNT, data->blksz*data->blocks); 703 mci_writel(host, BLKSIZ, data->blksz); 704 } 705 706 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 707 708 /* this is the first command, send the initialization clock */ 709 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 710 cmdflags |= SDMMC_CMD_INIT; 711 712 if (data) { 713 dw_mci_submit_data(host, data); 714 wmb(); 715 } 716 717 dw_mci_start_command(host, cmd, cmdflags); 718 719 if (mrq->stop) 720 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 721 } 722 723 static void dw_mci_start_request(struct dw_mci *host, 724 struct dw_mci_slot *slot) 725 { 726 struct mmc_request *mrq = slot->mrq; 727 struct mmc_command *cmd; 728 729 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 730 __dw_mci_start_request(host, slot, cmd); 731 } 732 733 /* must be called with host->lock held */ 734 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 735 struct mmc_request *mrq) 736 { 737 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 738 host->state); 739 740 slot->mrq = mrq; 741 742 if (host->state == STATE_IDLE) { 743 host->state = STATE_SENDING_CMD; 744 dw_mci_start_request(host, slot); 745 } else { 746 list_add_tail(&slot->queue_node, &host->queue); 747 } 748 } 749 750 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 751 { 752 struct dw_mci_slot *slot = mmc_priv(mmc); 753 struct dw_mci *host = slot->host; 754 755 WARN_ON(slot->mrq); 756 757 /* 758 * The check for card presence and queueing of the request must be 759 * atomic, otherwise the card could be removed in between and the 760 * request wouldn't fail until another card was inserted. 761 */ 762 spin_lock_bh(&host->lock); 763 764 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 765 spin_unlock_bh(&host->lock); 766 mrq->cmd->error = -ENOMEDIUM; 767 mmc_request_done(mmc, mrq); 768 return; 769 } 770 771 dw_mci_queue_request(host, slot, mrq); 772 773 spin_unlock_bh(&host->lock); 774 } 775 776 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 777 { 778 struct dw_mci_slot *slot = mmc_priv(mmc); 779 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 780 u32 regs; 781 782 switch (ios->bus_width) { 783 case MMC_BUS_WIDTH_4: 784 slot->ctype = SDMMC_CTYPE_4BIT; 785 break; 786 case MMC_BUS_WIDTH_8: 787 slot->ctype = SDMMC_CTYPE_8BIT; 788 break; 789 default: 790 /* set default 1 bit mode */ 791 slot->ctype = SDMMC_CTYPE_1BIT; 792 } 793 794 regs = mci_readl(slot->host, UHS_REG); 795 796 /* DDR mode set */ 797 if (ios->timing == MMC_TIMING_UHS_DDR50) 798 regs |= ((0x1 << slot->id) << 16); 799 else 800 regs &= ~((0x1 << slot->id) << 16); 801 802 mci_writel(slot->host, UHS_REG, regs); 803 804 if (ios->clock) { 805 /* 806 * Use mirror of ios->clock to prevent race with mmc 807 * core ios update when finding the minimum. 808 */ 809 slot->clock = ios->clock; 810 } 811 812 if (drv_data && drv_data->set_ios) 813 drv_data->set_ios(slot->host, ios); 814 815 /* Slot specific timing and width adjustment */ 816 dw_mci_setup_bus(slot, false); 817 818 switch (ios->power_mode) { 819 case MMC_POWER_UP: 820 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 821 /* Power up slot */ 822 if (slot->host->pdata->setpower) 823 slot->host->pdata->setpower(slot->id, mmc->ocr_avail); 824 regs = mci_readl(slot->host, PWREN); 825 regs |= (1 << slot->id); 826 mci_writel(slot->host, PWREN, regs); 827 break; 828 case MMC_POWER_OFF: 829 /* Power down slot */ 830 if (slot->host->pdata->setpower) 831 slot->host->pdata->setpower(slot->id, 0); 832 regs = mci_readl(slot->host, PWREN); 833 regs &= ~(1 << slot->id); 834 mci_writel(slot->host, PWREN, regs); 835 break; 836 default: 837 break; 838 } 839 } 840 841 static int dw_mci_get_ro(struct mmc_host *mmc) 842 { 843 int read_only; 844 struct dw_mci_slot *slot = mmc_priv(mmc); 845 struct dw_mci_board *brd = slot->host->pdata; 846 847 /* Use platform get_ro function, else try on board write protect */ 848 if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) 849 read_only = 0; 850 else if (brd->get_ro) 851 read_only = brd->get_ro(slot->id); 852 else if (gpio_is_valid(slot->wp_gpio)) 853 read_only = gpio_get_value(slot->wp_gpio); 854 else 855 read_only = 856 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 857 858 dev_dbg(&mmc->class_dev, "card is %s\n", 859 read_only ? "read-only" : "read-write"); 860 861 return read_only; 862 } 863 864 static int dw_mci_get_cd(struct mmc_host *mmc) 865 { 866 int present; 867 struct dw_mci_slot *slot = mmc_priv(mmc); 868 struct dw_mci_board *brd = slot->host->pdata; 869 870 /* Use platform get_cd function, else try onboard card detect */ 871 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 872 present = 1; 873 else if (brd->get_cd) 874 present = !brd->get_cd(slot->id); 875 else 876 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 877 == 0 ? 1 : 0; 878 879 if (present) 880 dev_dbg(&mmc->class_dev, "card is present\n"); 881 else 882 dev_dbg(&mmc->class_dev, "card is not present\n"); 883 884 return present; 885 } 886 887 /* 888 * Disable lower power mode. 889 * 890 * Low power mode will stop the card clock when idle. According to the 891 * description of the CLKENA register we should disable low power mode 892 * for SDIO cards if we need SDIO interrupts to work. 893 * 894 * This function is fast if low power mode is already disabled. 895 */ 896 static void dw_mci_disable_low_power(struct dw_mci_slot *slot) 897 { 898 struct dw_mci *host = slot->host; 899 u32 clk_en_a; 900 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 901 902 clk_en_a = mci_readl(host, CLKENA); 903 904 if (clk_en_a & clken_low_pwr) { 905 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr); 906 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 907 SDMMC_CMD_PRV_DAT_WAIT, 0); 908 } 909 } 910 911 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 912 { 913 struct dw_mci_slot *slot = mmc_priv(mmc); 914 struct dw_mci *host = slot->host; 915 u32 int_mask; 916 917 /* Enable/disable Slot Specific SDIO interrupt */ 918 int_mask = mci_readl(host, INTMASK); 919 if (enb) { 920 /* 921 * Turn off low power mode if it was enabled. This is a bit of 922 * a heavy operation and we disable / enable IRQs a lot, so 923 * we'll leave low power mode disabled and it will get 924 * re-enabled again in dw_mci_setup_bus(). 925 */ 926 dw_mci_disable_low_power(slot); 927 928 mci_writel(host, INTMASK, 929 (int_mask | SDMMC_INT_SDIO(slot->id))); 930 } else { 931 mci_writel(host, INTMASK, 932 (int_mask & ~SDMMC_INT_SDIO(slot->id))); 933 } 934 } 935 936 static const struct mmc_host_ops dw_mci_ops = { 937 .request = dw_mci_request, 938 .pre_req = dw_mci_pre_req, 939 .post_req = dw_mci_post_req, 940 .set_ios = dw_mci_set_ios, 941 .get_ro = dw_mci_get_ro, 942 .get_cd = dw_mci_get_cd, 943 .enable_sdio_irq = dw_mci_enable_sdio_irq, 944 }; 945 946 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 947 __releases(&host->lock) 948 __acquires(&host->lock) 949 { 950 struct dw_mci_slot *slot; 951 struct mmc_host *prev_mmc = host->cur_slot->mmc; 952 953 WARN_ON(host->cmd || host->data); 954 955 host->cur_slot->mrq = NULL; 956 host->mrq = NULL; 957 if (!list_empty(&host->queue)) { 958 slot = list_entry(host->queue.next, 959 struct dw_mci_slot, queue_node); 960 list_del(&slot->queue_node); 961 dev_vdbg(host->dev, "list not empty: %s is next\n", 962 mmc_hostname(slot->mmc)); 963 host->state = STATE_SENDING_CMD; 964 dw_mci_start_request(host, slot); 965 } else { 966 dev_vdbg(host->dev, "list empty\n"); 967 host->state = STATE_IDLE; 968 } 969 970 spin_unlock(&host->lock); 971 mmc_request_done(prev_mmc, mrq); 972 spin_lock(&host->lock); 973 } 974 975 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 976 { 977 u32 status = host->cmd_status; 978 979 host->cmd_status = 0; 980 981 /* Read the response from the card (up to 16 bytes) */ 982 if (cmd->flags & MMC_RSP_PRESENT) { 983 if (cmd->flags & MMC_RSP_136) { 984 cmd->resp[3] = mci_readl(host, RESP0); 985 cmd->resp[2] = mci_readl(host, RESP1); 986 cmd->resp[1] = mci_readl(host, RESP2); 987 cmd->resp[0] = mci_readl(host, RESP3); 988 } else { 989 cmd->resp[0] = mci_readl(host, RESP0); 990 cmd->resp[1] = 0; 991 cmd->resp[2] = 0; 992 cmd->resp[3] = 0; 993 } 994 } 995 996 if (status & SDMMC_INT_RTO) 997 cmd->error = -ETIMEDOUT; 998 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 999 cmd->error = -EILSEQ; 1000 else if (status & SDMMC_INT_RESP_ERR) 1001 cmd->error = -EIO; 1002 else 1003 cmd->error = 0; 1004 1005 if (cmd->error) { 1006 /* newer ip versions need a delay between retries */ 1007 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1008 mdelay(20); 1009 1010 if (cmd->data) { 1011 dw_mci_stop_dma(host); 1012 host->data = NULL; 1013 } 1014 } 1015 } 1016 1017 static void dw_mci_tasklet_func(unsigned long priv) 1018 { 1019 struct dw_mci *host = (struct dw_mci *)priv; 1020 struct mmc_data *data; 1021 struct mmc_command *cmd; 1022 enum dw_mci_state state; 1023 enum dw_mci_state prev_state; 1024 u32 status, ctrl; 1025 1026 spin_lock(&host->lock); 1027 1028 state = host->state; 1029 data = host->data; 1030 1031 do { 1032 prev_state = state; 1033 1034 switch (state) { 1035 case STATE_IDLE: 1036 break; 1037 1038 case STATE_SENDING_CMD: 1039 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1040 &host->pending_events)) 1041 break; 1042 1043 cmd = host->cmd; 1044 host->cmd = NULL; 1045 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1046 dw_mci_command_complete(host, cmd); 1047 if (cmd == host->mrq->sbc && !cmd->error) { 1048 prev_state = state = STATE_SENDING_CMD; 1049 __dw_mci_start_request(host, host->cur_slot, 1050 host->mrq->cmd); 1051 goto unlock; 1052 } 1053 1054 if (!host->mrq->data || cmd->error) { 1055 dw_mci_request_end(host, host->mrq); 1056 goto unlock; 1057 } 1058 1059 prev_state = state = STATE_SENDING_DATA; 1060 /* fall through */ 1061 1062 case STATE_SENDING_DATA: 1063 if (test_and_clear_bit(EVENT_DATA_ERROR, 1064 &host->pending_events)) { 1065 dw_mci_stop_dma(host); 1066 if (data->stop) 1067 send_stop_cmd(host, data); 1068 state = STATE_DATA_ERROR; 1069 break; 1070 } 1071 1072 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1073 &host->pending_events)) 1074 break; 1075 1076 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 1077 prev_state = state = STATE_DATA_BUSY; 1078 /* fall through */ 1079 1080 case STATE_DATA_BUSY: 1081 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1082 &host->pending_events)) 1083 break; 1084 1085 host->data = NULL; 1086 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1087 status = host->data_status; 1088 1089 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1090 if (status & SDMMC_INT_DTO) { 1091 data->error = -ETIMEDOUT; 1092 } else if (status & SDMMC_INT_DCRC) { 1093 data->error = -EILSEQ; 1094 } else if (status & SDMMC_INT_EBE && 1095 host->dir_status == 1096 DW_MCI_SEND_STATUS) { 1097 /* 1098 * No data CRC status was returned. 1099 * The number of bytes transferred will 1100 * be exaggerated in PIO mode. 1101 */ 1102 data->bytes_xfered = 0; 1103 data->error = -ETIMEDOUT; 1104 } else { 1105 dev_err(host->dev, 1106 "data FIFO error " 1107 "(status=%08x)\n", 1108 status); 1109 data->error = -EIO; 1110 } 1111 /* 1112 * After an error, there may be data lingering 1113 * in the FIFO, so reset it - doing so 1114 * generates a block interrupt, hence setting 1115 * the scatter-gather pointer to NULL. 1116 */ 1117 sg_miter_stop(&host->sg_miter); 1118 host->sg = NULL; 1119 ctrl = mci_readl(host, CTRL); 1120 ctrl |= SDMMC_CTRL_FIFO_RESET; 1121 mci_writel(host, CTRL, ctrl); 1122 } else { 1123 data->bytes_xfered = data->blocks * data->blksz; 1124 data->error = 0; 1125 } 1126 1127 if (!data->stop) { 1128 dw_mci_request_end(host, host->mrq); 1129 goto unlock; 1130 } 1131 1132 if (host->mrq->sbc && !data->error) { 1133 data->stop->error = 0; 1134 dw_mci_request_end(host, host->mrq); 1135 goto unlock; 1136 } 1137 1138 prev_state = state = STATE_SENDING_STOP; 1139 if (!data->error) 1140 send_stop_cmd(host, data); 1141 /* fall through */ 1142 1143 case STATE_SENDING_STOP: 1144 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1145 &host->pending_events)) 1146 break; 1147 1148 host->cmd = NULL; 1149 dw_mci_command_complete(host, host->mrq->stop); 1150 dw_mci_request_end(host, host->mrq); 1151 goto unlock; 1152 1153 case STATE_DATA_ERROR: 1154 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1155 &host->pending_events)) 1156 break; 1157 1158 state = STATE_DATA_BUSY; 1159 break; 1160 } 1161 } while (state != prev_state); 1162 1163 host->state = state; 1164 unlock: 1165 spin_unlock(&host->lock); 1166 1167 } 1168 1169 /* push final bytes to part_buf, only use during push */ 1170 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 1171 { 1172 memcpy((void *)&host->part_buf, buf, cnt); 1173 host->part_buf_count = cnt; 1174 } 1175 1176 /* append bytes to part_buf, only use during push */ 1177 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 1178 { 1179 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 1180 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 1181 host->part_buf_count += cnt; 1182 return cnt; 1183 } 1184 1185 /* pull first bytes from part_buf, only use during pull */ 1186 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 1187 { 1188 cnt = min(cnt, (int)host->part_buf_count); 1189 if (cnt) { 1190 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 1191 cnt); 1192 host->part_buf_count -= cnt; 1193 host->part_buf_start += cnt; 1194 } 1195 return cnt; 1196 } 1197 1198 /* pull final bytes from the part_buf, assuming it's just been filled */ 1199 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 1200 { 1201 memcpy(buf, &host->part_buf, cnt); 1202 host->part_buf_start = cnt; 1203 host->part_buf_count = (1 << host->data_shift) - cnt; 1204 } 1205 1206 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1207 { 1208 struct mmc_data *data = host->data; 1209 int init_cnt = cnt; 1210 1211 /* try and push anything in the part_buf */ 1212 if (unlikely(host->part_buf_count)) { 1213 int len = dw_mci_push_part_bytes(host, buf, cnt); 1214 buf += len; 1215 cnt -= len; 1216 if (host->part_buf_count == 2) { 1217 mci_writew(host, DATA(host->data_offset), 1218 host->part_buf16); 1219 host->part_buf_count = 0; 1220 } 1221 } 1222 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1223 if (unlikely((unsigned long)buf & 0x1)) { 1224 while (cnt >= 2) { 1225 u16 aligned_buf[64]; 1226 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1227 int items = len >> 1; 1228 int i; 1229 /* memcpy from input buffer into aligned buffer */ 1230 memcpy(aligned_buf, buf, len); 1231 buf += len; 1232 cnt -= len; 1233 /* push data from aligned buffer into fifo */ 1234 for (i = 0; i < items; ++i) 1235 mci_writew(host, DATA(host->data_offset), 1236 aligned_buf[i]); 1237 } 1238 } else 1239 #endif 1240 { 1241 u16 *pdata = buf; 1242 for (; cnt >= 2; cnt -= 2) 1243 mci_writew(host, DATA(host->data_offset), *pdata++); 1244 buf = pdata; 1245 } 1246 /* put anything remaining in the part_buf */ 1247 if (cnt) { 1248 dw_mci_set_part_bytes(host, buf, cnt); 1249 /* Push data if we have reached the expected data length */ 1250 if ((data->bytes_xfered + init_cnt) == 1251 (data->blksz * data->blocks)) 1252 mci_writew(host, DATA(host->data_offset), 1253 host->part_buf16); 1254 } 1255 } 1256 1257 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1258 { 1259 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1260 if (unlikely((unsigned long)buf & 0x1)) { 1261 while (cnt >= 2) { 1262 /* pull data from fifo into aligned buffer */ 1263 u16 aligned_buf[64]; 1264 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1265 int items = len >> 1; 1266 int i; 1267 for (i = 0; i < items; ++i) 1268 aligned_buf[i] = mci_readw(host, 1269 DATA(host->data_offset)); 1270 /* memcpy from aligned buffer into output buffer */ 1271 memcpy(buf, aligned_buf, len); 1272 buf += len; 1273 cnt -= len; 1274 } 1275 } else 1276 #endif 1277 { 1278 u16 *pdata = buf; 1279 for (; cnt >= 2; cnt -= 2) 1280 *pdata++ = mci_readw(host, DATA(host->data_offset)); 1281 buf = pdata; 1282 } 1283 if (cnt) { 1284 host->part_buf16 = mci_readw(host, DATA(host->data_offset)); 1285 dw_mci_pull_final_bytes(host, buf, cnt); 1286 } 1287 } 1288 1289 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1290 { 1291 struct mmc_data *data = host->data; 1292 int init_cnt = cnt; 1293 1294 /* try and push anything in the part_buf */ 1295 if (unlikely(host->part_buf_count)) { 1296 int len = dw_mci_push_part_bytes(host, buf, cnt); 1297 buf += len; 1298 cnt -= len; 1299 if (host->part_buf_count == 4) { 1300 mci_writel(host, DATA(host->data_offset), 1301 host->part_buf32); 1302 host->part_buf_count = 0; 1303 } 1304 } 1305 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1306 if (unlikely((unsigned long)buf & 0x3)) { 1307 while (cnt >= 4) { 1308 u32 aligned_buf[32]; 1309 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1310 int items = len >> 2; 1311 int i; 1312 /* memcpy from input buffer into aligned buffer */ 1313 memcpy(aligned_buf, buf, len); 1314 buf += len; 1315 cnt -= len; 1316 /* push data from aligned buffer into fifo */ 1317 for (i = 0; i < items; ++i) 1318 mci_writel(host, DATA(host->data_offset), 1319 aligned_buf[i]); 1320 } 1321 } else 1322 #endif 1323 { 1324 u32 *pdata = buf; 1325 for (; cnt >= 4; cnt -= 4) 1326 mci_writel(host, DATA(host->data_offset), *pdata++); 1327 buf = pdata; 1328 } 1329 /* put anything remaining in the part_buf */ 1330 if (cnt) { 1331 dw_mci_set_part_bytes(host, buf, cnt); 1332 /* Push data if we have reached the expected data length */ 1333 if ((data->bytes_xfered + init_cnt) == 1334 (data->blksz * data->blocks)) 1335 mci_writel(host, DATA(host->data_offset), 1336 host->part_buf32); 1337 } 1338 } 1339 1340 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1341 { 1342 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1343 if (unlikely((unsigned long)buf & 0x3)) { 1344 while (cnt >= 4) { 1345 /* pull data from fifo into aligned buffer */ 1346 u32 aligned_buf[32]; 1347 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1348 int items = len >> 2; 1349 int i; 1350 for (i = 0; i < items; ++i) 1351 aligned_buf[i] = mci_readl(host, 1352 DATA(host->data_offset)); 1353 /* memcpy from aligned buffer into output buffer */ 1354 memcpy(buf, aligned_buf, len); 1355 buf += len; 1356 cnt -= len; 1357 } 1358 } else 1359 #endif 1360 { 1361 u32 *pdata = buf; 1362 for (; cnt >= 4; cnt -= 4) 1363 *pdata++ = mci_readl(host, DATA(host->data_offset)); 1364 buf = pdata; 1365 } 1366 if (cnt) { 1367 host->part_buf32 = mci_readl(host, DATA(host->data_offset)); 1368 dw_mci_pull_final_bytes(host, buf, cnt); 1369 } 1370 } 1371 1372 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1373 { 1374 struct mmc_data *data = host->data; 1375 int init_cnt = cnt; 1376 1377 /* try and push anything in the part_buf */ 1378 if (unlikely(host->part_buf_count)) { 1379 int len = dw_mci_push_part_bytes(host, buf, cnt); 1380 buf += len; 1381 cnt -= len; 1382 1383 if (host->part_buf_count == 8) { 1384 mci_writeq(host, DATA(host->data_offset), 1385 host->part_buf); 1386 host->part_buf_count = 0; 1387 } 1388 } 1389 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1390 if (unlikely((unsigned long)buf & 0x7)) { 1391 while (cnt >= 8) { 1392 u64 aligned_buf[16]; 1393 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1394 int items = len >> 3; 1395 int i; 1396 /* memcpy from input buffer into aligned buffer */ 1397 memcpy(aligned_buf, buf, len); 1398 buf += len; 1399 cnt -= len; 1400 /* push data from aligned buffer into fifo */ 1401 for (i = 0; i < items; ++i) 1402 mci_writeq(host, DATA(host->data_offset), 1403 aligned_buf[i]); 1404 } 1405 } else 1406 #endif 1407 { 1408 u64 *pdata = buf; 1409 for (; cnt >= 8; cnt -= 8) 1410 mci_writeq(host, DATA(host->data_offset), *pdata++); 1411 buf = pdata; 1412 } 1413 /* put anything remaining in the part_buf */ 1414 if (cnt) { 1415 dw_mci_set_part_bytes(host, buf, cnt); 1416 /* Push data if we have reached the expected data length */ 1417 if ((data->bytes_xfered + init_cnt) == 1418 (data->blksz * data->blocks)) 1419 mci_writeq(host, DATA(host->data_offset), 1420 host->part_buf); 1421 } 1422 } 1423 1424 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1425 { 1426 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1427 if (unlikely((unsigned long)buf & 0x7)) { 1428 while (cnt >= 8) { 1429 /* pull data from fifo into aligned buffer */ 1430 u64 aligned_buf[16]; 1431 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1432 int items = len >> 3; 1433 int i; 1434 for (i = 0; i < items; ++i) 1435 aligned_buf[i] = mci_readq(host, 1436 DATA(host->data_offset)); 1437 /* memcpy from aligned buffer into output buffer */ 1438 memcpy(buf, aligned_buf, len); 1439 buf += len; 1440 cnt -= len; 1441 } 1442 } else 1443 #endif 1444 { 1445 u64 *pdata = buf; 1446 for (; cnt >= 8; cnt -= 8) 1447 *pdata++ = mci_readq(host, DATA(host->data_offset)); 1448 buf = pdata; 1449 } 1450 if (cnt) { 1451 host->part_buf = mci_readq(host, DATA(host->data_offset)); 1452 dw_mci_pull_final_bytes(host, buf, cnt); 1453 } 1454 } 1455 1456 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 1457 { 1458 int len; 1459 1460 /* get remaining partial bytes */ 1461 len = dw_mci_pull_part_bytes(host, buf, cnt); 1462 if (unlikely(len == cnt)) 1463 return; 1464 buf += len; 1465 cnt -= len; 1466 1467 /* get the rest of the data */ 1468 host->pull_data(host, buf, cnt); 1469 } 1470 1471 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 1472 { 1473 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1474 void *buf; 1475 unsigned int offset; 1476 struct mmc_data *data = host->data; 1477 int shift = host->data_shift; 1478 u32 status; 1479 unsigned int len; 1480 unsigned int remain, fcnt; 1481 1482 do { 1483 if (!sg_miter_next(sg_miter)) 1484 goto done; 1485 1486 host->sg = sg_miter->piter.sg; 1487 buf = sg_miter->addr; 1488 remain = sg_miter->length; 1489 offset = 0; 1490 1491 do { 1492 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 1493 << shift) + host->part_buf_count; 1494 len = min(remain, fcnt); 1495 if (!len) 1496 break; 1497 dw_mci_pull_data(host, (void *)(buf + offset), len); 1498 data->bytes_xfered += len; 1499 offset += len; 1500 remain -= len; 1501 } while (remain); 1502 1503 sg_miter->consumed = offset; 1504 status = mci_readl(host, MINTSTS); 1505 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1506 /* if the RXDR is ready read again */ 1507 } while ((status & SDMMC_INT_RXDR) || 1508 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 1509 1510 if (!remain) { 1511 if (!sg_miter_next(sg_miter)) 1512 goto done; 1513 sg_miter->consumed = 0; 1514 } 1515 sg_miter_stop(sg_miter); 1516 return; 1517 1518 done: 1519 sg_miter_stop(sg_miter); 1520 host->sg = NULL; 1521 smp_wmb(); 1522 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1523 } 1524 1525 static void dw_mci_write_data_pio(struct dw_mci *host) 1526 { 1527 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1528 void *buf; 1529 unsigned int offset; 1530 struct mmc_data *data = host->data; 1531 int shift = host->data_shift; 1532 u32 status; 1533 unsigned int len; 1534 unsigned int fifo_depth = host->fifo_depth; 1535 unsigned int remain, fcnt; 1536 1537 do { 1538 if (!sg_miter_next(sg_miter)) 1539 goto done; 1540 1541 host->sg = sg_miter->piter.sg; 1542 buf = sg_miter->addr; 1543 remain = sg_miter->length; 1544 offset = 0; 1545 1546 do { 1547 fcnt = ((fifo_depth - 1548 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 1549 << shift) - host->part_buf_count; 1550 len = min(remain, fcnt); 1551 if (!len) 1552 break; 1553 host->push_data(host, (void *)(buf + offset), len); 1554 data->bytes_xfered += len; 1555 offset += len; 1556 remain -= len; 1557 } while (remain); 1558 1559 sg_miter->consumed = offset; 1560 status = mci_readl(host, MINTSTS); 1561 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1562 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 1563 1564 if (!remain) { 1565 if (!sg_miter_next(sg_miter)) 1566 goto done; 1567 sg_miter->consumed = 0; 1568 } 1569 sg_miter_stop(sg_miter); 1570 return; 1571 1572 done: 1573 sg_miter_stop(sg_miter); 1574 host->sg = NULL; 1575 smp_wmb(); 1576 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1577 } 1578 1579 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 1580 { 1581 if (!host->cmd_status) 1582 host->cmd_status = status; 1583 1584 smp_wmb(); 1585 1586 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1587 tasklet_schedule(&host->tasklet); 1588 } 1589 1590 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 1591 { 1592 struct dw_mci *host = dev_id; 1593 u32 pending; 1594 int i; 1595 1596 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 1597 1598 if (pending) { 1599 1600 /* 1601 * DTO fix - version 2.10a and below, and only if internal DMA 1602 * is configured. 1603 */ 1604 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 1605 if (!pending && 1606 ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 1607 pending |= SDMMC_INT_DATA_OVER; 1608 } 1609 1610 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 1611 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 1612 host->cmd_status = pending; 1613 smp_wmb(); 1614 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1615 } 1616 1617 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 1618 /* if there is an error report DATA_ERROR */ 1619 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 1620 host->data_status = pending; 1621 smp_wmb(); 1622 set_bit(EVENT_DATA_ERROR, &host->pending_events); 1623 tasklet_schedule(&host->tasklet); 1624 } 1625 1626 if (pending & SDMMC_INT_DATA_OVER) { 1627 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 1628 if (!host->data_status) 1629 host->data_status = pending; 1630 smp_wmb(); 1631 if (host->dir_status == DW_MCI_RECV_STATUS) { 1632 if (host->sg != NULL) 1633 dw_mci_read_data_pio(host, true); 1634 } 1635 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1636 tasklet_schedule(&host->tasklet); 1637 } 1638 1639 if (pending & SDMMC_INT_RXDR) { 1640 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1641 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 1642 dw_mci_read_data_pio(host, false); 1643 } 1644 1645 if (pending & SDMMC_INT_TXDR) { 1646 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1647 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 1648 dw_mci_write_data_pio(host); 1649 } 1650 1651 if (pending & SDMMC_INT_CMD_DONE) { 1652 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 1653 dw_mci_cmd_interrupt(host, pending); 1654 } 1655 1656 if (pending & SDMMC_INT_CD) { 1657 mci_writel(host, RINTSTS, SDMMC_INT_CD); 1658 queue_work(host->card_workqueue, &host->card_work); 1659 } 1660 1661 /* Handle SDIO Interrupts */ 1662 for (i = 0; i < host->num_slots; i++) { 1663 struct dw_mci_slot *slot = host->slot[i]; 1664 if (pending & SDMMC_INT_SDIO(i)) { 1665 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i)); 1666 mmc_signal_sdio_irq(slot->mmc); 1667 } 1668 } 1669 1670 } 1671 1672 #ifdef CONFIG_MMC_DW_IDMAC 1673 /* Handle DMA interrupts */ 1674 pending = mci_readl(host, IDSTS); 1675 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 1676 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI); 1677 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 1678 host->dma_ops->complete(host); 1679 } 1680 #endif 1681 1682 return IRQ_HANDLED; 1683 } 1684 1685 static void dw_mci_work_routine_card(struct work_struct *work) 1686 { 1687 struct dw_mci *host = container_of(work, struct dw_mci, card_work); 1688 int i; 1689 1690 for (i = 0; i < host->num_slots; i++) { 1691 struct dw_mci_slot *slot = host->slot[i]; 1692 struct mmc_host *mmc = slot->mmc; 1693 struct mmc_request *mrq; 1694 int present; 1695 u32 ctrl; 1696 1697 present = dw_mci_get_cd(mmc); 1698 while (present != slot->last_detect_state) { 1699 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1700 present ? "inserted" : "removed"); 1701 1702 spin_lock_bh(&host->lock); 1703 1704 /* Card change detected */ 1705 slot->last_detect_state = present; 1706 1707 /* Mark card as present if applicable */ 1708 if (present != 0) 1709 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1710 1711 /* Clean up queue if present */ 1712 mrq = slot->mrq; 1713 if (mrq) { 1714 if (mrq == host->mrq) { 1715 host->data = NULL; 1716 host->cmd = NULL; 1717 1718 switch (host->state) { 1719 case STATE_IDLE: 1720 break; 1721 case STATE_SENDING_CMD: 1722 mrq->cmd->error = -ENOMEDIUM; 1723 if (!mrq->data) 1724 break; 1725 /* fall through */ 1726 case STATE_SENDING_DATA: 1727 mrq->data->error = -ENOMEDIUM; 1728 dw_mci_stop_dma(host); 1729 break; 1730 case STATE_DATA_BUSY: 1731 case STATE_DATA_ERROR: 1732 if (mrq->data->error == -EINPROGRESS) 1733 mrq->data->error = -ENOMEDIUM; 1734 if (!mrq->stop) 1735 break; 1736 /* fall through */ 1737 case STATE_SENDING_STOP: 1738 mrq->stop->error = -ENOMEDIUM; 1739 break; 1740 } 1741 1742 dw_mci_request_end(host, mrq); 1743 } else { 1744 list_del(&slot->queue_node); 1745 mrq->cmd->error = -ENOMEDIUM; 1746 if (mrq->data) 1747 mrq->data->error = -ENOMEDIUM; 1748 if (mrq->stop) 1749 mrq->stop->error = -ENOMEDIUM; 1750 1751 spin_unlock(&host->lock); 1752 mmc_request_done(slot->mmc, mrq); 1753 spin_lock(&host->lock); 1754 } 1755 } 1756 1757 /* Power down slot */ 1758 if (present == 0) { 1759 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1760 1761 /* 1762 * Clear down the FIFO - doing so generates a 1763 * block interrupt, hence setting the 1764 * scatter-gather pointer to NULL. 1765 */ 1766 sg_miter_stop(&host->sg_miter); 1767 host->sg = NULL; 1768 1769 ctrl = mci_readl(host, CTRL); 1770 ctrl |= SDMMC_CTRL_FIFO_RESET; 1771 mci_writel(host, CTRL, ctrl); 1772 1773 #ifdef CONFIG_MMC_DW_IDMAC 1774 ctrl = mci_readl(host, BMOD); 1775 /* Software reset of DMA */ 1776 ctrl |= SDMMC_IDMAC_SWRESET; 1777 mci_writel(host, BMOD, ctrl); 1778 #endif 1779 1780 } 1781 1782 spin_unlock_bh(&host->lock); 1783 1784 present = dw_mci_get_cd(mmc); 1785 } 1786 1787 mmc_detect_change(slot->mmc, 1788 msecs_to_jiffies(host->pdata->detect_delay_ms)); 1789 } 1790 } 1791 1792 #ifdef CONFIG_OF 1793 /* given a slot id, find out the device node representing that slot */ 1794 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 1795 { 1796 struct device_node *np; 1797 const __be32 *addr; 1798 int len; 1799 1800 if (!dev || !dev->of_node) 1801 return NULL; 1802 1803 for_each_child_of_node(dev->of_node, np) { 1804 addr = of_get_property(np, "reg", &len); 1805 if (!addr || (len < sizeof(int))) 1806 continue; 1807 if (be32_to_cpup(addr) == slot) 1808 return np; 1809 } 1810 return NULL; 1811 } 1812 1813 static struct dw_mci_of_slot_quirks { 1814 char *quirk; 1815 int id; 1816 } of_slot_quirks[] = { 1817 { 1818 .quirk = "disable-wp", 1819 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, 1820 }, 1821 }; 1822 1823 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 1824 { 1825 struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 1826 int quirks = 0; 1827 int idx; 1828 1829 /* get quirks */ 1830 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) 1831 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) 1832 quirks |= of_slot_quirks[idx].id; 1833 1834 return quirks; 1835 } 1836 1837 /* find out bus-width for a given slot */ 1838 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) 1839 { 1840 struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 1841 u32 bus_wd = 1; 1842 1843 if (!np) 1844 return 1; 1845 1846 if (of_property_read_u32(np, "bus-width", &bus_wd)) 1847 dev_err(dev, "bus-width property not found, assuming width" 1848 " as 1\n"); 1849 return bus_wd; 1850 } 1851 1852 /* find the write protect gpio for a given slot; or -1 if none specified */ 1853 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) 1854 { 1855 struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 1856 int gpio; 1857 1858 if (!np) 1859 return -EINVAL; 1860 1861 gpio = of_get_named_gpio(np, "wp-gpios", 0); 1862 1863 /* Having a missing entry is valid; return silently */ 1864 if (!gpio_is_valid(gpio)) 1865 return -EINVAL; 1866 1867 if (devm_gpio_request(dev, gpio, "dw-mci-wp")) { 1868 dev_warn(dev, "gpio [%d] request failed\n", gpio); 1869 return -EINVAL; 1870 } 1871 1872 return gpio; 1873 } 1874 #else /* CONFIG_OF */ 1875 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) 1876 { 1877 return 0; 1878 } 1879 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) 1880 { 1881 return 1; 1882 } 1883 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 1884 { 1885 return NULL; 1886 } 1887 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot) 1888 { 1889 return -EINVAL; 1890 } 1891 #endif /* CONFIG_OF */ 1892 1893 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 1894 { 1895 struct mmc_host *mmc; 1896 struct dw_mci_slot *slot; 1897 const struct dw_mci_drv_data *drv_data = host->drv_data; 1898 int ctrl_id, ret; 1899 u8 bus_width; 1900 1901 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 1902 if (!mmc) 1903 return -ENOMEM; 1904 1905 slot = mmc_priv(mmc); 1906 slot->id = id; 1907 slot->mmc = mmc; 1908 slot->host = host; 1909 host->slot[id] = slot; 1910 1911 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 1912 1913 mmc->ops = &dw_mci_ops; 1914 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); 1915 mmc->f_max = host->bus_hz; 1916 1917 if (host->pdata->get_ocr) 1918 mmc->ocr_avail = host->pdata->get_ocr(id); 1919 else 1920 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1921 1922 /* 1923 * Start with slot power disabled, it will be enabled when a card 1924 * is detected. 1925 */ 1926 if (host->pdata->setpower) 1927 host->pdata->setpower(id, 0); 1928 1929 if (host->pdata->caps) 1930 mmc->caps = host->pdata->caps; 1931 1932 if (host->pdata->pm_caps) 1933 mmc->pm_caps = host->pdata->pm_caps; 1934 1935 if (host->dev->of_node) { 1936 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 1937 if (ctrl_id < 0) 1938 ctrl_id = 0; 1939 } else { 1940 ctrl_id = to_platform_device(host->dev)->id; 1941 } 1942 if (drv_data && drv_data->caps) 1943 mmc->caps |= drv_data->caps[ctrl_id]; 1944 1945 if (host->pdata->caps2) 1946 mmc->caps2 = host->pdata->caps2; 1947 1948 if (host->pdata->get_bus_wd) 1949 bus_width = host->pdata->get_bus_wd(slot->id); 1950 else if (host->dev->of_node) 1951 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id); 1952 else 1953 bus_width = 1; 1954 1955 switch (bus_width) { 1956 case 8: 1957 mmc->caps |= MMC_CAP_8_BIT_DATA; 1958 case 4: 1959 mmc->caps |= MMC_CAP_4_BIT_DATA; 1960 } 1961 1962 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) 1963 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 1964 1965 if (host->pdata->blk_settings) { 1966 mmc->max_segs = host->pdata->blk_settings->max_segs; 1967 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 1968 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 1969 mmc->max_req_size = host->pdata->blk_settings->max_req_size; 1970 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 1971 } else { 1972 /* Useful defaults if platform data is unset. */ 1973 #ifdef CONFIG_MMC_DW_IDMAC 1974 mmc->max_segs = host->ring_size; 1975 mmc->max_blk_size = 65536; 1976 mmc->max_blk_count = host->ring_size; 1977 mmc->max_seg_size = 0x1000; 1978 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; 1979 #else 1980 mmc->max_segs = 64; 1981 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 1982 mmc->max_blk_count = 512; 1983 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1984 mmc->max_seg_size = mmc->max_req_size; 1985 #endif /* CONFIG_MMC_DW_IDMAC */ 1986 } 1987 1988 host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc"); 1989 if (IS_ERR(host->vmmc)) { 1990 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc)); 1991 host->vmmc = NULL; 1992 } else { 1993 ret = regulator_enable(host->vmmc); 1994 if (ret) { 1995 dev_err(host->dev, 1996 "failed to enable regulator: %d\n", ret); 1997 goto err_setup_bus; 1998 } 1999 } 2000 2001 if (dw_mci_get_cd(mmc)) 2002 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2003 else 2004 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2005 2006 slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id); 2007 2008 ret = mmc_add_host(mmc); 2009 if (ret) 2010 goto err_setup_bus; 2011 2012 #if defined(CONFIG_DEBUG_FS) 2013 dw_mci_init_debugfs(slot); 2014 #endif 2015 2016 /* Card initially undetected */ 2017 slot->last_detect_state = 0; 2018 2019 /* 2020 * Card may have been plugged in prior to boot so we 2021 * need to run the detect tasklet 2022 */ 2023 queue_work(host->card_workqueue, &host->card_work); 2024 2025 return 0; 2026 2027 err_setup_bus: 2028 mmc_free_host(mmc); 2029 return -EINVAL; 2030 } 2031 2032 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2033 { 2034 /* Shutdown detect IRQ */ 2035 if (slot->host->pdata->exit) 2036 slot->host->pdata->exit(id); 2037 2038 /* Debugfs stuff is cleaned up by mmc core */ 2039 mmc_remove_host(slot->mmc); 2040 slot->host->slot[id] = NULL; 2041 mmc_free_host(slot->mmc); 2042 } 2043 2044 static void dw_mci_init_dma(struct dw_mci *host) 2045 { 2046 /* Alloc memory for sg translation */ 2047 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2048 &host->sg_dma, GFP_KERNEL); 2049 if (!host->sg_cpu) { 2050 dev_err(host->dev, "%s: could not alloc DMA memory\n", 2051 __func__); 2052 goto no_dma; 2053 } 2054 2055 /* Determine which DMA interface to use */ 2056 #ifdef CONFIG_MMC_DW_IDMAC 2057 host->dma_ops = &dw_mci_idmac_ops; 2058 dev_info(host->dev, "Using internal DMA controller.\n"); 2059 #endif 2060 2061 if (!host->dma_ops) 2062 goto no_dma; 2063 2064 if (host->dma_ops->init && host->dma_ops->start && 2065 host->dma_ops->stop && host->dma_ops->cleanup) { 2066 if (host->dma_ops->init(host)) { 2067 dev_err(host->dev, "%s: Unable to initialize " 2068 "DMA Controller.\n", __func__); 2069 goto no_dma; 2070 } 2071 } else { 2072 dev_err(host->dev, "DMA initialization not found.\n"); 2073 goto no_dma; 2074 } 2075 2076 host->use_dma = 1; 2077 return; 2078 2079 no_dma: 2080 dev_info(host->dev, "Using PIO mode.\n"); 2081 host->use_dma = 0; 2082 return; 2083 } 2084 2085 static bool mci_wait_reset(struct device *dev, struct dw_mci *host) 2086 { 2087 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2088 unsigned int ctrl; 2089 2090 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 2091 SDMMC_CTRL_DMA_RESET)); 2092 2093 /* wait till resets clear */ 2094 do { 2095 ctrl = mci_readl(host, CTRL); 2096 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 2097 SDMMC_CTRL_DMA_RESET))) 2098 return true; 2099 } while (time_before(jiffies, timeout)); 2100 2101 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl); 2102 2103 return false; 2104 } 2105 2106 #ifdef CONFIG_OF 2107 static struct dw_mci_of_quirks { 2108 char *quirk; 2109 int id; 2110 } of_quirks[] = { 2111 { 2112 .quirk = "supports-highspeed", 2113 .id = DW_MCI_QUIRK_HIGHSPEED, 2114 }, { 2115 .quirk = "broken-cd", 2116 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 2117 }, 2118 }; 2119 2120 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2121 { 2122 struct dw_mci_board *pdata; 2123 struct device *dev = host->dev; 2124 struct device_node *np = dev->of_node; 2125 const struct dw_mci_drv_data *drv_data = host->drv_data; 2126 int idx, ret; 2127 2128 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2129 if (!pdata) { 2130 dev_err(dev, "could not allocate memory for pdata\n"); 2131 return ERR_PTR(-ENOMEM); 2132 } 2133 2134 /* find out number of slots supported */ 2135 if (of_property_read_u32(dev->of_node, "num-slots", 2136 &pdata->num_slots)) { 2137 dev_info(dev, "num-slots property not found, " 2138 "assuming 1 slot is available\n"); 2139 pdata->num_slots = 1; 2140 } 2141 2142 /* get quirks */ 2143 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2144 if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2145 pdata->quirks |= of_quirks[idx].id; 2146 2147 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2148 dev_info(dev, "fifo-depth property not found, using " 2149 "value of FIFOTH register as default\n"); 2150 2151 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2152 2153 if (drv_data && drv_data->parse_dt) { 2154 ret = drv_data->parse_dt(host); 2155 if (ret) 2156 return ERR_PTR(ret); 2157 } 2158 2159 if (of_find_property(np, "keep-power-in-suspend", NULL)) 2160 pdata->pm_caps |= MMC_PM_KEEP_POWER; 2161 2162 if (of_find_property(np, "enable-sdio-wakeup", NULL)) 2163 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2164 2165 return pdata; 2166 } 2167 2168 #else /* CONFIG_OF */ 2169 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2170 { 2171 return ERR_PTR(-EINVAL); 2172 } 2173 #endif /* CONFIG_OF */ 2174 2175 int dw_mci_probe(struct dw_mci *host) 2176 { 2177 const struct dw_mci_drv_data *drv_data = host->drv_data; 2178 int width, i, ret = 0; 2179 u32 fifo_size; 2180 int init_slots = 0; 2181 2182 if (!host->pdata) { 2183 host->pdata = dw_mci_parse_dt(host); 2184 if (IS_ERR(host->pdata)) { 2185 dev_err(host->dev, "platform data not available\n"); 2186 return -EINVAL; 2187 } 2188 } 2189 2190 if (!host->pdata->select_slot && host->pdata->num_slots > 1) { 2191 dev_err(host->dev, 2192 "Platform data must supply select_slot function\n"); 2193 return -ENODEV; 2194 } 2195 2196 host->biu_clk = devm_clk_get(host->dev, "biu"); 2197 if (IS_ERR(host->biu_clk)) { 2198 dev_dbg(host->dev, "biu clock not available\n"); 2199 } else { 2200 ret = clk_prepare_enable(host->biu_clk); 2201 if (ret) { 2202 dev_err(host->dev, "failed to enable biu clock\n"); 2203 return ret; 2204 } 2205 } 2206 2207 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2208 if (IS_ERR(host->ciu_clk)) { 2209 dev_dbg(host->dev, "ciu clock not available\n"); 2210 } else { 2211 ret = clk_prepare_enable(host->ciu_clk); 2212 if (ret) { 2213 dev_err(host->dev, "failed to enable ciu clock\n"); 2214 goto err_clk_biu; 2215 } 2216 } 2217 2218 if (IS_ERR(host->ciu_clk)) 2219 host->bus_hz = host->pdata->bus_hz; 2220 else 2221 host->bus_hz = clk_get_rate(host->ciu_clk); 2222 2223 if (drv_data && drv_data->setup_clock) { 2224 ret = drv_data->setup_clock(host); 2225 if (ret) { 2226 dev_err(host->dev, 2227 "implementation specific clock setup failed\n"); 2228 goto err_clk_ciu; 2229 } 2230 } 2231 2232 if (!host->bus_hz) { 2233 dev_err(host->dev, 2234 "Platform data must supply bus speed\n"); 2235 ret = -ENODEV; 2236 goto err_clk_ciu; 2237 } 2238 2239 host->quirks = host->pdata->quirks; 2240 2241 spin_lock_init(&host->lock); 2242 INIT_LIST_HEAD(&host->queue); 2243 2244 /* 2245 * Get the host data width - this assumes that HCON has been set with 2246 * the correct values. 2247 */ 2248 i = (mci_readl(host, HCON) >> 7) & 0x7; 2249 if (!i) { 2250 host->push_data = dw_mci_push_data16; 2251 host->pull_data = dw_mci_pull_data16; 2252 width = 16; 2253 host->data_shift = 1; 2254 } else if (i == 2) { 2255 host->push_data = dw_mci_push_data64; 2256 host->pull_data = dw_mci_pull_data64; 2257 width = 64; 2258 host->data_shift = 3; 2259 } else { 2260 /* Check for a reserved value, and warn if it is */ 2261 WARN((i != 1), 2262 "HCON reports a reserved host data width!\n" 2263 "Defaulting to 32-bit access.\n"); 2264 host->push_data = dw_mci_push_data32; 2265 host->pull_data = dw_mci_pull_data32; 2266 width = 32; 2267 host->data_shift = 2; 2268 } 2269 2270 /* Reset all blocks */ 2271 if (!mci_wait_reset(host->dev, host)) 2272 return -ENODEV; 2273 2274 host->dma_ops = host->pdata->dma_ops; 2275 dw_mci_init_dma(host); 2276 2277 /* Clear the interrupts for the host controller */ 2278 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2279 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2280 2281 /* Put in max timeout */ 2282 mci_writel(host, TMOUT, 0xFFFFFFFF); 2283 2284 /* 2285 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2286 * Tx Mark = fifo_size / 2 DMA Size = 8 2287 */ 2288 if (!host->pdata->fifo_depth) { 2289 /* 2290 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2291 * have been overwritten by the bootloader, just like we're 2292 * about to do, so if you know the value for your hardware, you 2293 * should put it in the platform data. 2294 */ 2295 fifo_size = mci_readl(host, FIFOTH); 2296 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2297 } else { 2298 fifo_size = host->pdata->fifo_depth; 2299 } 2300 host->fifo_depth = fifo_size; 2301 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | 2302 ((fifo_size/2) << 0)); 2303 mci_writel(host, FIFOTH, host->fifoth_val); 2304 2305 /* disable clock to CIU */ 2306 mci_writel(host, CLKENA, 0); 2307 mci_writel(host, CLKSRC, 0); 2308 2309 /* 2310 * In 2.40a spec, Data offset is changed. 2311 * Need to check the version-id and set data-offset for DATA register. 2312 */ 2313 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 2314 dev_info(host->dev, "Version ID is %04x\n", host->verid); 2315 2316 if (host->verid < DW_MMC_240A) 2317 host->data_offset = DATA_OFFSET; 2318 else 2319 host->data_offset = DATA_240A_OFFSET; 2320 2321 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2322 host->card_workqueue = alloc_workqueue("dw-mci-card", 2323 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1); 2324 if (!host->card_workqueue) 2325 goto err_dmaunmap; 2326 INIT_WORK(&host->card_work, dw_mci_work_routine_card); 2327 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2328 host->irq_flags, "dw-mci", host); 2329 if (ret) 2330 goto err_workqueue; 2331 2332 if (host->pdata->num_slots) 2333 host->num_slots = host->pdata->num_slots; 2334 else 2335 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2336 2337 /* 2338 * Enable interrupts for command done, data over, data empty, card det, 2339 * receive ready and error such as transmit, receive timeout, crc error 2340 */ 2341 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2342 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2343 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2344 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2345 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 2346 2347 dev_info(host->dev, "DW MMC controller at irq %d, " 2348 "%d bit host data width, " 2349 "%u deep fifo\n", 2350 host->irq, width, fifo_size); 2351 2352 /* We need at least one slot to succeed */ 2353 for (i = 0; i < host->num_slots; i++) { 2354 ret = dw_mci_init_slot(host, i); 2355 if (ret) 2356 dev_dbg(host->dev, "slot %d init failed\n", i); 2357 else 2358 init_slots++; 2359 } 2360 2361 if (init_slots) { 2362 dev_info(host->dev, "%d slots initialized\n", init_slots); 2363 } else { 2364 dev_dbg(host->dev, "attempted to initialize %d slots, " 2365 "but failed on all\n", host->num_slots); 2366 goto err_workqueue; 2367 } 2368 2369 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 2370 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2371 2372 return 0; 2373 2374 err_workqueue: 2375 destroy_workqueue(host->card_workqueue); 2376 2377 err_dmaunmap: 2378 if (host->use_dma && host->dma_ops->exit) 2379 host->dma_ops->exit(host); 2380 2381 if (host->vmmc) 2382 regulator_disable(host->vmmc); 2383 2384 err_clk_ciu: 2385 if (!IS_ERR(host->ciu_clk)) 2386 clk_disable_unprepare(host->ciu_clk); 2387 2388 err_clk_biu: 2389 if (!IS_ERR(host->biu_clk)) 2390 clk_disable_unprepare(host->biu_clk); 2391 2392 return ret; 2393 } 2394 EXPORT_SYMBOL(dw_mci_probe); 2395 2396 void dw_mci_remove(struct dw_mci *host) 2397 { 2398 int i; 2399 2400 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2401 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2402 2403 for (i = 0; i < host->num_slots; i++) { 2404 dev_dbg(host->dev, "remove slot %d\n", i); 2405 if (host->slot[i]) 2406 dw_mci_cleanup_slot(host->slot[i], i); 2407 } 2408 2409 /* disable clock to CIU */ 2410 mci_writel(host, CLKENA, 0); 2411 mci_writel(host, CLKSRC, 0); 2412 2413 destroy_workqueue(host->card_workqueue); 2414 2415 if (host->use_dma && host->dma_ops->exit) 2416 host->dma_ops->exit(host); 2417 2418 if (host->vmmc) 2419 regulator_disable(host->vmmc); 2420 2421 if (!IS_ERR(host->ciu_clk)) 2422 clk_disable_unprepare(host->ciu_clk); 2423 2424 if (!IS_ERR(host->biu_clk)) 2425 clk_disable_unprepare(host->biu_clk); 2426 } 2427 EXPORT_SYMBOL(dw_mci_remove); 2428 2429 2430 2431 #ifdef CONFIG_PM_SLEEP 2432 /* 2433 * TODO: we should probably disable the clock to the card in the suspend path. 2434 */ 2435 int dw_mci_suspend(struct dw_mci *host) 2436 { 2437 int i, ret = 0; 2438 2439 for (i = 0; i < host->num_slots; i++) { 2440 struct dw_mci_slot *slot = host->slot[i]; 2441 if (!slot) 2442 continue; 2443 ret = mmc_suspend_host(slot->mmc); 2444 if (ret < 0) { 2445 while (--i >= 0) { 2446 slot = host->slot[i]; 2447 if (slot) 2448 mmc_resume_host(host->slot[i]->mmc); 2449 } 2450 return ret; 2451 } 2452 } 2453 2454 if (host->vmmc) 2455 regulator_disable(host->vmmc); 2456 2457 return 0; 2458 } 2459 EXPORT_SYMBOL(dw_mci_suspend); 2460 2461 int dw_mci_resume(struct dw_mci *host) 2462 { 2463 int i, ret; 2464 2465 if (host->vmmc) { 2466 ret = regulator_enable(host->vmmc); 2467 if (ret) { 2468 dev_err(host->dev, 2469 "failed to enable regulator: %d\n", ret); 2470 return ret; 2471 } 2472 } 2473 2474 if (!mci_wait_reset(host->dev, host)) { 2475 ret = -ENODEV; 2476 return ret; 2477 } 2478 2479 if (host->use_dma && host->dma_ops->init) 2480 host->dma_ops->init(host); 2481 2482 /* Restore the old value at FIFOTH register */ 2483 mci_writel(host, FIFOTH, host->fifoth_val); 2484 2485 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2486 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2487 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2488 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2489 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2490 2491 for (i = 0; i < host->num_slots; i++) { 2492 struct dw_mci_slot *slot = host->slot[i]; 2493 if (!slot) 2494 continue; 2495 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 2496 dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 2497 dw_mci_setup_bus(slot, true); 2498 } 2499 2500 ret = mmc_resume_host(host->slot[i]->mmc); 2501 if (ret < 0) 2502 return ret; 2503 } 2504 return 0; 2505 } 2506 EXPORT_SYMBOL(dw_mci_resume); 2507 #endif /* CONFIG_PM_SLEEP */ 2508 2509 static int __init dw_mci_init(void) 2510 { 2511 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 2512 return 0; 2513 } 2514 2515 static void __exit dw_mci_exit(void) 2516 { 2517 } 2518 2519 module_init(dw_mci_init); 2520 module_exit(dw_mci_exit); 2521 2522 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 2523 MODULE_AUTHOR("NXP Semiconductor VietNam"); 2524 MODULE_AUTHOR("Imagination Technologies Ltd"); 2525 MODULE_LICENSE("GPL v2"); 2526