1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare Multimedia Card Interface driver 4 * (Based on NXP driver for lpc 31xx) 5 * 6 * Copyright (C) 2009 NXP Semiconductors 7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8 */ 9 10 #include <linux/blkdev.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/device.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/iopoll.h> 19 #include <linux/ioport.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 #include <linux/stat.h> 26 #include <linux/delay.h> 27 #include <linux/irq.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/bitops.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/of.h> 36 #include <linux/of_gpio.h> 37 #include <linux/mmc/slot-gpio.h> 38 39 #include "dw_mmc.h" 40 41 /* Common flag combinations */ 42 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 43 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 44 SDMMC_INT_EBE | SDMMC_INT_HLE) 45 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 46 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 47 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 48 DW_MCI_CMD_ERROR_FLAGS) 49 #define DW_MCI_SEND_STATUS 1 50 #define DW_MCI_RECV_STATUS 2 51 #define DW_MCI_DMA_THRESHOLD 16 52 53 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 54 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 55 56 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 57 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 58 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 59 SDMMC_IDMAC_INT_TI) 60 61 #define DESC_RING_BUF_SZ PAGE_SIZE 62 63 struct idmac_desc_64addr { 64 u32 des0; /* Control Descriptor */ 65 #define IDMAC_OWN_CLR64(x) \ 66 !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 67 68 u32 des1; /* Reserved */ 69 70 u32 des2; /*Buffer sizes */ 71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 74 75 u32 des3; /* Reserved */ 76 77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 79 80 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 81 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 82 }; 83 84 struct idmac_desc { 85 __le32 des0; /* Control Descriptor */ 86 #define IDMAC_DES0_DIC BIT(1) 87 #define IDMAC_DES0_LD BIT(2) 88 #define IDMAC_DES0_FD BIT(3) 89 #define IDMAC_DES0_CH BIT(4) 90 #define IDMAC_DES0_ER BIT(5) 91 #define IDMAC_DES0_CES BIT(30) 92 #define IDMAC_DES0_OWN BIT(31) 93 94 __le32 des1; /* Buffer sizes */ 95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 96 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 97 98 __le32 des2; /* buffer 1 physical address */ 99 100 __le32 des3; /* buffer 2 physical address */ 101 }; 102 103 /* Each descriptor can transfer up to 4KB of data in chained mode */ 104 #define DW_MCI_DESC_DATA_LENGTH 0x1000 105 106 #if defined(CONFIG_DEBUG_FS) 107 static int dw_mci_req_show(struct seq_file *s, void *v) 108 { 109 struct dw_mci_slot *slot = s->private; 110 struct mmc_request *mrq; 111 struct mmc_command *cmd; 112 struct mmc_command *stop; 113 struct mmc_data *data; 114 115 /* Make sure we get a consistent snapshot */ 116 spin_lock_bh(&slot->host->lock); 117 mrq = slot->mrq; 118 119 if (mrq) { 120 cmd = mrq->cmd; 121 data = mrq->data; 122 stop = mrq->stop; 123 124 if (cmd) 125 seq_printf(s, 126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 127 cmd->opcode, cmd->arg, cmd->flags, 128 cmd->resp[0], cmd->resp[1], cmd->resp[2], 129 cmd->resp[2], cmd->error); 130 if (data) 131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 132 data->bytes_xfered, data->blocks, 133 data->blksz, data->flags, data->error); 134 if (stop) 135 seq_printf(s, 136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 137 stop->opcode, stop->arg, stop->flags, 138 stop->resp[0], stop->resp[1], stop->resp[2], 139 stop->resp[2], stop->error); 140 } 141 142 spin_unlock_bh(&slot->host->lock); 143 144 return 0; 145 } 146 DEFINE_SHOW_ATTRIBUTE(dw_mci_req); 147 148 static int dw_mci_regs_show(struct seq_file *s, void *v) 149 { 150 struct dw_mci *host = s->private; 151 152 pm_runtime_get_sync(host->dev); 153 154 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 155 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 156 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 157 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 158 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 159 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 160 161 pm_runtime_put_autosuspend(host->dev); 162 163 return 0; 164 } 165 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs); 166 167 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 168 { 169 struct mmc_host *mmc = slot->mmc; 170 struct dw_mci *host = slot->host; 171 struct dentry *root; 172 173 root = mmc->debugfs_root; 174 if (!root) 175 return; 176 177 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops); 178 debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops); 179 debugfs_create_u32("state", S_IRUSR, root, &host->state); 180 debugfs_create_xul("pending_events", S_IRUSR, root, 181 &host->pending_events); 182 debugfs_create_xul("completed_events", S_IRUSR, root, 183 &host->completed_events); 184 } 185 #endif /* defined(CONFIG_DEBUG_FS) */ 186 187 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 188 { 189 u32 ctrl; 190 191 ctrl = mci_readl(host, CTRL); 192 ctrl |= reset; 193 mci_writel(host, CTRL, ctrl); 194 195 /* wait till resets clear */ 196 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 197 !(ctrl & reset), 198 1, 500 * USEC_PER_MSEC)) { 199 dev_err(host->dev, 200 "Timeout resetting block (ctrl reset %#x)\n", 201 ctrl & reset); 202 return false; 203 } 204 205 return true; 206 } 207 208 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 209 { 210 u32 status; 211 212 /* 213 * Databook says that before issuing a new data transfer command 214 * we need to check to see if the card is busy. Data transfer commands 215 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 216 * 217 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 218 * expected. 219 */ 220 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 221 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 222 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 223 status, 224 !(status & SDMMC_STATUS_BUSY), 225 10, 500 * USEC_PER_MSEC)) 226 dev_err(host->dev, "Busy; trying anyway\n"); 227 } 228 } 229 230 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 231 { 232 struct dw_mci *host = slot->host; 233 unsigned int cmd_status = 0; 234 235 mci_writel(host, CMDARG, arg); 236 wmb(); /* drain writebuffer */ 237 dw_mci_wait_while_busy(host, cmd); 238 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 239 240 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 241 !(cmd_status & SDMMC_CMD_START), 242 1, 500 * USEC_PER_MSEC)) 243 dev_err(&slot->mmc->class_dev, 244 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 245 cmd, arg, cmd_status); 246 } 247 248 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 249 { 250 struct dw_mci_slot *slot = mmc_priv(mmc); 251 struct dw_mci *host = slot->host; 252 u32 cmdr; 253 254 cmd->error = -EINPROGRESS; 255 cmdr = cmd->opcode; 256 257 if (cmd->opcode == MMC_STOP_TRANSMISSION || 258 cmd->opcode == MMC_GO_IDLE_STATE || 259 cmd->opcode == MMC_GO_INACTIVE_STATE || 260 (cmd->opcode == SD_IO_RW_DIRECT && 261 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 262 cmdr |= SDMMC_CMD_STOP; 263 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 264 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 265 266 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 267 u32 clk_en_a; 268 269 /* Special bit makes CMD11 not die */ 270 cmdr |= SDMMC_CMD_VOLT_SWITCH; 271 272 /* Change state to continue to handle CMD11 weirdness */ 273 WARN_ON(slot->host->state != STATE_SENDING_CMD); 274 slot->host->state = STATE_SENDING_CMD11; 275 276 /* 277 * We need to disable low power mode (automatic clock stop) 278 * while doing voltage switch so we don't confuse the card, 279 * since stopping the clock is a specific part of the UHS 280 * voltage change dance. 281 * 282 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 283 * unconditionally turned back on in dw_mci_setup_bus() if it's 284 * ever called with a non-zero clock. That shouldn't happen 285 * until the voltage change is all done. 286 */ 287 clk_en_a = mci_readl(host, CLKENA); 288 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 289 mci_writel(host, CLKENA, clk_en_a); 290 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 291 SDMMC_CMD_PRV_DAT_WAIT, 0); 292 } 293 294 if (cmd->flags & MMC_RSP_PRESENT) { 295 /* We expect a response, so set this bit */ 296 cmdr |= SDMMC_CMD_RESP_EXP; 297 if (cmd->flags & MMC_RSP_136) 298 cmdr |= SDMMC_CMD_RESP_LONG; 299 } 300 301 if (cmd->flags & MMC_RSP_CRC) 302 cmdr |= SDMMC_CMD_RESP_CRC; 303 304 if (cmd->data) { 305 cmdr |= SDMMC_CMD_DAT_EXP; 306 if (cmd->data->flags & MMC_DATA_WRITE) 307 cmdr |= SDMMC_CMD_DAT_WR; 308 } 309 310 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 311 cmdr |= SDMMC_CMD_USE_HOLD_REG; 312 313 return cmdr; 314 } 315 316 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 317 { 318 struct mmc_command *stop; 319 u32 cmdr; 320 321 if (!cmd->data) 322 return 0; 323 324 stop = &host->stop_abort; 325 cmdr = cmd->opcode; 326 memset(stop, 0, sizeof(struct mmc_command)); 327 328 if (cmdr == MMC_READ_SINGLE_BLOCK || 329 cmdr == MMC_READ_MULTIPLE_BLOCK || 330 cmdr == MMC_WRITE_BLOCK || 331 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 332 cmdr == MMC_SEND_TUNING_BLOCK || 333 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 334 stop->opcode = MMC_STOP_TRANSMISSION; 335 stop->arg = 0; 336 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 337 } else if (cmdr == SD_IO_RW_EXTENDED) { 338 stop->opcode = SD_IO_RW_DIRECT; 339 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 340 ((cmd->arg >> 28) & 0x7); 341 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 342 } else { 343 return 0; 344 } 345 346 cmdr = stop->opcode | SDMMC_CMD_STOP | 347 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 348 349 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 350 cmdr |= SDMMC_CMD_USE_HOLD_REG; 351 352 return cmdr; 353 } 354 355 static inline void dw_mci_set_cto(struct dw_mci *host) 356 { 357 unsigned int cto_clks; 358 unsigned int cto_div; 359 unsigned int cto_ms; 360 unsigned long irqflags; 361 362 cto_clks = mci_readl(host, TMOUT) & 0xff; 363 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 364 if (cto_div == 0) 365 cto_div = 1; 366 367 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 368 host->bus_hz); 369 370 /* add a bit spare time */ 371 cto_ms += 10; 372 373 /* 374 * The durations we're working with are fairly short so we have to be 375 * extra careful about synchronization here. Specifically in hardware a 376 * command timeout is _at most_ 5.1 ms, so that means we expect an 377 * interrupt (either command done or timeout) to come rather quickly 378 * after the mci_writel. ...but just in case we have a long interrupt 379 * latency let's add a bit of paranoia. 380 * 381 * In general we'll assume that at least an interrupt will be asserted 382 * in hardware by the time the cto_timer runs. ...and if it hasn't 383 * been asserted in hardware by that time then we'll assume it'll never 384 * come. 385 */ 386 spin_lock_irqsave(&host->irq_lock, irqflags); 387 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 388 mod_timer(&host->cto_timer, 389 jiffies + msecs_to_jiffies(cto_ms) + 1); 390 spin_unlock_irqrestore(&host->irq_lock, irqflags); 391 } 392 393 static void dw_mci_start_command(struct dw_mci *host, 394 struct mmc_command *cmd, u32 cmd_flags) 395 { 396 host->cmd = cmd; 397 dev_vdbg(host->dev, 398 "start command: ARGR=0x%08x CMDR=0x%08x\n", 399 cmd->arg, cmd_flags); 400 401 mci_writel(host, CMDARG, cmd->arg); 402 wmb(); /* drain writebuffer */ 403 dw_mci_wait_while_busy(host, cmd_flags); 404 405 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 406 407 /* response expected command only */ 408 if (cmd_flags & SDMMC_CMD_RESP_EXP) 409 dw_mci_set_cto(host); 410 } 411 412 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 413 { 414 struct mmc_command *stop = &host->stop_abort; 415 416 dw_mci_start_command(host, stop, host->stop_cmdr); 417 } 418 419 /* DMA interface functions */ 420 static void dw_mci_stop_dma(struct dw_mci *host) 421 { 422 if (host->using_dma) { 423 host->dma_ops->stop(host); 424 host->dma_ops->cleanup(host); 425 } 426 427 /* Data transfer was stopped by the interrupt handler */ 428 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 429 } 430 431 static void dw_mci_dma_cleanup(struct dw_mci *host) 432 { 433 struct mmc_data *data = host->data; 434 435 if (data && data->host_cookie == COOKIE_MAPPED) { 436 dma_unmap_sg(host->dev, 437 data->sg, 438 data->sg_len, 439 mmc_get_dma_dir(data)); 440 data->host_cookie = COOKIE_UNMAPPED; 441 } 442 } 443 444 static void dw_mci_idmac_reset(struct dw_mci *host) 445 { 446 u32 bmod = mci_readl(host, BMOD); 447 /* Software reset of DMA */ 448 bmod |= SDMMC_IDMAC_SWRESET; 449 mci_writel(host, BMOD, bmod); 450 } 451 452 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 453 { 454 u32 temp; 455 456 /* Disable and reset the IDMAC interface */ 457 temp = mci_readl(host, CTRL); 458 temp &= ~SDMMC_CTRL_USE_IDMAC; 459 temp |= SDMMC_CTRL_DMA_RESET; 460 mci_writel(host, CTRL, temp); 461 462 /* Stop the IDMAC running */ 463 temp = mci_readl(host, BMOD); 464 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 465 temp |= SDMMC_IDMAC_SWRESET; 466 mci_writel(host, BMOD, temp); 467 } 468 469 static void dw_mci_dmac_complete_dma(void *arg) 470 { 471 struct dw_mci *host = arg; 472 struct mmc_data *data = host->data; 473 474 dev_vdbg(host->dev, "DMA complete\n"); 475 476 if ((host->use_dma == TRANS_MODE_EDMAC) && 477 data && (data->flags & MMC_DATA_READ)) 478 /* Invalidate cache after read */ 479 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 480 data->sg, 481 data->sg_len, 482 DMA_FROM_DEVICE); 483 484 host->dma_ops->cleanup(host); 485 486 /* 487 * If the card was removed, data will be NULL. No point in trying to 488 * send the stop command or waiting for NBUSY in this case. 489 */ 490 if (data) { 491 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 492 tasklet_schedule(&host->tasklet); 493 } 494 } 495 496 static int dw_mci_idmac_init(struct dw_mci *host) 497 { 498 int i; 499 500 if (host->dma_64bit_address == 1) { 501 struct idmac_desc_64addr *p; 502 /* Number of descriptors in the ring buffer */ 503 host->ring_size = 504 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 505 506 /* Forward link the descriptor list */ 507 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 508 i++, p++) { 509 p->des6 = (host->sg_dma + 510 (sizeof(struct idmac_desc_64addr) * 511 (i + 1))) & 0xffffffff; 512 513 p->des7 = (u64)(host->sg_dma + 514 (sizeof(struct idmac_desc_64addr) * 515 (i + 1))) >> 32; 516 /* Initialize reserved and buffer size fields to "0" */ 517 p->des0 = 0; 518 p->des1 = 0; 519 p->des2 = 0; 520 p->des3 = 0; 521 } 522 523 /* Set the last descriptor as the end-of-ring descriptor */ 524 p->des6 = host->sg_dma & 0xffffffff; 525 p->des7 = (u64)host->sg_dma >> 32; 526 p->des0 = IDMAC_DES0_ER; 527 528 } else { 529 struct idmac_desc *p; 530 /* Number of descriptors in the ring buffer */ 531 host->ring_size = 532 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 533 534 /* Forward link the descriptor list */ 535 for (i = 0, p = host->sg_cpu; 536 i < host->ring_size - 1; 537 i++, p++) { 538 p->des3 = cpu_to_le32(host->sg_dma + 539 (sizeof(struct idmac_desc) * (i + 1))); 540 p->des0 = 0; 541 p->des1 = 0; 542 } 543 544 /* Set the last descriptor as the end-of-ring descriptor */ 545 p->des3 = cpu_to_le32(host->sg_dma); 546 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 547 } 548 549 dw_mci_idmac_reset(host); 550 551 if (host->dma_64bit_address == 1) { 552 /* Mask out interrupts - get Tx & Rx complete only */ 553 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 554 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 555 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 556 557 /* Set the descriptor base address */ 558 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 559 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 560 561 } else { 562 /* Mask out interrupts - get Tx & Rx complete only */ 563 mci_writel(host, IDSTS, IDMAC_INT_CLR); 564 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 565 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 566 567 /* Set the descriptor base address */ 568 mci_writel(host, DBADDR, host->sg_dma); 569 } 570 571 return 0; 572 } 573 574 static inline int dw_mci_prepare_desc64(struct dw_mci *host, 575 struct mmc_data *data, 576 unsigned int sg_len) 577 { 578 unsigned int desc_len; 579 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 580 u32 val; 581 int i; 582 583 desc_first = desc_last = desc = host->sg_cpu; 584 585 for (i = 0; i < sg_len; i++) { 586 unsigned int length = sg_dma_len(&data->sg[i]); 587 588 u64 mem_addr = sg_dma_address(&data->sg[i]); 589 590 for ( ; length ; desc++) { 591 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 592 length : DW_MCI_DESC_DATA_LENGTH; 593 594 length -= desc_len; 595 596 /* 597 * Wait for the former clear OWN bit operation 598 * of IDMAC to make sure that this descriptor 599 * isn't still owned by IDMAC as IDMAC's write 600 * ops and CPU's read ops are asynchronous. 601 */ 602 if (readl_poll_timeout_atomic(&desc->des0, val, 603 !(val & IDMAC_DES0_OWN), 604 10, 100 * USEC_PER_MSEC)) 605 goto err_own_bit; 606 607 /* 608 * Set the OWN bit and disable interrupts 609 * for this descriptor 610 */ 611 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 612 IDMAC_DES0_CH; 613 614 /* Buffer length */ 615 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 616 617 /* Physical address to DMA to/from */ 618 desc->des4 = mem_addr & 0xffffffff; 619 desc->des5 = mem_addr >> 32; 620 621 /* Update physical address for the next desc */ 622 mem_addr += desc_len; 623 624 /* Save pointer to the last descriptor */ 625 desc_last = desc; 626 } 627 } 628 629 /* Set first descriptor */ 630 desc_first->des0 |= IDMAC_DES0_FD; 631 632 /* Set last descriptor */ 633 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 634 desc_last->des0 |= IDMAC_DES0_LD; 635 636 return 0; 637 err_own_bit: 638 /* restore the descriptor chain as it's polluted */ 639 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 640 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 641 dw_mci_idmac_init(host); 642 return -EINVAL; 643 } 644 645 646 static inline int dw_mci_prepare_desc32(struct dw_mci *host, 647 struct mmc_data *data, 648 unsigned int sg_len) 649 { 650 unsigned int desc_len; 651 struct idmac_desc *desc_first, *desc_last, *desc; 652 u32 val; 653 int i; 654 655 desc_first = desc_last = desc = host->sg_cpu; 656 657 for (i = 0; i < sg_len; i++) { 658 unsigned int length = sg_dma_len(&data->sg[i]); 659 660 u32 mem_addr = sg_dma_address(&data->sg[i]); 661 662 for ( ; length ; desc++) { 663 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 664 length : DW_MCI_DESC_DATA_LENGTH; 665 666 length -= desc_len; 667 668 /* 669 * Wait for the former clear OWN bit operation 670 * of IDMAC to make sure that this descriptor 671 * isn't still owned by IDMAC as IDMAC's write 672 * ops and CPU's read ops are asynchronous. 673 */ 674 if (readl_poll_timeout_atomic(&desc->des0, val, 675 IDMAC_OWN_CLR64(val), 676 10, 677 100 * USEC_PER_MSEC)) 678 goto err_own_bit; 679 680 /* 681 * Set the OWN bit and disable interrupts 682 * for this descriptor 683 */ 684 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 685 IDMAC_DES0_DIC | 686 IDMAC_DES0_CH); 687 688 /* Buffer length */ 689 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 690 691 /* Physical address to DMA to/from */ 692 desc->des2 = cpu_to_le32(mem_addr); 693 694 /* Update physical address for the next desc */ 695 mem_addr += desc_len; 696 697 /* Save pointer to the last descriptor */ 698 desc_last = desc; 699 } 700 } 701 702 /* Set first descriptor */ 703 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 704 705 /* Set last descriptor */ 706 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 707 IDMAC_DES0_DIC)); 708 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 709 710 return 0; 711 err_own_bit: 712 /* restore the descriptor chain as it's polluted */ 713 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 714 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 715 dw_mci_idmac_init(host); 716 return -EINVAL; 717 } 718 719 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 720 { 721 u32 temp; 722 int ret; 723 724 if (host->dma_64bit_address == 1) 725 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 726 else 727 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 728 729 if (ret) 730 goto out; 731 732 /* drain writebuffer */ 733 wmb(); 734 735 /* Make sure to reset DMA in case we did PIO before this */ 736 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 737 dw_mci_idmac_reset(host); 738 739 /* Select IDMAC interface */ 740 temp = mci_readl(host, CTRL); 741 temp |= SDMMC_CTRL_USE_IDMAC; 742 mci_writel(host, CTRL, temp); 743 744 /* drain writebuffer */ 745 wmb(); 746 747 /* Enable the IDMAC */ 748 temp = mci_readl(host, BMOD); 749 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 750 mci_writel(host, BMOD, temp); 751 752 /* Start it running */ 753 mci_writel(host, PLDMND, 1); 754 755 out: 756 return ret; 757 } 758 759 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 760 .init = dw_mci_idmac_init, 761 .start = dw_mci_idmac_start_dma, 762 .stop = dw_mci_idmac_stop_dma, 763 .complete = dw_mci_dmac_complete_dma, 764 .cleanup = dw_mci_dma_cleanup, 765 }; 766 767 static void dw_mci_edmac_stop_dma(struct dw_mci *host) 768 { 769 dmaengine_terminate_async(host->dms->ch); 770 } 771 772 static int dw_mci_edmac_start_dma(struct dw_mci *host, 773 unsigned int sg_len) 774 { 775 struct dma_slave_config cfg; 776 struct dma_async_tx_descriptor *desc = NULL; 777 struct scatterlist *sgl = host->data->sg; 778 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 779 u32 sg_elems = host->data->sg_len; 780 u32 fifoth_val; 781 u32 fifo_offset = host->fifo_reg - host->regs; 782 int ret = 0; 783 784 /* Set external dma config: burst size, burst width */ 785 cfg.dst_addr = host->phy_regs + fifo_offset; 786 cfg.src_addr = cfg.dst_addr; 787 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 788 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 789 790 /* Match burst msize with external dma config */ 791 fifoth_val = mci_readl(host, FIFOTH); 792 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 793 cfg.src_maxburst = cfg.dst_maxburst; 794 795 if (host->data->flags & MMC_DATA_WRITE) 796 cfg.direction = DMA_MEM_TO_DEV; 797 else 798 cfg.direction = DMA_DEV_TO_MEM; 799 800 ret = dmaengine_slave_config(host->dms->ch, &cfg); 801 if (ret) { 802 dev_err(host->dev, "Failed to config edmac.\n"); 803 return -EBUSY; 804 } 805 806 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 807 sg_len, cfg.direction, 808 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 809 if (!desc) { 810 dev_err(host->dev, "Can't prepare slave sg.\n"); 811 return -EBUSY; 812 } 813 814 /* Set dw_mci_dmac_complete_dma as callback */ 815 desc->callback = dw_mci_dmac_complete_dma; 816 desc->callback_param = (void *)host; 817 dmaengine_submit(desc); 818 819 /* Flush cache before write */ 820 if (host->data->flags & MMC_DATA_WRITE) 821 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 822 sg_elems, DMA_TO_DEVICE); 823 824 dma_async_issue_pending(host->dms->ch); 825 826 return 0; 827 } 828 829 static int dw_mci_edmac_init(struct dw_mci *host) 830 { 831 /* Request external dma channel */ 832 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 833 if (!host->dms) 834 return -ENOMEM; 835 836 host->dms->ch = dma_request_chan(host->dev, "rx-tx"); 837 if (IS_ERR(host->dms->ch)) { 838 int ret = PTR_ERR(host->dms->ch); 839 840 dev_err(host->dev, "Failed to get external DMA channel.\n"); 841 kfree(host->dms); 842 host->dms = NULL; 843 return ret; 844 } 845 846 return 0; 847 } 848 849 static void dw_mci_edmac_exit(struct dw_mci *host) 850 { 851 if (host->dms) { 852 if (host->dms->ch) { 853 dma_release_channel(host->dms->ch); 854 host->dms->ch = NULL; 855 } 856 kfree(host->dms); 857 host->dms = NULL; 858 } 859 } 860 861 static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 862 .init = dw_mci_edmac_init, 863 .exit = dw_mci_edmac_exit, 864 .start = dw_mci_edmac_start_dma, 865 .stop = dw_mci_edmac_stop_dma, 866 .complete = dw_mci_dmac_complete_dma, 867 .cleanup = dw_mci_dma_cleanup, 868 }; 869 870 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 871 struct mmc_data *data, 872 int cookie) 873 { 874 struct scatterlist *sg; 875 unsigned int i, sg_len; 876 877 if (data->host_cookie == COOKIE_PRE_MAPPED) 878 return data->sg_len; 879 880 /* 881 * We don't do DMA on "complex" transfers, i.e. with 882 * non-word-aligned buffers or lengths. Also, we don't bother 883 * with all the DMA setup overhead for short transfers. 884 */ 885 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 886 return -EINVAL; 887 888 if (data->blksz & 3) 889 return -EINVAL; 890 891 for_each_sg(data->sg, sg, data->sg_len, i) { 892 if (sg->offset & 3 || sg->length & 3) 893 return -EINVAL; 894 } 895 896 sg_len = dma_map_sg(host->dev, 897 data->sg, 898 data->sg_len, 899 mmc_get_dma_dir(data)); 900 if (sg_len == 0) 901 return -EINVAL; 902 903 data->host_cookie = cookie; 904 905 return sg_len; 906 } 907 908 static void dw_mci_pre_req(struct mmc_host *mmc, 909 struct mmc_request *mrq) 910 { 911 struct dw_mci_slot *slot = mmc_priv(mmc); 912 struct mmc_data *data = mrq->data; 913 914 if (!slot->host->use_dma || !data) 915 return; 916 917 /* This data might be unmapped at this time */ 918 data->host_cookie = COOKIE_UNMAPPED; 919 920 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 921 COOKIE_PRE_MAPPED) < 0) 922 data->host_cookie = COOKIE_UNMAPPED; 923 } 924 925 static void dw_mci_post_req(struct mmc_host *mmc, 926 struct mmc_request *mrq, 927 int err) 928 { 929 struct dw_mci_slot *slot = mmc_priv(mmc); 930 struct mmc_data *data = mrq->data; 931 932 if (!slot->host->use_dma || !data) 933 return; 934 935 if (data->host_cookie != COOKIE_UNMAPPED) 936 dma_unmap_sg(slot->host->dev, 937 data->sg, 938 data->sg_len, 939 mmc_get_dma_dir(data)); 940 data->host_cookie = COOKIE_UNMAPPED; 941 } 942 943 static int dw_mci_get_cd(struct mmc_host *mmc) 944 { 945 int present; 946 struct dw_mci_slot *slot = mmc_priv(mmc); 947 struct dw_mci *host = slot->host; 948 int gpio_cd = mmc_gpio_get_cd(mmc); 949 950 /* Use platform get_cd function, else try onboard card detect */ 951 if (((mmc->caps & MMC_CAP_NEEDS_POLL) 952 || !mmc_card_is_removable(mmc))) { 953 present = 1; 954 955 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 956 if (mmc->caps & MMC_CAP_NEEDS_POLL) { 957 dev_info(&mmc->class_dev, 958 "card is polling.\n"); 959 } else { 960 dev_info(&mmc->class_dev, 961 "card is non-removable.\n"); 962 } 963 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 964 } 965 966 return present; 967 } else if (gpio_cd >= 0) 968 present = gpio_cd; 969 else 970 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 971 == 0 ? 1 : 0; 972 973 spin_lock_bh(&host->lock); 974 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 975 dev_dbg(&mmc->class_dev, "card is present\n"); 976 else if (!present && 977 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 978 dev_dbg(&mmc->class_dev, "card is not present\n"); 979 spin_unlock_bh(&host->lock); 980 981 return present; 982 } 983 984 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 985 { 986 unsigned int blksz = data->blksz; 987 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 988 u32 fifo_width = 1 << host->data_shift; 989 u32 blksz_depth = blksz / fifo_width, fifoth_val; 990 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 991 int idx = ARRAY_SIZE(mszs) - 1; 992 993 /* pio should ship this scenario */ 994 if (!host->use_dma) 995 return; 996 997 tx_wmark = (host->fifo_depth) / 2; 998 tx_wmark_invers = host->fifo_depth - tx_wmark; 999 1000 /* 1001 * MSIZE is '1', 1002 * if blksz is not a multiple of the FIFO width 1003 */ 1004 if (blksz % fifo_width) 1005 goto done; 1006 1007 do { 1008 if (!((blksz_depth % mszs[idx]) || 1009 (tx_wmark_invers % mszs[idx]))) { 1010 msize = idx; 1011 rx_wmark = mszs[idx] - 1; 1012 break; 1013 } 1014 } while (--idx > 0); 1015 /* 1016 * If idx is '0', it won't be tried 1017 * Thus, initial values are uesed 1018 */ 1019 done: 1020 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 1021 mci_writel(host, FIFOTH, fifoth_val); 1022 } 1023 1024 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1025 { 1026 unsigned int blksz = data->blksz; 1027 u32 blksz_depth, fifo_depth; 1028 u16 thld_size; 1029 u8 enable; 1030 1031 /* 1032 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 1033 * in the FIFO region, so we really shouldn't access it). 1034 */ 1035 if (host->verid < DW_MMC_240A || 1036 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 1037 return; 1038 1039 /* 1040 * Card write Threshold is introduced since 2.80a 1041 * It's used when HS400 mode is enabled. 1042 */ 1043 if (data->flags & MMC_DATA_WRITE && 1044 host->timing != MMC_TIMING_MMC_HS400) 1045 goto disable; 1046 1047 if (data->flags & MMC_DATA_WRITE) 1048 enable = SDMMC_CARD_WR_THR_EN; 1049 else 1050 enable = SDMMC_CARD_RD_THR_EN; 1051 1052 if (host->timing != MMC_TIMING_MMC_HS200 && 1053 host->timing != MMC_TIMING_UHS_SDR104 && 1054 host->timing != MMC_TIMING_MMC_HS400) 1055 goto disable; 1056 1057 blksz_depth = blksz / (1 << host->data_shift); 1058 fifo_depth = host->fifo_depth; 1059 1060 if (blksz_depth > fifo_depth) 1061 goto disable; 1062 1063 /* 1064 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1065 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1066 * Currently just choose blksz. 1067 */ 1068 thld_size = blksz; 1069 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1070 return; 1071 1072 disable: 1073 mci_writel(host, CDTHRCTL, 0); 1074 } 1075 1076 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1077 { 1078 unsigned long irqflags; 1079 int sg_len; 1080 u32 temp; 1081 1082 host->using_dma = 0; 1083 1084 /* If we don't have a channel, we can't do DMA */ 1085 if (!host->use_dma) 1086 return -ENODEV; 1087 1088 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1089 if (sg_len < 0) { 1090 host->dma_ops->stop(host); 1091 return sg_len; 1092 } 1093 1094 host->using_dma = 1; 1095 1096 if (host->use_dma == TRANS_MODE_IDMAC) 1097 dev_vdbg(host->dev, 1098 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1099 (unsigned long)host->sg_cpu, 1100 (unsigned long)host->sg_dma, 1101 sg_len); 1102 1103 /* 1104 * Decide the MSIZE and RX/TX Watermark. 1105 * If current block size is same with previous size, 1106 * no need to update fifoth. 1107 */ 1108 if (host->prev_blksz != data->blksz) 1109 dw_mci_adjust_fifoth(host, data); 1110 1111 /* Enable the DMA interface */ 1112 temp = mci_readl(host, CTRL); 1113 temp |= SDMMC_CTRL_DMA_ENABLE; 1114 mci_writel(host, CTRL, temp); 1115 1116 /* Disable RX/TX IRQs, let DMA handle it */ 1117 spin_lock_irqsave(&host->irq_lock, irqflags); 1118 temp = mci_readl(host, INTMASK); 1119 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1120 mci_writel(host, INTMASK, temp); 1121 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1122 1123 if (host->dma_ops->start(host, sg_len)) { 1124 host->dma_ops->stop(host); 1125 /* We can't do DMA, try PIO for this one */ 1126 dev_dbg(host->dev, 1127 "%s: fall back to PIO mode for current transfer\n", 1128 __func__); 1129 return -ENODEV; 1130 } 1131 1132 return 0; 1133 } 1134 1135 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1136 { 1137 unsigned long irqflags; 1138 int flags = SG_MITER_ATOMIC; 1139 u32 temp; 1140 1141 data->error = -EINPROGRESS; 1142 1143 WARN_ON(host->data); 1144 host->sg = NULL; 1145 host->data = data; 1146 1147 if (data->flags & MMC_DATA_READ) 1148 host->dir_status = DW_MCI_RECV_STATUS; 1149 else 1150 host->dir_status = DW_MCI_SEND_STATUS; 1151 1152 dw_mci_ctrl_thld(host, data); 1153 1154 if (dw_mci_submit_data_dma(host, data)) { 1155 if (host->data->flags & MMC_DATA_READ) 1156 flags |= SG_MITER_TO_SG; 1157 else 1158 flags |= SG_MITER_FROM_SG; 1159 1160 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1161 host->sg = data->sg; 1162 host->part_buf_start = 0; 1163 host->part_buf_count = 0; 1164 1165 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1166 1167 spin_lock_irqsave(&host->irq_lock, irqflags); 1168 temp = mci_readl(host, INTMASK); 1169 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1170 mci_writel(host, INTMASK, temp); 1171 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1172 1173 temp = mci_readl(host, CTRL); 1174 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1175 mci_writel(host, CTRL, temp); 1176 1177 /* 1178 * Use the initial fifoth_val for PIO mode. If wm_algined 1179 * is set, we set watermark same as data size. 1180 * If next issued data may be transfered by DMA mode, 1181 * prev_blksz should be invalidated. 1182 */ 1183 if (host->wm_aligned) 1184 dw_mci_adjust_fifoth(host, data); 1185 else 1186 mci_writel(host, FIFOTH, host->fifoth_val); 1187 host->prev_blksz = 0; 1188 } else { 1189 /* 1190 * Keep the current block size. 1191 * It will be used to decide whether to update 1192 * fifoth register next time. 1193 */ 1194 host->prev_blksz = data->blksz; 1195 } 1196 } 1197 1198 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1199 { 1200 struct dw_mci *host = slot->host; 1201 unsigned int clock = slot->clock; 1202 u32 div; 1203 u32 clk_en_a; 1204 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1205 1206 /* We must continue to set bit 28 in CMD until the change is complete */ 1207 if (host->state == STATE_WAITING_CMD11_DONE) 1208 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1209 1210 slot->mmc->actual_clock = 0; 1211 1212 if (!clock) { 1213 mci_writel(host, CLKENA, 0); 1214 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1215 } else if (clock != host->current_speed || force_clkinit) { 1216 div = host->bus_hz / clock; 1217 if (host->bus_hz % clock && host->bus_hz > clock) 1218 /* 1219 * move the + 1 after the divide to prevent 1220 * over-clocking the card. 1221 */ 1222 div += 1; 1223 1224 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1225 1226 if ((clock != slot->__clk_old && 1227 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1228 force_clkinit) { 1229 /* Silent the verbose log if calling from PM context */ 1230 if (!force_clkinit) 1231 dev_info(&slot->mmc->class_dev, 1232 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1233 slot->id, host->bus_hz, clock, 1234 div ? ((host->bus_hz / div) >> 1) : 1235 host->bus_hz, div); 1236 1237 /* 1238 * If card is polling, display the message only 1239 * one time at boot time. 1240 */ 1241 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1242 slot->mmc->f_min == clock) 1243 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1244 } 1245 1246 /* disable clock */ 1247 mci_writel(host, CLKENA, 0); 1248 mci_writel(host, CLKSRC, 0); 1249 1250 /* inform CIU */ 1251 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1252 1253 /* set clock to desired speed */ 1254 mci_writel(host, CLKDIV, div); 1255 1256 /* inform CIU */ 1257 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1258 1259 /* enable clock; only low power if no SDIO */ 1260 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1261 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1262 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1263 mci_writel(host, CLKENA, clk_en_a); 1264 1265 /* inform CIU */ 1266 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1267 1268 /* keep the last clock value that was requested from core */ 1269 slot->__clk_old = clock; 1270 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : 1271 host->bus_hz; 1272 } 1273 1274 host->current_speed = clock; 1275 1276 /* Set the current slot bus width */ 1277 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1278 } 1279 1280 static void __dw_mci_start_request(struct dw_mci *host, 1281 struct dw_mci_slot *slot, 1282 struct mmc_command *cmd) 1283 { 1284 struct mmc_request *mrq; 1285 struct mmc_data *data; 1286 u32 cmdflags; 1287 1288 mrq = slot->mrq; 1289 1290 host->mrq = mrq; 1291 1292 host->pending_events = 0; 1293 host->completed_events = 0; 1294 host->cmd_status = 0; 1295 host->data_status = 0; 1296 host->dir_status = 0; 1297 1298 data = cmd->data; 1299 if (data) { 1300 mci_writel(host, TMOUT, 0xFFFFFFFF); 1301 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1302 mci_writel(host, BLKSIZ, data->blksz); 1303 } 1304 1305 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1306 1307 /* this is the first command, send the initialization clock */ 1308 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1309 cmdflags |= SDMMC_CMD_INIT; 1310 1311 if (data) { 1312 dw_mci_submit_data(host, data); 1313 wmb(); /* drain writebuffer */ 1314 } 1315 1316 dw_mci_start_command(host, cmd, cmdflags); 1317 1318 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1319 unsigned long irqflags; 1320 1321 /* 1322 * Databook says to fail after 2ms w/ no response, but evidence 1323 * shows that sometimes the cmd11 interrupt takes over 130ms. 1324 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1325 * is just about to roll over. 1326 * 1327 * We do this whole thing under spinlock and only if the 1328 * command hasn't already completed (indicating the the irq 1329 * already ran so we don't want the timeout). 1330 */ 1331 spin_lock_irqsave(&host->irq_lock, irqflags); 1332 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1333 mod_timer(&host->cmd11_timer, 1334 jiffies + msecs_to_jiffies(500) + 1); 1335 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1336 } 1337 1338 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1339 } 1340 1341 static void dw_mci_start_request(struct dw_mci *host, 1342 struct dw_mci_slot *slot) 1343 { 1344 struct mmc_request *mrq = slot->mrq; 1345 struct mmc_command *cmd; 1346 1347 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1348 __dw_mci_start_request(host, slot, cmd); 1349 } 1350 1351 /* must be called with host->lock held */ 1352 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1353 struct mmc_request *mrq) 1354 { 1355 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1356 host->state); 1357 1358 slot->mrq = mrq; 1359 1360 if (host->state == STATE_WAITING_CMD11_DONE) { 1361 dev_warn(&slot->mmc->class_dev, 1362 "Voltage change didn't complete\n"); 1363 /* 1364 * this case isn't expected to happen, so we can 1365 * either crash here or just try to continue on 1366 * in the closest possible state 1367 */ 1368 host->state = STATE_IDLE; 1369 } 1370 1371 if (host->state == STATE_IDLE) { 1372 host->state = STATE_SENDING_CMD; 1373 dw_mci_start_request(host, slot); 1374 } else { 1375 list_add_tail(&slot->queue_node, &host->queue); 1376 } 1377 } 1378 1379 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1380 { 1381 struct dw_mci_slot *slot = mmc_priv(mmc); 1382 struct dw_mci *host = slot->host; 1383 1384 WARN_ON(slot->mrq); 1385 1386 /* 1387 * The check for card presence and queueing of the request must be 1388 * atomic, otherwise the card could be removed in between and the 1389 * request wouldn't fail until another card was inserted. 1390 */ 1391 1392 if (!dw_mci_get_cd(mmc)) { 1393 mrq->cmd->error = -ENOMEDIUM; 1394 mmc_request_done(mmc, mrq); 1395 return; 1396 } 1397 1398 spin_lock_bh(&host->lock); 1399 1400 dw_mci_queue_request(host, slot, mrq); 1401 1402 spin_unlock_bh(&host->lock); 1403 } 1404 1405 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1406 { 1407 struct dw_mci_slot *slot = mmc_priv(mmc); 1408 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1409 u32 regs; 1410 int ret; 1411 1412 switch (ios->bus_width) { 1413 case MMC_BUS_WIDTH_4: 1414 slot->ctype = SDMMC_CTYPE_4BIT; 1415 break; 1416 case MMC_BUS_WIDTH_8: 1417 slot->ctype = SDMMC_CTYPE_8BIT; 1418 break; 1419 default: 1420 /* set default 1 bit mode */ 1421 slot->ctype = SDMMC_CTYPE_1BIT; 1422 } 1423 1424 regs = mci_readl(slot->host, UHS_REG); 1425 1426 /* DDR mode set */ 1427 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1428 ios->timing == MMC_TIMING_UHS_DDR50 || 1429 ios->timing == MMC_TIMING_MMC_HS400) 1430 regs |= ((0x1 << slot->id) << 16); 1431 else 1432 regs &= ~((0x1 << slot->id) << 16); 1433 1434 mci_writel(slot->host, UHS_REG, regs); 1435 slot->host->timing = ios->timing; 1436 1437 /* 1438 * Use mirror of ios->clock to prevent race with mmc 1439 * core ios update when finding the minimum. 1440 */ 1441 slot->clock = ios->clock; 1442 1443 if (drv_data && drv_data->set_ios) 1444 drv_data->set_ios(slot->host, ios); 1445 1446 switch (ios->power_mode) { 1447 case MMC_POWER_UP: 1448 if (!IS_ERR(mmc->supply.vmmc)) { 1449 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1450 ios->vdd); 1451 if (ret) { 1452 dev_err(slot->host->dev, 1453 "failed to enable vmmc regulator\n"); 1454 /*return, if failed turn on vmmc*/ 1455 return; 1456 } 1457 } 1458 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1459 regs = mci_readl(slot->host, PWREN); 1460 regs |= (1 << slot->id); 1461 mci_writel(slot->host, PWREN, regs); 1462 break; 1463 case MMC_POWER_ON: 1464 if (!slot->host->vqmmc_enabled) { 1465 if (!IS_ERR(mmc->supply.vqmmc)) { 1466 ret = regulator_enable(mmc->supply.vqmmc); 1467 if (ret < 0) 1468 dev_err(slot->host->dev, 1469 "failed to enable vqmmc\n"); 1470 else 1471 slot->host->vqmmc_enabled = true; 1472 1473 } else { 1474 /* Keep track so we don't reset again */ 1475 slot->host->vqmmc_enabled = true; 1476 } 1477 1478 /* Reset our state machine after powering on */ 1479 dw_mci_ctrl_reset(slot->host, 1480 SDMMC_CTRL_ALL_RESET_FLAGS); 1481 } 1482 1483 /* Adjust clock / bus width after power is up */ 1484 dw_mci_setup_bus(slot, false); 1485 1486 break; 1487 case MMC_POWER_OFF: 1488 /* Turn clock off before power goes down */ 1489 dw_mci_setup_bus(slot, false); 1490 1491 if (!IS_ERR(mmc->supply.vmmc)) 1492 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1493 1494 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1495 regulator_disable(mmc->supply.vqmmc); 1496 slot->host->vqmmc_enabled = false; 1497 1498 regs = mci_readl(slot->host, PWREN); 1499 regs &= ~(1 << slot->id); 1500 mci_writel(slot->host, PWREN, regs); 1501 break; 1502 default: 1503 break; 1504 } 1505 1506 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1507 slot->host->state = STATE_IDLE; 1508 } 1509 1510 static int dw_mci_card_busy(struct mmc_host *mmc) 1511 { 1512 struct dw_mci_slot *slot = mmc_priv(mmc); 1513 u32 status; 1514 1515 /* 1516 * Check the busy bit which is low when DAT[3:0] 1517 * (the data lines) are 0000 1518 */ 1519 status = mci_readl(slot->host, STATUS); 1520 1521 return !!(status & SDMMC_STATUS_BUSY); 1522 } 1523 1524 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1525 { 1526 struct dw_mci_slot *slot = mmc_priv(mmc); 1527 struct dw_mci *host = slot->host; 1528 const struct dw_mci_drv_data *drv_data = host->drv_data; 1529 u32 uhs; 1530 u32 v18 = SDMMC_UHS_18V << slot->id; 1531 int ret; 1532 1533 if (drv_data && drv_data->switch_voltage) 1534 return drv_data->switch_voltage(mmc, ios); 1535 1536 /* 1537 * Program the voltage. Note that some instances of dw_mmc may use 1538 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1539 * does no harm but you need to set the regulator directly. Try both. 1540 */ 1541 uhs = mci_readl(host, UHS_REG); 1542 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1543 uhs &= ~v18; 1544 else 1545 uhs |= v18; 1546 1547 if (!IS_ERR(mmc->supply.vqmmc)) { 1548 ret = mmc_regulator_set_vqmmc(mmc, ios); 1549 if (ret < 0) { 1550 dev_dbg(&mmc->class_dev, 1551 "Regulator set error %d - %s V\n", 1552 ret, uhs & v18 ? "1.8" : "3.3"); 1553 return ret; 1554 } 1555 } 1556 mci_writel(host, UHS_REG, uhs); 1557 1558 return 0; 1559 } 1560 1561 static int dw_mci_get_ro(struct mmc_host *mmc) 1562 { 1563 int read_only; 1564 struct dw_mci_slot *slot = mmc_priv(mmc); 1565 int gpio_ro = mmc_gpio_get_ro(mmc); 1566 1567 /* Use platform get_ro function, else try on board write protect */ 1568 if (gpio_ro >= 0) 1569 read_only = gpio_ro; 1570 else 1571 read_only = 1572 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1573 1574 dev_dbg(&mmc->class_dev, "card is %s\n", 1575 read_only ? "read-only" : "read-write"); 1576 1577 return read_only; 1578 } 1579 1580 static void dw_mci_hw_reset(struct mmc_host *mmc) 1581 { 1582 struct dw_mci_slot *slot = mmc_priv(mmc); 1583 struct dw_mci *host = slot->host; 1584 int reset; 1585 1586 if (host->use_dma == TRANS_MODE_IDMAC) 1587 dw_mci_idmac_reset(host); 1588 1589 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1590 SDMMC_CTRL_FIFO_RESET)) 1591 return; 1592 1593 /* 1594 * According to eMMC spec, card reset procedure: 1595 * tRstW >= 1us: RST_n pulse width 1596 * tRSCA >= 200us: RST_n to Command time 1597 * tRSTH >= 1us: RST_n high period 1598 */ 1599 reset = mci_readl(host, RST_N); 1600 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1601 mci_writel(host, RST_N, reset); 1602 usleep_range(1, 2); 1603 reset |= SDMMC_RST_HWACTIVE << slot->id; 1604 mci_writel(host, RST_N, reset); 1605 usleep_range(200, 300); 1606 } 1607 1608 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1609 { 1610 struct dw_mci_slot *slot = mmc_priv(mmc); 1611 struct dw_mci *host = slot->host; 1612 1613 /* 1614 * Low power mode will stop the card clock when idle. According to the 1615 * description of the CLKENA register we should disable low power mode 1616 * for SDIO cards if we need SDIO interrupts to work. 1617 */ 1618 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1619 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1620 u32 clk_en_a_old; 1621 u32 clk_en_a; 1622 1623 clk_en_a_old = mci_readl(host, CLKENA); 1624 1625 if (card->type == MMC_TYPE_SDIO || 1626 card->type == MMC_TYPE_SD_COMBO) { 1627 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1628 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1629 } else { 1630 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1631 clk_en_a = clk_en_a_old | clken_low_pwr; 1632 } 1633 1634 if (clk_en_a != clk_en_a_old) { 1635 mci_writel(host, CLKENA, clk_en_a); 1636 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1637 SDMMC_CMD_PRV_DAT_WAIT, 0); 1638 } 1639 } 1640 } 1641 1642 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 1643 { 1644 struct dw_mci *host = slot->host; 1645 unsigned long irqflags; 1646 u32 int_mask; 1647 1648 spin_lock_irqsave(&host->irq_lock, irqflags); 1649 1650 /* Enable/disable Slot Specific SDIO interrupt */ 1651 int_mask = mci_readl(host, INTMASK); 1652 if (enb) 1653 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1654 else 1655 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1656 mci_writel(host, INTMASK, int_mask); 1657 1658 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1659 } 1660 1661 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1662 { 1663 struct dw_mci_slot *slot = mmc_priv(mmc); 1664 struct dw_mci *host = slot->host; 1665 1666 __dw_mci_enable_sdio_irq(slot, enb); 1667 1668 /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1669 if (enb) 1670 pm_runtime_get_noresume(host->dev); 1671 else 1672 pm_runtime_put_noidle(host->dev); 1673 } 1674 1675 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 1676 { 1677 struct dw_mci_slot *slot = mmc_priv(mmc); 1678 1679 __dw_mci_enable_sdio_irq(slot, 1); 1680 } 1681 1682 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1683 { 1684 struct dw_mci_slot *slot = mmc_priv(mmc); 1685 struct dw_mci *host = slot->host; 1686 const struct dw_mci_drv_data *drv_data = host->drv_data; 1687 int err = -EINVAL; 1688 1689 if (drv_data && drv_data->execute_tuning) 1690 err = drv_data->execute_tuning(slot, opcode); 1691 return err; 1692 } 1693 1694 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1695 struct mmc_ios *ios) 1696 { 1697 struct dw_mci_slot *slot = mmc_priv(mmc); 1698 struct dw_mci *host = slot->host; 1699 const struct dw_mci_drv_data *drv_data = host->drv_data; 1700 1701 if (drv_data && drv_data->prepare_hs400_tuning) 1702 return drv_data->prepare_hs400_tuning(host, ios); 1703 1704 return 0; 1705 } 1706 1707 static bool dw_mci_reset(struct dw_mci *host) 1708 { 1709 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 1710 bool ret = false; 1711 u32 status = 0; 1712 1713 /* 1714 * Resetting generates a block interrupt, hence setting 1715 * the scatter-gather pointer to NULL. 1716 */ 1717 if (host->sg) { 1718 sg_miter_stop(&host->sg_miter); 1719 host->sg = NULL; 1720 } 1721 1722 if (host->use_dma) 1723 flags |= SDMMC_CTRL_DMA_RESET; 1724 1725 if (dw_mci_ctrl_reset(host, flags)) { 1726 /* 1727 * In all cases we clear the RAWINTS 1728 * register to clear any interrupts. 1729 */ 1730 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1731 1732 if (!host->use_dma) { 1733 ret = true; 1734 goto ciu_out; 1735 } 1736 1737 /* Wait for dma_req to be cleared */ 1738 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 1739 status, 1740 !(status & SDMMC_STATUS_DMA_REQ), 1741 1, 500 * USEC_PER_MSEC)) { 1742 dev_err(host->dev, 1743 "%s: Timeout waiting for dma_req to be cleared\n", 1744 __func__); 1745 goto ciu_out; 1746 } 1747 1748 /* when using DMA next we reset the fifo again */ 1749 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 1750 goto ciu_out; 1751 } else { 1752 /* if the controller reset bit did clear, then set clock regs */ 1753 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 1754 dev_err(host->dev, 1755 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 1756 __func__); 1757 goto ciu_out; 1758 } 1759 } 1760 1761 if (host->use_dma == TRANS_MODE_IDMAC) 1762 /* It is also required that we reinit idmac */ 1763 dw_mci_idmac_init(host); 1764 1765 ret = true; 1766 1767 ciu_out: 1768 /* After a CTRL reset we need to have CIU set clock registers */ 1769 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 1770 1771 return ret; 1772 } 1773 1774 static const struct mmc_host_ops dw_mci_ops = { 1775 .request = dw_mci_request, 1776 .pre_req = dw_mci_pre_req, 1777 .post_req = dw_mci_post_req, 1778 .set_ios = dw_mci_set_ios, 1779 .get_ro = dw_mci_get_ro, 1780 .get_cd = dw_mci_get_cd, 1781 .hw_reset = dw_mci_hw_reset, 1782 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1783 .ack_sdio_irq = dw_mci_ack_sdio_irq, 1784 .execute_tuning = dw_mci_execute_tuning, 1785 .card_busy = dw_mci_card_busy, 1786 .start_signal_voltage_switch = dw_mci_switch_voltage, 1787 .init_card = dw_mci_init_card, 1788 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1789 }; 1790 1791 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1792 __releases(&host->lock) 1793 __acquires(&host->lock) 1794 { 1795 struct dw_mci_slot *slot; 1796 struct mmc_host *prev_mmc = host->slot->mmc; 1797 1798 WARN_ON(host->cmd || host->data); 1799 1800 host->slot->mrq = NULL; 1801 host->mrq = NULL; 1802 if (!list_empty(&host->queue)) { 1803 slot = list_entry(host->queue.next, 1804 struct dw_mci_slot, queue_node); 1805 list_del(&slot->queue_node); 1806 dev_vdbg(host->dev, "list not empty: %s is next\n", 1807 mmc_hostname(slot->mmc)); 1808 host->state = STATE_SENDING_CMD; 1809 dw_mci_start_request(host, slot); 1810 } else { 1811 dev_vdbg(host->dev, "list empty\n"); 1812 1813 if (host->state == STATE_SENDING_CMD11) 1814 host->state = STATE_WAITING_CMD11_DONE; 1815 else 1816 host->state = STATE_IDLE; 1817 } 1818 1819 spin_unlock(&host->lock); 1820 mmc_request_done(prev_mmc, mrq); 1821 spin_lock(&host->lock); 1822 } 1823 1824 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1825 { 1826 u32 status = host->cmd_status; 1827 1828 host->cmd_status = 0; 1829 1830 /* Read the response from the card (up to 16 bytes) */ 1831 if (cmd->flags & MMC_RSP_PRESENT) { 1832 if (cmd->flags & MMC_RSP_136) { 1833 cmd->resp[3] = mci_readl(host, RESP0); 1834 cmd->resp[2] = mci_readl(host, RESP1); 1835 cmd->resp[1] = mci_readl(host, RESP2); 1836 cmd->resp[0] = mci_readl(host, RESP3); 1837 } else { 1838 cmd->resp[0] = mci_readl(host, RESP0); 1839 cmd->resp[1] = 0; 1840 cmd->resp[2] = 0; 1841 cmd->resp[3] = 0; 1842 } 1843 } 1844 1845 if (status & SDMMC_INT_RTO) 1846 cmd->error = -ETIMEDOUT; 1847 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1848 cmd->error = -EILSEQ; 1849 else if (status & SDMMC_INT_RESP_ERR) 1850 cmd->error = -EIO; 1851 else 1852 cmd->error = 0; 1853 1854 return cmd->error; 1855 } 1856 1857 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1858 { 1859 u32 status = host->data_status; 1860 1861 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1862 if (status & SDMMC_INT_DRTO) { 1863 data->error = -ETIMEDOUT; 1864 } else if (status & SDMMC_INT_DCRC) { 1865 data->error = -EILSEQ; 1866 } else if (status & SDMMC_INT_EBE) { 1867 if (host->dir_status == 1868 DW_MCI_SEND_STATUS) { 1869 /* 1870 * No data CRC status was returned. 1871 * The number of bytes transferred 1872 * will be exaggerated in PIO mode. 1873 */ 1874 data->bytes_xfered = 0; 1875 data->error = -ETIMEDOUT; 1876 } else if (host->dir_status == 1877 DW_MCI_RECV_STATUS) { 1878 data->error = -EILSEQ; 1879 } 1880 } else { 1881 /* SDMMC_INT_SBE is included */ 1882 data->error = -EILSEQ; 1883 } 1884 1885 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1886 1887 /* 1888 * After an error, there may be data lingering 1889 * in the FIFO 1890 */ 1891 dw_mci_reset(host); 1892 } else { 1893 data->bytes_xfered = data->blocks * data->blksz; 1894 data->error = 0; 1895 } 1896 1897 return data->error; 1898 } 1899 1900 static void dw_mci_set_drto(struct dw_mci *host) 1901 { 1902 unsigned int drto_clks; 1903 unsigned int drto_div; 1904 unsigned int drto_ms; 1905 unsigned long irqflags; 1906 1907 drto_clks = mci_readl(host, TMOUT) >> 8; 1908 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 1909 if (drto_div == 0) 1910 drto_div = 1; 1911 1912 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 1913 host->bus_hz); 1914 1915 /* add a bit spare time */ 1916 drto_ms += 10; 1917 1918 spin_lock_irqsave(&host->irq_lock, irqflags); 1919 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1920 mod_timer(&host->dto_timer, 1921 jiffies + msecs_to_jiffies(drto_ms)); 1922 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1923 } 1924 1925 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 1926 { 1927 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1928 return false; 1929 1930 /* 1931 * Really be certain that the timer has stopped. This is a bit of 1932 * paranoia and could only really happen if we had really bad 1933 * interrupt latency and the interrupt routine and timeout were 1934 * running concurrently so that the del_timer() in the interrupt 1935 * handler couldn't run. 1936 */ 1937 WARN_ON(del_timer_sync(&host->cto_timer)); 1938 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1939 1940 return true; 1941 } 1942 1943 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 1944 { 1945 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1946 return false; 1947 1948 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 1949 WARN_ON(del_timer_sync(&host->dto_timer)); 1950 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1951 1952 return true; 1953 } 1954 1955 static void dw_mci_tasklet_func(struct tasklet_struct *t) 1956 { 1957 struct dw_mci *host = from_tasklet(host, t, tasklet); 1958 struct mmc_data *data; 1959 struct mmc_command *cmd; 1960 struct mmc_request *mrq; 1961 enum dw_mci_state state; 1962 enum dw_mci_state prev_state; 1963 unsigned int err; 1964 1965 spin_lock(&host->lock); 1966 1967 state = host->state; 1968 data = host->data; 1969 mrq = host->mrq; 1970 1971 do { 1972 prev_state = state; 1973 1974 switch (state) { 1975 case STATE_IDLE: 1976 case STATE_WAITING_CMD11_DONE: 1977 break; 1978 1979 case STATE_SENDING_CMD11: 1980 case STATE_SENDING_CMD: 1981 if (!dw_mci_clear_pending_cmd_complete(host)) 1982 break; 1983 1984 cmd = host->cmd; 1985 host->cmd = NULL; 1986 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1987 err = dw_mci_command_complete(host, cmd); 1988 if (cmd == mrq->sbc && !err) { 1989 __dw_mci_start_request(host, host->slot, 1990 mrq->cmd); 1991 goto unlock; 1992 } 1993 1994 if (cmd->data && err) { 1995 /* 1996 * During UHS tuning sequence, sending the stop 1997 * command after the response CRC error would 1998 * throw the system into a confused state 1999 * causing all future tuning phases to report 2000 * failure. 2001 * 2002 * In such case controller will move into a data 2003 * transfer state after a response error or 2004 * response CRC error. Let's let that finish 2005 * before trying to send a stop, so we'll go to 2006 * STATE_SENDING_DATA. 2007 * 2008 * Although letting the data transfer take place 2009 * will waste a bit of time (we already know 2010 * the command was bad), it can't cause any 2011 * errors since it's possible it would have 2012 * taken place anyway if this tasklet got 2013 * delayed. Allowing the transfer to take place 2014 * avoids races and keeps things simple. 2015 */ 2016 if (err != -ETIMEDOUT) { 2017 state = STATE_SENDING_DATA; 2018 continue; 2019 } 2020 2021 dw_mci_stop_dma(host); 2022 send_stop_abort(host, data); 2023 state = STATE_SENDING_STOP; 2024 break; 2025 } 2026 2027 if (!cmd->data || err) { 2028 dw_mci_request_end(host, mrq); 2029 goto unlock; 2030 } 2031 2032 prev_state = state = STATE_SENDING_DATA; 2033 fallthrough; 2034 2035 case STATE_SENDING_DATA: 2036 /* 2037 * We could get a data error and never a transfer 2038 * complete so we'd better check for it here. 2039 * 2040 * Note that we don't really care if we also got a 2041 * transfer complete; stopping the DMA and sending an 2042 * abort won't hurt. 2043 */ 2044 if (test_and_clear_bit(EVENT_DATA_ERROR, 2045 &host->pending_events)) { 2046 dw_mci_stop_dma(host); 2047 if (!(host->data_status & (SDMMC_INT_DRTO | 2048 SDMMC_INT_EBE))) 2049 send_stop_abort(host, data); 2050 state = STATE_DATA_ERROR; 2051 break; 2052 } 2053 2054 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2055 &host->pending_events)) { 2056 /* 2057 * If all data-related interrupts don't come 2058 * within the given time in reading data state. 2059 */ 2060 if (host->dir_status == DW_MCI_RECV_STATUS) 2061 dw_mci_set_drto(host); 2062 break; 2063 } 2064 2065 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 2066 2067 /* 2068 * Handle an EVENT_DATA_ERROR that might have shown up 2069 * before the transfer completed. This might not have 2070 * been caught by the check above because the interrupt 2071 * could have gone off between the previous check and 2072 * the check for transfer complete. 2073 * 2074 * Technically this ought not be needed assuming we 2075 * get a DATA_COMPLETE eventually (we'll notice the 2076 * error and end the request), but it shouldn't hurt. 2077 * 2078 * This has the advantage of sending the stop command. 2079 */ 2080 if (test_and_clear_bit(EVENT_DATA_ERROR, 2081 &host->pending_events)) { 2082 dw_mci_stop_dma(host); 2083 if (!(host->data_status & (SDMMC_INT_DRTO | 2084 SDMMC_INT_EBE))) 2085 send_stop_abort(host, data); 2086 state = STATE_DATA_ERROR; 2087 break; 2088 } 2089 prev_state = state = STATE_DATA_BUSY; 2090 2091 fallthrough; 2092 2093 case STATE_DATA_BUSY: 2094 if (!dw_mci_clear_pending_data_complete(host)) { 2095 /* 2096 * If data error interrupt comes but data over 2097 * interrupt doesn't come within the given time. 2098 * in reading data state. 2099 */ 2100 if (host->dir_status == DW_MCI_RECV_STATUS) 2101 dw_mci_set_drto(host); 2102 break; 2103 } 2104 2105 host->data = NULL; 2106 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2107 err = dw_mci_data_complete(host, data); 2108 2109 if (!err) { 2110 if (!data->stop || mrq->sbc) { 2111 if (mrq->sbc && data->stop) 2112 data->stop->error = 0; 2113 dw_mci_request_end(host, mrq); 2114 goto unlock; 2115 } 2116 2117 /* stop command for open-ended transfer*/ 2118 if (data->stop) 2119 send_stop_abort(host, data); 2120 } else { 2121 /* 2122 * If we don't have a command complete now we'll 2123 * never get one since we just reset everything; 2124 * better end the request. 2125 * 2126 * If we do have a command complete we'll fall 2127 * through to the SENDING_STOP command and 2128 * everything will be peachy keen. 2129 */ 2130 if (!test_bit(EVENT_CMD_COMPLETE, 2131 &host->pending_events)) { 2132 host->cmd = NULL; 2133 dw_mci_request_end(host, mrq); 2134 goto unlock; 2135 } 2136 } 2137 2138 /* 2139 * If err has non-zero, 2140 * stop-abort command has been already issued. 2141 */ 2142 prev_state = state = STATE_SENDING_STOP; 2143 2144 fallthrough; 2145 2146 case STATE_SENDING_STOP: 2147 if (!dw_mci_clear_pending_cmd_complete(host)) 2148 break; 2149 2150 /* CMD error in data command */ 2151 if (mrq->cmd->error && mrq->data) 2152 dw_mci_reset(host); 2153 2154 host->cmd = NULL; 2155 host->data = NULL; 2156 2157 if (!mrq->sbc && mrq->stop) 2158 dw_mci_command_complete(host, mrq->stop); 2159 else 2160 host->cmd_status = 0; 2161 2162 dw_mci_request_end(host, mrq); 2163 goto unlock; 2164 2165 case STATE_DATA_ERROR: 2166 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2167 &host->pending_events)) 2168 break; 2169 2170 state = STATE_DATA_BUSY; 2171 break; 2172 } 2173 } while (state != prev_state); 2174 2175 host->state = state; 2176 unlock: 2177 spin_unlock(&host->lock); 2178 2179 } 2180 2181 /* push final bytes to part_buf, only use during push */ 2182 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2183 { 2184 memcpy((void *)&host->part_buf, buf, cnt); 2185 host->part_buf_count = cnt; 2186 } 2187 2188 /* append bytes to part_buf, only use during push */ 2189 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2190 { 2191 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2192 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2193 host->part_buf_count += cnt; 2194 return cnt; 2195 } 2196 2197 /* pull first bytes from part_buf, only use during pull */ 2198 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2199 { 2200 cnt = min_t(int, cnt, host->part_buf_count); 2201 if (cnt) { 2202 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2203 cnt); 2204 host->part_buf_count -= cnt; 2205 host->part_buf_start += cnt; 2206 } 2207 return cnt; 2208 } 2209 2210 /* pull final bytes from the part_buf, assuming it's just been filled */ 2211 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2212 { 2213 memcpy(buf, &host->part_buf, cnt); 2214 host->part_buf_start = cnt; 2215 host->part_buf_count = (1 << host->data_shift) - cnt; 2216 } 2217 2218 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2219 { 2220 struct mmc_data *data = host->data; 2221 int init_cnt = cnt; 2222 2223 /* try and push anything in the part_buf */ 2224 if (unlikely(host->part_buf_count)) { 2225 int len = dw_mci_push_part_bytes(host, buf, cnt); 2226 2227 buf += len; 2228 cnt -= len; 2229 if (host->part_buf_count == 2) { 2230 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2231 host->part_buf_count = 0; 2232 } 2233 } 2234 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2235 if (unlikely((unsigned long)buf & 0x1)) { 2236 while (cnt >= 2) { 2237 u16 aligned_buf[64]; 2238 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2239 int items = len >> 1; 2240 int i; 2241 /* memcpy from input buffer into aligned buffer */ 2242 memcpy(aligned_buf, buf, len); 2243 buf += len; 2244 cnt -= len; 2245 /* push data from aligned buffer into fifo */ 2246 for (i = 0; i < items; ++i) 2247 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2248 } 2249 } else 2250 #endif 2251 { 2252 u16 *pdata = buf; 2253 2254 for (; cnt >= 2; cnt -= 2) 2255 mci_fifo_writew(host->fifo_reg, *pdata++); 2256 buf = pdata; 2257 } 2258 /* put anything remaining in the part_buf */ 2259 if (cnt) { 2260 dw_mci_set_part_bytes(host, buf, cnt); 2261 /* Push data if we have reached the expected data length */ 2262 if ((data->bytes_xfered + init_cnt) == 2263 (data->blksz * data->blocks)) 2264 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2265 } 2266 } 2267 2268 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2269 { 2270 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2271 if (unlikely((unsigned long)buf & 0x1)) { 2272 while (cnt >= 2) { 2273 /* pull data from fifo into aligned buffer */ 2274 u16 aligned_buf[64]; 2275 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2276 int items = len >> 1; 2277 int i; 2278 2279 for (i = 0; i < items; ++i) 2280 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2281 /* memcpy from aligned buffer into output buffer */ 2282 memcpy(buf, aligned_buf, len); 2283 buf += len; 2284 cnt -= len; 2285 } 2286 } else 2287 #endif 2288 { 2289 u16 *pdata = buf; 2290 2291 for (; cnt >= 2; cnt -= 2) 2292 *pdata++ = mci_fifo_readw(host->fifo_reg); 2293 buf = pdata; 2294 } 2295 if (cnt) { 2296 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2297 dw_mci_pull_final_bytes(host, buf, cnt); 2298 } 2299 } 2300 2301 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2302 { 2303 struct mmc_data *data = host->data; 2304 int init_cnt = cnt; 2305 2306 /* try and push anything in the part_buf */ 2307 if (unlikely(host->part_buf_count)) { 2308 int len = dw_mci_push_part_bytes(host, buf, cnt); 2309 2310 buf += len; 2311 cnt -= len; 2312 if (host->part_buf_count == 4) { 2313 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2314 host->part_buf_count = 0; 2315 } 2316 } 2317 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2318 if (unlikely((unsigned long)buf & 0x3)) { 2319 while (cnt >= 4) { 2320 u32 aligned_buf[32]; 2321 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2322 int items = len >> 2; 2323 int i; 2324 /* memcpy from input buffer into aligned buffer */ 2325 memcpy(aligned_buf, buf, len); 2326 buf += len; 2327 cnt -= len; 2328 /* push data from aligned buffer into fifo */ 2329 for (i = 0; i < items; ++i) 2330 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2331 } 2332 } else 2333 #endif 2334 { 2335 u32 *pdata = buf; 2336 2337 for (; cnt >= 4; cnt -= 4) 2338 mci_fifo_writel(host->fifo_reg, *pdata++); 2339 buf = pdata; 2340 } 2341 /* put anything remaining in the part_buf */ 2342 if (cnt) { 2343 dw_mci_set_part_bytes(host, buf, cnt); 2344 /* Push data if we have reached the expected data length */ 2345 if ((data->bytes_xfered + init_cnt) == 2346 (data->blksz * data->blocks)) 2347 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2348 } 2349 } 2350 2351 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2352 { 2353 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2354 if (unlikely((unsigned long)buf & 0x3)) { 2355 while (cnt >= 4) { 2356 /* pull data from fifo into aligned buffer */ 2357 u32 aligned_buf[32]; 2358 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2359 int items = len >> 2; 2360 int i; 2361 2362 for (i = 0; i < items; ++i) 2363 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2364 /* memcpy from aligned buffer into output buffer */ 2365 memcpy(buf, aligned_buf, len); 2366 buf += len; 2367 cnt -= len; 2368 } 2369 } else 2370 #endif 2371 { 2372 u32 *pdata = buf; 2373 2374 for (; cnt >= 4; cnt -= 4) 2375 *pdata++ = mci_fifo_readl(host->fifo_reg); 2376 buf = pdata; 2377 } 2378 if (cnt) { 2379 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2380 dw_mci_pull_final_bytes(host, buf, cnt); 2381 } 2382 } 2383 2384 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2385 { 2386 struct mmc_data *data = host->data; 2387 int init_cnt = cnt; 2388 2389 /* try and push anything in the part_buf */ 2390 if (unlikely(host->part_buf_count)) { 2391 int len = dw_mci_push_part_bytes(host, buf, cnt); 2392 2393 buf += len; 2394 cnt -= len; 2395 2396 if (host->part_buf_count == 8) { 2397 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2398 host->part_buf_count = 0; 2399 } 2400 } 2401 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2402 if (unlikely((unsigned long)buf & 0x7)) { 2403 while (cnt >= 8) { 2404 u64 aligned_buf[16]; 2405 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2406 int items = len >> 3; 2407 int i; 2408 /* memcpy from input buffer into aligned buffer */ 2409 memcpy(aligned_buf, buf, len); 2410 buf += len; 2411 cnt -= len; 2412 /* push data from aligned buffer into fifo */ 2413 for (i = 0; i < items; ++i) 2414 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2415 } 2416 } else 2417 #endif 2418 { 2419 u64 *pdata = buf; 2420 2421 for (; cnt >= 8; cnt -= 8) 2422 mci_fifo_writeq(host->fifo_reg, *pdata++); 2423 buf = pdata; 2424 } 2425 /* put anything remaining in the part_buf */ 2426 if (cnt) { 2427 dw_mci_set_part_bytes(host, buf, cnt); 2428 /* Push data if we have reached the expected data length */ 2429 if ((data->bytes_xfered + init_cnt) == 2430 (data->blksz * data->blocks)) 2431 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2432 } 2433 } 2434 2435 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2436 { 2437 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2438 if (unlikely((unsigned long)buf & 0x7)) { 2439 while (cnt >= 8) { 2440 /* pull data from fifo into aligned buffer */ 2441 u64 aligned_buf[16]; 2442 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2443 int items = len >> 3; 2444 int i; 2445 2446 for (i = 0; i < items; ++i) 2447 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2448 2449 /* memcpy from aligned buffer into output buffer */ 2450 memcpy(buf, aligned_buf, len); 2451 buf += len; 2452 cnt -= len; 2453 } 2454 } else 2455 #endif 2456 { 2457 u64 *pdata = buf; 2458 2459 for (; cnt >= 8; cnt -= 8) 2460 *pdata++ = mci_fifo_readq(host->fifo_reg); 2461 buf = pdata; 2462 } 2463 if (cnt) { 2464 host->part_buf = mci_fifo_readq(host->fifo_reg); 2465 dw_mci_pull_final_bytes(host, buf, cnt); 2466 } 2467 } 2468 2469 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2470 { 2471 int len; 2472 2473 /* get remaining partial bytes */ 2474 len = dw_mci_pull_part_bytes(host, buf, cnt); 2475 if (unlikely(len == cnt)) 2476 return; 2477 buf += len; 2478 cnt -= len; 2479 2480 /* get the rest of the data */ 2481 host->pull_data(host, buf, cnt); 2482 } 2483 2484 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2485 { 2486 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2487 void *buf; 2488 unsigned int offset; 2489 struct mmc_data *data = host->data; 2490 int shift = host->data_shift; 2491 u32 status; 2492 unsigned int len; 2493 unsigned int remain, fcnt; 2494 2495 do { 2496 if (!sg_miter_next(sg_miter)) 2497 goto done; 2498 2499 host->sg = sg_miter->piter.sg; 2500 buf = sg_miter->addr; 2501 remain = sg_miter->length; 2502 offset = 0; 2503 2504 do { 2505 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2506 << shift) + host->part_buf_count; 2507 len = min(remain, fcnt); 2508 if (!len) 2509 break; 2510 dw_mci_pull_data(host, (void *)(buf + offset), len); 2511 data->bytes_xfered += len; 2512 offset += len; 2513 remain -= len; 2514 } while (remain); 2515 2516 sg_miter->consumed = offset; 2517 status = mci_readl(host, MINTSTS); 2518 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2519 /* if the RXDR is ready read again */ 2520 } while ((status & SDMMC_INT_RXDR) || 2521 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2522 2523 if (!remain) { 2524 if (!sg_miter_next(sg_miter)) 2525 goto done; 2526 sg_miter->consumed = 0; 2527 } 2528 sg_miter_stop(sg_miter); 2529 return; 2530 2531 done: 2532 sg_miter_stop(sg_miter); 2533 host->sg = NULL; 2534 smp_wmb(); /* drain writebuffer */ 2535 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2536 } 2537 2538 static void dw_mci_write_data_pio(struct dw_mci *host) 2539 { 2540 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2541 void *buf; 2542 unsigned int offset; 2543 struct mmc_data *data = host->data; 2544 int shift = host->data_shift; 2545 u32 status; 2546 unsigned int len; 2547 unsigned int fifo_depth = host->fifo_depth; 2548 unsigned int remain, fcnt; 2549 2550 do { 2551 if (!sg_miter_next(sg_miter)) 2552 goto done; 2553 2554 host->sg = sg_miter->piter.sg; 2555 buf = sg_miter->addr; 2556 remain = sg_miter->length; 2557 offset = 0; 2558 2559 do { 2560 fcnt = ((fifo_depth - 2561 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2562 << shift) - host->part_buf_count; 2563 len = min(remain, fcnt); 2564 if (!len) 2565 break; 2566 host->push_data(host, (void *)(buf + offset), len); 2567 data->bytes_xfered += len; 2568 offset += len; 2569 remain -= len; 2570 } while (remain); 2571 2572 sg_miter->consumed = offset; 2573 status = mci_readl(host, MINTSTS); 2574 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2575 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2576 2577 if (!remain) { 2578 if (!sg_miter_next(sg_miter)) 2579 goto done; 2580 sg_miter->consumed = 0; 2581 } 2582 sg_miter_stop(sg_miter); 2583 return; 2584 2585 done: 2586 sg_miter_stop(sg_miter); 2587 host->sg = NULL; 2588 smp_wmb(); /* drain writebuffer */ 2589 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2590 } 2591 2592 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2593 { 2594 del_timer(&host->cto_timer); 2595 2596 if (!host->cmd_status) 2597 host->cmd_status = status; 2598 2599 smp_wmb(); /* drain writebuffer */ 2600 2601 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2602 tasklet_schedule(&host->tasklet); 2603 } 2604 2605 static void dw_mci_handle_cd(struct dw_mci *host) 2606 { 2607 struct dw_mci_slot *slot = host->slot; 2608 2609 if (slot->mmc->ops->card_event) 2610 slot->mmc->ops->card_event(slot->mmc); 2611 mmc_detect_change(slot->mmc, 2612 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2613 } 2614 2615 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2616 { 2617 struct dw_mci *host = dev_id; 2618 u32 pending; 2619 struct dw_mci_slot *slot = host->slot; 2620 2621 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2622 2623 if (pending) { 2624 /* Check volt switch first, since it can look like an error */ 2625 if ((host->state == STATE_SENDING_CMD11) && 2626 (pending & SDMMC_INT_VOLT_SWITCH)) { 2627 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2628 pending &= ~SDMMC_INT_VOLT_SWITCH; 2629 2630 /* 2631 * Hold the lock; we know cmd11_timer can't be kicked 2632 * off after the lock is released, so safe to delete. 2633 */ 2634 spin_lock(&host->irq_lock); 2635 dw_mci_cmd_interrupt(host, pending); 2636 spin_unlock(&host->irq_lock); 2637 2638 del_timer(&host->cmd11_timer); 2639 } 2640 2641 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2642 spin_lock(&host->irq_lock); 2643 2644 del_timer(&host->cto_timer); 2645 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2646 host->cmd_status = pending; 2647 smp_wmb(); /* drain writebuffer */ 2648 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2649 2650 spin_unlock(&host->irq_lock); 2651 } 2652 2653 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2654 /* if there is an error report DATA_ERROR */ 2655 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2656 host->data_status = pending; 2657 smp_wmb(); /* drain writebuffer */ 2658 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2659 tasklet_schedule(&host->tasklet); 2660 } 2661 2662 if (pending & SDMMC_INT_DATA_OVER) { 2663 spin_lock(&host->irq_lock); 2664 2665 del_timer(&host->dto_timer); 2666 2667 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2668 if (!host->data_status) 2669 host->data_status = pending; 2670 smp_wmb(); /* drain writebuffer */ 2671 if (host->dir_status == DW_MCI_RECV_STATUS) { 2672 if (host->sg != NULL) 2673 dw_mci_read_data_pio(host, true); 2674 } 2675 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2676 tasklet_schedule(&host->tasklet); 2677 2678 spin_unlock(&host->irq_lock); 2679 } 2680 2681 if (pending & SDMMC_INT_RXDR) { 2682 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2683 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2684 dw_mci_read_data_pio(host, false); 2685 } 2686 2687 if (pending & SDMMC_INT_TXDR) { 2688 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2689 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2690 dw_mci_write_data_pio(host); 2691 } 2692 2693 if (pending & SDMMC_INT_CMD_DONE) { 2694 spin_lock(&host->irq_lock); 2695 2696 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2697 dw_mci_cmd_interrupt(host, pending); 2698 2699 spin_unlock(&host->irq_lock); 2700 } 2701 2702 if (pending & SDMMC_INT_CD) { 2703 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2704 dw_mci_handle_cd(host); 2705 } 2706 2707 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2708 mci_writel(host, RINTSTS, 2709 SDMMC_INT_SDIO(slot->sdio_id)); 2710 __dw_mci_enable_sdio_irq(slot, 0); 2711 sdio_signal_irq(slot->mmc); 2712 } 2713 2714 } 2715 2716 if (host->use_dma != TRANS_MODE_IDMAC) 2717 return IRQ_HANDLED; 2718 2719 /* Handle IDMA interrupts */ 2720 if (host->dma_64bit_address == 1) { 2721 pending = mci_readl(host, IDSTS64); 2722 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2723 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2724 SDMMC_IDMAC_INT_RI); 2725 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2726 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2727 host->dma_ops->complete((void *)host); 2728 } 2729 } else { 2730 pending = mci_readl(host, IDSTS); 2731 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2732 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2733 SDMMC_IDMAC_INT_RI); 2734 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2735 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2736 host->dma_ops->complete((void *)host); 2737 } 2738 } 2739 2740 return IRQ_HANDLED; 2741 } 2742 2743 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) 2744 { 2745 struct dw_mci *host = slot->host; 2746 const struct dw_mci_drv_data *drv_data = host->drv_data; 2747 struct mmc_host *mmc = slot->mmc; 2748 int ctrl_id; 2749 2750 if (host->pdata->caps) 2751 mmc->caps = host->pdata->caps; 2752 2753 if (host->pdata->pm_caps) 2754 mmc->pm_caps = host->pdata->pm_caps; 2755 2756 if (host->dev->of_node) { 2757 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2758 if (ctrl_id < 0) 2759 ctrl_id = 0; 2760 } else { 2761 ctrl_id = to_platform_device(host->dev)->id; 2762 } 2763 2764 if (drv_data && drv_data->caps) { 2765 if (ctrl_id >= drv_data->num_caps) { 2766 dev_err(host->dev, "invalid controller id %d\n", 2767 ctrl_id); 2768 return -EINVAL; 2769 } 2770 mmc->caps |= drv_data->caps[ctrl_id]; 2771 } 2772 2773 if (host->pdata->caps2) 2774 mmc->caps2 = host->pdata->caps2; 2775 2776 mmc->f_min = DW_MCI_FREQ_MIN; 2777 if (!mmc->f_max) 2778 mmc->f_max = DW_MCI_FREQ_MAX; 2779 2780 /* Process SDIO IRQs through the sdio_irq_work. */ 2781 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2782 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2783 2784 return 0; 2785 } 2786 2787 static int dw_mci_init_slot(struct dw_mci *host) 2788 { 2789 struct mmc_host *mmc; 2790 struct dw_mci_slot *slot; 2791 int ret; 2792 2793 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2794 if (!mmc) 2795 return -ENOMEM; 2796 2797 slot = mmc_priv(mmc); 2798 slot->id = 0; 2799 slot->sdio_id = host->sdio_id0 + slot->id; 2800 slot->mmc = mmc; 2801 slot->host = host; 2802 host->slot = slot; 2803 2804 mmc->ops = &dw_mci_ops; 2805 2806 /*if there are external regulators, get them*/ 2807 ret = mmc_regulator_get_supply(mmc); 2808 if (ret) 2809 goto err_host_allocated; 2810 2811 if (!mmc->ocr_avail) 2812 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2813 2814 ret = mmc_of_parse(mmc); 2815 if (ret) 2816 goto err_host_allocated; 2817 2818 ret = dw_mci_init_slot_caps(slot); 2819 if (ret) 2820 goto err_host_allocated; 2821 2822 /* Useful defaults if platform data is unset. */ 2823 if (host->use_dma == TRANS_MODE_IDMAC) { 2824 mmc->max_segs = host->ring_size; 2825 mmc->max_blk_size = 65535; 2826 mmc->max_seg_size = 0x1000; 2827 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2828 mmc->max_blk_count = mmc->max_req_size / 512; 2829 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2830 mmc->max_segs = 64; 2831 mmc->max_blk_size = 65535; 2832 mmc->max_blk_count = 65535; 2833 mmc->max_req_size = 2834 mmc->max_blk_size * mmc->max_blk_count; 2835 mmc->max_seg_size = mmc->max_req_size; 2836 } else { 2837 /* TRANS_MODE_PIO */ 2838 mmc->max_segs = 64; 2839 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2840 mmc->max_blk_count = 512; 2841 mmc->max_req_size = mmc->max_blk_size * 2842 mmc->max_blk_count; 2843 mmc->max_seg_size = mmc->max_req_size; 2844 } 2845 2846 dw_mci_get_cd(mmc); 2847 2848 ret = mmc_add_host(mmc); 2849 if (ret) 2850 goto err_host_allocated; 2851 2852 #if defined(CONFIG_DEBUG_FS) 2853 dw_mci_init_debugfs(slot); 2854 #endif 2855 2856 return 0; 2857 2858 err_host_allocated: 2859 mmc_free_host(mmc); 2860 return ret; 2861 } 2862 2863 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2864 { 2865 /* Debugfs stuff is cleaned up by mmc core */ 2866 mmc_remove_host(slot->mmc); 2867 slot->host->slot = NULL; 2868 mmc_free_host(slot->mmc); 2869 } 2870 2871 static void dw_mci_init_dma(struct dw_mci *host) 2872 { 2873 int addr_config; 2874 struct device *dev = host->dev; 2875 2876 /* 2877 * Check tansfer mode from HCON[17:16] 2878 * Clear the ambiguous description of dw_mmc databook: 2879 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2880 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2881 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2882 * 2b'11: Non DW DMA Interface -> pio only 2883 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2884 * simpler request/acknowledge handshake mechanism and both of them 2885 * are regarded as external dma master for dw_mmc. 2886 */ 2887 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2888 if (host->use_dma == DMA_INTERFACE_IDMA) { 2889 host->use_dma = TRANS_MODE_IDMAC; 2890 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2891 host->use_dma == DMA_INTERFACE_GDMA) { 2892 host->use_dma = TRANS_MODE_EDMAC; 2893 } else { 2894 goto no_dma; 2895 } 2896 2897 /* Determine which DMA interface to use */ 2898 if (host->use_dma == TRANS_MODE_IDMAC) { 2899 /* 2900 * Check ADDR_CONFIG bit in HCON to find 2901 * IDMAC address bus width 2902 */ 2903 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2904 2905 if (addr_config == 1) { 2906 /* host supports IDMAC in 64-bit address mode */ 2907 host->dma_64bit_address = 1; 2908 dev_info(host->dev, 2909 "IDMAC supports 64-bit address mode.\n"); 2910 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2911 dma_set_coherent_mask(host->dev, 2912 DMA_BIT_MASK(64)); 2913 } else { 2914 /* host supports IDMAC in 32-bit address mode */ 2915 host->dma_64bit_address = 0; 2916 dev_info(host->dev, 2917 "IDMAC supports 32-bit address mode.\n"); 2918 } 2919 2920 /* Alloc memory for sg translation */ 2921 host->sg_cpu = dmam_alloc_coherent(host->dev, 2922 DESC_RING_BUF_SZ, 2923 &host->sg_dma, GFP_KERNEL); 2924 if (!host->sg_cpu) { 2925 dev_err(host->dev, 2926 "%s: could not alloc DMA memory\n", 2927 __func__); 2928 goto no_dma; 2929 } 2930 2931 host->dma_ops = &dw_mci_idmac_ops; 2932 dev_info(host->dev, "Using internal DMA controller.\n"); 2933 } else { 2934 /* TRANS_MODE_EDMAC: check dma bindings again */ 2935 if ((device_property_read_string_array(dev, "dma-names", 2936 NULL, 0) < 0) || 2937 !device_property_present(dev, "dmas")) { 2938 goto no_dma; 2939 } 2940 host->dma_ops = &dw_mci_edmac_ops; 2941 dev_info(host->dev, "Using external DMA controller.\n"); 2942 } 2943 2944 if (host->dma_ops->init && host->dma_ops->start && 2945 host->dma_ops->stop && host->dma_ops->cleanup) { 2946 if (host->dma_ops->init(host)) { 2947 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2948 __func__); 2949 goto no_dma; 2950 } 2951 } else { 2952 dev_err(host->dev, "DMA initialization not found.\n"); 2953 goto no_dma; 2954 } 2955 2956 return; 2957 2958 no_dma: 2959 dev_info(host->dev, "Using PIO mode.\n"); 2960 host->use_dma = TRANS_MODE_PIO; 2961 } 2962 2963 static void dw_mci_cmd11_timer(struct timer_list *t) 2964 { 2965 struct dw_mci *host = from_timer(host, t, cmd11_timer); 2966 2967 if (host->state != STATE_SENDING_CMD11) { 2968 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2969 return; 2970 } 2971 2972 host->cmd_status = SDMMC_INT_RTO; 2973 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2974 tasklet_schedule(&host->tasklet); 2975 } 2976 2977 static void dw_mci_cto_timer(struct timer_list *t) 2978 { 2979 struct dw_mci *host = from_timer(host, t, cto_timer); 2980 unsigned long irqflags; 2981 u32 pending; 2982 2983 spin_lock_irqsave(&host->irq_lock, irqflags); 2984 2985 /* 2986 * If somehow we have very bad interrupt latency it's remotely possible 2987 * that the timer could fire while the interrupt is still pending or 2988 * while the interrupt is midway through running. Let's be paranoid 2989 * and detect those two cases. Note that this is paranoia is somewhat 2990 * justified because in this function we don't actually cancel the 2991 * pending command in the controller--we just assume it will never come. 2992 */ 2993 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2994 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 2995 /* The interrupt should fire; no need to act but we can warn */ 2996 dev_warn(host->dev, "Unexpected interrupt latency\n"); 2997 goto exit; 2998 } 2999 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 3000 /* Presumably interrupt handler couldn't delete the timer */ 3001 dev_warn(host->dev, "CTO timeout when already completed\n"); 3002 goto exit; 3003 } 3004 3005 /* 3006 * Continued paranoia to make sure we're in the state we expect. 3007 * This paranoia isn't really justified but it seems good to be safe. 3008 */ 3009 switch (host->state) { 3010 case STATE_SENDING_CMD11: 3011 case STATE_SENDING_CMD: 3012 case STATE_SENDING_STOP: 3013 /* 3014 * If CMD_DONE interrupt does NOT come in sending command 3015 * state, we should notify the driver to terminate current 3016 * transfer and report a command timeout to the core. 3017 */ 3018 host->cmd_status = SDMMC_INT_RTO; 3019 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3020 tasklet_schedule(&host->tasklet); 3021 break; 3022 default: 3023 dev_warn(host->dev, "Unexpected command timeout, state %d\n", 3024 host->state); 3025 break; 3026 } 3027 3028 exit: 3029 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3030 } 3031 3032 static void dw_mci_dto_timer(struct timer_list *t) 3033 { 3034 struct dw_mci *host = from_timer(host, t, dto_timer); 3035 unsigned long irqflags; 3036 u32 pending; 3037 3038 spin_lock_irqsave(&host->irq_lock, irqflags); 3039 3040 /* 3041 * The DTO timer is much longer than the CTO timer, so it's even less 3042 * likely that we'll these cases, but it pays to be paranoid. 3043 */ 3044 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3045 if (pending & SDMMC_INT_DATA_OVER) { 3046 /* The interrupt should fire; no need to act but we can warn */ 3047 dev_warn(host->dev, "Unexpected data interrupt latency\n"); 3048 goto exit; 3049 } 3050 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 3051 /* Presumably interrupt handler couldn't delete the timer */ 3052 dev_warn(host->dev, "DTO timeout when already completed\n"); 3053 goto exit; 3054 } 3055 3056 /* 3057 * Continued paranoia to make sure we're in the state we expect. 3058 * This paranoia isn't really justified but it seems good to be safe. 3059 */ 3060 switch (host->state) { 3061 case STATE_SENDING_DATA: 3062 case STATE_DATA_BUSY: 3063 /* 3064 * If DTO interrupt does NOT come in sending data state, 3065 * we should notify the driver to terminate current transfer 3066 * and report a data timeout to the core. 3067 */ 3068 host->data_status = SDMMC_INT_DRTO; 3069 set_bit(EVENT_DATA_ERROR, &host->pending_events); 3070 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 3071 tasklet_schedule(&host->tasklet); 3072 break; 3073 default: 3074 dev_warn(host->dev, "Unexpected data timeout, state %d\n", 3075 host->state); 3076 break; 3077 } 3078 3079 exit: 3080 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3081 } 3082 3083 #ifdef CONFIG_OF 3084 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3085 { 3086 struct dw_mci_board *pdata; 3087 struct device *dev = host->dev; 3088 const struct dw_mci_drv_data *drv_data = host->drv_data; 3089 int ret; 3090 u32 clock_frequency; 3091 3092 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3093 if (!pdata) 3094 return ERR_PTR(-ENOMEM); 3095 3096 /* find reset controller when exist */ 3097 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3098 if (IS_ERR(pdata->rstc)) { 3099 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3100 return ERR_PTR(-EPROBE_DEFER); 3101 } 3102 3103 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 3104 dev_info(dev, 3105 "fifo-depth property not found, using value of FIFOTH register as default\n"); 3106 3107 device_property_read_u32(dev, "card-detect-delay", 3108 &pdata->detect_delay_ms); 3109 3110 device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3111 3112 if (device_property_present(dev, "fifo-watermark-aligned")) 3113 host->wm_aligned = true; 3114 3115 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 3116 pdata->bus_hz = clock_frequency; 3117 3118 if (drv_data && drv_data->parse_dt) { 3119 ret = drv_data->parse_dt(host); 3120 if (ret) 3121 return ERR_PTR(ret); 3122 } 3123 3124 return pdata; 3125 } 3126 3127 #else /* CONFIG_OF */ 3128 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3129 { 3130 return ERR_PTR(-EINVAL); 3131 } 3132 #endif /* CONFIG_OF */ 3133 3134 static void dw_mci_enable_cd(struct dw_mci *host) 3135 { 3136 unsigned long irqflags; 3137 u32 temp; 3138 3139 /* 3140 * No need for CD if all slots have a non-error GPIO 3141 * as well as broken card detection is found. 3142 */ 3143 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3144 return; 3145 3146 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3147 spin_lock_irqsave(&host->irq_lock, irqflags); 3148 temp = mci_readl(host, INTMASK); 3149 temp |= SDMMC_INT_CD; 3150 mci_writel(host, INTMASK, temp); 3151 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3152 } 3153 } 3154 3155 int dw_mci_probe(struct dw_mci *host) 3156 { 3157 const struct dw_mci_drv_data *drv_data = host->drv_data; 3158 int width, i, ret = 0; 3159 u32 fifo_size; 3160 3161 if (!host->pdata) { 3162 host->pdata = dw_mci_parse_dt(host); 3163 if (IS_ERR(host->pdata)) 3164 return dev_err_probe(host->dev, PTR_ERR(host->pdata), 3165 "platform data not available\n"); 3166 } 3167 3168 host->biu_clk = devm_clk_get(host->dev, "biu"); 3169 if (IS_ERR(host->biu_clk)) { 3170 dev_dbg(host->dev, "biu clock not available\n"); 3171 } else { 3172 ret = clk_prepare_enable(host->biu_clk); 3173 if (ret) { 3174 dev_err(host->dev, "failed to enable biu clock\n"); 3175 return ret; 3176 } 3177 } 3178 3179 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3180 if (IS_ERR(host->ciu_clk)) { 3181 dev_dbg(host->dev, "ciu clock not available\n"); 3182 host->bus_hz = host->pdata->bus_hz; 3183 } else { 3184 ret = clk_prepare_enable(host->ciu_clk); 3185 if (ret) { 3186 dev_err(host->dev, "failed to enable ciu clock\n"); 3187 goto err_clk_biu; 3188 } 3189 3190 if (host->pdata->bus_hz) { 3191 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3192 if (ret) 3193 dev_warn(host->dev, 3194 "Unable to set bus rate to %uHz\n", 3195 host->pdata->bus_hz); 3196 } 3197 host->bus_hz = clk_get_rate(host->ciu_clk); 3198 } 3199 3200 if (!host->bus_hz) { 3201 dev_err(host->dev, 3202 "Platform data must supply bus speed\n"); 3203 ret = -ENODEV; 3204 goto err_clk_ciu; 3205 } 3206 3207 if (!IS_ERR(host->pdata->rstc)) { 3208 reset_control_assert(host->pdata->rstc); 3209 usleep_range(10, 50); 3210 reset_control_deassert(host->pdata->rstc); 3211 } 3212 3213 if (drv_data && drv_data->init) { 3214 ret = drv_data->init(host); 3215 if (ret) { 3216 dev_err(host->dev, 3217 "implementation specific init failed\n"); 3218 goto err_clk_ciu; 3219 } 3220 } 3221 3222 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 3223 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 3224 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 3225 3226 spin_lock_init(&host->lock); 3227 spin_lock_init(&host->irq_lock); 3228 INIT_LIST_HEAD(&host->queue); 3229 3230 /* 3231 * Get the host data width - this assumes that HCON has been set with 3232 * the correct values. 3233 */ 3234 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3235 if (!i) { 3236 host->push_data = dw_mci_push_data16; 3237 host->pull_data = dw_mci_pull_data16; 3238 width = 16; 3239 host->data_shift = 1; 3240 } else if (i == 2) { 3241 host->push_data = dw_mci_push_data64; 3242 host->pull_data = dw_mci_pull_data64; 3243 width = 64; 3244 host->data_shift = 3; 3245 } else { 3246 /* Check for a reserved value, and warn if it is */ 3247 WARN((i != 1), 3248 "HCON reports a reserved host data width!\n" 3249 "Defaulting to 32-bit access.\n"); 3250 host->push_data = dw_mci_push_data32; 3251 host->pull_data = dw_mci_pull_data32; 3252 width = 32; 3253 host->data_shift = 2; 3254 } 3255 3256 /* Reset all blocks */ 3257 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3258 ret = -ENODEV; 3259 goto err_clk_ciu; 3260 } 3261 3262 host->dma_ops = host->pdata->dma_ops; 3263 dw_mci_init_dma(host); 3264 3265 /* Clear the interrupts for the host controller */ 3266 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3267 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3268 3269 /* Put in max timeout */ 3270 mci_writel(host, TMOUT, 0xFFFFFFFF); 3271 3272 /* 3273 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3274 * Tx Mark = fifo_size / 2 DMA Size = 8 3275 */ 3276 if (!host->pdata->fifo_depth) { 3277 /* 3278 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3279 * have been overwritten by the bootloader, just like we're 3280 * about to do, so if you know the value for your hardware, you 3281 * should put it in the platform data. 3282 */ 3283 fifo_size = mci_readl(host, FIFOTH); 3284 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3285 } else { 3286 fifo_size = host->pdata->fifo_depth; 3287 } 3288 host->fifo_depth = fifo_size; 3289 host->fifoth_val = 3290 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3291 mci_writel(host, FIFOTH, host->fifoth_val); 3292 3293 /* disable clock to CIU */ 3294 mci_writel(host, CLKENA, 0); 3295 mci_writel(host, CLKSRC, 0); 3296 3297 /* 3298 * In 2.40a spec, Data offset is changed. 3299 * Need to check the version-id and set data-offset for DATA register. 3300 */ 3301 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3302 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3303 3304 if (host->data_addr_override) 3305 host->fifo_reg = host->regs + host->data_addr_override; 3306 else if (host->verid < DW_MMC_240A) 3307 host->fifo_reg = host->regs + DATA_OFFSET; 3308 else 3309 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3310 3311 tasklet_setup(&host->tasklet, dw_mci_tasklet_func); 3312 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3313 host->irq_flags, "dw-mci", host); 3314 if (ret) 3315 goto err_dmaunmap; 3316 3317 /* 3318 * Enable interrupts for command done, data over, data empty, 3319 * receive ready and error such as transmit, receive timeout, crc error 3320 */ 3321 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3322 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3323 DW_MCI_ERROR_FLAGS); 3324 /* Enable mci interrupt */ 3325 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3326 3327 dev_info(host->dev, 3328 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3329 host->irq, width, fifo_size); 3330 3331 /* We need at least one slot to succeed */ 3332 ret = dw_mci_init_slot(host); 3333 if (ret) { 3334 dev_dbg(host->dev, "slot %d init failed\n", i); 3335 goto err_dmaunmap; 3336 } 3337 3338 /* Now that slots are all setup, we can enable card detect */ 3339 dw_mci_enable_cd(host); 3340 3341 return 0; 3342 3343 err_dmaunmap: 3344 if (host->use_dma && host->dma_ops->exit) 3345 host->dma_ops->exit(host); 3346 3347 if (!IS_ERR(host->pdata->rstc)) 3348 reset_control_assert(host->pdata->rstc); 3349 3350 err_clk_ciu: 3351 clk_disable_unprepare(host->ciu_clk); 3352 3353 err_clk_biu: 3354 clk_disable_unprepare(host->biu_clk); 3355 3356 return ret; 3357 } 3358 EXPORT_SYMBOL(dw_mci_probe); 3359 3360 void dw_mci_remove(struct dw_mci *host) 3361 { 3362 dev_dbg(host->dev, "remove slot\n"); 3363 if (host->slot) 3364 dw_mci_cleanup_slot(host->slot); 3365 3366 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3367 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3368 3369 /* disable clock to CIU */ 3370 mci_writel(host, CLKENA, 0); 3371 mci_writel(host, CLKSRC, 0); 3372 3373 if (host->use_dma && host->dma_ops->exit) 3374 host->dma_ops->exit(host); 3375 3376 if (!IS_ERR(host->pdata->rstc)) 3377 reset_control_assert(host->pdata->rstc); 3378 3379 clk_disable_unprepare(host->ciu_clk); 3380 clk_disable_unprepare(host->biu_clk); 3381 } 3382 EXPORT_SYMBOL(dw_mci_remove); 3383 3384 3385 3386 #ifdef CONFIG_PM 3387 int dw_mci_runtime_suspend(struct device *dev) 3388 { 3389 struct dw_mci *host = dev_get_drvdata(dev); 3390 3391 if (host->use_dma && host->dma_ops->exit) 3392 host->dma_ops->exit(host); 3393 3394 clk_disable_unprepare(host->ciu_clk); 3395 3396 if (host->slot && 3397 (mmc_can_gpio_cd(host->slot->mmc) || 3398 !mmc_card_is_removable(host->slot->mmc))) 3399 clk_disable_unprepare(host->biu_clk); 3400 3401 return 0; 3402 } 3403 EXPORT_SYMBOL(dw_mci_runtime_suspend); 3404 3405 int dw_mci_runtime_resume(struct device *dev) 3406 { 3407 int ret = 0; 3408 struct dw_mci *host = dev_get_drvdata(dev); 3409 3410 if (host->slot && 3411 (mmc_can_gpio_cd(host->slot->mmc) || 3412 !mmc_card_is_removable(host->slot->mmc))) { 3413 ret = clk_prepare_enable(host->biu_clk); 3414 if (ret) 3415 return ret; 3416 } 3417 3418 ret = clk_prepare_enable(host->ciu_clk); 3419 if (ret) 3420 goto err; 3421 3422 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3423 clk_disable_unprepare(host->ciu_clk); 3424 ret = -ENODEV; 3425 goto err; 3426 } 3427 3428 if (host->use_dma && host->dma_ops->init) 3429 host->dma_ops->init(host); 3430 3431 /* 3432 * Restore the initial value at FIFOTH register 3433 * And Invalidate the prev_blksz with zero 3434 */ 3435 mci_writel(host, FIFOTH, host->fifoth_val); 3436 host->prev_blksz = 0; 3437 3438 /* Put in max timeout */ 3439 mci_writel(host, TMOUT, 0xFFFFFFFF); 3440 3441 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3442 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3443 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3444 DW_MCI_ERROR_FLAGS); 3445 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3446 3447 3448 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3449 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3450 3451 /* Force setup bus to guarantee available clock output */ 3452 dw_mci_setup_bus(host->slot, true); 3453 3454 /* Re-enable SDIO interrupts. */ 3455 if (sdio_irq_claimed(host->slot->mmc)) 3456 __dw_mci_enable_sdio_irq(host->slot, 1); 3457 3458 /* Now that slots are all setup, we can enable card detect */ 3459 dw_mci_enable_cd(host); 3460 3461 return 0; 3462 3463 err: 3464 if (host->slot && 3465 (mmc_can_gpio_cd(host->slot->mmc) || 3466 !mmc_card_is_removable(host->slot->mmc))) 3467 clk_disable_unprepare(host->biu_clk); 3468 3469 return ret; 3470 } 3471 EXPORT_SYMBOL(dw_mci_runtime_resume); 3472 #endif /* CONFIG_PM */ 3473 3474 static int __init dw_mci_init(void) 3475 { 3476 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3477 return 0; 3478 } 3479 3480 static void __exit dw_mci_exit(void) 3481 { 3482 } 3483 3484 module_init(dw_mci_init); 3485 module_exit(dw_mci_exit); 3486 3487 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3488 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3489 MODULE_AUTHOR("Imagination Technologies Ltd"); 3490 MODULE_LICENSE("GPL v2"); 3491