1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/ioport.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/stat.h> 28 #include <linux/delay.h> 29 #include <linux/irq.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/dw_mmc.h> 33 #include <linux/bitops.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/workqueue.h> 36 #include <linux/of.h> 37 38 #include "dw_mmc.h" 39 40 /* Common flag combinations */ 41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \ 42 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 43 SDMMC_INT_EBE) 44 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 45 SDMMC_INT_RESP_ERR) 46 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 47 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 48 #define DW_MCI_SEND_STATUS 1 49 #define DW_MCI_RECV_STATUS 2 50 #define DW_MCI_DMA_THRESHOLD 16 51 52 #ifdef CONFIG_MMC_DW_IDMAC 53 struct idmac_desc { 54 u32 des0; /* Control Descriptor */ 55 #define IDMAC_DES0_DIC BIT(1) 56 #define IDMAC_DES0_LD BIT(2) 57 #define IDMAC_DES0_FD BIT(3) 58 #define IDMAC_DES0_CH BIT(4) 59 #define IDMAC_DES0_ER BIT(5) 60 #define IDMAC_DES0_CES BIT(30) 61 #define IDMAC_DES0_OWN BIT(31) 62 63 u32 des1; /* Buffer sizes */ 64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 65 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 66 67 u32 des2; /* buffer 1 physical address */ 68 69 u32 des3; /* buffer 2 physical address */ 70 }; 71 #endif /* CONFIG_MMC_DW_IDMAC */ 72 73 /** 74 * struct dw_mci_slot - MMC slot state 75 * @mmc: The mmc_host representing this slot. 76 * @host: The MMC controller this slot is using. 77 * @ctype: Card type for this slot. 78 * @mrq: mmc_request currently being processed or waiting to be 79 * processed, or NULL when the slot is idle. 80 * @queue_node: List node for placing this node in the @queue list of 81 * &struct dw_mci. 82 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 83 * @flags: Random state bits associated with the slot. 84 * @id: Number of this slot. 85 * @last_detect_state: Most recently observed card detect state. 86 */ 87 struct dw_mci_slot { 88 struct mmc_host *mmc; 89 struct dw_mci *host; 90 91 u32 ctype; 92 93 struct mmc_request *mrq; 94 struct list_head queue_node; 95 96 unsigned int clock; 97 unsigned long flags; 98 #define DW_MMC_CARD_PRESENT 0 99 #define DW_MMC_CARD_NEED_INIT 1 100 int id; 101 int last_detect_state; 102 }; 103 104 #if defined(CONFIG_DEBUG_FS) 105 static int dw_mci_req_show(struct seq_file *s, void *v) 106 { 107 struct dw_mci_slot *slot = s->private; 108 struct mmc_request *mrq; 109 struct mmc_command *cmd; 110 struct mmc_command *stop; 111 struct mmc_data *data; 112 113 /* Make sure we get a consistent snapshot */ 114 spin_lock_bh(&slot->host->lock); 115 mrq = slot->mrq; 116 117 if (mrq) { 118 cmd = mrq->cmd; 119 data = mrq->data; 120 stop = mrq->stop; 121 122 if (cmd) 123 seq_printf(s, 124 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 125 cmd->opcode, cmd->arg, cmd->flags, 126 cmd->resp[0], cmd->resp[1], cmd->resp[2], 127 cmd->resp[2], cmd->error); 128 if (data) 129 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 130 data->bytes_xfered, data->blocks, 131 data->blksz, data->flags, data->error); 132 if (stop) 133 seq_printf(s, 134 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 135 stop->opcode, stop->arg, stop->flags, 136 stop->resp[0], stop->resp[1], stop->resp[2], 137 stop->resp[2], stop->error); 138 } 139 140 spin_unlock_bh(&slot->host->lock); 141 142 return 0; 143 } 144 145 static int dw_mci_req_open(struct inode *inode, struct file *file) 146 { 147 return single_open(file, dw_mci_req_show, inode->i_private); 148 } 149 150 static const struct file_operations dw_mci_req_fops = { 151 .owner = THIS_MODULE, 152 .open = dw_mci_req_open, 153 .read = seq_read, 154 .llseek = seq_lseek, 155 .release = single_release, 156 }; 157 158 static int dw_mci_regs_show(struct seq_file *s, void *v) 159 { 160 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 161 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 162 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 163 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 164 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 165 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 166 167 return 0; 168 } 169 170 static int dw_mci_regs_open(struct inode *inode, struct file *file) 171 { 172 return single_open(file, dw_mci_regs_show, inode->i_private); 173 } 174 175 static const struct file_operations dw_mci_regs_fops = { 176 .owner = THIS_MODULE, 177 .open = dw_mci_regs_open, 178 .read = seq_read, 179 .llseek = seq_lseek, 180 .release = single_release, 181 }; 182 183 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 184 { 185 struct mmc_host *mmc = slot->mmc; 186 struct dw_mci *host = slot->host; 187 struct dentry *root; 188 struct dentry *node; 189 190 root = mmc->debugfs_root; 191 if (!root) 192 return; 193 194 node = debugfs_create_file("regs", S_IRUSR, root, host, 195 &dw_mci_regs_fops); 196 if (!node) 197 goto err; 198 199 node = debugfs_create_file("req", S_IRUSR, root, slot, 200 &dw_mci_req_fops); 201 if (!node) 202 goto err; 203 204 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 205 if (!node) 206 goto err; 207 208 node = debugfs_create_x32("pending_events", S_IRUSR, root, 209 (u32 *)&host->pending_events); 210 if (!node) 211 goto err; 212 213 node = debugfs_create_x32("completed_events", S_IRUSR, root, 214 (u32 *)&host->completed_events); 215 if (!node) 216 goto err; 217 218 return; 219 220 err: 221 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 222 } 223 #endif /* defined(CONFIG_DEBUG_FS) */ 224 225 static void dw_mci_set_timeout(struct dw_mci *host) 226 { 227 /* timeout (maximum) */ 228 mci_writel(host, TMOUT, 0xffffffff); 229 } 230 231 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 232 { 233 struct mmc_data *data; 234 struct dw_mci_slot *slot = mmc_priv(mmc); 235 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 236 u32 cmdr; 237 cmd->error = -EINPROGRESS; 238 239 cmdr = cmd->opcode; 240 241 if (cmdr == MMC_STOP_TRANSMISSION) 242 cmdr |= SDMMC_CMD_STOP; 243 else 244 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 245 246 if (cmd->flags & MMC_RSP_PRESENT) { 247 /* We expect a response, so set this bit */ 248 cmdr |= SDMMC_CMD_RESP_EXP; 249 if (cmd->flags & MMC_RSP_136) 250 cmdr |= SDMMC_CMD_RESP_LONG; 251 } 252 253 if (cmd->flags & MMC_RSP_CRC) 254 cmdr |= SDMMC_CMD_RESP_CRC; 255 256 data = cmd->data; 257 if (data) { 258 cmdr |= SDMMC_CMD_DAT_EXP; 259 if (data->flags & MMC_DATA_STREAM) 260 cmdr |= SDMMC_CMD_STRM_MODE; 261 if (data->flags & MMC_DATA_WRITE) 262 cmdr |= SDMMC_CMD_DAT_WR; 263 } 264 265 if (drv_data && drv_data->prepare_command) 266 drv_data->prepare_command(slot->host, &cmdr); 267 268 return cmdr; 269 } 270 271 static void dw_mci_start_command(struct dw_mci *host, 272 struct mmc_command *cmd, u32 cmd_flags) 273 { 274 host->cmd = cmd; 275 dev_vdbg(host->dev, 276 "start command: ARGR=0x%08x CMDR=0x%08x\n", 277 cmd->arg, cmd_flags); 278 279 mci_writel(host, CMDARG, cmd->arg); 280 wmb(); 281 282 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 283 } 284 285 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data) 286 { 287 dw_mci_start_command(host, data->stop, host->stop_cmdr); 288 } 289 290 /* DMA interface functions */ 291 static void dw_mci_stop_dma(struct dw_mci *host) 292 { 293 if (host->using_dma) { 294 host->dma_ops->stop(host); 295 host->dma_ops->cleanup(host); 296 } else { 297 /* Data transfer was stopped by the interrupt handler */ 298 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 299 } 300 } 301 302 static int dw_mci_get_dma_dir(struct mmc_data *data) 303 { 304 if (data->flags & MMC_DATA_WRITE) 305 return DMA_TO_DEVICE; 306 else 307 return DMA_FROM_DEVICE; 308 } 309 310 #ifdef CONFIG_MMC_DW_IDMAC 311 static void dw_mci_dma_cleanup(struct dw_mci *host) 312 { 313 struct mmc_data *data = host->data; 314 315 if (data) 316 if (!data->host_cookie) 317 dma_unmap_sg(host->dev, 318 data->sg, 319 data->sg_len, 320 dw_mci_get_dma_dir(data)); 321 } 322 323 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 324 { 325 u32 temp; 326 327 /* Disable and reset the IDMAC interface */ 328 temp = mci_readl(host, CTRL); 329 temp &= ~SDMMC_CTRL_USE_IDMAC; 330 temp |= SDMMC_CTRL_DMA_RESET; 331 mci_writel(host, CTRL, temp); 332 333 /* Stop the IDMAC running */ 334 temp = mci_readl(host, BMOD); 335 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 336 mci_writel(host, BMOD, temp); 337 } 338 339 static void dw_mci_idmac_complete_dma(struct dw_mci *host) 340 { 341 struct mmc_data *data = host->data; 342 343 dev_vdbg(host->dev, "DMA complete\n"); 344 345 host->dma_ops->cleanup(host); 346 347 /* 348 * If the card was removed, data will be NULL. No point in trying to 349 * send the stop command or waiting for NBUSY in this case. 350 */ 351 if (data) { 352 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 353 tasklet_schedule(&host->tasklet); 354 } 355 } 356 357 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 358 unsigned int sg_len) 359 { 360 int i; 361 struct idmac_desc *desc = host->sg_cpu; 362 363 for (i = 0; i < sg_len; i++, desc++) { 364 unsigned int length = sg_dma_len(&data->sg[i]); 365 u32 mem_addr = sg_dma_address(&data->sg[i]); 366 367 /* Set the OWN bit and disable interrupts for this descriptor */ 368 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; 369 370 /* Buffer length */ 371 IDMAC_SET_BUFFER1_SIZE(desc, length); 372 373 /* Physical address to DMA to/from */ 374 desc->des2 = mem_addr; 375 } 376 377 /* Set first descriptor */ 378 desc = host->sg_cpu; 379 desc->des0 |= IDMAC_DES0_FD; 380 381 /* Set last descriptor */ 382 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 383 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 384 desc->des0 |= IDMAC_DES0_LD; 385 386 wmb(); 387 } 388 389 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 390 { 391 u32 temp; 392 393 dw_mci_translate_sglist(host, host->data, sg_len); 394 395 /* Select IDMAC interface */ 396 temp = mci_readl(host, CTRL); 397 temp |= SDMMC_CTRL_USE_IDMAC; 398 mci_writel(host, CTRL, temp); 399 400 wmb(); 401 402 /* Enable the IDMAC */ 403 temp = mci_readl(host, BMOD); 404 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 405 mci_writel(host, BMOD, temp); 406 407 /* Start it running */ 408 mci_writel(host, PLDMND, 1); 409 } 410 411 static int dw_mci_idmac_init(struct dw_mci *host) 412 { 413 struct idmac_desc *p; 414 int i; 415 416 /* Number of descriptors in the ring buffer */ 417 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 418 419 /* Forward link the descriptor list */ 420 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 421 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1)); 422 423 /* Set the last descriptor as the end-of-ring descriptor */ 424 p->des3 = host->sg_dma; 425 p->des0 = IDMAC_DES0_ER; 426 427 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET); 428 429 /* Mask out interrupts - get Tx & Rx complete only */ 430 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI | 431 SDMMC_IDMAC_INT_TI); 432 433 /* Set the descriptor base address */ 434 mci_writel(host, DBADDR, host->sg_dma); 435 return 0; 436 } 437 438 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 439 .init = dw_mci_idmac_init, 440 .start = dw_mci_idmac_start_dma, 441 .stop = dw_mci_idmac_stop_dma, 442 .complete = dw_mci_idmac_complete_dma, 443 .cleanup = dw_mci_dma_cleanup, 444 }; 445 #endif /* CONFIG_MMC_DW_IDMAC */ 446 447 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 448 struct mmc_data *data, 449 bool next) 450 { 451 struct scatterlist *sg; 452 unsigned int i, sg_len; 453 454 if (!next && data->host_cookie) 455 return data->host_cookie; 456 457 /* 458 * We don't do DMA on "complex" transfers, i.e. with 459 * non-word-aligned buffers or lengths. Also, we don't bother 460 * with all the DMA setup overhead for short transfers. 461 */ 462 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 463 return -EINVAL; 464 465 if (data->blksz & 3) 466 return -EINVAL; 467 468 for_each_sg(data->sg, sg, data->sg_len, i) { 469 if (sg->offset & 3 || sg->length & 3) 470 return -EINVAL; 471 } 472 473 sg_len = dma_map_sg(host->dev, 474 data->sg, 475 data->sg_len, 476 dw_mci_get_dma_dir(data)); 477 if (sg_len == 0) 478 return -EINVAL; 479 480 if (next) 481 data->host_cookie = sg_len; 482 483 return sg_len; 484 } 485 486 static void dw_mci_pre_req(struct mmc_host *mmc, 487 struct mmc_request *mrq, 488 bool is_first_req) 489 { 490 struct dw_mci_slot *slot = mmc_priv(mmc); 491 struct mmc_data *data = mrq->data; 492 493 if (!slot->host->use_dma || !data) 494 return; 495 496 if (data->host_cookie) { 497 data->host_cookie = 0; 498 return; 499 } 500 501 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 502 data->host_cookie = 0; 503 } 504 505 static void dw_mci_post_req(struct mmc_host *mmc, 506 struct mmc_request *mrq, 507 int err) 508 { 509 struct dw_mci_slot *slot = mmc_priv(mmc); 510 struct mmc_data *data = mrq->data; 511 512 if (!slot->host->use_dma || !data) 513 return; 514 515 if (data->host_cookie) 516 dma_unmap_sg(slot->host->dev, 517 data->sg, 518 data->sg_len, 519 dw_mci_get_dma_dir(data)); 520 data->host_cookie = 0; 521 } 522 523 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 524 { 525 int sg_len; 526 u32 temp; 527 528 host->using_dma = 0; 529 530 /* If we don't have a channel, we can't do DMA */ 531 if (!host->use_dma) 532 return -ENODEV; 533 534 sg_len = dw_mci_pre_dma_transfer(host, data, 0); 535 if (sg_len < 0) { 536 host->dma_ops->stop(host); 537 return sg_len; 538 } 539 540 host->using_dma = 1; 541 542 dev_vdbg(host->dev, 543 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 544 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 545 sg_len); 546 547 /* Enable the DMA interface */ 548 temp = mci_readl(host, CTRL); 549 temp |= SDMMC_CTRL_DMA_ENABLE; 550 mci_writel(host, CTRL, temp); 551 552 /* Disable RX/TX IRQs, let DMA handle it */ 553 temp = mci_readl(host, INTMASK); 554 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 555 mci_writel(host, INTMASK, temp); 556 557 host->dma_ops->start(host, sg_len); 558 559 return 0; 560 } 561 562 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 563 { 564 u32 temp; 565 566 data->error = -EINPROGRESS; 567 568 WARN_ON(host->data); 569 host->sg = NULL; 570 host->data = data; 571 572 if (data->flags & MMC_DATA_READ) 573 host->dir_status = DW_MCI_RECV_STATUS; 574 else 575 host->dir_status = DW_MCI_SEND_STATUS; 576 577 if (dw_mci_submit_data_dma(host, data)) { 578 int flags = SG_MITER_ATOMIC; 579 if (host->data->flags & MMC_DATA_READ) 580 flags |= SG_MITER_TO_SG; 581 else 582 flags |= SG_MITER_FROM_SG; 583 584 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 585 host->sg = data->sg; 586 host->part_buf_start = 0; 587 host->part_buf_count = 0; 588 589 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 590 temp = mci_readl(host, INTMASK); 591 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 592 mci_writel(host, INTMASK, temp); 593 594 temp = mci_readl(host, CTRL); 595 temp &= ~SDMMC_CTRL_DMA_ENABLE; 596 mci_writel(host, CTRL, temp); 597 } 598 } 599 600 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 601 { 602 struct dw_mci *host = slot->host; 603 unsigned long timeout = jiffies + msecs_to_jiffies(500); 604 unsigned int cmd_status = 0; 605 606 mci_writel(host, CMDARG, arg); 607 wmb(); 608 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 609 610 while (time_before(jiffies, timeout)) { 611 cmd_status = mci_readl(host, CMD); 612 if (!(cmd_status & SDMMC_CMD_START)) 613 return; 614 } 615 dev_err(&slot->mmc->class_dev, 616 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 617 cmd, arg, cmd_status); 618 } 619 620 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 621 { 622 struct dw_mci *host = slot->host; 623 u32 div; 624 u32 clk_en_a; 625 626 if (slot->clock != host->current_speed || force_clkinit) { 627 div = host->bus_hz / slot->clock; 628 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock) 629 /* 630 * move the + 1 after the divide to prevent 631 * over-clocking the card. 632 */ 633 div += 1; 634 635 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0; 636 637 dev_info(&slot->mmc->class_dev, 638 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ" 639 " div = %d)\n", slot->id, host->bus_hz, slot->clock, 640 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div); 641 642 /* disable clock */ 643 mci_writel(host, CLKENA, 0); 644 mci_writel(host, CLKSRC, 0); 645 646 /* inform CIU */ 647 mci_send_cmd(slot, 648 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 649 650 /* set clock to desired speed */ 651 mci_writel(host, CLKDIV, div); 652 653 /* inform CIU */ 654 mci_send_cmd(slot, 655 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 656 657 /* enable clock; only low power if no SDIO */ 658 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 659 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id))) 660 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 661 mci_writel(host, CLKENA, clk_en_a); 662 663 /* inform CIU */ 664 mci_send_cmd(slot, 665 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 666 667 host->current_speed = slot->clock; 668 } 669 670 /* Set the current slot bus width */ 671 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 672 } 673 674 static void __dw_mci_start_request(struct dw_mci *host, 675 struct dw_mci_slot *slot, 676 struct mmc_command *cmd) 677 { 678 struct mmc_request *mrq; 679 struct mmc_data *data; 680 u32 cmdflags; 681 682 mrq = slot->mrq; 683 if (host->pdata->select_slot) 684 host->pdata->select_slot(slot->id); 685 686 host->cur_slot = slot; 687 host->mrq = mrq; 688 689 host->pending_events = 0; 690 host->completed_events = 0; 691 host->data_status = 0; 692 693 data = cmd->data; 694 if (data) { 695 dw_mci_set_timeout(host); 696 mci_writel(host, BYTCNT, data->blksz*data->blocks); 697 mci_writel(host, BLKSIZ, data->blksz); 698 } 699 700 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 701 702 /* this is the first command, send the initialization clock */ 703 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 704 cmdflags |= SDMMC_CMD_INIT; 705 706 if (data) { 707 dw_mci_submit_data(host, data); 708 wmb(); 709 } 710 711 dw_mci_start_command(host, cmd, cmdflags); 712 713 if (mrq->stop) 714 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 715 } 716 717 static void dw_mci_start_request(struct dw_mci *host, 718 struct dw_mci_slot *slot) 719 { 720 struct mmc_request *mrq = slot->mrq; 721 struct mmc_command *cmd; 722 723 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 724 __dw_mci_start_request(host, slot, cmd); 725 } 726 727 /* must be called with host->lock held */ 728 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 729 struct mmc_request *mrq) 730 { 731 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 732 host->state); 733 734 slot->mrq = mrq; 735 736 if (host->state == STATE_IDLE) { 737 host->state = STATE_SENDING_CMD; 738 dw_mci_start_request(host, slot); 739 } else { 740 list_add_tail(&slot->queue_node, &host->queue); 741 } 742 } 743 744 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 745 { 746 struct dw_mci_slot *slot = mmc_priv(mmc); 747 struct dw_mci *host = slot->host; 748 749 WARN_ON(slot->mrq); 750 751 /* 752 * The check for card presence and queueing of the request must be 753 * atomic, otherwise the card could be removed in between and the 754 * request wouldn't fail until another card was inserted. 755 */ 756 spin_lock_bh(&host->lock); 757 758 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 759 spin_unlock_bh(&host->lock); 760 mrq->cmd->error = -ENOMEDIUM; 761 mmc_request_done(mmc, mrq); 762 return; 763 } 764 765 dw_mci_queue_request(host, slot, mrq); 766 767 spin_unlock_bh(&host->lock); 768 } 769 770 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 771 { 772 struct dw_mci_slot *slot = mmc_priv(mmc); 773 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 774 u32 regs; 775 776 switch (ios->bus_width) { 777 case MMC_BUS_WIDTH_4: 778 slot->ctype = SDMMC_CTYPE_4BIT; 779 break; 780 case MMC_BUS_WIDTH_8: 781 slot->ctype = SDMMC_CTYPE_8BIT; 782 break; 783 default: 784 /* set default 1 bit mode */ 785 slot->ctype = SDMMC_CTYPE_1BIT; 786 } 787 788 regs = mci_readl(slot->host, UHS_REG); 789 790 /* DDR mode set */ 791 if (ios->timing == MMC_TIMING_UHS_DDR50) 792 regs |= (0x1 << slot->id) << 16; 793 else 794 regs &= ~(0x1 << slot->id) << 16; 795 796 mci_writel(slot->host, UHS_REG, regs); 797 798 if (ios->clock) { 799 /* 800 * Use mirror of ios->clock to prevent race with mmc 801 * core ios update when finding the minimum. 802 */ 803 slot->clock = ios->clock; 804 } 805 806 if (drv_data && drv_data->set_ios) 807 drv_data->set_ios(slot->host, ios); 808 809 /* Slot specific timing and width adjustment */ 810 dw_mci_setup_bus(slot, false); 811 812 switch (ios->power_mode) { 813 case MMC_POWER_UP: 814 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 815 break; 816 default: 817 break; 818 } 819 } 820 821 static int dw_mci_get_ro(struct mmc_host *mmc) 822 { 823 int read_only; 824 struct dw_mci_slot *slot = mmc_priv(mmc); 825 struct dw_mci_board *brd = slot->host->pdata; 826 827 /* Use platform get_ro function, else try on board write protect */ 828 if (brd->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT) 829 read_only = 0; 830 else if (brd->get_ro) 831 read_only = brd->get_ro(slot->id); 832 else 833 read_only = 834 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 835 836 dev_dbg(&mmc->class_dev, "card is %s\n", 837 read_only ? "read-only" : "read-write"); 838 839 return read_only; 840 } 841 842 static int dw_mci_get_cd(struct mmc_host *mmc) 843 { 844 int present; 845 struct dw_mci_slot *slot = mmc_priv(mmc); 846 struct dw_mci_board *brd = slot->host->pdata; 847 848 /* Use platform get_cd function, else try onboard card detect */ 849 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 850 present = 1; 851 else if (brd->get_cd) 852 present = !brd->get_cd(slot->id); 853 else 854 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 855 == 0 ? 1 : 0; 856 857 if (present) 858 dev_dbg(&mmc->class_dev, "card is present\n"); 859 else 860 dev_dbg(&mmc->class_dev, "card is not present\n"); 861 862 return present; 863 } 864 865 /* 866 * Disable lower power mode. 867 * 868 * Low power mode will stop the card clock when idle. According to the 869 * description of the CLKENA register we should disable low power mode 870 * for SDIO cards if we need SDIO interrupts to work. 871 * 872 * This function is fast if low power mode is already disabled. 873 */ 874 static void dw_mci_disable_low_power(struct dw_mci_slot *slot) 875 { 876 struct dw_mci *host = slot->host; 877 u32 clk_en_a; 878 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 879 880 clk_en_a = mci_readl(host, CLKENA); 881 882 if (clk_en_a & clken_low_pwr) { 883 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr); 884 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 885 SDMMC_CMD_PRV_DAT_WAIT, 0); 886 } 887 } 888 889 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 890 { 891 struct dw_mci_slot *slot = mmc_priv(mmc); 892 struct dw_mci *host = slot->host; 893 u32 int_mask; 894 895 /* Enable/disable Slot Specific SDIO interrupt */ 896 int_mask = mci_readl(host, INTMASK); 897 if (enb) { 898 /* 899 * Turn off low power mode if it was enabled. This is a bit of 900 * a heavy operation and we disable / enable IRQs a lot, so 901 * we'll leave low power mode disabled and it will get 902 * re-enabled again in dw_mci_setup_bus(). 903 */ 904 dw_mci_disable_low_power(slot); 905 906 mci_writel(host, INTMASK, 907 (int_mask | SDMMC_INT_SDIO(slot->id))); 908 } else { 909 mci_writel(host, INTMASK, 910 (int_mask & ~SDMMC_INT_SDIO(slot->id))); 911 } 912 } 913 914 static const struct mmc_host_ops dw_mci_ops = { 915 .request = dw_mci_request, 916 .pre_req = dw_mci_pre_req, 917 .post_req = dw_mci_post_req, 918 .set_ios = dw_mci_set_ios, 919 .get_ro = dw_mci_get_ro, 920 .get_cd = dw_mci_get_cd, 921 .enable_sdio_irq = dw_mci_enable_sdio_irq, 922 }; 923 924 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 925 __releases(&host->lock) 926 __acquires(&host->lock) 927 { 928 struct dw_mci_slot *slot; 929 struct mmc_host *prev_mmc = host->cur_slot->mmc; 930 931 WARN_ON(host->cmd || host->data); 932 933 host->cur_slot->mrq = NULL; 934 host->mrq = NULL; 935 if (!list_empty(&host->queue)) { 936 slot = list_entry(host->queue.next, 937 struct dw_mci_slot, queue_node); 938 list_del(&slot->queue_node); 939 dev_vdbg(host->dev, "list not empty: %s is next\n", 940 mmc_hostname(slot->mmc)); 941 host->state = STATE_SENDING_CMD; 942 dw_mci_start_request(host, slot); 943 } else { 944 dev_vdbg(host->dev, "list empty\n"); 945 host->state = STATE_IDLE; 946 } 947 948 spin_unlock(&host->lock); 949 mmc_request_done(prev_mmc, mrq); 950 spin_lock(&host->lock); 951 } 952 953 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 954 { 955 u32 status = host->cmd_status; 956 957 host->cmd_status = 0; 958 959 /* Read the response from the card (up to 16 bytes) */ 960 if (cmd->flags & MMC_RSP_PRESENT) { 961 if (cmd->flags & MMC_RSP_136) { 962 cmd->resp[3] = mci_readl(host, RESP0); 963 cmd->resp[2] = mci_readl(host, RESP1); 964 cmd->resp[1] = mci_readl(host, RESP2); 965 cmd->resp[0] = mci_readl(host, RESP3); 966 } else { 967 cmd->resp[0] = mci_readl(host, RESP0); 968 cmd->resp[1] = 0; 969 cmd->resp[2] = 0; 970 cmd->resp[3] = 0; 971 } 972 } 973 974 if (status & SDMMC_INT_RTO) 975 cmd->error = -ETIMEDOUT; 976 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 977 cmd->error = -EILSEQ; 978 else if (status & SDMMC_INT_RESP_ERR) 979 cmd->error = -EIO; 980 else 981 cmd->error = 0; 982 983 if (cmd->error) { 984 /* newer ip versions need a delay between retries */ 985 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 986 mdelay(20); 987 988 if (cmd->data) { 989 dw_mci_stop_dma(host); 990 host->data = NULL; 991 } 992 } 993 } 994 995 static void dw_mci_tasklet_func(unsigned long priv) 996 { 997 struct dw_mci *host = (struct dw_mci *)priv; 998 struct mmc_data *data; 999 struct mmc_command *cmd; 1000 enum dw_mci_state state; 1001 enum dw_mci_state prev_state; 1002 u32 status, ctrl; 1003 1004 spin_lock(&host->lock); 1005 1006 state = host->state; 1007 data = host->data; 1008 1009 do { 1010 prev_state = state; 1011 1012 switch (state) { 1013 case STATE_IDLE: 1014 break; 1015 1016 case STATE_SENDING_CMD: 1017 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1018 &host->pending_events)) 1019 break; 1020 1021 cmd = host->cmd; 1022 host->cmd = NULL; 1023 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1024 dw_mci_command_complete(host, cmd); 1025 if (cmd == host->mrq->sbc && !cmd->error) { 1026 prev_state = state = STATE_SENDING_CMD; 1027 __dw_mci_start_request(host, host->cur_slot, 1028 host->mrq->cmd); 1029 goto unlock; 1030 } 1031 1032 if (!host->mrq->data || cmd->error) { 1033 dw_mci_request_end(host, host->mrq); 1034 goto unlock; 1035 } 1036 1037 prev_state = state = STATE_SENDING_DATA; 1038 /* fall through */ 1039 1040 case STATE_SENDING_DATA: 1041 if (test_and_clear_bit(EVENT_DATA_ERROR, 1042 &host->pending_events)) { 1043 dw_mci_stop_dma(host); 1044 if (data->stop) 1045 send_stop_cmd(host, data); 1046 state = STATE_DATA_ERROR; 1047 break; 1048 } 1049 1050 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1051 &host->pending_events)) 1052 break; 1053 1054 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 1055 prev_state = state = STATE_DATA_BUSY; 1056 /* fall through */ 1057 1058 case STATE_DATA_BUSY: 1059 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1060 &host->pending_events)) 1061 break; 1062 1063 host->data = NULL; 1064 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1065 status = host->data_status; 1066 1067 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1068 if (status & SDMMC_INT_DTO) { 1069 data->error = -ETIMEDOUT; 1070 } else if (status & SDMMC_INT_DCRC) { 1071 data->error = -EILSEQ; 1072 } else if (status & SDMMC_INT_EBE && 1073 host->dir_status == 1074 DW_MCI_SEND_STATUS) { 1075 /* 1076 * No data CRC status was returned. 1077 * The number of bytes transferred will 1078 * be exaggerated in PIO mode. 1079 */ 1080 data->bytes_xfered = 0; 1081 data->error = -ETIMEDOUT; 1082 } else { 1083 dev_err(host->dev, 1084 "data FIFO error " 1085 "(status=%08x)\n", 1086 status); 1087 data->error = -EIO; 1088 } 1089 /* 1090 * After an error, there may be data lingering 1091 * in the FIFO, so reset it - doing so 1092 * generates a block interrupt, hence setting 1093 * the scatter-gather pointer to NULL. 1094 */ 1095 sg_miter_stop(&host->sg_miter); 1096 host->sg = NULL; 1097 ctrl = mci_readl(host, CTRL); 1098 ctrl |= SDMMC_CTRL_FIFO_RESET; 1099 mci_writel(host, CTRL, ctrl); 1100 } else { 1101 data->bytes_xfered = data->blocks * data->blksz; 1102 data->error = 0; 1103 } 1104 1105 if (!data->stop) { 1106 dw_mci_request_end(host, host->mrq); 1107 goto unlock; 1108 } 1109 1110 if (host->mrq->sbc && !data->error) { 1111 data->stop->error = 0; 1112 dw_mci_request_end(host, host->mrq); 1113 goto unlock; 1114 } 1115 1116 prev_state = state = STATE_SENDING_STOP; 1117 if (!data->error) 1118 send_stop_cmd(host, data); 1119 /* fall through */ 1120 1121 case STATE_SENDING_STOP: 1122 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1123 &host->pending_events)) 1124 break; 1125 1126 host->cmd = NULL; 1127 dw_mci_command_complete(host, host->mrq->stop); 1128 dw_mci_request_end(host, host->mrq); 1129 goto unlock; 1130 1131 case STATE_DATA_ERROR: 1132 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1133 &host->pending_events)) 1134 break; 1135 1136 state = STATE_DATA_BUSY; 1137 break; 1138 } 1139 } while (state != prev_state); 1140 1141 host->state = state; 1142 unlock: 1143 spin_unlock(&host->lock); 1144 1145 } 1146 1147 /* push final bytes to part_buf, only use during push */ 1148 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 1149 { 1150 memcpy((void *)&host->part_buf, buf, cnt); 1151 host->part_buf_count = cnt; 1152 } 1153 1154 /* append bytes to part_buf, only use during push */ 1155 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 1156 { 1157 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 1158 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 1159 host->part_buf_count += cnt; 1160 return cnt; 1161 } 1162 1163 /* pull first bytes from part_buf, only use during pull */ 1164 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 1165 { 1166 cnt = min(cnt, (int)host->part_buf_count); 1167 if (cnt) { 1168 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 1169 cnt); 1170 host->part_buf_count -= cnt; 1171 host->part_buf_start += cnt; 1172 } 1173 return cnt; 1174 } 1175 1176 /* pull final bytes from the part_buf, assuming it's just been filled */ 1177 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 1178 { 1179 memcpy(buf, &host->part_buf, cnt); 1180 host->part_buf_start = cnt; 1181 host->part_buf_count = (1 << host->data_shift) - cnt; 1182 } 1183 1184 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1185 { 1186 /* try and push anything in the part_buf */ 1187 if (unlikely(host->part_buf_count)) { 1188 int len = dw_mci_push_part_bytes(host, buf, cnt); 1189 buf += len; 1190 cnt -= len; 1191 if (!sg_next(host->sg) || host->part_buf_count == 2) { 1192 mci_writew(host, DATA(host->data_offset), 1193 host->part_buf16); 1194 host->part_buf_count = 0; 1195 } 1196 } 1197 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1198 if (unlikely((unsigned long)buf & 0x1)) { 1199 while (cnt >= 2) { 1200 u16 aligned_buf[64]; 1201 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1202 int items = len >> 1; 1203 int i; 1204 /* memcpy from input buffer into aligned buffer */ 1205 memcpy(aligned_buf, buf, len); 1206 buf += len; 1207 cnt -= len; 1208 /* push data from aligned buffer into fifo */ 1209 for (i = 0; i < items; ++i) 1210 mci_writew(host, DATA(host->data_offset), 1211 aligned_buf[i]); 1212 } 1213 } else 1214 #endif 1215 { 1216 u16 *pdata = buf; 1217 for (; cnt >= 2; cnt -= 2) 1218 mci_writew(host, DATA(host->data_offset), *pdata++); 1219 buf = pdata; 1220 } 1221 /* put anything remaining in the part_buf */ 1222 if (cnt) { 1223 dw_mci_set_part_bytes(host, buf, cnt); 1224 if (!sg_next(host->sg)) 1225 mci_writew(host, DATA(host->data_offset), 1226 host->part_buf16); 1227 } 1228 } 1229 1230 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1231 { 1232 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1233 if (unlikely((unsigned long)buf & 0x1)) { 1234 while (cnt >= 2) { 1235 /* pull data from fifo into aligned buffer */ 1236 u16 aligned_buf[64]; 1237 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1238 int items = len >> 1; 1239 int i; 1240 for (i = 0; i < items; ++i) 1241 aligned_buf[i] = mci_readw(host, 1242 DATA(host->data_offset)); 1243 /* memcpy from aligned buffer into output buffer */ 1244 memcpy(buf, aligned_buf, len); 1245 buf += len; 1246 cnt -= len; 1247 } 1248 } else 1249 #endif 1250 { 1251 u16 *pdata = buf; 1252 for (; cnt >= 2; cnt -= 2) 1253 *pdata++ = mci_readw(host, DATA(host->data_offset)); 1254 buf = pdata; 1255 } 1256 if (cnt) { 1257 host->part_buf16 = mci_readw(host, DATA(host->data_offset)); 1258 dw_mci_pull_final_bytes(host, buf, cnt); 1259 } 1260 } 1261 1262 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1263 { 1264 /* try and push anything in the part_buf */ 1265 if (unlikely(host->part_buf_count)) { 1266 int len = dw_mci_push_part_bytes(host, buf, cnt); 1267 buf += len; 1268 cnt -= len; 1269 if (!sg_next(host->sg) || host->part_buf_count == 4) { 1270 mci_writel(host, DATA(host->data_offset), 1271 host->part_buf32); 1272 host->part_buf_count = 0; 1273 } 1274 } 1275 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1276 if (unlikely((unsigned long)buf & 0x3)) { 1277 while (cnt >= 4) { 1278 u32 aligned_buf[32]; 1279 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1280 int items = len >> 2; 1281 int i; 1282 /* memcpy from input buffer into aligned buffer */ 1283 memcpy(aligned_buf, buf, len); 1284 buf += len; 1285 cnt -= len; 1286 /* push data from aligned buffer into fifo */ 1287 for (i = 0; i < items; ++i) 1288 mci_writel(host, DATA(host->data_offset), 1289 aligned_buf[i]); 1290 } 1291 } else 1292 #endif 1293 { 1294 u32 *pdata = buf; 1295 for (; cnt >= 4; cnt -= 4) 1296 mci_writel(host, DATA(host->data_offset), *pdata++); 1297 buf = pdata; 1298 } 1299 /* put anything remaining in the part_buf */ 1300 if (cnt) { 1301 dw_mci_set_part_bytes(host, buf, cnt); 1302 if (!sg_next(host->sg)) 1303 mci_writel(host, DATA(host->data_offset), 1304 host->part_buf32); 1305 } 1306 } 1307 1308 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1309 { 1310 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1311 if (unlikely((unsigned long)buf & 0x3)) { 1312 while (cnt >= 4) { 1313 /* pull data from fifo into aligned buffer */ 1314 u32 aligned_buf[32]; 1315 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1316 int items = len >> 2; 1317 int i; 1318 for (i = 0; i < items; ++i) 1319 aligned_buf[i] = mci_readl(host, 1320 DATA(host->data_offset)); 1321 /* memcpy from aligned buffer into output buffer */ 1322 memcpy(buf, aligned_buf, len); 1323 buf += len; 1324 cnt -= len; 1325 } 1326 } else 1327 #endif 1328 { 1329 u32 *pdata = buf; 1330 for (; cnt >= 4; cnt -= 4) 1331 *pdata++ = mci_readl(host, DATA(host->data_offset)); 1332 buf = pdata; 1333 } 1334 if (cnt) { 1335 host->part_buf32 = mci_readl(host, DATA(host->data_offset)); 1336 dw_mci_pull_final_bytes(host, buf, cnt); 1337 } 1338 } 1339 1340 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1341 { 1342 /* try and push anything in the part_buf */ 1343 if (unlikely(host->part_buf_count)) { 1344 int len = dw_mci_push_part_bytes(host, buf, cnt); 1345 buf += len; 1346 cnt -= len; 1347 if (!sg_next(host->sg) || host->part_buf_count == 8) { 1348 mci_writew(host, DATA(host->data_offset), 1349 host->part_buf); 1350 host->part_buf_count = 0; 1351 } 1352 } 1353 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1354 if (unlikely((unsigned long)buf & 0x7)) { 1355 while (cnt >= 8) { 1356 u64 aligned_buf[16]; 1357 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1358 int items = len >> 3; 1359 int i; 1360 /* memcpy from input buffer into aligned buffer */ 1361 memcpy(aligned_buf, buf, len); 1362 buf += len; 1363 cnt -= len; 1364 /* push data from aligned buffer into fifo */ 1365 for (i = 0; i < items; ++i) 1366 mci_writeq(host, DATA(host->data_offset), 1367 aligned_buf[i]); 1368 } 1369 } else 1370 #endif 1371 { 1372 u64 *pdata = buf; 1373 for (; cnt >= 8; cnt -= 8) 1374 mci_writeq(host, DATA(host->data_offset), *pdata++); 1375 buf = pdata; 1376 } 1377 /* put anything remaining in the part_buf */ 1378 if (cnt) { 1379 dw_mci_set_part_bytes(host, buf, cnt); 1380 if (!sg_next(host->sg)) 1381 mci_writeq(host, DATA(host->data_offset), 1382 host->part_buf); 1383 } 1384 } 1385 1386 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1387 { 1388 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1389 if (unlikely((unsigned long)buf & 0x7)) { 1390 while (cnt >= 8) { 1391 /* pull data from fifo into aligned buffer */ 1392 u64 aligned_buf[16]; 1393 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1394 int items = len >> 3; 1395 int i; 1396 for (i = 0; i < items; ++i) 1397 aligned_buf[i] = mci_readq(host, 1398 DATA(host->data_offset)); 1399 /* memcpy from aligned buffer into output buffer */ 1400 memcpy(buf, aligned_buf, len); 1401 buf += len; 1402 cnt -= len; 1403 } 1404 } else 1405 #endif 1406 { 1407 u64 *pdata = buf; 1408 for (; cnt >= 8; cnt -= 8) 1409 *pdata++ = mci_readq(host, DATA(host->data_offset)); 1410 buf = pdata; 1411 } 1412 if (cnt) { 1413 host->part_buf = mci_readq(host, DATA(host->data_offset)); 1414 dw_mci_pull_final_bytes(host, buf, cnt); 1415 } 1416 } 1417 1418 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 1419 { 1420 int len; 1421 1422 /* get remaining partial bytes */ 1423 len = dw_mci_pull_part_bytes(host, buf, cnt); 1424 if (unlikely(len == cnt)) 1425 return; 1426 buf += len; 1427 cnt -= len; 1428 1429 /* get the rest of the data */ 1430 host->pull_data(host, buf, cnt); 1431 } 1432 1433 static void dw_mci_read_data_pio(struct dw_mci *host) 1434 { 1435 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1436 void *buf; 1437 unsigned int offset; 1438 struct mmc_data *data = host->data; 1439 int shift = host->data_shift; 1440 u32 status; 1441 unsigned int nbytes = 0, len; 1442 unsigned int remain, fcnt; 1443 1444 do { 1445 if (!sg_miter_next(sg_miter)) 1446 goto done; 1447 1448 host->sg = sg_miter->__sg; 1449 buf = sg_miter->addr; 1450 remain = sg_miter->length; 1451 offset = 0; 1452 1453 do { 1454 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 1455 << shift) + host->part_buf_count; 1456 len = min(remain, fcnt); 1457 if (!len) 1458 break; 1459 dw_mci_pull_data(host, (void *)(buf + offset), len); 1460 offset += len; 1461 nbytes += len; 1462 remain -= len; 1463 } while (remain); 1464 1465 sg_miter->consumed = offset; 1466 status = mci_readl(host, MINTSTS); 1467 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1468 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/ 1469 data->bytes_xfered += nbytes; 1470 1471 if (!remain) { 1472 if (!sg_miter_next(sg_miter)) 1473 goto done; 1474 sg_miter->consumed = 0; 1475 } 1476 sg_miter_stop(sg_miter); 1477 return; 1478 1479 done: 1480 data->bytes_xfered += nbytes; 1481 sg_miter_stop(sg_miter); 1482 host->sg = NULL; 1483 smp_wmb(); 1484 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1485 } 1486 1487 static void dw_mci_write_data_pio(struct dw_mci *host) 1488 { 1489 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1490 void *buf; 1491 unsigned int offset; 1492 struct mmc_data *data = host->data; 1493 int shift = host->data_shift; 1494 u32 status; 1495 unsigned int nbytes = 0, len; 1496 unsigned int fifo_depth = host->fifo_depth; 1497 unsigned int remain, fcnt; 1498 1499 do { 1500 if (!sg_miter_next(sg_miter)) 1501 goto done; 1502 1503 host->sg = sg_miter->__sg; 1504 buf = sg_miter->addr; 1505 remain = sg_miter->length; 1506 offset = 0; 1507 1508 do { 1509 fcnt = ((fifo_depth - 1510 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 1511 << shift) - host->part_buf_count; 1512 len = min(remain, fcnt); 1513 if (!len) 1514 break; 1515 host->push_data(host, (void *)(buf + offset), len); 1516 offset += len; 1517 nbytes += len; 1518 remain -= len; 1519 } while (remain); 1520 1521 sg_miter->consumed = offset; 1522 status = mci_readl(host, MINTSTS); 1523 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1524 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 1525 data->bytes_xfered += nbytes; 1526 1527 if (!remain) { 1528 if (!sg_miter_next(sg_miter)) 1529 goto done; 1530 sg_miter->consumed = 0; 1531 } 1532 sg_miter_stop(sg_miter); 1533 return; 1534 1535 done: 1536 data->bytes_xfered += nbytes; 1537 sg_miter_stop(sg_miter); 1538 host->sg = NULL; 1539 smp_wmb(); 1540 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1541 } 1542 1543 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 1544 { 1545 if (!host->cmd_status) 1546 host->cmd_status = status; 1547 1548 smp_wmb(); 1549 1550 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1551 tasklet_schedule(&host->tasklet); 1552 } 1553 1554 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 1555 { 1556 struct dw_mci *host = dev_id; 1557 u32 pending; 1558 unsigned int pass_count = 0; 1559 int i; 1560 1561 do { 1562 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 1563 1564 /* 1565 * DTO fix - version 2.10a and below, and only if internal DMA 1566 * is configured. 1567 */ 1568 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 1569 if (!pending && 1570 ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 1571 pending |= SDMMC_INT_DATA_OVER; 1572 } 1573 1574 if (!pending) 1575 break; 1576 1577 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 1578 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 1579 host->cmd_status = pending; 1580 smp_wmb(); 1581 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1582 } 1583 1584 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 1585 /* if there is an error report DATA_ERROR */ 1586 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 1587 host->data_status = pending; 1588 smp_wmb(); 1589 set_bit(EVENT_DATA_ERROR, &host->pending_events); 1590 tasklet_schedule(&host->tasklet); 1591 } 1592 1593 if (pending & SDMMC_INT_DATA_OVER) { 1594 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 1595 if (!host->data_status) 1596 host->data_status = pending; 1597 smp_wmb(); 1598 if (host->dir_status == DW_MCI_RECV_STATUS) { 1599 if (host->sg != NULL) 1600 dw_mci_read_data_pio(host); 1601 } 1602 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1603 tasklet_schedule(&host->tasklet); 1604 } 1605 1606 if (pending & SDMMC_INT_RXDR) { 1607 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1608 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 1609 dw_mci_read_data_pio(host); 1610 } 1611 1612 if (pending & SDMMC_INT_TXDR) { 1613 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1614 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 1615 dw_mci_write_data_pio(host); 1616 } 1617 1618 if (pending & SDMMC_INT_CMD_DONE) { 1619 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 1620 dw_mci_cmd_interrupt(host, pending); 1621 } 1622 1623 if (pending & SDMMC_INT_CD) { 1624 mci_writel(host, RINTSTS, SDMMC_INT_CD); 1625 queue_work(host->card_workqueue, &host->card_work); 1626 } 1627 1628 /* Handle SDIO Interrupts */ 1629 for (i = 0; i < host->num_slots; i++) { 1630 struct dw_mci_slot *slot = host->slot[i]; 1631 if (pending & SDMMC_INT_SDIO(i)) { 1632 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i)); 1633 mmc_signal_sdio_irq(slot->mmc); 1634 } 1635 } 1636 1637 } while (pass_count++ < 5); 1638 1639 #ifdef CONFIG_MMC_DW_IDMAC 1640 /* Handle DMA interrupts */ 1641 pending = mci_readl(host, IDSTS); 1642 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 1643 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI); 1644 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 1645 host->dma_ops->complete(host); 1646 } 1647 #endif 1648 1649 return IRQ_HANDLED; 1650 } 1651 1652 static void dw_mci_work_routine_card(struct work_struct *work) 1653 { 1654 struct dw_mci *host = container_of(work, struct dw_mci, card_work); 1655 int i; 1656 1657 for (i = 0; i < host->num_slots; i++) { 1658 struct dw_mci_slot *slot = host->slot[i]; 1659 struct mmc_host *mmc = slot->mmc; 1660 struct mmc_request *mrq; 1661 int present; 1662 u32 ctrl; 1663 1664 present = dw_mci_get_cd(mmc); 1665 while (present != slot->last_detect_state) { 1666 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1667 present ? "inserted" : "removed"); 1668 1669 /* Power up slot (before spin_lock, may sleep) */ 1670 if (present != 0 && host->pdata->setpower) 1671 host->pdata->setpower(slot->id, mmc->ocr_avail); 1672 1673 spin_lock_bh(&host->lock); 1674 1675 /* Card change detected */ 1676 slot->last_detect_state = present; 1677 1678 /* Mark card as present if applicable */ 1679 if (present != 0) 1680 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1681 1682 /* Clean up queue if present */ 1683 mrq = slot->mrq; 1684 if (mrq) { 1685 if (mrq == host->mrq) { 1686 host->data = NULL; 1687 host->cmd = NULL; 1688 1689 switch (host->state) { 1690 case STATE_IDLE: 1691 break; 1692 case STATE_SENDING_CMD: 1693 mrq->cmd->error = -ENOMEDIUM; 1694 if (!mrq->data) 1695 break; 1696 /* fall through */ 1697 case STATE_SENDING_DATA: 1698 mrq->data->error = -ENOMEDIUM; 1699 dw_mci_stop_dma(host); 1700 break; 1701 case STATE_DATA_BUSY: 1702 case STATE_DATA_ERROR: 1703 if (mrq->data->error == -EINPROGRESS) 1704 mrq->data->error = -ENOMEDIUM; 1705 if (!mrq->stop) 1706 break; 1707 /* fall through */ 1708 case STATE_SENDING_STOP: 1709 mrq->stop->error = -ENOMEDIUM; 1710 break; 1711 } 1712 1713 dw_mci_request_end(host, mrq); 1714 } else { 1715 list_del(&slot->queue_node); 1716 mrq->cmd->error = -ENOMEDIUM; 1717 if (mrq->data) 1718 mrq->data->error = -ENOMEDIUM; 1719 if (mrq->stop) 1720 mrq->stop->error = -ENOMEDIUM; 1721 1722 spin_unlock(&host->lock); 1723 mmc_request_done(slot->mmc, mrq); 1724 spin_lock(&host->lock); 1725 } 1726 } 1727 1728 /* Power down slot */ 1729 if (present == 0) { 1730 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1731 1732 /* 1733 * Clear down the FIFO - doing so generates a 1734 * block interrupt, hence setting the 1735 * scatter-gather pointer to NULL. 1736 */ 1737 sg_miter_stop(&host->sg_miter); 1738 host->sg = NULL; 1739 1740 ctrl = mci_readl(host, CTRL); 1741 ctrl |= SDMMC_CTRL_FIFO_RESET; 1742 mci_writel(host, CTRL, ctrl); 1743 1744 #ifdef CONFIG_MMC_DW_IDMAC 1745 ctrl = mci_readl(host, BMOD); 1746 /* Software reset of DMA */ 1747 ctrl |= SDMMC_IDMAC_SWRESET; 1748 mci_writel(host, BMOD, ctrl); 1749 #endif 1750 1751 } 1752 1753 spin_unlock_bh(&host->lock); 1754 1755 /* Power down slot (after spin_unlock, may sleep) */ 1756 if (present == 0 && host->pdata->setpower) 1757 host->pdata->setpower(slot->id, 0); 1758 1759 present = dw_mci_get_cd(mmc); 1760 } 1761 1762 mmc_detect_change(slot->mmc, 1763 msecs_to_jiffies(host->pdata->detect_delay_ms)); 1764 } 1765 } 1766 1767 #ifdef CONFIG_OF 1768 /* given a slot id, find out the device node representing that slot */ 1769 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 1770 { 1771 struct device_node *np; 1772 const __be32 *addr; 1773 int len; 1774 1775 if (!dev || !dev->of_node) 1776 return NULL; 1777 1778 for_each_child_of_node(dev->of_node, np) { 1779 addr = of_get_property(np, "reg", &len); 1780 if (!addr || (len < sizeof(int))) 1781 continue; 1782 if (be32_to_cpup(addr) == slot) 1783 return np; 1784 } 1785 return NULL; 1786 } 1787 1788 /* find out bus-width for a given slot */ 1789 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) 1790 { 1791 struct device_node *np = dw_mci_of_find_slot_node(dev, slot); 1792 u32 bus_wd = 1; 1793 1794 if (!np) 1795 return 1; 1796 1797 if (of_property_read_u32(np, "bus-width", &bus_wd)) 1798 dev_err(dev, "bus-width property not found, assuming width" 1799 " as 1\n"); 1800 return bus_wd; 1801 } 1802 #else /* CONFIG_OF */ 1803 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot) 1804 { 1805 return 1; 1806 } 1807 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) 1808 { 1809 return NULL; 1810 } 1811 #endif /* CONFIG_OF */ 1812 1813 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 1814 { 1815 struct mmc_host *mmc; 1816 struct dw_mci_slot *slot; 1817 const struct dw_mci_drv_data *drv_data = host->drv_data; 1818 int ctrl_id, ret; 1819 u8 bus_width; 1820 1821 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 1822 if (!mmc) 1823 return -ENOMEM; 1824 1825 slot = mmc_priv(mmc); 1826 slot->id = id; 1827 slot->mmc = mmc; 1828 slot->host = host; 1829 host->slot[id] = slot; 1830 1831 mmc->ops = &dw_mci_ops; 1832 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); 1833 mmc->f_max = host->bus_hz; 1834 1835 if (host->pdata->get_ocr) 1836 mmc->ocr_avail = host->pdata->get_ocr(id); 1837 else 1838 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1839 1840 /* 1841 * Start with slot power disabled, it will be enabled when a card 1842 * is detected. 1843 */ 1844 if (host->pdata->setpower) 1845 host->pdata->setpower(id, 0); 1846 1847 if (host->pdata->caps) 1848 mmc->caps = host->pdata->caps; 1849 1850 if (host->pdata->pm_caps) 1851 mmc->pm_caps = host->pdata->pm_caps; 1852 1853 if (host->dev->of_node) { 1854 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 1855 if (ctrl_id < 0) 1856 ctrl_id = 0; 1857 } else { 1858 ctrl_id = to_platform_device(host->dev)->id; 1859 } 1860 if (drv_data && drv_data->caps) 1861 mmc->caps |= drv_data->caps[ctrl_id]; 1862 1863 if (host->pdata->caps2) 1864 mmc->caps2 = host->pdata->caps2; 1865 1866 if (host->pdata->get_bus_wd) 1867 bus_width = host->pdata->get_bus_wd(slot->id); 1868 else if (host->dev->of_node) 1869 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id); 1870 else 1871 bus_width = 1; 1872 1873 if (drv_data && drv_data->setup_bus) { 1874 struct device_node *slot_np; 1875 slot_np = dw_mci_of_find_slot_node(host->dev, slot->id); 1876 ret = drv_data->setup_bus(host, slot_np, bus_width); 1877 if (ret) 1878 goto err_setup_bus; 1879 } 1880 1881 switch (bus_width) { 1882 case 8: 1883 mmc->caps |= MMC_CAP_8_BIT_DATA; 1884 case 4: 1885 mmc->caps |= MMC_CAP_4_BIT_DATA; 1886 } 1887 1888 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) 1889 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 1890 1891 if (host->pdata->blk_settings) { 1892 mmc->max_segs = host->pdata->blk_settings->max_segs; 1893 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 1894 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 1895 mmc->max_req_size = host->pdata->blk_settings->max_req_size; 1896 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 1897 } else { 1898 /* Useful defaults if platform data is unset. */ 1899 #ifdef CONFIG_MMC_DW_IDMAC 1900 mmc->max_segs = host->ring_size; 1901 mmc->max_blk_size = 65536; 1902 mmc->max_blk_count = host->ring_size; 1903 mmc->max_seg_size = 0x1000; 1904 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; 1905 #else 1906 mmc->max_segs = 64; 1907 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 1908 mmc->max_blk_count = 512; 1909 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1910 mmc->max_seg_size = mmc->max_req_size; 1911 #endif /* CONFIG_MMC_DW_IDMAC */ 1912 } 1913 1914 host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc"); 1915 if (IS_ERR(host->vmmc)) { 1916 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc)); 1917 host->vmmc = NULL; 1918 } else 1919 regulator_enable(host->vmmc); 1920 1921 if (dw_mci_get_cd(mmc)) 1922 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1923 else 1924 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1925 1926 mmc_add_host(mmc); 1927 1928 #if defined(CONFIG_DEBUG_FS) 1929 dw_mci_init_debugfs(slot); 1930 #endif 1931 1932 /* Card initially undetected */ 1933 slot->last_detect_state = 0; 1934 1935 /* 1936 * Card may have been plugged in prior to boot so we 1937 * need to run the detect tasklet 1938 */ 1939 queue_work(host->card_workqueue, &host->card_work); 1940 1941 return 0; 1942 1943 err_setup_bus: 1944 mmc_free_host(mmc); 1945 return -EINVAL; 1946 } 1947 1948 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 1949 { 1950 /* Shutdown detect IRQ */ 1951 if (slot->host->pdata->exit) 1952 slot->host->pdata->exit(id); 1953 1954 /* Debugfs stuff is cleaned up by mmc core */ 1955 mmc_remove_host(slot->mmc); 1956 slot->host->slot[id] = NULL; 1957 mmc_free_host(slot->mmc); 1958 } 1959 1960 static void dw_mci_init_dma(struct dw_mci *host) 1961 { 1962 /* Alloc memory for sg translation */ 1963 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 1964 &host->sg_dma, GFP_KERNEL); 1965 if (!host->sg_cpu) { 1966 dev_err(host->dev, "%s: could not alloc DMA memory\n", 1967 __func__); 1968 goto no_dma; 1969 } 1970 1971 /* Determine which DMA interface to use */ 1972 #ifdef CONFIG_MMC_DW_IDMAC 1973 host->dma_ops = &dw_mci_idmac_ops; 1974 dev_info(host->dev, "Using internal DMA controller.\n"); 1975 #endif 1976 1977 if (!host->dma_ops) 1978 goto no_dma; 1979 1980 if (host->dma_ops->init && host->dma_ops->start && 1981 host->dma_ops->stop && host->dma_ops->cleanup) { 1982 if (host->dma_ops->init(host)) { 1983 dev_err(host->dev, "%s: Unable to initialize " 1984 "DMA Controller.\n", __func__); 1985 goto no_dma; 1986 } 1987 } else { 1988 dev_err(host->dev, "DMA initialization not found.\n"); 1989 goto no_dma; 1990 } 1991 1992 host->use_dma = 1; 1993 return; 1994 1995 no_dma: 1996 dev_info(host->dev, "Using PIO mode.\n"); 1997 host->use_dma = 0; 1998 return; 1999 } 2000 2001 static bool mci_wait_reset(struct device *dev, struct dw_mci *host) 2002 { 2003 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2004 unsigned int ctrl; 2005 2006 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 2007 SDMMC_CTRL_DMA_RESET)); 2008 2009 /* wait till resets clear */ 2010 do { 2011 ctrl = mci_readl(host, CTRL); 2012 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 2013 SDMMC_CTRL_DMA_RESET))) 2014 return true; 2015 } while (time_before(jiffies, timeout)); 2016 2017 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl); 2018 2019 return false; 2020 } 2021 2022 #ifdef CONFIG_OF 2023 static struct dw_mci_of_quirks { 2024 char *quirk; 2025 int id; 2026 } of_quirks[] = { 2027 { 2028 .quirk = "supports-highspeed", 2029 .id = DW_MCI_QUIRK_HIGHSPEED, 2030 }, { 2031 .quirk = "broken-cd", 2032 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 2033 }, 2034 }; 2035 2036 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2037 { 2038 struct dw_mci_board *pdata; 2039 struct device *dev = host->dev; 2040 struct device_node *np = dev->of_node; 2041 const struct dw_mci_drv_data *drv_data = host->drv_data; 2042 int idx, ret; 2043 2044 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2045 if (!pdata) { 2046 dev_err(dev, "could not allocate memory for pdata\n"); 2047 return ERR_PTR(-ENOMEM); 2048 } 2049 2050 /* find out number of slots supported */ 2051 if (of_property_read_u32(dev->of_node, "num-slots", 2052 &pdata->num_slots)) { 2053 dev_info(dev, "num-slots property not found, " 2054 "assuming 1 slot is available\n"); 2055 pdata->num_slots = 1; 2056 } 2057 2058 /* get quirks */ 2059 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2060 if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2061 pdata->quirks |= of_quirks[idx].id; 2062 2063 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2064 dev_info(dev, "fifo-depth property not found, using " 2065 "value of FIFOTH register as default\n"); 2066 2067 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2068 2069 if (drv_data && drv_data->parse_dt) { 2070 ret = drv_data->parse_dt(host); 2071 if (ret) 2072 return ERR_PTR(ret); 2073 } 2074 2075 if (of_find_property(np, "keep-power-in-suspend", NULL)) 2076 pdata->pm_caps |= MMC_PM_KEEP_POWER; 2077 2078 if (of_find_property(np, "enable-sdio-wakeup", NULL)) 2079 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2080 2081 return pdata; 2082 } 2083 2084 #else /* CONFIG_OF */ 2085 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2086 { 2087 return ERR_PTR(-EINVAL); 2088 } 2089 #endif /* CONFIG_OF */ 2090 2091 int dw_mci_probe(struct dw_mci *host) 2092 { 2093 const struct dw_mci_drv_data *drv_data = host->drv_data; 2094 int width, i, ret = 0; 2095 u32 fifo_size; 2096 int init_slots = 0; 2097 2098 if (!host->pdata) { 2099 host->pdata = dw_mci_parse_dt(host); 2100 if (IS_ERR(host->pdata)) { 2101 dev_err(host->dev, "platform data not available\n"); 2102 return -EINVAL; 2103 } 2104 } 2105 2106 if (!host->pdata->select_slot && host->pdata->num_slots > 1) { 2107 dev_err(host->dev, 2108 "Platform data must supply select_slot function\n"); 2109 return -ENODEV; 2110 } 2111 2112 host->biu_clk = devm_clk_get(host->dev, "biu"); 2113 if (IS_ERR(host->biu_clk)) { 2114 dev_dbg(host->dev, "biu clock not available\n"); 2115 } else { 2116 ret = clk_prepare_enable(host->biu_clk); 2117 if (ret) { 2118 dev_err(host->dev, "failed to enable biu clock\n"); 2119 return ret; 2120 } 2121 } 2122 2123 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2124 if (IS_ERR(host->ciu_clk)) { 2125 dev_dbg(host->dev, "ciu clock not available\n"); 2126 } else { 2127 ret = clk_prepare_enable(host->ciu_clk); 2128 if (ret) { 2129 dev_err(host->dev, "failed to enable ciu clock\n"); 2130 goto err_clk_biu; 2131 } 2132 } 2133 2134 if (IS_ERR(host->ciu_clk)) 2135 host->bus_hz = host->pdata->bus_hz; 2136 else 2137 host->bus_hz = clk_get_rate(host->ciu_clk); 2138 2139 if (drv_data && drv_data->setup_clock) { 2140 ret = drv_data->setup_clock(host); 2141 if (ret) { 2142 dev_err(host->dev, 2143 "implementation specific clock setup failed\n"); 2144 goto err_clk_ciu; 2145 } 2146 } 2147 2148 if (!host->bus_hz) { 2149 dev_err(host->dev, 2150 "Platform data must supply bus speed\n"); 2151 ret = -ENODEV; 2152 goto err_clk_ciu; 2153 } 2154 2155 host->quirks = host->pdata->quirks; 2156 2157 spin_lock_init(&host->lock); 2158 INIT_LIST_HEAD(&host->queue); 2159 2160 /* 2161 * Get the host data width - this assumes that HCON has been set with 2162 * the correct values. 2163 */ 2164 i = (mci_readl(host, HCON) >> 7) & 0x7; 2165 if (!i) { 2166 host->push_data = dw_mci_push_data16; 2167 host->pull_data = dw_mci_pull_data16; 2168 width = 16; 2169 host->data_shift = 1; 2170 } else if (i == 2) { 2171 host->push_data = dw_mci_push_data64; 2172 host->pull_data = dw_mci_pull_data64; 2173 width = 64; 2174 host->data_shift = 3; 2175 } else { 2176 /* Check for a reserved value, and warn if it is */ 2177 WARN((i != 1), 2178 "HCON reports a reserved host data width!\n" 2179 "Defaulting to 32-bit access.\n"); 2180 host->push_data = dw_mci_push_data32; 2181 host->pull_data = dw_mci_pull_data32; 2182 width = 32; 2183 host->data_shift = 2; 2184 } 2185 2186 /* Reset all blocks */ 2187 if (!mci_wait_reset(host->dev, host)) 2188 return -ENODEV; 2189 2190 host->dma_ops = host->pdata->dma_ops; 2191 dw_mci_init_dma(host); 2192 2193 /* Clear the interrupts for the host controller */ 2194 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2195 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2196 2197 /* Put in max timeout */ 2198 mci_writel(host, TMOUT, 0xFFFFFFFF); 2199 2200 /* 2201 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2202 * Tx Mark = fifo_size / 2 DMA Size = 8 2203 */ 2204 if (!host->pdata->fifo_depth) { 2205 /* 2206 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2207 * have been overwritten by the bootloader, just like we're 2208 * about to do, so if you know the value for your hardware, you 2209 * should put it in the platform data. 2210 */ 2211 fifo_size = mci_readl(host, FIFOTH); 2212 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2213 } else { 2214 fifo_size = host->pdata->fifo_depth; 2215 } 2216 host->fifo_depth = fifo_size; 2217 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | 2218 ((fifo_size/2) << 0)); 2219 mci_writel(host, FIFOTH, host->fifoth_val); 2220 2221 /* disable clock to CIU */ 2222 mci_writel(host, CLKENA, 0); 2223 mci_writel(host, CLKSRC, 0); 2224 2225 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2226 host->card_workqueue = alloc_workqueue("dw-mci-card", 2227 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1); 2228 if (!host->card_workqueue) 2229 goto err_dmaunmap; 2230 INIT_WORK(&host->card_work, dw_mci_work_routine_card); 2231 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2232 host->irq_flags, "dw-mci", host); 2233 if (ret) 2234 goto err_workqueue; 2235 2236 if (host->pdata->num_slots) 2237 host->num_slots = host->pdata->num_slots; 2238 else 2239 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2240 2241 /* 2242 * Enable interrupts for command done, data over, data empty, card det, 2243 * receive ready and error such as transmit, receive timeout, crc error 2244 */ 2245 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2246 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2247 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2248 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2249 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 2250 2251 dev_info(host->dev, "DW MMC controller at irq %d, " 2252 "%d bit host data width, " 2253 "%u deep fifo\n", 2254 host->irq, width, fifo_size); 2255 2256 /* We need at least one slot to succeed */ 2257 for (i = 0; i < host->num_slots; i++) { 2258 ret = dw_mci_init_slot(host, i); 2259 if (ret) 2260 dev_dbg(host->dev, "slot %d init failed\n", i); 2261 else 2262 init_slots++; 2263 } 2264 2265 if (init_slots) { 2266 dev_info(host->dev, "%d slots initialized\n", init_slots); 2267 } else { 2268 dev_dbg(host->dev, "attempted to initialize %d slots, " 2269 "but failed on all\n", host->num_slots); 2270 goto err_workqueue; 2271 } 2272 2273 /* 2274 * In 2.40a spec, Data offset is changed. 2275 * Need to check the version-id and set data-offset for DATA register. 2276 */ 2277 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 2278 dev_info(host->dev, "Version ID is %04x\n", host->verid); 2279 2280 if (host->verid < DW_MMC_240A) 2281 host->data_offset = DATA_OFFSET; 2282 else 2283 host->data_offset = DATA_240A_OFFSET; 2284 2285 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 2286 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 2287 2288 return 0; 2289 2290 err_workqueue: 2291 destroy_workqueue(host->card_workqueue); 2292 2293 err_dmaunmap: 2294 if (host->use_dma && host->dma_ops->exit) 2295 host->dma_ops->exit(host); 2296 2297 if (host->vmmc) 2298 regulator_disable(host->vmmc); 2299 2300 err_clk_ciu: 2301 if (!IS_ERR(host->ciu_clk)) 2302 clk_disable_unprepare(host->ciu_clk); 2303 2304 err_clk_biu: 2305 if (!IS_ERR(host->biu_clk)) 2306 clk_disable_unprepare(host->biu_clk); 2307 2308 return ret; 2309 } 2310 EXPORT_SYMBOL(dw_mci_probe); 2311 2312 void dw_mci_remove(struct dw_mci *host) 2313 { 2314 int i; 2315 2316 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2317 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2318 2319 for (i = 0; i < host->num_slots; i++) { 2320 dev_dbg(host->dev, "remove slot %d\n", i); 2321 if (host->slot[i]) 2322 dw_mci_cleanup_slot(host->slot[i], i); 2323 } 2324 2325 /* disable clock to CIU */ 2326 mci_writel(host, CLKENA, 0); 2327 mci_writel(host, CLKSRC, 0); 2328 2329 destroy_workqueue(host->card_workqueue); 2330 2331 if (host->use_dma && host->dma_ops->exit) 2332 host->dma_ops->exit(host); 2333 2334 if (host->vmmc) 2335 regulator_disable(host->vmmc); 2336 2337 if (!IS_ERR(host->ciu_clk)) 2338 clk_disable_unprepare(host->ciu_clk); 2339 2340 if (!IS_ERR(host->biu_clk)) 2341 clk_disable_unprepare(host->biu_clk); 2342 } 2343 EXPORT_SYMBOL(dw_mci_remove); 2344 2345 2346 2347 #ifdef CONFIG_PM_SLEEP 2348 /* 2349 * TODO: we should probably disable the clock to the card in the suspend path. 2350 */ 2351 int dw_mci_suspend(struct dw_mci *host) 2352 { 2353 int i, ret = 0; 2354 2355 for (i = 0; i < host->num_slots; i++) { 2356 struct dw_mci_slot *slot = host->slot[i]; 2357 if (!slot) 2358 continue; 2359 ret = mmc_suspend_host(slot->mmc); 2360 if (ret < 0) { 2361 while (--i >= 0) { 2362 slot = host->slot[i]; 2363 if (slot) 2364 mmc_resume_host(host->slot[i]->mmc); 2365 } 2366 return ret; 2367 } 2368 } 2369 2370 if (host->vmmc) 2371 regulator_disable(host->vmmc); 2372 2373 return 0; 2374 } 2375 EXPORT_SYMBOL(dw_mci_suspend); 2376 2377 int dw_mci_resume(struct dw_mci *host) 2378 { 2379 int i, ret; 2380 2381 if (host->vmmc) 2382 regulator_enable(host->vmmc); 2383 2384 if (!mci_wait_reset(host->dev, host)) { 2385 ret = -ENODEV; 2386 return ret; 2387 } 2388 2389 if (host->use_dma && host->dma_ops->init) 2390 host->dma_ops->init(host); 2391 2392 /* Restore the old value at FIFOTH register */ 2393 mci_writel(host, FIFOTH, host->fifoth_val); 2394 2395 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2396 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2397 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2398 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2399 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2400 2401 for (i = 0; i < host->num_slots; i++) { 2402 struct dw_mci_slot *slot = host->slot[i]; 2403 if (!slot) 2404 continue; 2405 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 2406 dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 2407 dw_mci_setup_bus(slot, true); 2408 } 2409 2410 ret = mmc_resume_host(host->slot[i]->mmc); 2411 if (ret < 0) 2412 return ret; 2413 } 2414 return 0; 2415 } 2416 EXPORT_SYMBOL(dw_mci_resume); 2417 #endif /* CONFIG_PM_SLEEP */ 2418 2419 static int __init dw_mci_init(void) 2420 { 2421 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver"); 2422 return 0; 2423 } 2424 2425 static void __exit dw_mci_exit(void) 2426 { 2427 } 2428 2429 module_init(dw_mci_init); 2430 module_exit(dw_mci_exit); 2431 2432 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 2433 MODULE_AUTHOR("NXP Semiconductor VietNam"); 2434 MODULE_AUTHOR("Imagination Technologies Ltd"); 2435 MODULE_LICENSE("GPL v2"); 2436