1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare Multimedia Card Interface driver 4 * (Based on NXP driver for lpc 31xx) 5 * 6 * Copyright (C) 2009 NXP Semiconductors 7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8 */ 9 10 #include <linux/blkdev.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/device.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/iopoll.h> 19 #include <linux/ioport.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 #include <linux/stat.h> 26 #include <linux/delay.h> 27 #include <linux/irq.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/bitops.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/of.h> 36 #include <linux/of_gpio.h> 37 #include <linux/mmc/slot-gpio.h> 38 39 #include "dw_mmc.h" 40 41 /* Common flag combinations */ 42 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 43 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 44 SDMMC_INT_EBE | SDMMC_INT_HLE) 45 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 46 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 47 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 48 DW_MCI_CMD_ERROR_FLAGS) 49 #define DW_MCI_SEND_STATUS 1 50 #define DW_MCI_RECV_STATUS 2 51 #define DW_MCI_DMA_THRESHOLD 16 52 53 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 54 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 55 56 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 57 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 58 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 59 SDMMC_IDMAC_INT_TI) 60 61 #define DESC_RING_BUF_SZ PAGE_SIZE 62 63 struct idmac_desc_64addr { 64 u32 des0; /* Control Descriptor */ 65 #define IDMAC_OWN_CLR64(x) \ 66 !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 67 68 u32 des1; /* Reserved */ 69 70 u32 des2; /*Buffer sizes */ 71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 74 75 u32 des3; /* Reserved */ 76 77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 79 80 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 81 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 82 }; 83 84 struct idmac_desc { 85 __le32 des0; /* Control Descriptor */ 86 #define IDMAC_DES0_DIC BIT(1) 87 #define IDMAC_DES0_LD BIT(2) 88 #define IDMAC_DES0_FD BIT(3) 89 #define IDMAC_DES0_CH BIT(4) 90 #define IDMAC_DES0_ER BIT(5) 91 #define IDMAC_DES0_CES BIT(30) 92 #define IDMAC_DES0_OWN BIT(31) 93 94 __le32 des1; /* Buffer sizes */ 95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 96 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 97 98 __le32 des2; /* buffer 1 physical address */ 99 100 __le32 des3; /* buffer 2 physical address */ 101 }; 102 103 /* Each descriptor can transfer up to 4KB of data in chained mode */ 104 #define DW_MCI_DESC_DATA_LENGTH 0x1000 105 106 #if defined(CONFIG_DEBUG_FS) 107 static int dw_mci_req_show(struct seq_file *s, void *v) 108 { 109 struct dw_mci_slot *slot = s->private; 110 struct mmc_request *mrq; 111 struct mmc_command *cmd; 112 struct mmc_command *stop; 113 struct mmc_data *data; 114 115 /* Make sure we get a consistent snapshot */ 116 spin_lock_bh(&slot->host->lock); 117 mrq = slot->mrq; 118 119 if (mrq) { 120 cmd = mrq->cmd; 121 data = mrq->data; 122 stop = mrq->stop; 123 124 if (cmd) 125 seq_printf(s, 126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 127 cmd->opcode, cmd->arg, cmd->flags, 128 cmd->resp[0], cmd->resp[1], cmd->resp[2], 129 cmd->resp[2], cmd->error); 130 if (data) 131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 132 data->bytes_xfered, data->blocks, 133 data->blksz, data->flags, data->error); 134 if (stop) 135 seq_printf(s, 136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 137 stop->opcode, stop->arg, stop->flags, 138 stop->resp[0], stop->resp[1], stop->resp[2], 139 stop->resp[2], stop->error); 140 } 141 142 spin_unlock_bh(&slot->host->lock); 143 144 return 0; 145 } 146 DEFINE_SHOW_ATTRIBUTE(dw_mci_req); 147 148 static int dw_mci_regs_show(struct seq_file *s, void *v) 149 { 150 struct dw_mci *host = s->private; 151 152 pm_runtime_get_sync(host->dev); 153 154 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 155 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 156 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 157 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 158 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 159 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 160 161 pm_runtime_put_autosuspend(host->dev); 162 163 return 0; 164 } 165 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs); 166 167 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 168 { 169 struct mmc_host *mmc = slot->mmc; 170 struct dw_mci *host = slot->host; 171 struct dentry *root; 172 173 root = mmc->debugfs_root; 174 if (!root) 175 return; 176 177 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops); 178 debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops); 179 debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 180 debugfs_create_x32("pending_events", S_IRUSR, root, 181 (u32 *)&host->pending_events); 182 debugfs_create_x32("completed_events", S_IRUSR, root, 183 (u32 *)&host->completed_events); 184 } 185 #endif /* defined(CONFIG_DEBUG_FS) */ 186 187 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 188 { 189 u32 ctrl; 190 191 ctrl = mci_readl(host, CTRL); 192 ctrl |= reset; 193 mci_writel(host, CTRL, ctrl); 194 195 /* wait till resets clear */ 196 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 197 !(ctrl & reset), 198 1, 500 * USEC_PER_MSEC)) { 199 dev_err(host->dev, 200 "Timeout resetting block (ctrl reset %#x)\n", 201 ctrl & reset); 202 return false; 203 } 204 205 return true; 206 } 207 208 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 209 { 210 u32 status; 211 212 /* 213 * Databook says that before issuing a new data transfer command 214 * we need to check to see if the card is busy. Data transfer commands 215 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 216 * 217 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 218 * expected. 219 */ 220 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 221 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 222 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 223 status, 224 !(status & SDMMC_STATUS_BUSY), 225 10, 500 * USEC_PER_MSEC)) 226 dev_err(host->dev, "Busy; trying anyway\n"); 227 } 228 } 229 230 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 231 { 232 struct dw_mci *host = slot->host; 233 unsigned int cmd_status = 0; 234 235 mci_writel(host, CMDARG, arg); 236 wmb(); /* drain writebuffer */ 237 dw_mci_wait_while_busy(host, cmd); 238 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 239 240 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 241 !(cmd_status & SDMMC_CMD_START), 242 1, 500 * USEC_PER_MSEC)) 243 dev_err(&slot->mmc->class_dev, 244 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 245 cmd, arg, cmd_status); 246 } 247 248 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 249 { 250 struct dw_mci_slot *slot = mmc_priv(mmc); 251 struct dw_mci *host = slot->host; 252 u32 cmdr; 253 254 cmd->error = -EINPROGRESS; 255 cmdr = cmd->opcode; 256 257 if (cmd->opcode == MMC_STOP_TRANSMISSION || 258 cmd->opcode == MMC_GO_IDLE_STATE || 259 cmd->opcode == MMC_GO_INACTIVE_STATE || 260 (cmd->opcode == SD_IO_RW_DIRECT && 261 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 262 cmdr |= SDMMC_CMD_STOP; 263 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 264 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 265 266 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 267 u32 clk_en_a; 268 269 /* Special bit makes CMD11 not die */ 270 cmdr |= SDMMC_CMD_VOLT_SWITCH; 271 272 /* Change state to continue to handle CMD11 weirdness */ 273 WARN_ON(slot->host->state != STATE_SENDING_CMD); 274 slot->host->state = STATE_SENDING_CMD11; 275 276 /* 277 * We need to disable low power mode (automatic clock stop) 278 * while doing voltage switch so we don't confuse the card, 279 * since stopping the clock is a specific part of the UHS 280 * voltage change dance. 281 * 282 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 283 * unconditionally turned back on in dw_mci_setup_bus() if it's 284 * ever called with a non-zero clock. That shouldn't happen 285 * until the voltage change is all done. 286 */ 287 clk_en_a = mci_readl(host, CLKENA); 288 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 289 mci_writel(host, CLKENA, clk_en_a); 290 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 291 SDMMC_CMD_PRV_DAT_WAIT, 0); 292 } 293 294 if (cmd->flags & MMC_RSP_PRESENT) { 295 /* We expect a response, so set this bit */ 296 cmdr |= SDMMC_CMD_RESP_EXP; 297 if (cmd->flags & MMC_RSP_136) 298 cmdr |= SDMMC_CMD_RESP_LONG; 299 } 300 301 if (cmd->flags & MMC_RSP_CRC) 302 cmdr |= SDMMC_CMD_RESP_CRC; 303 304 if (cmd->data) { 305 cmdr |= SDMMC_CMD_DAT_EXP; 306 if (cmd->data->flags & MMC_DATA_WRITE) 307 cmdr |= SDMMC_CMD_DAT_WR; 308 } 309 310 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 311 cmdr |= SDMMC_CMD_USE_HOLD_REG; 312 313 return cmdr; 314 } 315 316 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 317 { 318 struct mmc_command *stop; 319 u32 cmdr; 320 321 if (!cmd->data) 322 return 0; 323 324 stop = &host->stop_abort; 325 cmdr = cmd->opcode; 326 memset(stop, 0, sizeof(struct mmc_command)); 327 328 if (cmdr == MMC_READ_SINGLE_BLOCK || 329 cmdr == MMC_READ_MULTIPLE_BLOCK || 330 cmdr == MMC_WRITE_BLOCK || 331 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 332 cmdr == MMC_SEND_TUNING_BLOCK || 333 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 334 stop->opcode = MMC_STOP_TRANSMISSION; 335 stop->arg = 0; 336 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 337 } else if (cmdr == SD_IO_RW_EXTENDED) { 338 stop->opcode = SD_IO_RW_DIRECT; 339 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 340 ((cmd->arg >> 28) & 0x7); 341 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 342 } else { 343 return 0; 344 } 345 346 cmdr = stop->opcode | SDMMC_CMD_STOP | 347 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 348 349 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 350 cmdr |= SDMMC_CMD_USE_HOLD_REG; 351 352 return cmdr; 353 } 354 355 static inline void dw_mci_set_cto(struct dw_mci *host) 356 { 357 unsigned int cto_clks; 358 unsigned int cto_div; 359 unsigned int cto_ms; 360 unsigned long irqflags; 361 362 cto_clks = mci_readl(host, TMOUT) & 0xff; 363 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 364 if (cto_div == 0) 365 cto_div = 1; 366 367 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 368 host->bus_hz); 369 370 /* add a bit spare time */ 371 cto_ms += 10; 372 373 /* 374 * The durations we're working with are fairly short so we have to be 375 * extra careful about synchronization here. Specifically in hardware a 376 * command timeout is _at most_ 5.1 ms, so that means we expect an 377 * interrupt (either command done or timeout) to come rather quickly 378 * after the mci_writel. ...but just in case we have a long interrupt 379 * latency let's add a bit of paranoia. 380 * 381 * In general we'll assume that at least an interrupt will be asserted 382 * in hardware by the time the cto_timer runs. ...and if it hasn't 383 * been asserted in hardware by that time then we'll assume it'll never 384 * come. 385 */ 386 spin_lock_irqsave(&host->irq_lock, irqflags); 387 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 388 mod_timer(&host->cto_timer, 389 jiffies + msecs_to_jiffies(cto_ms) + 1); 390 spin_unlock_irqrestore(&host->irq_lock, irqflags); 391 } 392 393 static void dw_mci_start_command(struct dw_mci *host, 394 struct mmc_command *cmd, u32 cmd_flags) 395 { 396 host->cmd = cmd; 397 dev_vdbg(host->dev, 398 "start command: ARGR=0x%08x CMDR=0x%08x\n", 399 cmd->arg, cmd_flags); 400 401 mci_writel(host, CMDARG, cmd->arg); 402 wmb(); /* drain writebuffer */ 403 dw_mci_wait_while_busy(host, cmd_flags); 404 405 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 406 407 /* response expected command only */ 408 if (cmd_flags & SDMMC_CMD_RESP_EXP) 409 dw_mci_set_cto(host); 410 } 411 412 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 413 { 414 struct mmc_command *stop = &host->stop_abort; 415 416 dw_mci_start_command(host, stop, host->stop_cmdr); 417 } 418 419 /* DMA interface functions */ 420 static void dw_mci_stop_dma(struct dw_mci *host) 421 { 422 if (host->using_dma) { 423 host->dma_ops->stop(host); 424 host->dma_ops->cleanup(host); 425 } 426 427 /* Data transfer was stopped by the interrupt handler */ 428 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 429 } 430 431 static void dw_mci_dma_cleanup(struct dw_mci *host) 432 { 433 struct mmc_data *data = host->data; 434 435 if (data && data->host_cookie == COOKIE_MAPPED) { 436 dma_unmap_sg(host->dev, 437 data->sg, 438 data->sg_len, 439 mmc_get_dma_dir(data)); 440 data->host_cookie = COOKIE_UNMAPPED; 441 } 442 } 443 444 static void dw_mci_idmac_reset(struct dw_mci *host) 445 { 446 u32 bmod = mci_readl(host, BMOD); 447 /* Software reset of DMA */ 448 bmod |= SDMMC_IDMAC_SWRESET; 449 mci_writel(host, BMOD, bmod); 450 } 451 452 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 453 { 454 u32 temp; 455 456 /* Disable and reset the IDMAC interface */ 457 temp = mci_readl(host, CTRL); 458 temp &= ~SDMMC_CTRL_USE_IDMAC; 459 temp |= SDMMC_CTRL_DMA_RESET; 460 mci_writel(host, CTRL, temp); 461 462 /* Stop the IDMAC running */ 463 temp = mci_readl(host, BMOD); 464 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 465 temp |= SDMMC_IDMAC_SWRESET; 466 mci_writel(host, BMOD, temp); 467 } 468 469 static void dw_mci_dmac_complete_dma(void *arg) 470 { 471 struct dw_mci *host = arg; 472 struct mmc_data *data = host->data; 473 474 dev_vdbg(host->dev, "DMA complete\n"); 475 476 if ((host->use_dma == TRANS_MODE_EDMAC) && 477 data && (data->flags & MMC_DATA_READ)) 478 /* Invalidate cache after read */ 479 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 480 data->sg, 481 data->sg_len, 482 DMA_FROM_DEVICE); 483 484 host->dma_ops->cleanup(host); 485 486 /* 487 * If the card was removed, data will be NULL. No point in trying to 488 * send the stop command or waiting for NBUSY in this case. 489 */ 490 if (data) { 491 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 492 tasklet_schedule(&host->tasklet); 493 } 494 } 495 496 static int dw_mci_idmac_init(struct dw_mci *host) 497 { 498 int i; 499 500 if (host->dma_64bit_address == 1) { 501 struct idmac_desc_64addr *p; 502 /* Number of descriptors in the ring buffer */ 503 host->ring_size = 504 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 505 506 /* Forward link the descriptor list */ 507 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 508 i++, p++) { 509 p->des6 = (host->sg_dma + 510 (sizeof(struct idmac_desc_64addr) * 511 (i + 1))) & 0xffffffff; 512 513 p->des7 = (u64)(host->sg_dma + 514 (sizeof(struct idmac_desc_64addr) * 515 (i + 1))) >> 32; 516 /* Initialize reserved and buffer size fields to "0" */ 517 p->des0 = 0; 518 p->des1 = 0; 519 p->des2 = 0; 520 p->des3 = 0; 521 } 522 523 /* Set the last descriptor as the end-of-ring descriptor */ 524 p->des6 = host->sg_dma & 0xffffffff; 525 p->des7 = (u64)host->sg_dma >> 32; 526 p->des0 = IDMAC_DES0_ER; 527 528 } else { 529 struct idmac_desc *p; 530 /* Number of descriptors in the ring buffer */ 531 host->ring_size = 532 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 533 534 /* Forward link the descriptor list */ 535 for (i = 0, p = host->sg_cpu; 536 i < host->ring_size - 1; 537 i++, p++) { 538 p->des3 = cpu_to_le32(host->sg_dma + 539 (sizeof(struct idmac_desc) * (i + 1))); 540 p->des0 = 0; 541 p->des1 = 0; 542 } 543 544 /* Set the last descriptor as the end-of-ring descriptor */ 545 p->des3 = cpu_to_le32(host->sg_dma); 546 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 547 } 548 549 dw_mci_idmac_reset(host); 550 551 if (host->dma_64bit_address == 1) { 552 /* Mask out interrupts - get Tx & Rx complete only */ 553 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 554 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 555 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 556 557 /* Set the descriptor base address */ 558 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 559 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 560 561 } else { 562 /* Mask out interrupts - get Tx & Rx complete only */ 563 mci_writel(host, IDSTS, IDMAC_INT_CLR); 564 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 565 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 566 567 /* Set the descriptor base address */ 568 mci_writel(host, DBADDR, host->sg_dma); 569 } 570 571 return 0; 572 } 573 574 static inline int dw_mci_prepare_desc64(struct dw_mci *host, 575 struct mmc_data *data, 576 unsigned int sg_len) 577 { 578 unsigned int desc_len; 579 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 580 u32 val; 581 int i; 582 583 desc_first = desc_last = desc = host->sg_cpu; 584 585 for (i = 0; i < sg_len; i++) { 586 unsigned int length = sg_dma_len(&data->sg[i]); 587 588 u64 mem_addr = sg_dma_address(&data->sg[i]); 589 590 for ( ; length ; desc++) { 591 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 592 length : DW_MCI_DESC_DATA_LENGTH; 593 594 length -= desc_len; 595 596 /* 597 * Wait for the former clear OWN bit operation 598 * of IDMAC to make sure that this descriptor 599 * isn't still owned by IDMAC as IDMAC's write 600 * ops and CPU's read ops are asynchronous. 601 */ 602 if (readl_poll_timeout_atomic(&desc->des0, val, 603 !(val & IDMAC_DES0_OWN), 604 10, 100 * USEC_PER_MSEC)) 605 goto err_own_bit; 606 607 /* 608 * Set the OWN bit and disable interrupts 609 * for this descriptor 610 */ 611 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 612 IDMAC_DES0_CH; 613 614 /* Buffer length */ 615 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 616 617 /* Physical address to DMA to/from */ 618 desc->des4 = mem_addr & 0xffffffff; 619 desc->des5 = mem_addr >> 32; 620 621 /* Update physical address for the next desc */ 622 mem_addr += desc_len; 623 624 /* Save pointer to the last descriptor */ 625 desc_last = desc; 626 } 627 } 628 629 /* Set first descriptor */ 630 desc_first->des0 |= IDMAC_DES0_FD; 631 632 /* Set last descriptor */ 633 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 634 desc_last->des0 |= IDMAC_DES0_LD; 635 636 return 0; 637 err_own_bit: 638 /* restore the descriptor chain as it's polluted */ 639 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 640 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 641 dw_mci_idmac_init(host); 642 return -EINVAL; 643 } 644 645 646 static inline int dw_mci_prepare_desc32(struct dw_mci *host, 647 struct mmc_data *data, 648 unsigned int sg_len) 649 { 650 unsigned int desc_len; 651 struct idmac_desc *desc_first, *desc_last, *desc; 652 u32 val; 653 int i; 654 655 desc_first = desc_last = desc = host->sg_cpu; 656 657 for (i = 0; i < sg_len; i++) { 658 unsigned int length = sg_dma_len(&data->sg[i]); 659 660 u32 mem_addr = sg_dma_address(&data->sg[i]); 661 662 for ( ; length ; desc++) { 663 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 664 length : DW_MCI_DESC_DATA_LENGTH; 665 666 length -= desc_len; 667 668 /* 669 * Wait for the former clear OWN bit operation 670 * of IDMAC to make sure that this descriptor 671 * isn't still owned by IDMAC as IDMAC's write 672 * ops and CPU's read ops are asynchronous. 673 */ 674 if (readl_poll_timeout_atomic(&desc->des0, val, 675 IDMAC_OWN_CLR64(val), 676 10, 677 100 * USEC_PER_MSEC)) 678 goto err_own_bit; 679 680 /* 681 * Set the OWN bit and disable interrupts 682 * for this descriptor 683 */ 684 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 685 IDMAC_DES0_DIC | 686 IDMAC_DES0_CH); 687 688 /* Buffer length */ 689 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 690 691 /* Physical address to DMA to/from */ 692 desc->des2 = cpu_to_le32(mem_addr); 693 694 /* Update physical address for the next desc */ 695 mem_addr += desc_len; 696 697 /* Save pointer to the last descriptor */ 698 desc_last = desc; 699 } 700 } 701 702 /* Set first descriptor */ 703 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 704 705 /* Set last descriptor */ 706 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 707 IDMAC_DES0_DIC)); 708 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 709 710 return 0; 711 err_own_bit: 712 /* restore the descriptor chain as it's polluted */ 713 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 714 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 715 dw_mci_idmac_init(host); 716 return -EINVAL; 717 } 718 719 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 720 { 721 u32 temp; 722 int ret; 723 724 if (host->dma_64bit_address == 1) 725 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 726 else 727 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 728 729 if (ret) 730 goto out; 731 732 /* drain writebuffer */ 733 wmb(); 734 735 /* Make sure to reset DMA in case we did PIO before this */ 736 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 737 dw_mci_idmac_reset(host); 738 739 /* Select IDMAC interface */ 740 temp = mci_readl(host, CTRL); 741 temp |= SDMMC_CTRL_USE_IDMAC; 742 mci_writel(host, CTRL, temp); 743 744 /* drain writebuffer */ 745 wmb(); 746 747 /* Enable the IDMAC */ 748 temp = mci_readl(host, BMOD); 749 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 750 mci_writel(host, BMOD, temp); 751 752 /* Start it running */ 753 mci_writel(host, PLDMND, 1); 754 755 out: 756 return ret; 757 } 758 759 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 760 .init = dw_mci_idmac_init, 761 .start = dw_mci_idmac_start_dma, 762 .stop = dw_mci_idmac_stop_dma, 763 .complete = dw_mci_dmac_complete_dma, 764 .cleanup = dw_mci_dma_cleanup, 765 }; 766 767 static void dw_mci_edmac_stop_dma(struct dw_mci *host) 768 { 769 dmaengine_terminate_async(host->dms->ch); 770 } 771 772 static int dw_mci_edmac_start_dma(struct dw_mci *host, 773 unsigned int sg_len) 774 { 775 struct dma_slave_config cfg; 776 struct dma_async_tx_descriptor *desc = NULL; 777 struct scatterlist *sgl = host->data->sg; 778 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 779 u32 sg_elems = host->data->sg_len; 780 u32 fifoth_val; 781 u32 fifo_offset = host->fifo_reg - host->regs; 782 int ret = 0; 783 784 /* Set external dma config: burst size, burst width */ 785 cfg.dst_addr = host->phy_regs + fifo_offset; 786 cfg.src_addr = cfg.dst_addr; 787 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 788 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 789 790 /* Match burst msize with external dma config */ 791 fifoth_val = mci_readl(host, FIFOTH); 792 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 793 cfg.src_maxburst = cfg.dst_maxburst; 794 795 if (host->data->flags & MMC_DATA_WRITE) 796 cfg.direction = DMA_MEM_TO_DEV; 797 else 798 cfg.direction = DMA_DEV_TO_MEM; 799 800 ret = dmaengine_slave_config(host->dms->ch, &cfg); 801 if (ret) { 802 dev_err(host->dev, "Failed to config edmac.\n"); 803 return -EBUSY; 804 } 805 806 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 807 sg_len, cfg.direction, 808 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 809 if (!desc) { 810 dev_err(host->dev, "Can't prepare slave sg.\n"); 811 return -EBUSY; 812 } 813 814 /* Set dw_mci_dmac_complete_dma as callback */ 815 desc->callback = dw_mci_dmac_complete_dma; 816 desc->callback_param = (void *)host; 817 dmaengine_submit(desc); 818 819 /* Flush cache before write */ 820 if (host->data->flags & MMC_DATA_WRITE) 821 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 822 sg_elems, DMA_TO_DEVICE); 823 824 dma_async_issue_pending(host->dms->ch); 825 826 return 0; 827 } 828 829 static int dw_mci_edmac_init(struct dw_mci *host) 830 { 831 /* Request external dma channel */ 832 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 833 if (!host->dms) 834 return -ENOMEM; 835 836 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 837 if (!host->dms->ch) { 838 dev_err(host->dev, "Failed to get external DMA channel.\n"); 839 kfree(host->dms); 840 host->dms = NULL; 841 return -ENXIO; 842 } 843 844 return 0; 845 } 846 847 static void dw_mci_edmac_exit(struct dw_mci *host) 848 { 849 if (host->dms) { 850 if (host->dms->ch) { 851 dma_release_channel(host->dms->ch); 852 host->dms->ch = NULL; 853 } 854 kfree(host->dms); 855 host->dms = NULL; 856 } 857 } 858 859 static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 860 .init = dw_mci_edmac_init, 861 .exit = dw_mci_edmac_exit, 862 .start = dw_mci_edmac_start_dma, 863 .stop = dw_mci_edmac_stop_dma, 864 .complete = dw_mci_dmac_complete_dma, 865 .cleanup = dw_mci_dma_cleanup, 866 }; 867 868 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 869 struct mmc_data *data, 870 int cookie) 871 { 872 struct scatterlist *sg; 873 unsigned int i, sg_len; 874 875 if (data->host_cookie == COOKIE_PRE_MAPPED) 876 return data->sg_len; 877 878 /* 879 * We don't do DMA on "complex" transfers, i.e. with 880 * non-word-aligned buffers or lengths. Also, we don't bother 881 * with all the DMA setup overhead for short transfers. 882 */ 883 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 884 return -EINVAL; 885 886 if (data->blksz & 3) 887 return -EINVAL; 888 889 for_each_sg(data->sg, sg, data->sg_len, i) { 890 if (sg->offset & 3 || sg->length & 3) 891 return -EINVAL; 892 } 893 894 sg_len = dma_map_sg(host->dev, 895 data->sg, 896 data->sg_len, 897 mmc_get_dma_dir(data)); 898 if (sg_len == 0) 899 return -EINVAL; 900 901 data->host_cookie = cookie; 902 903 return sg_len; 904 } 905 906 static void dw_mci_pre_req(struct mmc_host *mmc, 907 struct mmc_request *mrq) 908 { 909 struct dw_mci_slot *slot = mmc_priv(mmc); 910 struct mmc_data *data = mrq->data; 911 912 if (!slot->host->use_dma || !data) 913 return; 914 915 /* This data might be unmapped at this time */ 916 data->host_cookie = COOKIE_UNMAPPED; 917 918 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 919 COOKIE_PRE_MAPPED) < 0) 920 data->host_cookie = COOKIE_UNMAPPED; 921 } 922 923 static void dw_mci_post_req(struct mmc_host *mmc, 924 struct mmc_request *mrq, 925 int err) 926 { 927 struct dw_mci_slot *slot = mmc_priv(mmc); 928 struct mmc_data *data = mrq->data; 929 930 if (!slot->host->use_dma || !data) 931 return; 932 933 if (data->host_cookie != COOKIE_UNMAPPED) 934 dma_unmap_sg(slot->host->dev, 935 data->sg, 936 data->sg_len, 937 mmc_get_dma_dir(data)); 938 data->host_cookie = COOKIE_UNMAPPED; 939 } 940 941 static int dw_mci_get_cd(struct mmc_host *mmc) 942 { 943 int present; 944 struct dw_mci_slot *slot = mmc_priv(mmc); 945 struct dw_mci *host = slot->host; 946 int gpio_cd = mmc_gpio_get_cd(mmc); 947 948 /* Use platform get_cd function, else try onboard card detect */ 949 if (((mmc->caps & MMC_CAP_NEEDS_POLL) 950 || !mmc_card_is_removable(mmc))) { 951 present = 1; 952 953 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 954 if (mmc->caps & MMC_CAP_NEEDS_POLL) { 955 dev_info(&mmc->class_dev, 956 "card is polling.\n"); 957 } else { 958 dev_info(&mmc->class_dev, 959 "card is non-removable.\n"); 960 } 961 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 962 } 963 964 return present; 965 } else if (gpio_cd >= 0) 966 present = gpio_cd; 967 else 968 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 969 == 0 ? 1 : 0; 970 971 spin_lock_bh(&host->lock); 972 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 973 dev_dbg(&mmc->class_dev, "card is present\n"); 974 else if (!present && 975 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 976 dev_dbg(&mmc->class_dev, "card is not present\n"); 977 spin_unlock_bh(&host->lock); 978 979 return present; 980 } 981 982 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 983 { 984 unsigned int blksz = data->blksz; 985 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 986 u32 fifo_width = 1 << host->data_shift; 987 u32 blksz_depth = blksz / fifo_width, fifoth_val; 988 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 989 int idx = ARRAY_SIZE(mszs) - 1; 990 991 /* pio should ship this scenario */ 992 if (!host->use_dma) 993 return; 994 995 tx_wmark = (host->fifo_depth) / 2; 996 tx_wmark_invers = host->fifo_depth - tx_wmark; 997 998 /* 999 * MSIZE is '1', 1000 * if blksz is not a multiple of the FIFO width 1001 */ 1002 if (blksz % fifo_width) 1003 goto done; 1004 1005 do { 1006 if (!((blksz_depth % mszs[idx]) || 1007 (tx_wmark_invers % mszs[idx]))) { 1008 msize = idx; 1009 rx_wmark = mszs[idx] - 1; 1010 break; 1011 } 1012 } while (--idx > 0); 1013 /* 1014 * If idx is '0', it won't be tried 1015 * Thus, initial values are uesed 1016 */ 1017 done: 1018 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 1019 mci_writel(host, FIFOTH, fifoth_val); 1020 } 1021 1022 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1023 { 1024 unsigned int blksz = data->blksz; 1025 u32 blksz_depth, fifo_depth; 1026 u16 thld_size; 1027 u8 enable; 1028 1029 /* 1030 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 1031 * in the FIFO region, so we really shouldn't access it). 1032 */ 1033 if (host->verid < DW_MMC_240A || 1034 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 1035 return; 1036 1037 /* 1038 * Card write Threshold is introduced since 2.80a 1039 * It's used when HS400 mode is enabled. 1040 */ 1041 if (data->flags & MMC_DATA_WRITE && 1042 host->timing != MMC_TIMING_MMC_HS400) 1043 goto disable; 1044 1045 if (data->flags & MMC_DATA_WRITE) 1046 enable = SDMMC_CARD_WR_THR_EN; 1047 else 1048 enable = SDMMC_CARD_RD_THR_EN; 1049 1050 if (host->timing != MMC_TIMING_MMC_HS200 && 1051 host->timing != MMC_TIMING_UHS_SDR104 && 1052 host->timing != MMC_TIMING_MMC_HS400) 1053 goto disable; 1054 1055 blksz_depth = blksz / (1 << host->data_shift); 1056 fifo_depth = host->fifo_depth; 1057 1058 if (blksz_depth > fifo_depth) 1059 goto disable; 1060 1061 /* 1062 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1063 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1064 * Currently just choose blksz. 1065 */ 1066 thld_size = blksz; 1067 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1068 return; 1069 1070 disable: 1071 mci_writel(host, CDTHRCTL, 0); 1072 } 1073 1074 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1075 { 1076 unsigned long irqflags; 1077 int sg_len; 1078 u32 temp; 1079 1080 host->using_dma = 0; 1081 1082 /* If we don't have a channel, we can't do DMA */ 1083 if (!host->use_dma) 1084 return -ENODEV; 1085 1086 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1087 if (sg_len < 0) { 1088 host->dma_ops->stop(host); 1089 return sg_len; 1090 } 1091 1092 host->using_dma = 1; 1093 1094 if (host->use_dma == TRANS_MODE_IDMAC) 1095 dev_vdbg(host->dev, 1096 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1097 (unsigned long)host->sg_cpu, 1098 (unsigned long)host->sg_dma, 1099 sg_len); 1100 1101 /* 1102 * Decide the MSIZE and RX/TX Watermark. 1103 * If current block size is same with previous size, 1104 * no need to update fifoth. 1105 */ 1106 if (host->prev_blksz != data->blksz) 1107 dw_mci_adjust_fifoth(host, data); 1108 1109 /* Enable the DMA interface */ 1110 temp = mci_readl(host, CTRL); 1111 temp |= SDMMC_CTRL_DMA_ENABLE; 1112 mci_writel(host, CTRL, temp); 1113 1114 /* Disable RX/TX IRQs, let DMA handle it */ 1115 spin_lock_irqsave(&host->irq_lock, irqflags); 1116 temp = mci_readl(host, INTMASK); 1117 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1118 mci_writel(host, INTMASK, temp); 1119 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1120 1121 if (host->dma_ops->start(host, sg_len)) { 1122 host->dma_ops->stop(host); 1123 /* We can't do DMA, try PIO for this one */ 1124 dev_dbg(host->dev, 1125 "%s: fall back to PIO mode for current transfer\n", 1126 __func__); 1127 return -ENODEV; 1128 } 1129 1130 return 0; 1131 } 1132 1133 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1134 { 1135 unsigned long irqflags; 1136 int flags = SG_MITER_ATOMIC; 1137 u32 temp; 1138 1139 data->error = -EINPROGRESS; 1140 1141 WARN_ON(host->data); 1142 host->sg = NULL; 1143 host->data = data; 1144 1145 if (data->flags & MMC_DATA_READ) 1146 host->dir_status = DW_MCI_RECV_STATUS; 1147 else 1148 host->dir_status = DW_MCI_SEND_STATUS; 1149 1150 dw_mci_ctrl_thld(host, data); 1151 1152 if (dw_mci_submit_data_dma(host, data)) { 1153 if (host->data->flags & MMC_DATA_READ) 1154 flags |= SG_MITER_TO_SG; 1155 else 1156 flags |= SG_MITER_FROM_SG; 1157 1158 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1159 host->sg = data->sg; 1160 host->part_buf_start = 0; 1161 host->part_buf_count = 0; 1162 1163 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1164 1165 spin_lock_irqsave(&host->irq_lock, irqflags); 1166 temp = mci_readl(host, INTMASK); 1167 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1168 mci_writel(host, INTMASK, temp); 1169 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1170 1171 temp = mci_readl(host, CTRL); 1172 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1173 mci_writel(host, CTRL, temp); 1174 1175 /* 1176 * Use the initial fifoth_val for PIO mode. If wm_algined 1177 * is set, we set watermark same as data size. 1178 * If next issued data may be transfered by DMA mode, 1179 * prev_blksz should be invalidated. 1180 */ 1181 if (host->wm_aligned) 1182 dw_mci_adjust_fifoth(host, data); 1183 else 1184 mci_writel(host, FIFOTH, host->fifoth_val); 1185 host->prev_blksz = 0; 1186 } else { 1187 /* 1188 * Keep the current block size. 1189 * It will be used to decide whether to update 1190 * fifoth register next time. 1191 */ 1192 host->prev_blksz = data->blksz; 1193 } 1194 } 1195 1196 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1197 { 1198 struct dw_mci *host = slot->host; 1199 unsigned int clock = slot->clock; 1200 u32 div; 1201 u32 clk_en_a; 1202 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1203 1204 /* We must continue to set bit 28 in CMD until the change is complete */ 1205 if (host->state == STATE_WAITING_CMD11_DONE) 1206 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1207 1208 slot->mmc->actual_clock = 0; 1209 1210 if (!clock) { 1211 mci_writel(host, CLKENA, 0); 1212 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1213 } else if (clock != host->current_speed || force_clkinit) { 1214 div = host->bus_hz / clock; 1215 if (host->bus_hz % clock && host->bus_hz > clock) 1216 /* 1217 * move the + 1 after the divide to prevent 1218 * over-clocking the card. 1219 */ 1220 div += 1; 1221 1222 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1223 1224 if ((clock != slot->__clk_old && 1225 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1226 force_clkinit) { 1227 /* Silent the verbose log if calling from PM context */ 1228 if (!force_clkinit) 1229 dev_info(&slot->mmc->class_dev, 1230 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1231 slot->id, host->bus_hz, clock, 1232 div ? ((host->bus_hz / div) >> 1) : 1233 host->bus_hz, div); 1234 1235 /* 1236 * If card is polling, display the message only 1237 * one time at boot time. 1238 */ 1239 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1240 slot->mmc->f_min == clock) 1241 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1242 } 1243 1244 /* disable clock */ 1245 mci_writel(host, CLKENA, 0); 1246 mci_writel(host, CLKSRC, 0); 1247 1248 /* inform CIU */ 1249 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1250 1251 /* set clock to desired speed */ 1252 mci_writel(host, CLKDIV, div); 1253 1254 /* inform CIU */ 1255 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1256 1257 /* enable clock; only low power if no SDIO */ 1258 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1259 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1260 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1261 mci_writel(host, CLKENA, clk_en_a); 1262 1263 /* inform CIU */ 1264 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1265 1266 /* keep the last clock value that was requested from core */ 1267 slot->__clk_old = clock; 1268 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : 1269 host->bus_hz; 1270 } 1271 1272 host->current_speed = clock; 1273 1274 /* Set the current slot bus width */ 1275 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1276 } 1277 1278 static void __dw_mci_start_request(struct dw_mci *host, 1279 struct dw_mci_slot *slot, 1280 struct mmc_command *cmd) 1281 { 1282 struct mmc_request *mrq; 1283 struct mmc_data *data; 1284 u32 cmdflags; 1285 1286 mrq = slot->mrq; 1287 1288 host->mrq = mrq; 1289 1290 host->pending_events = 0; 1291 host->completed_events = 0; 1292 host->cmd_status = 0; 1293 host->data_status = 0; 1294 host->dir_status = 0; 1295 1296 data = cmd->data; 1297 if (data) { 1298 mci_writel(host, TMOUT, 0xFFFFFFFF); 1299 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1300 mci_writel(host, BLKSIZ, data->blksz); 1301 } 1302 1303 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1304 1305 /* this is the first command, send the initialization clock */ 1306 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1307 cmdflags |= SDMMC_CMD_INIT; 1308 1309 if (data) { 1310 dw_mci_submit_data(host, data); 1311 wmb(); /* drain writebuffer */ 1312 } 1313 1314 dw_mci_start_command(host, cmd, cmdflags); 1315 1316 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1317 unsigned long irqflags; 1318 1319 /* 1320 * Databook says to fail after 2ms w/ no response, but evidence 1321 * shows that sometimes the cmd11 interrupt takes over 130ms. 1322 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1323 * is just about to roll over. 1324 * 1325 * We do this whole thing under spinlock and only if the 1326 * command hasn't already completed (indicating the the irq 1327 * already ran so we don't want the timeout). 1328 */ 1329 spin_lock_irqsave(&host->irq_lock, irqflags); 1330 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1331 mod_timer(&host->cmd11_timer, 1332 jiffies + msecs_to_jiffies(500) + 1); 1333 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1334 } 1335 1336 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1337 } 1338 1339 static void dw_mci_start_request(struct dw_mci *host, 1340 struct dw_mci_slot *slot) 1341 { 1342 struct mmc_request *mrq = slot->mrq; 1343 struct mmc_command *cmd; 1344 1345 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1346 __dw_mci_start_request(host, slot, cmd); 1347 } 1348 1349 /* must be called with host->lock held */ 1350 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1351 struct mmc_request *mrq) 1352 { 1353 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1354 host->state); 1355 1356 slot->mrq = mrq; 1357 1358 if (host->state == STATE_WAITING_CMD11_DONE) { 1359 dev_warn(&slot->mmc->class_dev, 1360 "Voltage change didn't complete\n"); 1361 /* 1362 * this case isn't expected to happen, so we can 1363 * either crash here or just try to continue on 1364 * in the closest possible state 1365 */ 1366 host->state = STATE_IDLE; 1367 } 1368 1369 if (host->state == STATE_IDLE) { 1370 host->state = STATE_SENDING_CMD; 1371 dw_mci_start_request(host, slot); 1372 } else { 1373 list_add_tail(&slot->queue_node, &host->queue); 1374 } 1375 } 1376 1377 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1378 { 1379 struct dw_mci_slot *slot = mmc_priv(mmc); 1380 struct dw_mci *host = slot->host; 1381 1382 WARN_ON(slot->mrq); 1383 1384 /* 1385 * The check for card presence and queueing of the request must be 1386 * atomic, otherwise the card could be removed in between and the 1387 * request wouldn't fail until another card was inserted. 1388 */ 1389 1390 if (!dw_mci_get_cd(mmc)) { 1391 mrq->cmd->error = -ENOMEDIUM; 1392 mmc_request_done(mmc, mrq); 1393 return; 1394 } 1395 1396 spin_lock_bh(&host->lock); 1397 1398 dw_mci_queue_request(host, slot, mrq); 1399 1400 spin_unlock_bh(&host->lock); 1401 } 1402 1403 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1404 { 1405 struct dw_mci_slot *slot = mmc_priv(mmc); 1406 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1407 u32 regs; 1408 int ret; 1409 1410 switch (ios->bus_width) { 1411 case MMC_BUS_WIDTH_4: 1412 slot->ctype = SDMMC_CTYPE_4BIT; 1413 break; 1414 case MMC_BUS_WIDTH_8: 1415 slot->ctype = SDMMC_CTYPE_8BIT; 1416 break; 1417 default: 1418 /* set default 1 bit mode */ 1419 slot->ctype = SDMMC_CTYPE_1BIT; 1420 } 1421 1422 regs = mci_readl(slot->host, UHS_REG); 1423 1424 /* DDR mode set */ 1425 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1426 ios->timing == MMC_TIMING_UHS_DDR50 || 1427 ios->timing == MMC_TIMING_MMC_HS400) 1428 regs |= ((0x1 << slot->id) << 16); 1429 else 1430 regs &= ~((0x1 << slot->id) << 16); 1431 1432 mci_writel(slot->host, UHS_REG, regs); 1433 slot->host->timing = ios->timing; 1434 1435 /* 1436 * Use mirror of ios->clock to prevent race with mmc 1437 * core ios update when finding the minimum. 1438 */ 1439 slot->clock = ios->clock; 1440 1441 if (drv_data && drv_data->set_ios) 1442 drv_data->set_ios(slot->host, ios); 1443 1444 switch (ios->power_mode) { 1445 case MMC_POWER_UP: 1446 if (!IS_ERR(mmc->supply.vmmc)) { 1447 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1448 ios->vdd); 1449 if (ret) { 1450 dev_err(slot->host->dev, 1451 "failed to enable vmmc regulator\n"); 1452 /*return, if failed turn on vmmc*/ 1453 return; 1454 } 1455 } 1456 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1457 regs = mci_readl(slot->host, PWREN); 1458 regs |= (1 << slot->id); 1459 mci_writel(slot->host, PWREN, regs); 1460 break; 1461 case MMC_POWER_ON: 1462 if (!slot->host->vqmmc_enabled) { 1463 if (!IS_ERR(mmc->supply.vqmmc)) { 1464 ret = regulator_enable(mmc->supply.vqmmc); 1465 if (ret < 0) 1466 dev_err(slot->host->dev, 1467 "failed to enable vqmmc\n"); 1468 else 1469 slot->host->vqmmc_enabled = true; 1470 1471 } else { 1472 /* Keep track so we don't reset again */ 1473 slot->host->vqmmc_enabled = true; 1474 } 1475 1476 /* Reset our state machine after powering on */ 1477 dw_mci_ctrl_reset(slot->host, 1478 SDMMC_CTRL_ALL_RESET_FLAGS); 1479 } 1480 1481 /* Adjust clock / bus width after power is up */ 1482 dw_mci_setup_bus(slot, false); 1483 1484 break; 1485 case MMC_POWER_OFF: 1486 /* Turn clock off before power goes down */ 1487 dw_mci_setup_bus(slot, false); 1488 1489 if (!IS_ERR(mmc->supply.vmmc)) 1490 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1491 1492 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1493 regulator_disable(mmc->supply.vqmmc); 1494 slot->host->vqmmc_enabled = false; 1495 1496 regs = mci_readl(slot->host, PWREN); 1497 regs &= ~(1 << slot->id); 1498 mci_writel(slot->host, PWREN, regs); 1499 break; 1500 default: 1501 break; 1502 } 1503 1504 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1505 slot->host->state = STATE_IDLE; 1506 } 1507 1508 static int dw_mci_card_busy(struct mmc_host *mmc) 1509 { 1510 struct dw_mci_slot *slot = mmc_priv(mmc); 1511 u32 status; 1512 1513 /* 1514 * Check the busy bit which is low when DAT[3:0] 1515 * (the data lines) are 0000 1516 */ 1517 status = mci_readl(slot->host, STATUS); 1518 1519 return !!(status & SDMMC_STATUS_BUSY); 1520 } 1521 1522 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1523 { 1524 struct dw_mci_slot *slot = mmc_priv(mmc); 1525 struct dw_mci *host = slot->host; 1526 const struct dw_mci_drv_data *drv_data = host->drv_data; 1527 u32 uhs; 1528 u32 v18 = SDMMC_UHS_18V << slot->id; 1529 int ret; 1530 1531 if (drv_data && drv_data->switch_voltage) 1532 return drv_data->switch_voltage(mmc, ios); 1533 1534 /* 1535 * Program the voltage. Note that some instances of dw_mmc may use 1536 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1537 * does no harm but you need to set the regulator directly. Try both. 1538 */ 1539 uhs = mci_readl(host, UHS_REG); 1540 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1541 uhs &= ~v18; 1542 else 1543 uhs |= v18; 1544 1545 if (!IS_ERR(mmc->supply.vqmmc)) { 1546 ret = mmc_regulator_set_vqmmc(mmc, ios); 1547 1548 if (ret) { 1549 dev_dbg(&mmc->class_dev, 1550 "Regulator set error %d - %s V\n", 1551 ret, uhs & v18 ? "1.8" : "3.3"); 1552 return ret; 1553 } 1554 } 1555 mci_writel(host, UHS_REG, uhs); 1556 1557 return 0; 1558 } 1559 1560 static int dw_mci_get_ro(struct mmc_host *mmc) 1561 { 1562 int read_only; 1563 struct dw_mci_slot *slot = mmc_priv(mmc); 1564 int gpio_ro = mmc_gpio_get_ro(mmc); 1565 1566 /* Use platform get_ro function, else try on board write protect */ 1567 if (gpio_ro >= 0) 1568 read_only = gpio_ro; 1569 else 1570 read_only = 1571 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1572 1573 dev_dbg(&mmc->class_dev, "card is %s\n", 1574 read_only ? "read-only" : "read-write"); 1575 1576 return read_only; 1577 } 1578 1579 static void dw_mci_hw_reset(struct mmc_host *mmc) 1580 { 1581 struct dw_mci_slot *slot = mmc_priv(mmc); 1582 struct dw_mci *host = slot->host; 1583 int reset; 1584 1585 if (host->use_dma == TRANS_MODE_IDMAC) 1586 dw_mci_idmac_reset(host); 1587 1588 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1589 SDMMC_CTRL_FIFO_RESET)) 1590 return; 1591 1592 /* 1593 * According to eMMC spec, card reset procedure: 1594 * tRstW >= 1us: RST_n pulse width 1595 * tRSCA >= 200us: RST_n to Command time 1596 * tRSTH >= 1us: RST_n high period 1597 */ 1598 reset = mci_readl(host, RST_N); 1599 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1600 mci_writel(host, RST_N, reset); 1601 usleep_range(1, 2); 1602 reset |= SDMMC_RST_HWACTIVE << slot->id; 1603 mci_writel(host, RST_N, reset); 1604 usleep_range(200, 300); 1605 } 1606 1607 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1608 { 1609 struct dw_mci_slot *slot = mmc_priv(mmc); 1610 struct dw_mci *host = slot->host; 1611 1612 /* 1613 * Low power mode will stop the card clock when idle. According to the 1614 * description of the CLKENA register we should disable low power mode 1615 * for SDIO cards if we need SDIO interrupts to work. 1616 */ 1617 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1618 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1619 u32 clk_en_a_old; 1620 u32 clk_en_a; 1621 1622 clk_en_a_old = mci_readl(host, CLKENA); 1623 1624 if (card->type == MMC_TYPE_SDIO || 1625 card->type == MMC_TYPE_SD_COMBO) { 1626 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1627 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1628 } else { 1629 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1630 clk_en_a = clk_en_a_old | clken_low_pwr; 1631 } 1632 1633 if (clk_en_a != clk_en_a_old) { 1634 mci_writel(host, CLKENA, clk_en_a); 1635 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1636 SDMMC_CMD_PRV_DAT_WAIT, 0); 1637 } 1638 } 1639 } 1640 1641 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 1642 { 1643 struct dw_mci *host = slot->host; 1644 unsigned long irqflags; 1645 u32 int_mask; 1646 1647 spin_lock_irqsave(&host->irq_lock, irqflags); 1648 1649 /* Enable/disable Slot Specific SDIO interrupt */ 1650 int_mask = mci_readl(host, INTMASK); 1651 if (enb) 1652 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1653 else 1654 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1655 mci_writel(host, INTMASK, int_mask); 1656 1657 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1658 } 1659 1660 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1661 { 1662 struct dw_mci_slot *slot = mmc_priv(mmc); 1663 struct dw_mci *host = slot->host; 1664 1665 __dw_mci_enable_sdio_irq(slot, enb); 1666 1667 /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1668 if (enb) 1669 pm_runtime_get_noresume(host->dev); 1670 else 1671 pm_runtime_put_noidle(host->dev); 1672 } 1673 1674 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 1675 { 1676 struct dw_mci_slot *slot = mmc_priv(mmc); 1677 1678 __dw_mci_enable_sdio_irq(slot, 1); 1679 } 1680 1681 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1682 { 1683 struct dw_mci_slot *slot = mmc_priv(mmc); 1684 struct dw_mci *host = slot->host; 1685 const struct dw_mci_drv_data *drv_data = host->drv_data; 1686 int err = -EINVAL; 1687 1688 if (drv_data && drv_data->execute_tuning) 1689 err = drv_data->execute_tuning(slot, opcode); 1690 return err; 1691 } 1692 1693 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1694 struct mmc_ios *ios) 1695 { 1696 struct dw_mci_slot *slot = mmc_priv(mmc); 1697 struct dw_mci *host = slot->host; 1698 const struct dw_mci_drv_data *drv_data = host->drv_data; 1699 1700 if (drv_data && drv_data->prepare_hs400_tuning) 1701 return drv_data->prepare_hs400_tuning(host, ios); 1702 1703 return 0; 1704 } 1705 1706 static bool dw_mci_reset(struct dw_mci *host) 1707 { 1708 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 1709 bool ret = false; 1710 u32 status = 0; 1711 1712 /* 1713 * Resetting generates a block interrupt, hence setting 1714 * the scatter-gather pointer to NULL. 1715 */ 1716 if (host->sg) { 1717 sg_miter_stop(&host->sg_miter); 1718 host->sg = NULL; 1719 } 1720 1721 if (host->use_dma) 1722 flags |= SDMMC_CTRL_DMA_RESET; 1723 1724 if (dw_mci_ctrl_reset(host, flags)) { 1725 /* 1726 * In all cases we clear the RAWINTS 1727 * register to clear any interrupts. 1728 */ 1729 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1730 1731 if (!host->use_dma) { 1732 ret = true; 1733 goto ciu_out; 1734 } 1735 1736 /* Wait for dma_req to be cleared */ 1737 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 1738 status, 1739 !(status & SDMMC_STATUS_DMA_REQ), 1740 1, 500 * USEC_PER_MSEC)) { 1741 dev_err(host->dev, 1742 "%s: Timeout waiting for dma_req to be cleared\n", 1743 __func__); 1744 goto ciu_out; 1745 } 1746 1747 /* when using DMA next we reset the fifo again */ 1748 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 1749 goto ciu_out; 1750 } else { 1751 /* if the controller reset bit did clear, then set clock regs */ 1752 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 1753 dev_err(host->dev, 1754 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 1755 __func__); 1756 goto ciu_out; 1757 } 1758 } 1759 1760 if (host->use_dma == TRANS_MODE_IDMAC) 1761 /* It is also required that we reinit idmac */ 1762 dw_mci_idmac_init(host); 1763 1764 ret = true; 1765 1766 ciu_out: 1767 /* After a CTRL reset we need to have CIU set clock registers */ 1768 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 1769 1770 return ret; 1771 } 1772 1773 static const struct mmc_host_ops dw_mci_ops = { 1774 .request = dw_mci_request, 1775 .pre_req = dw_mci_pre_req, 1776 .post_req = dw_mci_post_req, 1777 .set_ios = dw_mci_set_ios, 1778 .get_ro = dw_mci_get_ro, 1779 .get_cd = dw_mci_get_cd, 1780 .hw_reset = dw_mci_hw_reset, 1781 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1782 .ack_sdio_irq = dw_mci_ack_sdio_irq, 1783 .execute_tuning = dw_mci_execute_tuning, 1784 .card_busy = dw_mci_card_busy, 1785 .start_signal_voltage_switch = dw_mci_switch_voltage, 1786 .init_card = dw_mci_init_card, 1787 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1788 }; 1789 1790 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1791 __releases(&host->lock) 1792 __acquires(&host->lock) 1793 { 1794 struct dw_mci_slot *slot; 1795 struct mmc_host *prev_mmc = host->slot->mmc; 1796 1797 WARN_ON(host->cmd || host->data); 1798 1799 host->slot->mrq = NULL; 1800 host->mrq = NULL; 1801 if (!list_empty(&host->queue)) { 1802 slot = list_entry(host->queue.next, 1803 struct dw_mci_slot, queue_node); 1804 list_del(&slot->queue_node); 1805 dev_vdbg(host->dev, "list not empty: %s is next\n", 1806 mmc_hostname(slot->mmc)); 1807 host->state = STATE_SENDING_CMD; 1808 dw_mci_start_request(host, slot); 1809 } else { 1810 dev_vdbg(host->dev, "list empty\n"); 1811 1812 if (host->state == STATE_SENDING_CMD11) 1813 host->state = STATE_WAITING_CMD11_DONE; 1814 else 1815 host->state = STATE_IDLE; 1816 } 1817 1818 spin_unlock(&host->lock); 1819 mmc_request_done(prev_mmc, mrq); 1820 spin_lock(&host->lock); 1821 } 1822 1823 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1824 { 1825 u32 status = host->cmd_status; 1826 1827 host->cmd_status = 0; 1828 1829 /* Read the response from the card (up to 16 bytes) */ 1830 if (cmd->flags & MMC_RSP_PRESENT) { 1831 if (cmd->flags & MMC_RSP_136) { 1832 cmd->resp[3] = mci_readl(host, RESP0); 1833 cmd->resp[2] = mci_readl(host, RESP1); 1834 cmd->resp[1] = mci_readl(host, RESP2); 1835 cmd->resp[0] = mci_readl(host, RESP3); 1836 } else { 1837 cmd->resp[0] = mci_readl(host, RESP0); 1838 cmd->resp[1] = 0; 1839 cmd->resp[2] = 0; 1840 cmd->resp[3] = 0; 1841 } 1842 } 1843 1844 if (status & SDMMC_INT_RTO) 1845 cmd->error = -ETIMEDOUT; 1846 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1847 cmd->error = -EILSEQ; 1848 else if (status & SDMMC_INT_RESP_ERR) 1849 cmd->error = -EIO; 1850 else 1851 cmd->error = 0; 1852 1853 return cmd->error; 1854 } 1855 1856 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1857 { 1858 u32 status = host->data_status; 1859 1860 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1861 if (status & SDMMC_INT_DRTO) { 1862 data->error = -ETIMEDOUT; 1863 } else if (status & SDMMC_INT_DCRC) { 1864 data->error = -EILSEQ; 1865 } else if (status & SDMMC_INT_EBE) { 1866 if (host->dir_status == 1867 DW_MCI_SEND_STATUS) { 1868 /* 1869 * No data CRC status was returned. 1870 * The number of bytes transferred 1871 * will be exaggerated in PIO mode. 1872 */ 1873 data->bytes_xfered = 0; 1874 data->error = -ETIMEDOUT; 1875 } else if (host->dir_status == 1876 DW_MCI_RECV_STATUS) { 1877 data->error = -EILSEQ; 1878 } 1879 } else { 1880 /* SDMMC_INT_SBE is included */ 1881 data->error = -EILSEQ; 1882 } 1883 1884 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1885 1886 /* 1887 * After an error, there may be data lingering 1888 * in the FIFO 1889 */ 1890 dw_mci_reset(host); 1891 } else { 1892 data->bytes_xfered = data->blocks * data->blksz; 1893 data->error = 0; 1894 } 1895 1896 return data->error; 1897 } 1898 1899 static void dw_mci_set_drto(struct dw_mci *host) 1900 { 1901 unsigned int drto_clks; 1902 unsigned int drto_div; 1903 unsigned int drto_ms; 1904 unsigned long irqflags; 1905 1906 drto_clks = mci_readl(host, TMOUT) >> 8; 1907 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 1908 if (drto_div == 0) 1909 drto_div = 1; 1910 1911 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 1912 host->bus_hz); 1913 1914 /* add a bit spare time */ 1915 drto_ms += 10; 1916 1917 spin_lock_irqsave(&host->irq_lock, irqflags); 1918 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1919 mod_timer(&host->dto_timer, 1920 jiffies + msecs_to_jiffies(drto_ms)); 1921 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1922 } 1923 1924 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 1925 { 1926 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1927 return false; 1928 1929 /* 1930 * Really be certain that the timer has stopped. This is a bit of 1931 * paranoia and could only really happen if we had really bad 1932 * interrupt latency and the interrupt routine and timeout were 1933 * running concurrently so that the del_timer() in the interrupt 1934 * handler couldn't run. 1935 */ 1936 WARN_ON(del_timer_sync(&host->cto_timer)); 1937 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1938 1939 return true; 1940 } 1941 1942 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 1943 { 1944 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1945 return false; 1946 1947 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 1948 WARN_ON(del_timer_sync(&host->dto_timer)); 1949 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1950 1951 return true; 1952 } 1953 1954 static void dw_mci_tasklet_func(unsigned long priv) 1955 { 1956 struct dw_mci *host = (struct dw_mci *)priv; 1957 struct mmc_data *data; 1958 struct mmc_command *cmd; 1959 struct mmc_request *mrq; 1960 enum dw_mci_state state; 1961 enum dw_mci_state prev_state; 1962 unsigned int err; 1963 1964 spin_lock(&host->lock); 1965 1966 state = host->state; 1967 data = host->data; 1968 mrq = host->mrq; 1969 1970 do { 1971 prev_state = state; 1972 1973 switch (state) { 1974 case STATE_IDLE: 1975 case STATE_WAITING_CMD11_DONE: 1976 break; 1977 1978 case STATE_SENDING_CMD11: 1979 case STATE_SENDING_CMD: 1980 if (!dw_mci_clear_pending_cmd_complete(host)) 1981 break; 1982 1983 cmd = host->cmd; 1984 host->cmd = NULL; 1985 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1986 err = dw_mci_command_complete(host, cmd); 1987 if (cmd == mrq->sbc && !err) { 1988 __dw_mci_start_request(host, host->slot, 1989 mrq->cmd); 1990 goto unlock; 1991 } 1992 1993 if (cmd->data && err) { 1994 /* 1995 * During UHS tuning sequence, sending the stop 1996 * command after the response CRC error would 1997 * throw the system into a confused state 1998 * causing all future tuning phases to report 1999 * failure. 2000 * 2001 * In such case controller will move into a data 2002 * transfer state after a response error or 2003 * response CRC error. Let's let that finish 2004 * before trying to send a stop, so we'll go to 2005 * STATE_SENDING_DATA. 2006 * 2007 * Although letting the data transfer take place 2008 * will waste a bit of time (we already know 2009 * the command was bad), it can't cause any 2010 * errors since it's possible it would have 2011 * taken place anyway if this tasklet got 2012 * delayed. Allowing the transfer to take place 2013 * avoids races and keeps things simple. 2014 */ 2015 if (err != -ETIMEDOUT) { 2016 state = STATE_SENDING_DATA; 2017 continue; 2018 } 2019 2020 dw_mci_stop_dma(host); 2021 send_stop_abort(host, data); 2022 state = STATE_SENDING_STOP; 2023 break; 2024 } 2025 2026 if (!cmd->data || err) { 2027 dw_mci_request_end(host, mrq); 2028 goto unlock; 2029 } 2030 2031 prev_state = state = STATE_SENDING_DATA; 2032 /* fall through */ 2033 2034 case STATE_SENDING_DATA: 2035 /* 2036 * We could get a data error and never a transfer 2037 * complete so we'd better check for it here. 2038 * 2039 * Note that we don't really care if we also got a 2040 * transfer complete; stopping the DMA and sending an 2041 * abort won't hurt. 2042 */ 2043 if (test_and_clear_bit(EVENT_DATA_ERROR, 2044 &host->pending_events)) { 2045 dw_mci_stop_dma(host); 2046 if (!(host->data_status & (SDMMC_INT_DRTO | 2047 SDMMC_INT_EBE))) 2048 send_stop_abort(host, data); 2049 state = STATE_DATA_ERROR; 2050 break; 2051 } 2052 2053 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2054 &host->pending_events)) { 2055 /* 2056 * If all data-related interrupts don't come 2057 * within the given time in reading data state. 2058 */ 2059 if (host->dir_status == DW_MCI_RECV_STATUS) 2060 dw_mci_set_drto(host); 2061 break; 2062 } 2063 2064 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 2065 2066 /* 2067 * Handle an EVENT_DATA_ERROR that might have shown up 2068 * before the transfer completed. This might not have 2069 * been caught by the check above because the interrupt 2070 * could have gone off between the previous check and 2071 * the check for transfer complete. 2072 * 2073 * Technically this ought not be needed assuming we 2074 * get a DATA_COMPLETE eventually (we'll notice the 2075 * error and end the request), but it shouldn't hurt. 2076 * 2077 * This has the advantage of sending the stop command. 2078 */ 2079 if (test_and_clear_bit(EVENT_DATA_ERROR, 2080 &host->pending_events)) { 2081 dw_mci_stop_dma(host); 2082 if (!(host->data_status & (SDMMC_INT_DRTO | 2083 SDMMC_INT_EBE))) 2084 send_stop_abort(host, data); 2085 state = STATE_DATA_ERROR; 2086 break; 2087 } 2088 prev_state = state = STATE_DATA_BUSY; 2089 2090 /* fall through */ 2091 2092 case STATE_DATA_BUSY: 2093 if (!dw_mci_clear_pending_data_complete(host)) { 2094 /* 2095 * If data error interrupt comes but data over 2096 * interrupt doesn't come within the given time. 2097 * in reading data state. 2098 */ 2099 if (host->dir_status == DW_MCI_RECV_STATUS) 2100 dw_mci_set_drto(host); 2101 break; 2102 } 2103 2104 host->data = NULL; 2105 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2106 err = dw_mci_data_complete(host, data); 2107 2108 if (!err) { 2109 if (!data->stop || mrq->sbc) { 2110 if (mrq->sbc && data->stop) 2111 data->stop->error = 0; 2112 dw_mci_request_end(host, mrq); 2113 goto unlock; 2114 } 2115 2116 /* stop command for open-ended transfer*/ 2117 if (data->stop) 2118 send_stop_abort(host, data); 2119 } else { 2120 /* 2121 * If we don't have a command complete now we'll 2122 * never get one since we just reset everything; 2123 * better end the request. 2124 * 2125 * If we do have a command complete we'll fall 2126 * through to the SENDING_STOP command and 2127 * everything will be peachy keen. 2128 */ 2129 if (!test_bit(EVENT_CMD_COMPLETE, 2130 &host->pending_events)) { 2131 host->cmd = NULL; 2132 dw_mci_request_end(host, mrq); 2133 goto unlock; 2134 } 2135 } 2136 2137 /* 2138 * If err has non-zero, 2139 * stop-abort command has been already issued. 2140 */ 2141 prev_state = state = STATE_SENDING_STOP; 2142 2143 /* fall through */ 2144 2145 case STATE_SENDING_STOP: 2146 if (!dw_mci_clear_pending_cmd_complete(host)) 2147 break; 2148 2149 /* CMD error in data command */ 2150 if (mrq->cmd->error && mrq->data) 2151 dw_mci_reset(host); 2152 2153 host->cmd = NULL; 2154 host->data = NULL; 2155 2156 if (!mrq->sbc && mrq->stop) 2157 dw_mci_command_complete(host, mrq->stop); 2158 else 2159 host->cmd_status = 0; 2160 2161 dw_mci_request_end(host, mrq); 2162 goto unlock; 2163 2164 case STATE_DATA_ERROR: 2165 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2166 &host->pending_events)) 2167 break; 2168 2169 state = STATE_DATA_BUSY; 2170 break; 2171 } 2172 } while (state != prev_state); 2173 2174 host->state = state; 2175 unlock: 2176 spin_unlock(&host->lock); 2177 2178 } 2179 2180 /* push final bytes to part_buf, only use during push */ 2181 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2182 { 2183 memcpy((void *)&host->part_buf, buf, cnt); 2184 host->part_buf_count = cnt; 2185 } 2186 2187 /* append bytes to part_buf, only use during push */ 2188 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2189 { 2190 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2191 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2192 host->part_buf_count += cnt; 2193 return cnt; 2194 } 2195 2196 /* pull first bytes from part_buf, only use during pull */ 2197 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2198 { 2199 cnt = min_t(int, cnt, host->part_buf_count); 2200 if (cnt) { 2201 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2202 cnt); 2203 host->part_buf_count -= cnt; 2204 host->part_buf_start += cnt; 2205 } 2206 return cnt; 2207 } 2208 2209 /* pull final bytes from the part_buf, assuming it's just been filled */ 2210 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2211 { 2212 memcpy(buf, &host->part_buf, cnt); 2213 host->part_buf_start = cnt; 2214 host->part_buf_count = (1 << host->data_shift) - cnt; 2215 } 2216 2217 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2218 { 2219 struct mmc_data *data = host->data; 2220 int init_cnt = cnt; 2221 2222 /* try and push anything in the part_buf */ 2223 if (unlikely(host->part_buf_count)) { 2224 int len = dw_mci_push_part_bytes(host, buf, cnt); 2225 2226 buf += len; 2227 cnt -= len; 2228 if (host->part_buf_count == 2) { 2229 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2230 host->part_buf_count = 0; 2231 } 2232 } 2233 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2234 if (unlikely((unsigned long)buf & 0x1)) { 2235 while (cnt >= 2) { 2236 u16 aligned_buf[64]; 2237 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2238 int items = len >> 1; 2239 int i; 2240 /* memcpy from input buffer into aligned buffer */ 2241 memcpy(aligned_buf, buf, len); 2242 buf += len; 2243 cnt -= len; 2244 /* push data from aligned buffer into fifo */ 2245 for (i = 0; i < items; ++i) 2246 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2247 } 2248 } else 2249 #endif 2250 { 2251 u16 *pdata = buf; 2252 2253 for (; cnt >= 2; cnt -= 2) 2254 mci_fifo_writew(host->fifo_reg, *pdata++); 2255 buf = pdata; 2256 } 2257 /* put anything remaining in the part_buf */ 2258 if (cnt) { 2259 dw_mci_set_part_bytes(host, buf, cnt); 2260 /* Push data if we have reached the expected data length */ 2261 if ((data->bytes_xfered + init_cnt) == 2262 (data->blksz * data->blocks)) 2263 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2264 } 2265 } 2266 2267 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2268 { 2269 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2270 if (unlikely((unsigned long)buf & 0x1)) { 2271 while (cnt >= 2) { 2272 /* pull data from fifo into aligned buffer */ 2273 u16 aligned_buf[64]; 2274 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2275 int items = len >> 1; 2276 int i; 2277 2278 for (i = 0; i < items; ++i) 2279 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2280 /* memcpy from aligned buffer into output buffer */ 2281 memcpy(buf, aligned_buf, len); 2282 buf += len; 2283 cnt -= len; 2284 } 2285 } else 2286 #endif 2287 { 2288 u16 *pdata = buf; 2289 2290 for (; cnt >= 2; cnt -= 2) 2291 *pdata++ = mci_fifo_readw(host->fifo_reg); 2292 buf = pdata; 2293 } 2294 if (cnt) { 2295 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2296 dw_mci_pull_final_bytes(host, buf, cnt); 2297 } 2298 } 2299 2300 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2301 { 2302 struct mmc_data *data = host->data; 2303 int init_cnt = cnt; 2304 2305 /* try and push anything in the part_buf */ 2306 if (unlikely(host->part_buf_count)) { 2307 int len = dw_mci_push_part_bytes(host, buf, cnt); 2308 2309 buf += len; 2310 cnt -= len; 2311 if (host->part_buf_count == 4) { 2312 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2313 host->part_buf_count = 0; 2314 } 2315 } 2316 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2317 if (unlikely((unsigned long)buf & 0x3)) { 2318 while (cnt >= 4) { 2319 u32 aligned_buf[32]; 2320 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2321 int items = len >> 2; 2322 int i; 2323 /* memcpy from input buffer into aligned buffer */ 2324 memcpy(aligned_buf, buf, len); 2325 buf += len; 2326 cnt -= len; 2327 /* push data from aligned buffer into fifo */ 2328 for (i = 0; i < items; ++i) 2329 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2330 } 2331 } else 2332 #endif 2333 { 2334 u32 *pdata = buf; 2335 2336 for (; cnt >= 4; cnt -= 4) 2337 mci_fifo_writel(host->fifo_reg, *pdata++); 2338 buf = pdata; 2339 } 2340 /* put anything remaining in the part_buf */ 2341 if (cnt) { 2342 dw_mci_set_part_bytes(host, buf, cnt); 2343 /* Push data if we have reached the expected data length */ 2344 if ((data->bytes_xfered + init_cnt) == 2345 (data->blksz * data->blocks)) 2346 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2347 } 2348 } 2349 2350 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2351 { 2352 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2353 if (unlikely((unsigned long)buf & 0x3)) { 2354 while (cnt >= 4) { 2355 /* pull data from fifo into aligned buffer */ 2356 u32 aligned_buf[32]; 2357 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2358 int items = len >> 2; 2359 int i; 2360 2361 for (i = 0; i < items; ++i) 2362 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2363 /* memcpy from aligned buffer into output buffer */ 2364 memcpy(buf, aligned_buf, len); 2365 buf += len; 2366 cnt -= len; 2367 } 2368 } else 2369 #endif 2370 { 2371 u32 *pdata = buf; 2372 2373 for (; cnt >= 4; cnt -= 4) 2374 *pdata++ = mci_fifo_readl(host->fifo_reg); 2375 buf = pdata; 2376 } 2377 if (cnt) { 2378 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2379 dw_mci_pull_final_bytes(host, buf, cnt); 2380 } 2381 } 2382 2383 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2384 { 2385 struct mmc_data *data = host->data; 2386 int init_cnt = cnt; 2387 2388 /* try and push anything in the part_buf */ 2389 if (unlikely(host->part_buf_count)) { 2390 int len = dw_mci_push_part_bytes(host, buf, cnt); 2391 2392 buf += len; 2393 cnt -= len; 2394 2395 if (host->part_buf_count == 8) { 2396 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2397 host->part_buf_count = 0; 2398 } 2399 } 2400 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2401 if (unlikely((unsigned long)buf & 0x7)) { 2402 while (cnt >= 8) { 2403 u64 aligned_buf[16]; 2404 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2405 int items = len >> 3; 2406 int i; 2407 /* memcpy from input buffer into aligned buffer */ 2408 memcpy(aligned_buf, buf, len); 2409 buf += len; 2410 cnt -= len; 2411 /* push data from aligned buffer into fifo */ 2412 for (i = 0; i < items; ++i) 2413 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2414 } 2415 } else 2416 #endif 2417 { 2418 u64 *pdata = buf; 2419 2420 for (; cnt >= 8; cnt -= 8) 2421 mci_fifo_writeq(host->fifo_reg, *pdata++); 2422 buf = pdata; 2423 } 2424 /* put anything remaining in the part_buf */ 2425 if (cnt) { 2426 dw_mci_set_part_bytes(host, buf, cnt); 2427 /* Push data if we have reached the expected data length */ 2428 if ((data->bytes_xfered + init_cnt) == 2429 (data->blksz * data->blocks)) 2430 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2431 } 2432 } 2433 2434 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2435 { 2436 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2437 if (unlikely((unsigned long)buf & 0x7)) { 2438 while (cnt >= 8) { 2439 /* pull data from fifo into aligned buffer */ 2440 u64 aligned_buf[16]; 2441 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2442 int items = len >> 3; 2443 int i; 2444 2445 for (i = 0; i < items; ++i) 2446 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2447 2448 /* memcpy from aligned buffer into output buffer */ 2449 memcpy(buf, aligned_buf, len); 2450 buf += len; 2451 cnt -= len; 2452 } 2453 } else 2454 #endif 2455 { 2456 u64 *pdata = buf; 2457 2458 for (; cnt >= 8; cnt -= 8) 2459 *pdata++ = mci_fifo_readq(host->fifo_reg); 2460 buf = pdata; 2461 } 2462 if (cnt) { 2463 host->part_buf = mci_fifo_readq(host->fifo_reg); 2464 dw_mci_pull_final_bytes(host, buf, cnt); 2465 } 2466 } 2467 2468 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2469 { 2470 int len; 2471 2472 /* get remaining partial bytes */ 2473 len = dw_mci_pull_part_bytes(host, buf, cnt); 2474 if (unlikely(len == cnt)) 2475 return; 2476 buf += len; 2477 cnt -= len; 2478 2479 /* get the rest of the data */ 2480 host->pull_data(host, buf, cnt); 2481 } 2482 2483 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2484 { 2485 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2486 void *buf; 2487 unsigned int offset; 2488 struct mmc_data *data = host->data; 2489 int shift = host->data_shift; 2490 u32 status; 2491 unsigned int len; 2492 unsigned int remain, fcnt; 2493 2494 do { 2495 if (!sg_miter_next(sg_miter)) 2496 goto done; 2497 2498 host->sg = sg_miter->piter.sg; 2499 buf = sg_miter->addr; 2500 remain = sg_miter->length; 2501 offset = 0; 2502 2503 do { 2504 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2505 << shift) + host->part_buf_count; 2506 len = min(remain, fcnt); 2507 if (!len) 2508 break; 2509 dw_mci_pull_data(host, (void *)(buf + offset), len); 2510 data->bytes_xfered += len; 2511 offset += len; 2512 remain -= len; 2513 } while (remain); 2514 2515 sg_miter->consumed = offset; 2516 status = mci_readl(host, MINTSTS); 2517 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2518 /* if the RXDR is ready read again */ 2519 } while ((status & SDMMC_INT_RXDR) || 2520 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2521 2522 if (!remain) { 2523 if (!sg_miter_next(sg_miter)) 2524 goto done; 2525 sg_miter->consumed = 0; 2526 } 2527 sg_miter_stop(sg_miter); 2528 return; 2529 2530 done: 2531 sg_miter_stop(sg_miter); 2532 host->sg = NULL; 2533 smp_wmb(); /* drain writebuffer */ 2534 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2535 } 2536 2537 static void dw_mci_write_data_pio(struct dw_mci *host) 2538 { 2539 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2540 void *buf; 2541 unsigned int offset; 2542 struct mmc_data *data = host->data; 2543 int shift = host->data_shift; 2544 u32 status; 2545 unsigned int len; 2546 unsigned int fifo_depth = host->fifo_depth; 2547 unsigned int remain, fcnt; 2548 2549 do { 2550 if (!sg_miter_next(sg_miter)) 2551 goto done; 2552 2553 host->sg = sg_miter->piter.sg; 2554 buf = sg_miter->addr; 2555 remain = sg_miter->length; 2556 offset = 0; 2557 2558 do { 2559 fcnt = ((fifo_depth - 2560 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2561 << shift) - host->part_buf_count; 2562 len = min(remain, fcnt); 2563 if (!len) 2564 break; 2565 host->push_data(host, (void *)(buf + offset), len); 2566 data->bytes_xfered += len; 2567 offset += len; 2568 remain -= len; 2569 } while (remain); 2570 2571 sg_miter->consumed = offset; 2572 status = mci_readl(host, MINTSTS); 2573 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2574 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2575 2576 if (!remain) { 2577 if (!sg_miter_next(sg_miter)) 2578 goto done; 2579 sg_miter->consumed = 0; 2580 } 2581 sg_miter_stop(sg_miter); 2582 return; 2583 2584 done: 2585 sg_miter_stop(sg_miter); 2586 host->sg = NULL; 2587 smp_wmb(); /* drain writebuffer */ 2588 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2589 } 2590 2591 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2592 { 2593 del_timer(&host->cto_timer); 2594 2595 if (!host->cmd_status) 2596 host->cmd_status = status; 2597 2598 smp_wmb(); /* drain writebuffer */ 2599 2600 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2601 tasklet_schedule(&host->tasklet); 2602 } 2603 2604 static void dw_mci_handle_cd(struct dw_mci *host) 2605 { 2606 struct dw_mci_slot *slot = host->slot; 2607 2608 if (slot->mmc->ops->card_event) 2609 slot->mmc->ops->card_event(slot->mmc); 2610 mmc_detect_change(slot->mmc, 2611 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2612 } 2613 2614 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2615 { 2616 struct dw_mci *host = dev_id; 2617 u32 pending; 2618 struct dw_mci_slot *slot = host->slot; 2619 unsigned long irqflags; 2620 2621 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2622 2623 if (pending) { 2624 /* Check volt switch first, since it can look like an error */ 2625 if ((host->state == STATE_SENDING_CMD11) && 2626 (pending & SDMMC_INT_VOLT_SWITCH)) { 2627 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2628 pending &= ~SDMMC_INT_VOLT_SWITCH; 2629 2630 /* 2631 * Hold the lock; we know cmd11_timer can't be kicked 2632 * off after the lock is released, so safe to delete. 2633 */ 2634 spin_lock_irqsave(&host->irq_lock, irqflags); 2635 dw_mci_cmd_interrupt(host, pending); 2636 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2637 2638 del_timer(&host->cmd11_timer); 2639 } 2640 2641 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2642 spin_lock_irqsave(&host->irq_lock, irqflags); 2643 2644 del_timer(&host->cto_timer); 2645 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2646 host->cmd_status = pending; 2647 smp_wmb(); /* drain writebuffer */ 2648 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2649 2650 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2651 } 2652 2653 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2654 /* if there is an error report DATA_ERROR */ 2655 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2656 host->data_status = pending; 2657 smp_wmb(); /* drain writebuffer */ 2658 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2659 tasklet_schedule(&host->tasklet); 2660 } 2661 2662 if (pending & SDMMC_INT_DATA_OVER) { 2663 spin_lock_irqsave(&host->irq_lock, irqflags); 2664 2665 del_timer(&host->dto_timer); 2666 2667 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2668 if (!host->data_status) 2669 host->data_status = pending; 2670 smp_wmb(); /* drain writebuffer */ 2671 if (host->dir_status == DW_MCI_RECV_STATUS) { 2672 if (host->sg != NULL) 2673 dw_mci_read_data_pio(host, true); 2674 } 2675 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2676 tasklet_schedule(&host->tasklet); 2677 2678 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2679 } 2680 2681 if (pending & SDMMC_INT_RXDR) { 2682 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2683 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2684 dw_mci_read_data_pio(host, false); 2685 } 2686 2687 if (pending & SDMMC_INT_TXDR) { 2688 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2689 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2690 dw_mci_write_data_pio(host); 2691 } 2692 2693 if (pending & SDMMC_INT_CMD_DONE) { 2694 spin_lock_irqsave(&host->irq_lock, irqflags); 2695 2696 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2697 dw_mci_cmd_interrupt(host, pending); 2698 2699 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2700 } 2701 2702 if (pending & SDMMC_INT_CD) { 2703 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2704 dw_mci_handle_cd(host); 2705 } 2706 2707 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2708 mci_writel(host, RINTSTS, 2709 SDMMC_INT_SDIO(slot->sdio_id)); 2710 __dw_mci_enable_sdio_irq(slot, 0); 2711 sdio_signal_irq(slot->mmc); 2712 } 2713 2714 } 2715 2716 if (host->use_dma != TRANS_MODE_IDMAC) 2717 return IRQ_HANDLED; 2718 2719 /* Handle IDMA interrupts */ 2720 if (host->dma_64bit_address == 1) { 2721 pending = mci_readl(host, IDSTS64); 2722 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2723 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2724 SDMMC_IDMAC_INT_RI); 2725 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2726 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2727 host->dma_ops->complete((void *)host); 2728 } 2729 } else { 2730 pending = mci_readl(host, IDSTS); 2731 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2732 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2733 SDMMC_IDMAC_INT_RI); 2734 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2735 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2736 host->dma_ops->complete((void *)host); 2737 } 2738 } 2739 2740 return IRQ_HANDLED; 2741 } 2742 2743 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) 2744 { 2745 struct dw_mci *host = slot->host; 2746 const struct dw_mci_drv_data *drv_data = host->drv_data; 2747 struct mmc_host *mmc = slot->mmc; 2748 int ctrl_id; 2749 2750 if (host->pdata->caps) 2751 mmc->caps = host->pdata->caps; 2752 2753 /* 2754 * Support MMC_CAP_ERASE by default. 2755 * It needs to use trim/discard/erase commands. 2756 */ 2757 mmc->caps |= MMC_CAP_ERASE; 2758 2759 if (host->pdata->pm_caps) 2760 mmc->pm_caps = host->pdata->pm_caps; 2761 2762 if (host->dev->of_node) { 2763 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2764 if (ctrl_id < 0) 2765 ctrl_id = 0; 2766 } else { 2767 ctrl_id = to_platform_device(host->dev)->id; 2768 } 2769 2770 if (drv_data && drv_data->caps) { 2771 if (ctrl_id >= drv_data->num_caps) { 2772 dev_err(host->dev, "invalid controller id %d\n", 2773 ctrl_id); 2774 return -EINVAL; 2775 } 2776 mmc->caps |= drv_data->caps[ctrl_id]; 2777 } 2778 2779 if (host->pdata->caps2) 2780 mmc->caps2 = host->pdata->caps2; 2781 2782 mmc->f_min = DW_MCI_FREQ_MIN; 2783 if (!mmc->f_max) 2784 mmc->f_max = DW_MCI_FREQ_MAX; 2785 2786 /* Process SDIO IRQs through the sdio_irq_work. */ 2787 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2788 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2789 2790 return 0; 2791 } 2792 2793 static int dw_mci_init_slot(struct dw_mci *host) 2794 { 2795 struct mmc_host *mmc; 2796 struct dw_mci_slot *slot; 2797 int ret; 2798 2799 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2800 if (!mmc) 2801 return -ENOMEM; 2802 2803 slot = mmc_priv(mmc); 2804 slot->id = 0; 2805 slot->sdio_id = host->sdio_id0 + slot->id; 2806 slot->mmc = mmc; 2807 slot->host = host; 2808 host->slot = slot; 2809 2810 mmc->ops = &dw_mci_ops; 2811 2812 /*if there are external regulators, get them*/ 2813 ret = mmc_regulator_get_supply(mmc); 2814 if (ret) 2815 goto err_host_allocated; 2816 2817 if (!mmc->ocr_avail) 2818 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2819 2820 ret = mmc_of_parse(mmc); 2821 if (ret) 2822 goto err_host_allocated; 2823 2824 ret = dw_mci_init_slot_caps(slot); 2825 if (ret) 2826 goto err_host_allocated; 2827 2828 /* Useful defaults if platform data is unset. */ 2829 if (host->use_dma == TRANS_MODE_IDMAC) { 2830 mmc->max_segs = host->ring_size; 2831 mmc->max_blk_size = 65535; 2832 mmc->max_seg_size = 0x1000; 2833 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2834 mmc->max_blk_count = mmc->max_req_size / 512; 2835 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2836 mmc->max_segs = 64; 2837 mmc->max_blk_size = 65535; 2838 mmc->max_blk_count = 65535; 2839 mmc->max_req_size = 2840 mmc->max_blk_size * mmc->max_blk_count; 2841 mmc->max_seg_size = mmc->max_req_size; 2842 } else { 2843 /* TRANS_MODE_PIO */ 2844 mmc->max_segs = 64; 2845 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2846 mmc->max_blk_count = 512; 2847 mmc->max_req_size = mmc->max_blk_size * 2848 mmc->max_blk_count; 2849 mmc->max_seg_size = mmc->max_req_size; 2850 } 2851 2852 dw_mci_get_cd(mmc); 2853 2854 ret = mmc_add_host(mmc); 2855 if (ret) 2856 goto err_host_allocated; 2857 2858 #if defined(CONFIG_DEBUG_FS) 2859 dw_mci_init_debugfs(slot); 2860 #endif 2861 2862 return 0; 2863 2864 err_host_allocated: 2865 mmc_free_host(mmc); 2866 return ret; 2867 } 2868 2869 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2870 { 2871 /* Debugfs stuff is cleaned up by mmc core */ 2872 mmc_remove_host(slot->mmc); 2873 slot->host->slot = NULL; 2874 mmc_free_host(slot->mmc); 2875 } 2876 2877 static void dw_mci_init_dma(struct dw_mci *host) 2878 { 2879 int addr_config; 2880 struct device *dev = host->dev; 2881 2882 /* 2883 * Check tansfer mode from HCON[17:16] 2884 * Clear the ambiguous description of dw_mmc databook: 2885 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2886 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2887 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2888 * 2b'11: Non DW DMA Interface -> pio only 2889 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2890 * simpler request/acknowledge handshake mechanism and both of them 2891 * are regarded as external dma master for dw_mmc. 2892 */ 2893 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2894 if (host->use_dma == DMA_INTERFACE_IDMA) { 2895 host->use_dma = TRANS_MODE_IDMAC; 2896 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2897 host->use_dma == DMA_INTERFACE_GDMA) { 2898 host->use_dma = TRANS_MODE_EDMAC; 2899 } else { 2900 goto no_dma; 2901 } 2902 2903 /* Determine which DMA interface to use */ 2904 if (host->use_dma == TRANS_MODE_IDMAC) { 2905 /* 2906 * Check ADDR_CONFIG bit in HCON to find 2907 * IDMAC address bus width 2908 */ 2909 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2910 2911 if (addr_config == 1) { 2912 /* host supports IDMAC in 64-bit address mode */ 2913 host->dma_64bit_address = 1; 2914 dev_info(host->dev, 2915 "IDMAC supports 64-bit address mode.\n"); 2916 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2917 dma_set_coherent_mask(host->dev, 2918 DMA_BIT_MASK(64)); 2919 } else { 2920 /* host supports IDMAC in 32-bit address mode */ 2921 host->dma_64bit_address = 0; 2922 dev_info(host->dev, 2923 "IDMAC supports 32-bit address mode.\n"); 2924 } 2925 2926 /* Alloc memory for sg translation */ 2927 host->sg_cpu = dmam_alloc_coherent(host->dev, 2928 DESC_RING_BUF_SZ, 2929 &host->sg_dma, GFP_KERNEL); 2930 if (!host->sg_cpu) { 2931 dev_err(host->dev, 2932 "%s: could not alloc DMA memory\n", 2933 __func__); 2934 goto no_dma; 2935 } 2936 2937 host->dma_ops = &dw_mci_idmac_ops; 2938 dev_info(host->dev, "Using internal DMA controller.\n"); 2939 } else { 2940 /* TRANS_MODE_EDMAC: check dma bindings again */ 2941 if ((device_property_read_string_array(dev, "dma-names", 2942 NULL, 0) < 0) || 2943 !device_property_present(dev, "dmas")) { 2944 goto no_dma; 2945 } 2946 host->dma_ops = &dw_mci_edmac_ops; 2947 dev_info(host->dev, "Using external DMA controller.\n"); 2948 } 2949 2950 if (host->dma_ops->init && host->dma_ops->start && 2951 host->dma_ops->stop && host->dma_ops->cleanup) { 2952 if (host->dma_ops->init(host)) { 2953 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2954 __func__); 2955 goto no_dma; 2956 } 2957 } else { 2958 dev_err(host->dev, "DMA initialization not found.\n"); 2959 goto no_dma; 2960 } 2961 2962 return; 2963 2964 no_dma: 2965 dev_info(host->dev, "Using PIO mode.\n"); 2966 host->use_dma = TRANS_MODE_PIO; 2967 } 2968 2969 static void dw_mci_cmd11_timer(struct timer_list *t) 2970 { 2971 struct dw_mci *host = from_timer(host, t, cmd11_timer); 2972 2973 if (host->state != STATE_SENDING_CMD11) { 2974 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2975 return; 2976 } 2977 2978 host->cmd_status = SDMMC_INT_RTO; 2979 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2980 tasklet_schedule(&host->tasklet); 2981 } 2982 2983 static void dw_mci_cto_timer(struct timer_list *t) 2984 { 2985 struct dw_mci *host = from_timer(host, t, cto_timer); 2986 unsigned long irqflags; 2987 u32 pending; 2988 2989 spin_lock_irqsave(&host->irq_lock, irqflags); 2990 2991 /* 2992 * If somehow we have very bad interrupt latency it's remotely possible 2993 * that the timer could fire while the interrupt is still pending or 2994 * while the interrupt is midway through running. Let's be paranoid 2995 * and detect those two cases. Note that this is paranoia is somewhat 2996 * justified because in this function we don't actually cancel the 2997 * pending command in the controller--we just assume it will never come. 2998 */ 2999 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3000 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 3001 /* The interrupt should fire; no need to act but we can warn */ 3002 dev_warn(host->dev, "Unexpected interrupt latency\n"); 3003 goto exit; 3004 } 3005 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 3006 /* Presumably interrupt handler couldn't delete the timer */ 3007 dev_warn(host->dev, "CTO timeout when already completed\n"); 3008 goto exit; 3009 } 3010 3011 /* 3012 * Continued paranoia to make sure we're in the state we expect. 3013 * This paranoia isn't really justified but it seems good to be safe. 3014 */ 3015 switch (host->state) { 3016 case STATE_SENDING_CMD11: 3017 case STATE_SENDING_CMD: 3018 case STATE_SENDING_STOP: 3019 /* 3020 * If CMD_DONE interrupt does NOT come in sending command 3021 * state, we should notify the driver to terminate current 3022 * transfer and report a command timeout to the core. 3023 */ 3024 host->cmd_status = SDMMC_INT_RTO; 3025 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3026 tasklet_schedule(&host->tasklet); 3027 break; 3028 default: 3029 dev_warn(host->dev, "Unexpected command timeout, state %d\n", 3030 host->state); 3031 break; 3032 } 3033 3034 exit: 3035 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3036 } 3037 3038 static void dw_mci_dto_timer(struct timer_list *t) 3039 { 3040 struct dw_mci *host = from_timer(host, t, dto_timer); 3041 unsigned long irqflags; 3042 u32 pending; 3043 3044 spin_lock_irqsave(&host->irq_lock, irqflags); 3045 3046 /* 3047 * The DTO timer is much longer than the CTO timer, so it's even less 3048 * likely that we'll these cases, but it pays to be paranoid. 3049 */ 3050 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3051 if (pending & SDMMC_INT_DATA_OVER) { 3052 /* The interrupt should fire; no need to act but we can warn */ 3053 dev_warn(host->dev, "Unexpected data interrupt latency\n"); 3054 goto exit; 3055 } 3056 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 3057 /* Presumably interrupt handler couldn't delete the timer */ 3058 dev_warn(host->dev, "DTO timeout when already completed\n"); 3059 goto exit; 3060 } 3061 3062 /* 3063 * Continued paranoia to make sure we're in the state we expect. 3064 * This paranoia isn't really justified but it seems good to be safe. 3065 */ 3066 switch (host->state) { 3067 case STATE_SENDING_DATA: 3068 case STATE_DATA_BUSY: 3069 /* 3070 * If DTO interrupt does NOT come in sending data state, 3071 * we should notify the driver to terminate current transfer 3072 * and report a data timeout to the core. 3073 */ 3074 host->data_status = SDMMC_INT_DRTO; 3075 set_bit(EVENT_DATA_ERROR, &host->pending_events); 3076 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 3077 tasklet_schedule(&host->tasklet); 3078 break; 3079 default: 3080 dev_warn(host->dev, "Unexpected data timeout, state %d\n", 3081 host->state); 3082 break; 3083 } 3084 3085 exit: 3086 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3087 } 3088 3089 #ifdef CONFIG_OF 3090 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3091 { 3092 struct dw_mci_board *pdata; 3093 struct device *dev = host->dev; 3094 const struct dw_mci_drv_data *drv_data = host->drv_data; 3095 int ret; 3096 u32 clock_frequency; 3097 3098 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3099 if (!pdata) 3100 return ERR_PTR(-ENOMEM); 3101 3102 /* find reset controller when exist */ 3103 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3104 if (IS_ERR(pdata->rstc)) { 3105 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3106 return ERR_PTR(-EPROBE_DEFER); 3107 } 3108 3109 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 3110 dev_info(dev, 3111 "fifo-depth property not found, using value of FIFOTH register as default\n"); 3112 3113 device_property_read_u32(dev, "card-detect-delay", 3114 &pdata->detect_delay_ms); 3115 3116 device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3117 3118 if (device_property_present(dev, "fifo-watermark-aligned")) 3119 host->wm_aligned = true; 3120 3121 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 3122 pdata->bus_hz = clock_frequency; 3123 3124 if (drv_data && drv_data->parse_dt) { 3125 ret = drv_data->parse_dt(host); 3126 if (ret) 3127 return ERR_PTR(ret); 3128 } 3129 3130 return pdata; 3131 } 3132 3133 #else /* CONFIG_OF */ 3134 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3135 { 3136 return ERR_PTR(-EINVAL); 3137 } 3138 #endif /* CONFIG_OF */ 3139 3140 static void dw_mci_enable_cd(struct dw_mci *host) 3141 { 3142 unsigned long irqflags; 3143 u32 temp; 3144 3145 /* 3146 * No need for CD if all slots have a non-error GPIO 3147 * as well as broken card detection is found. 3148 */ 3149 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3150 return; 3151 3152 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3153 spin_lock_irqsave(&host->irq_lock, irqflags); 3154 temp = mci_readl(host, INTMASK); 3155 temp |= SDMMC_INT_CD; 3156 mci_writel(host, INTMASK, temp); 3157 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3158 } 3159 } 3160 3161 int dw_mci_probe(struct dw_mci *host) 3162 { 3163 const struct dw_mci_drv_data *drv_data = host->drv_data; 3164 int width, i, ret = 0; 3165 u32 fifo_size; 3166 3167 if (!host->pdata) { 3168 host->pdata = dw_mci_parse_dt(host); 3169 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3170 return -EPROBE_DEFER; 3171 } else if (IS_ERR(host->pdata)) { 3172 dev_err(host->dev, "platform data not available\n"); 3173 return -EINVAL; 3174 } 3175 } 3176 3177 host->biu_clk = devm_clk_get(host->dev, "biu"); 3178 if (IS_ERR(host->biu_clk)) { 3179 dev_dbg(host->dev, "biu clock not available\n"); 3180 } else { 3181 ret = clk_prepare_enable(host->biu_clk); 3182 if (ret) { 3183 dev_err(host->dev, "failed to enable biu clock\n"); 3184 return ret; 3185 } 3186 } 3187 3188 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3189 if (IS_ERR(host->ciu_clk)) { 3190 dev_dbg(host->dev, "ciu clock not available\n"); 3191 host->bus_hz = host->pdata->bus_hz; 3192 } else { 3193 ret = clk_prepare_enable(host->ciu_clk); 3194 if (ret) { 3195 dev_err(host->dev, "failed to enable ciu clock\n"); 3196 goto err_clk_biu; 3197 } 3198 3199 if (host->pdata->bus_hz) { 3200 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3201 if (ret) 3202 dev_warn(host->dev, 3203 "Unable to set bus rate to %uHz\n", 3204 host->pdata->bus_hz); 3205 } 3206 host->bus_hz = clk_get_rate(host->ciu_clk); 3207 } 3208 3209 if (!host->bus_hz) { 3210 dev_err(host->dev, 3211 "Platform data must supply bus speed\n"); 3212 ret = -ENODEV; 3213 goto err_clk_ciu; 3214 } 3215 3216 if (!IS_ERR(host->pdata->rstc)) { 3217 reset_control_assert(host->pdata->rstc); 3218 usleep_range(10, 50); 3219 reset_control_deassert(host->pdata->rstc); 3220 } 3221 3222 if (drv_data && drv_data->init) { 3223 ret = drv_data->init(host); 3224 if (ret) { 3225 dev_err(host->dev, 3226 "implementation specific init failed\n"); 3227 goto err_clk_ciu; 3228 } 3229 } 3230 3231 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 3232 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 3233 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 3234 3235 spin_lock_init(&host->lock); 3236 spin_lock_init(&host->irq_lock); 3237 INIT_LIST_HEAD(&host->queue); 3238 3239 /* 3240 * Get the host data width - this assumes that HCON has been set with 3241 * the correct values. 3242 */ 3243 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3244 if (!i) { 3245 host->push_data = dw_mci_push_data16; 3246 host->pull_data = dw_mci_pull_data16; 3247 width = 16; 3248 host->data_shift = 1; 3249 } else if (i == 2) { 3250 host->push_data = dw_mci_push_data64; 3251 host->pull_data = dw_mci_pull_data64; 3252 width = 64; 3253 host->data_shift = 3; 3254 } else { 3255 /* Check for a reserved value, and warn if it is */ 3256 WARN((i != 1), 3257 "HCON reports a reserved host data width!\n" 3258 "Defaulting to 32-bit access.\n"); 3259 host->push_data = dw_mci_push_data32; 3260 host->pull_data = dw_mci_pull_data32; 3261 width = 32; 3262 host->data_shift = 2; 3263 } 3264 3265 /* Reset all blocks */ 3266 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3267 ret = -ENODEV; 3268 goto err_clk_ciu; 3269 } 3270 3271 host->dma_ops = host->pdata->dma_ops; 3272 dw_mci_init_dma(host); 3273 3274 /* Clear the interrupts for the host controller */ 3275 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3276 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3277 3278 /* Put in max timeout */ 3279 mci_writel(host, TMOUT, 0xFFFFFFFF); 3280 3281 /* 3282 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3283 * Tx Mark = fifo_size / 2 DMA Size = 8 3284 */ 3285 if (!host->pdata->fifo_depth) { 3286 /* 3287 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3288 * have been overwritten by the bootloader, just like we're 3289 * about to do, so if you know the value for your hardware, you 3290 * should put it in the platform data. 3291 */ 3292 fifo_size = mci_readl(host, FIFOTH); 3293 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3294 } else { 3295 fifo_size = host->pdata->fifo_depth; 3296 } 3297 host->fifo_depth = fifo_size; 3298 host->fifoth_val = 3299 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3300 mci_writel(host, FIFOTH, host->fifoth_val); 3301 3302 /* disable clock to CIU */ 3303 mci_writel(host, CLKENA, 0); 3304 mci_writel(host, CLKSRC, 0); 3305 3306 /* 3307 * In 2.40a spec, Data offset is changed. 3308 * Need to check the version-id and set data-offset for DATA register. 3309 */ 3310 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3311 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3312 3313 if (host->data_addr_override) 3314 host->fifo_reg = host->regs + host->data_addr_override; 3315 else if (host->verid < DW_MMC_240A) 3316 host->fifo_reg = host->regs + DATA_OFFSET; 3317 else 3318 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3319 3320 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3321 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3322 host->irq_flags, "dw-mci", host); 3323 if (ret) 3324 goto err_dmaunmap; 3325 3326 /* 3327 * Enable interrupts for command done, data over, data empty, 3328 * receive ready and error such as transmit, receive timeout, crc error 3329 */ 3330 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3331 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3332 DW_MCI_ERROR_FLAGS); 3333 /* Enable mci interrupt */ 3334 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3335 3336 dev_info(host->dev, 3337 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3338 host->irq, width, fifo_size); 3339 3340 /* We need at least one slot to succeed */ 3341 ret = dw_mci_init_slot(host); 3342 if (ret) { 3343 dev_dbg(host->dev, "slot %d init failed\n", i); 3344 goto err_dmaunmap; 3345 } 3346 3347 /* Now that slots are all setup, we can enable card detect */ 3348 dw_mci_enable_cd(host); 3349 3350 return 0; 3351 3352 err_dmaunmap: 3353 if (host->use_dma && host->dma_ops->exit) 3354 host->dma_ops->exit(host); 3355 3356 if (!IS_ERR(host->pdata->rstc)) 3357 reset_control_assert(host->pdata->rstc); 3358 3359 err_clk_ciu: 3360 clk_disable_unprepare(host->ciu_clk); 3361 3362 err_clk_biu: 3363 clk_disable_unprepare(host->biu_clk); 3364 3365 return ret; 3366 } 3367 EXPORT_SYMBOL(dw_mci_probe); 3368 3369 void dw_mci_remove(struct dw_mci *host) 3370 { 3371 dev_dbg(host->dev, "remove slot\n"); 3372 if (host->slot) 3373 dw_mci_cleanup_slot(host->slot); 3374 3375 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3376 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3377 3378 /* disable clock to CIU */ 3379 mci_writel(host, CLKENA, 0); 3380 mci_writel(host, CLKSRC, 0); 3381 3382 if (host->use_dma && host->dma_ops->exit) 3383 host->dma_ops->exit(host); 3384 3385 if (!IS_ERR(host->pdata->rstc)) 3386 reset_control_assert(host->pdata->rstc); 3387 3388 clk_disable_unprepare(host->ciu_clk); 3389 clk_disable_unprepare(host->biu_clk); 3390 } 3391 EXPORT_SYMBOL(dw_mci_remove); 3392 3393 3394 3395 #ifdef CONFIG_PM 3396 int dw_mci_runtime_suspend(struct device *dev) 3397 { 3398 struct dw_mci *host = dev_get_drvdata(dev); 3399 3400 if (host->use_dma && host->dma_ops->exit) 3401 host->dma_ops->exit(host); 3402 3403 clk_disable_unprepare(host->ciu_clk); 3404 3405 if (host->slot && 3406 (mmc_can_gpio_cd(host->slot->mmc) || 3407 !mmc_card_is_removable(host->slot->mmc))) 3408 clk_disable_unprepare(host->biu_clk); 3409 3410 return 0; 3411 } 3412 EXPORT_SYMBOL(dw_mci_runtime_suspend); 3413 3414 int dw_mci_runtime_resume(struct device *dev) 3415 { 3416 int ret = 0; 3417 struct dw_mci *host = dev_get_drvdata(dev); 3418 3419 if (host->slot && 3420 (mmc_can_gpio_cd(host->slot->mmc) || 3421 !mmc_card_is_removable(host->slot->mmc))) { 3422 ret = clk_prepare_enable(host->biu_clk); 3423 if (ret) 3424 return ret; 3425 } 3426 3427 ret = clk_prepare_enable(host->ciu_clk); 3428 if (ret) 3429 goto err; 3430 3431 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3432 clk_disable_unprepare(host->ciu_clk); 3433 ret = -ENODEV; 3434 goto err; 3435 } 3436 3437 if (host->use_dma && host->dma_ops->init) 3438 host->dma_ops->init(host); 3439 3440 /* 3441 * Restore the initial value at FIFOTH register 3442 * And Invalidate the prev_blksz with zero 3443 */ 3444 mci_writel(host, FIFOTH, host->fifoth_val); 3445 host->prev_blksz = 0; 3446 3447 /* Put in max timeout */ 3448 mci_writel(host, TMOUT, 0xFFFFFFFF); 3449 3450 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3451 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3452 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3453 DW_MCI_ERROR_FLAGS); 3454 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3455 3456 3457 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3458 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3459 3460 /* Force setup bus to guarantee available clock output */ 3461 dw_mci_setup_bus(host->slot, true); 3462 3463 /* Now that slots are all setup, we can enable card detect */ 3464 dw_mci_enable_cd(host); 3465 3466 return 0; 3467 3468 err: 3469 if (host->slot && 3470 (mmc_can_gpio_cd(host->slot->mmc) || 3471 !mmc_card_is_removable(host->slot->mmc))) 3472 clk_disable_unprepare(host->biu_clk); 3473 3474 return ret; 3475 } 3476 EXPORT_SYMBOL(dw_mci_runtime_resume); 3477 #endif /* CONFIG_PM */ 3478 3479 static int __init dw_mci_init(void) 3480 { 3481 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3482 return 0; 3483 } 3484 3485 static void __exit dw_mci_exit(void) 3486 { 3487 } 3488 3489 module_init(dw_mci_init); 3490 module_exit(dw_mci_exit); 3491 3492 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3493 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3494 MODULE_AUTHOR("Imagination Technologies Ltd"); 3495 MODULE_LICENSE("GPL v2"); 3496