1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/iopoll.h> 23 #include <linux/ioport.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/seq_file.h> 28 #include <linux/slab.h> 29 #include <linux/stat.h> 30 #include <linux/delay.h> 31 #include <linux/irq.h> 32 #include <linux/mmc/card.h> 33 #include <linux/mmc/host.h> 34 #include <linux/mmc/mmc.h> 35 #include <linux/mmc/sd.h> 36 #include <linux/mmc/sdio.h> 37 #include <linux/bitops.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/of.h> 40 #include <linux/of_gpio.h> 41 #include <linux/mmc/slot-gpio.h> 42 43 #include "dw_mmc.h" 44 45 /* Common flag combinations */ 46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 48 SDMMC_INT_EBE | SDMMC_INT_HLE) 49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 52 DW_MCI_CMD_ERROR_FLAGS) 53 #define DW_MCI_SEND_STATUS 1 54 #define DW_MCI_RECV_STATUS 2 55 #define DW_MCI_DMA_THRESHOLD 16 56 57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 59 60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63 SDMMC_IDMAC_INT_TI) 64 65 #define DESC_RING_BUF_SZ PAGE_SIZE 66 67 struct idmac_desc_64addr { 68 u32 des0; /* Control Descriptor */ 69 #define IDMAC_OWN_CLR64(x) \ 70 !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 71 72 u32 des1; /* Reserved */ 73 74 u32 des2; /*Buffer sizes */ 75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 78 79 u32 des3; /* Reserved */ 80 81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 83 84 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 85 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 86 }; 87 88 struct idmac_desc { 89 __le32 des0; /* Control Descriptor */ 90 #define IDMAC_DES0_DIC BIT(1) 91 #define IDMAC_DES0_LD BIT(2) 92 #define IDMAC_DES0_FD BIT(3) 93 #define IDMAC_DES0_CH BIT(4) 94 #define IDMAC_DES0_ER BIT(5) 95 #define IDMAC_DES0_CES BIT(30) 96 #define IDMAC_DES0_OWN BIT(31) 97 98 __le32 des1; /* Buffer sizes */ 99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101 102 __le32 des2; /* buffer 1 physical address */ 103 104 __le32 des3; /* buffer 2 physical address */ 105 }; 106 107 /* Each descriptor can transfer up to 4KB of data in chained mode */ 108 #define DW_MCI_DESC_DATA_LENGTH 0x1000 109 110 #if defined(CONFIG_DEBUG_FS) 111 static int dw_mci_req_show(struct seq_file *s, void *v) 112 { 113 struct dw_mci_slot *slot = s->private; 114 struct mmc_request *mrq; 115 struct mmc_command *cmd; 116 struct mmc_command *stop; 117 struct mmc_data *data; 118 119 /* Make sure we get a consistent snapshot */ 120 spin_lock_bh(&slot->host->lock); 121 mrq = slot->mrq; 122 123 if (mrq) { 124 cmd = mrq->cmd; 125 data = mrq->data; 126 stop = mrq->stop; 127 128 if (cmd) 129 seq_printf(s, 130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131 cmd->opcode, cmd->arg, cmd->flags, 132 cmd->resp[0], cmd->resp[1], cmd->resp[2], 133 cmd->resp[2], cmd->error); 134 if (data) 135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136 data->bytes_xfered, data->blocks, 137 data->blksz, data->flags, data->error); 138 if (stop) 139 seq_printf(s, 140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141 stop->opcode, stop->arg, stop->flags, 142 stop->resp[0], stop->resp[1], stop->resp[2], 143 stop->resp[2], stop->error); 144 } 145 146 spin_unlock_bh(&slot->host->lock); 147 148 return 0; 149 } 150 DEFINE_SHOW_ATTRIBUTE(dw_mci_req); 151 152 static int dw_mci_regs_show(struct seq_file *s, void *v) 153 { 154 struct dw_mci *host = s->private; 155 156 pm_runtime_get_sync(host->dev); 157 158 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 159 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 160 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 161 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 162 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 163 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 164 165 pm_runtime_put_autosuspend(host->dev); 166 167 return 0; 168 } 169 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs); 170 171 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 172 { 173 struct mmc_host *mmc = slot->mmc; 174 struct dw_mci *host = slot->host; 175 struct dentry *root; 176 struct dentry *node; 177 178 root = mmc->debugfs_root; 179 if (!root) 180 return; 181 182 node = debugfs_create_file("regs", S_IRUSR, root, host, 183 &dw_mci_regs_fops); 184 if (!node) 185 goto err; 186 187 node = debugfs_create_file("req", S_IRUSR, root, slot, 188 &dw_mci_req_fops); 189 if (!node) 190 goto err; 191 192 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 193 if (!node) 194 goto err; 195 196 node = debugfs_create_x32("pending_events", S_IRUSR, root, 197 (u32 *)&host->pending_events); 198 if (!node) 199 goto err; 200 201 node = debugfs_create_x32("completed_events", S_IRUSR, root, 202 (u32 *)&host->completed_events); 203 if (!node) 204 goto err; 205 206 return; 207 208 err: 209 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 210 } 211 #endif /* defined(CONFIG_DEBUG_FS) */ 212 213 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 214 { 215 u32 ctrl; 216 217 ctrl = mci_readl(host, CTRL); 218 ctrl |= reset; 219 mci_writel(host, CTRL, ctrl); 220 221 /* wait till resets clear */ 222 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 223 !(ctrl & reset), 224 1, 500 * USEC_PER_MSEC)) { 225 dev_err(host->dev, 226 "Timeout resetting block (ctrl reset %#x)\n", 227 ctrl & reset); 228 return false; 229 } 230 231 return true; 232 } 233 234 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 235 { 236 u32 status; 237 238 /* 239 * Databook says that before issuing a new data transfer command 240 * we need to check to see if the card is busy. Data transfer commands 241 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 242 * 243 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 244 * expected. 245 */ 246 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 247 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 248 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 249 status, 250 !(status & SDMMC_STATUS_BUSY), 251 10, 500 * USEC_PER_MSEC)) 252 dev_err(host->dev, "Busy; trying anyway\n"); 253 } 254 } 255 256 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 257 { 258 struct dw_mci *host = slot->host; 259 unsigned int cmd_status = 0; 260 261 mci_writel(host, CMDARG, arg); 262 wmb(); /* drain writebuffer */ 263 dw_mci_wait_while_busy(host, cmd); 264 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 265 266 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 267 !(cmd_status & SDMMC_CMD_START), 268 1, 500 * USEC_PER_MSEC)) 269 dev_err(&slot->mmc->class_dev, 270 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 271 cmd, arg, cmd_status); 272 } 273 274 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 275 { 276 struct dw_mci_slot *slot = mmc_priv(mmc); 277 struct dw_mci *host = slot->host; 278 u32 cmdr; 279 280 cmd->error = -EINPROGRESS; 281 cmdr = cmd->opcode; 282 283 if (cmd->opcode == MMC_STOP_TRANSMISSION || 284 cmd->opcode == MMC_GO_IDLE_STATE || 285 cmd->opcode == MMC_GO_INACTIVE_STATE || 286 (cmd->opcode == SD_IO_RW_DIRECT && 287 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 288 cmdr |= SDMMC_CMD_STOP; 289 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 290 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 291 292 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 293 u32 clk_en_a; 294 295 /* Special bit makes CMD11 not die */ 296 cmdr |= SDMMC_CMD_VOLT_SWITCH; 297 298 /* Change state to continue to handle CMD11 weirdness */ 299 WARN_ON(slot->host->state != STATE_SENDING_CMD); 300 slot->host->state = STATE_SENDING_CMD11; 301 302 /* 303 * We need to disable low power mode (automatic clock stop) 304 * while doing voltage switch so we don't confuse the card, 305 * since stopping the clock is a specific part of the UHS 306 * voltage change dance. 307 * 308 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 309 * unconditionally turned back on in dw_mci_setup_bus() if it's 310 * ever called with a non-zero clock. That shouldn't happen 311 * until the voltage change is all done. 312 */ 313 clk_en_a = mci_readl(host, CLKENA); 314 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 315 mci_writel(host, CLKENA, clk_en_a); 316 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 317 SDMMC_CMD_PRV_DAT_WAIT, 0); 318 } 319 320 if (cmd->flags & MMC_RSP_PRESENT) { 321 /* We expect a response, so set this bit */ 322 cmdr |= SDMMC_CMD_RESP_EXP; 323 if (cmd->flags & MMC_RSP_136) 324 cmdr |= SDMMC_CMD_RESP_LONG; 325 } 326 327 if (cmd->flags & MMC_RSP_CRC) 328 cmdr |= SDMMC_CMD_RESP_CRC; 329 330 if (cmd->data) { 331 cmdr |= SDMMC_CMD_DAT_EXP; 332 if (cmd->data->flags & MMC_DATA_WRITE) 333 cmdr |= SDMMC_CMD_DAT_WR; 334 } 335 336 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 337 cmdr |= SDMMC_CMD_USE_HOLD_REG; 338 339 return cmdr; 340 } 341 342 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 343 { 344 struct mmc_command *stop; 345 u32 cmdr; 346 347 if (!cmd->data) 348 return 0; 349 350 stop = &host->stop_abort; 351 cmdr = cmd->opcode; 352 memset(stop, 0, sizeof(struct mmc_command)); 353 354 if (cmdr == MMC_READ_SINGLE_BLOCK || 355 cmdr == MMC_READ_MULTIPLE_BLOCK || 356 cmdr == MMC_WRITE_BLOCK || 357 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 358 cmdr == MMC_SEND_TUNING_BLOCK || 359 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 360 stop->opcode = MMC_STOP_TRANSMISSION; 361 stop->arg = 0; 362 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 363 } else if (cmdr == SD_IO_RW_EXTENDED) { 364 stop->opcode = SD_IO_RW_DIRECT; 365 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 366 ((cmd->arg >> 28) & 0x7); 367 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 368 } else { 369 return 0; 370 } 371 372 cmdr = stop->opcode | SDMMC_CMD_STOP | 373 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 374 375 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 376 cmdr |= SDMMC_CMD_USE_HOLD_REG; 377 378 return cmdr; 379 } 380 381 static inline void dw_mci_set_cto(struct dw_mci *host) 382 { 383 unsigned int cto_clks; 384 unsigned int cto_div; 385 unsigned int cto_ms; 386 unsigned long irqflags; 387 388 cto_clks = mci_readl(host, TMOUT) & 0xff; 389 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 390 if (cto_div == 0) 391 cto_div = 1; 392 393 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 394 host->bus_hz); 395 396 /* add a bit spare time */ 397 cto_ms += 10; 398 399 /* 400 * The durations we're working with are fairly short so we have to be 401 * extra careful about synchronization here. Specifically in hardware a 402 * command timeout is _at most_ 5.1 ms, so that means we expect an 403 * interrupt (either command done or timeout) to come rather quickly 404 * after the mci_writel. ...but just in case we have a long interrupt 405 * latency let's add a bit of paranoia. 406 * 407 * In general we'll assume that at least an interrupt will be asserted 408 * in hardware by the time the cto_timer runs. ...and if it hasn't 409 * been asserted in hardware by that time then we'll assume it'll never 410 * come. 411 */ 412 spin_lock_irqsave(&host->irq_lock, irqflags); 413 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 414 mod_timer(&host->cto_timer, 415 jiffies + msecs_to_jiffies(cto_ms) + 1); 416 spin_unlock_irqrestore(&host->irq_lock, irqflags); 417 } 418 419 static void dw_mci_start_command(struct dw_mci *host, 420 struct mmc_command *cmd, u32 cmd_flags) 421 { 422 host->cmd = cmd; 423 dev_vdbg(host->dev, 424 "start command: ARGR=0x%08x CMDR=0x%08x\n", 425 cmd->arg, cmd_flags); 426 427 mci_writel(host, CMDARG, cmd->arg); 428 wmb(); /* drain writebuffer */ 429 dw_mci_wait_while_busy(host, cmd_flags); 430 431 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 432 433 /* response expected command only */ 434 if (cmd_flags & SDMMC_CMD_RESP_EXP) 435 dw_mci_set_cto(host); 436 } 437 438 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 439 { 440 struct mmc_command *stop = &host->stop_abort; 441 442 dw_mci_start_command(host, stop, host->stop_cmdr); 443 } 444 445 /* DMA interface functions */ 446 static void dw_mci_stop_dma(struct dw_mci *host) 447 { 448 if (host->using_dma) { 449 host->dma_ops->stop(host); 450 host->dma_ops->cleanup(host); 451 } 452 453 /* Data transfer was stopped by the interrupt handler */ 454 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 455 } 456 457 static void dw_mci_dma_cleanup(struct dw_mci *host) 458 { 459 struct mmc_data *data = host->data; 460 461 if (data && data->host_cookie == COOKIE_MAPPED) { 462 dma_unmap_sg(host->dev, 463 data->sg, 464 data->sg_len, 465 mmc_get_dma_dir(data)); 466 data->host_cookie = COOKIE_UNMAPPED; 467 } 468 } 469 470 static void dw_mci_idmac_reset(struct dw_mci *host) 471 { 472 u32 bmod = mci_readl(host, BMOD); 473 /* Software reset of DMA */ 474 bmod |= SDMMC_IDMAC_SWRESET; 475 mci_writel(host, BMOD, bmod); 476 } 477 478 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 479 { 480 u32 temp; 481 482 /* Disable and reset the IDMAC interface */ 483 temp = mci_readl(host, CTRL); 484 temp &= ~SDMMC_CTRL_USE_IDMAC; 485 temp |= SDMMC_CTRL_DMA_RESET; 486 mci_writel(host, CTRL, temp); 487 488 /* Stop the IDMAC running */ 489 temp = mci_readl(host, BMOD); 490 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 491 temp |= SDMMC_IDMAC_SWRESET; 492 mci_writel(host, BMOD, temp); 493 } 494 495 static void dw_mci_dmac_complete_dma(void *arg) 496 { 497 struct dw_mci *host = arg; 498 struct mmc_data *data = host->data; 499 500 dev_vdbg(host->dev, "DMA complete\n"); 501 502 if ((host->use_dma == TRANS_MODE_EDMAC) && 503 data && (data->flags & MMC_DATA_READ)) 504 /* Invalidate cache after read */ 505 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 506 data->sg, 507 data->sg_len, 508 DMA_FROM_DEVICE); 509 510 host->dma_ops->cleanup(host); 511 512 /* 513 * If the card was removed, data will be NULL. No point in trying to 514 * send the stop command or waiting for NBUSY in this case. 515 */ 516 if (data) { 517 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 518 tasklet_schedule(&host->tasklet); 519 } 520 } 521 522 static int dw_mci_idmac_init(struct dw_mci *host) 523 { 524 int i; 525 526 if (host->dma_64bit_address == 1) { 527 struct idmac_desc_64addr *p; 528 /* Number of descriptors in the ring buffer */ 529 host->ring_size = 530 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 531 532 /* Forward link the descriptor list */ 533 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 534 i++, p++) { 535 p->des6 = (host->sg_dma + 536 (sizeof(struct idmac_desc_64addr) * 537 (i + 1))) & 0xffffffff; 538 539 p->des7 = (u64)(host->sg_dma + 540 (sizeof(struct idmac_desc_64addr) * 541 (i + 1))) >> 32; 542 /* Initialize reserved and buffer size fields to "0" */ 543 p->des0 = 0; 544 p->des1 = 0; 545 p->des2 = 0; 546 p->des3 = 0; 547 } 548 549 /* Set the last descriptor as the end-of-ring descriptor */ 550 p->des6 = host->sg_dma & 0xffffffff; 551 p->des7 = (u64)host->sg_dma >> 32; 552 p->des0 = IDMAC_DES0_ER; 553 554 } else { 555 struct idmac_desc *p; 556 /* Number of descriptors in the ring buffer */ 557 host->ring_size = 558 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 559 560 /* Forward link the descriptor list */ 561 for (i = 0, p = host->sg_cpu; 562 i < host->ring_size - 1; 563 i++, p++) { 564 p->des3 = cpu_to_le32(host->sg_dma + 565 (sizeof(struct idmac_desc) * (i + 1))); 566 p->des0 = 0; 567 p->des1 = 0; 568 } 569 570 /* Set the last descriptor as the end-of-ring descriptor */ 571 p->des3 = cpu_to_le32(host->sg_dma); 572 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 573 } 574 575 dw_mci_idmac_reset(host); 576 577 if (host->dma_64bit_address == 1) { 578 /* Mask out interrupts - get Tx & Rx complete only */ 579 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 580 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 581 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 582 583 /* Set the descriptor base address */ 584 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 585 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 586 587 } else { 588 /* Mask out interrupts - get Tx & Rx complete only */ 589 mci_writel(host, IDSTS, IDMAC_INT_CLR); 590 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 591 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 592 593 /* Set the descriptor base address */ 594 mci_writel(host, DBADDR, host->sg_dma); 595 } 596 597 return 0; 598 } 599 600 static inline int dw_mci_prepare_desc64(struct dw_mci *host, 601 struct mmc_data *data, 602 unsigned int sg_len) 603 { 604 unsigned int desc_len; 605 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 606 u32 val; 607 int i; 608 609 desc_first = desc_last = desc = host->sg_cpu; 610 611 for (i = 0; i < sg_len; i++) { 612 unsigned int length = sg_dma_len(&data->sg[i]); 613 614 u64 mem_addr = sg_dma_address(&data->sg[i]); 615 616 for ( ; length ; desc++) { 617 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 618 length : DW_MCI_DESC_DATA_LENGTH; 619 620 length -= desc_len; 621 622 /* 623 * Wait for the former clear OWN bit operation 624 * of IDMAC to make sure that this descriptor 625 * isn't still owned by IDMAC as IDMAC's write 626 * ops and CPU's read ops are asynchronous. 627 */ 628 if (readl_poll_timeout_atomic(&desc->des0, val, 629 !(val & IDMAC_DES0_OWN), 630 10, 100 * USEC_PER_MSEC)) 631 goto err_own_bit; 632 633 /* 634 * Set the OWN bit and disable interrupts 635 * for this descriptor 636 */ 637 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 638 IDMAC_DES0_CH; 639 640 /* Buffer length */ 641 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 642 643 /* Physical address to DMA to/from */ 644 desc->des4 = mem_addr & 0xffffffff; 645 desc->des5 = mem_addr >> 32; 646 647 /* Update physical address for the next desc */ 648 mem_addr += desc_len; 649 650 /* Save pointer to the last descriptor */ 651 desc_last = desc; 652 } 653 } 654 655 /* Set first descriptor */ 656 desc_first->des0 |= IDMAC_DES0_FD; 657 658 /* Set last descriptor */ 659 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 660 desc_last->des0 |= IDMAC_DES0_LD; 661 662 return 0; 663 err_own_bit: 664 /* restore the descriptor chain as it's polluted */ 665 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 666 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 667 dw_mci_idmac_init(host); 668 return -EINVAL; 669 } 670 671 672 static inline int dw_mci_prepare_desc32(struct dw_mci *host, 673 struct mmc_data *data, 674 unsigned int sg_len) 675 { 676 unsigned int desc_len; 677 struct idmac_desc *desc_first, *desc_last, *desc; 678 u32 val; 679 int i; 680 681 desc_first = desc_last = desc = host->sg_cpu; 682 683 for (i = 0; i < sg_len; i++) { 684 unsigned int length = sg_dma_len(&data->sg[i]); 685 686 u32 mem_addr = sg_dma_address(&data->sg[i]); 687 688 for ( ; length ; desc++) { 689 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 690 length : DW_MCI_DESC_DATA_LENGTH; 691 692 length -= desc_len; 693 694 /* 695 * Wait for the former clear OWN bit operation 696 * of IDMAC to make sure that this descriptor 697 * isn't still owned by IDMAC as IDMAC's write 698 * ops and CPU's read ops are asynchronous. 699 */ 700 if (readl_poll_timeout_atomic(&desc->des0, val, 701 IDMAC_OWN_CLR64(val), 702 10, 703 100 * USEC_PER_MSEC)) 704 goto err_own_bit; 705 706 /* 707 * Set the OWN bit and disable interrupts 708 * for this descriptor 709 */ 710 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 711 IDMAC_DES0_DIC | 712 IDMAC_DES0_CH); 713 714 /* Buffer length */ 715 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 716 717 /* Physical address to DMA to/from */ 718 desc->des2 = cpu_to_le32(mem_addr); 719 720 /* Update physical address for the next desc */ 721 mem_addr += desc_len; 722 723 /* Save pointer to the last descriptor */ 724 desc_last = desc; 725 } 726 } 727 728 /* Set first descriptor */ 729 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 730 731 /* Set last descriptor */ 732 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 733 IDMAC_DES0_DIC)); 734 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 735 736 return 0; 737 err_own_bit: 738 /* restore the descriptor chain as it's polluted */ 739 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 740 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 741 dw_mci_idmac_init(host); 742 return -EINVAL; 743 } 744 745 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 746 { 747 u32 temp; 748 int ret; 749 750 if (host->dma_64bit_address == 1) 751 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 752 else 753 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 754 755 if (ret) 756 goto out; 757 758 /* drain writebuffer */ 759 wmb(); 760 761 /* Make sure to reset DMA in case we did PIO before this */ 762 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 763 dw_mci_idmac_reset(host); 764 765 /* Select IDMAC interface */ 766 temp = mci_readl(host, CTRL); 767 temp |= SDMMC_CTRL_USE_IDMAC; 768 mci_writel(host, CTRL, temp); 769 770 /* drain writebuffer */ 771 wmb(); 772 773 /* Enable the IDMAC */ 774 temp = mci_readl(host, BMOD); 775 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 776 mci_writel(host, BMOD, temp); 777 778 /* Start it running */ 779 mci_writel(host, PLDMND, 1); 780 781 out: 782 return ret; 783 } 784 785 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 786 .init = dw_mci_idmac_init, 787 .start = dw_mci_idmac_start_dma, 788 .stop = dw_mci_idmac_stop_dma, 789 .complete = dw_mci_dmac_complete_dma, 790 .cleanup = dw_mci_dma_cleanup, 791 }; 792 793 static void dw_mci_edmac_stop_dma(struct dw_mci *host) 794 { 795 dmaengine_terminate_async(host->dms->ch); 796 } 797 798 static int dw_mci_edmac_start_dma(struct dw_mci *host, 799 unsigned int sg_len) 800 { 801 struct dma_slave_config cfg; 802 struct dma_async_tx_descriptor *desc = NULL; 803 struct scatterlist *sgl = host->data->sg; 804 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 805 u32 sg_elems = host->data->sg_len; 806 u32 fifoth_val; 807 u32 fifo_offset = host->fifo_reg - host->regs; 808 int ret = 0; 809 810 /* Set external dma config: burst size, burst width */ 811 cfg.dst_addr = host->phy_regs + fifo_offset; 812 cfg.src_addr = cfg.dst_addr; 813 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 814 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 815 816 /* Match burst msize with external dma config */ 817 fifoth_val = mci_readl(host, FIFOTH); 818 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 819 cfg.src_maxburst = cfg.dst_maxburst; 820 821 if (host->data->flags & MMC_DATA_WRITE) 822 cfg.direction = DMA_MEM_TO_DEV; 823 else 824 cfg.direction = DMA_DEV_TO_MEM; 825 826 ret = dmaengine_slave_config(host->dms->ch, &cfg); 827 if (ret) { 828 dev_err(host->dev, "Failed to config edmac.\n"); 829 return -EBUSY; 830 } 831 832 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 833 sg_len, cfg.direction, 834 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 835 if (!desc) { 836 dev_err(host->dev, "Can't prepare slave sg.\n"); 837 return -EBUSY; 838 } 839 840 /* Set dw_mci_dmac_complete_dma as callback */ 841 desc->callback = dw_mci_dmac_complete_dma; 842 desc->callback_param = (void *)host; 843 dmaengine_submit(desc); 844 845 /* Flush cache before write */ 846 if (host->data->flags & MMC_DATA_WRITE) 847 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 848 sg_elems, DMA_TO_DEVICE); 849 850 dma_async_issue_pending(host->dms->ch); 851 852 return 0; 853 } 854 855 static int dw_mci_edmac_init(struct dw_mci *host) 856 { 857 /* Request external dma channel */ 858 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 859 if (!host->dms) 860 return -ENOMEM; 861 862 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 863 if (!host->dms->ch) { 864 dev_err(host->dev, "Failed to get external DMA channel.\n"); 865 kfree(host->dms); 866 host->dms = NULL; 867 return -ENXIO; 868 } 869 870 return 0; 871 } 872 873 static void dw_mci_edmac_exit(struct dw_mci *host) 874 { 875 if (host->dms) { 876 if (host->dms->ch) { 877 dma_release_channel(host->dms->ch); 878 host->dms->ch = NULL; 879 } 880 kfree(host->dms); 881 host->dms = NULL; 882 } 883 } 884 885 static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 886 .init = dw_mci_edmac_init, 887 .exit = dw_mci_edmac_exit, 888 .start = dw_mci_edmac_start_dma, 889 .stop = dw_mci_edmac_stop_dma, 890 .complete = dw_mci_dmac_complete_dma, 891 .cleanup = dw_mci_dma_cleanup, 892 }; 893 894 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 895 struct mmc_data *data, 896 int cookie) 897 { 898 struct scatterlist *sg; 899 unsigned int i, sg_len; 900 901 if (data->host_cookie == COOKIE_PRE_MAPPED) 902 return data->sg_len; 903 904 /* 905 * We don't do DMA on "complex" transfers, i.e. with 906 * non-word-aligned buffers or lengths. Also, we don't bother 907 * with all the DMA setup overhead for short transfers. 908 */ 909 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 910 return -EINVAL; 911 912 if (data->blksz & 3) 913 return -EINVAL; 914 915 for_each_sg(data->sg, sg, data->sg_len, i) { 916 if (sg->offset & 3 || sg->length & 3) 917 return -EINVAL; 918 } 919 920 sg_len = dma_map_sg(host->dev, 921 data->sg, 922 data->sg_len, 923 mmc_get_dma_dir(data)); 924 if (sg_len == 0) 925 return -EINVAL; 926 927 data->host_cookie = cookie; 928 929 return sg_len; 930 } 931 932 static void dw_mci_pre_req(struct mmc_host *mmc, 933 struct mmc_request *mrq) 934 { 935 struct dw_mci_slot *slot = mmc_priv(mmc); 936 struct mmc_data *data = mrq->data; 937 938 if (!slot->host->use_dma || !data) 939 return; 940 941 /* This data might be unmapped at this time */ 942 data->host_cookie = COOKIE_UNMAPPED; 943 944 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 945 COOKIE_PRE_MAPPED) < 0) 946 data->host_cookie = COOKIE_UNMAPPED; 947 } 948 949 static void dw_mci_post_req(struct mmc_host *mmc, 950 struct mmc_request *mrq, 951 int err) 952 { 953 struct dw_mci_slot *slot = mmc_priv(mmc); 954 struct mmc_data *data = mrq->data; 955 956 if (!slot->host->use_dma || !data) 957 return; 958 959 if (data->host_cookie != COOKIE_UNMAPPED) 960 dma_unmap_sg(slot->host->dev, 961 data->sg, 962 data->sg_len, 963 mmc_get_dma_dir(data)); 964 data->host_cookie = COOKIE_UNMAPPED; 965 } 966 967 static int dw_mci_get_cd(struct mmc_host *mmc) 968 { 969 int present; 970 struct dw_mci_slot *slot = mmc_priv(mmc); 971 struct dw_mci *host = slot->host; 972 int gpio_cd = mmc_gpio_get_cd(mmc); 973 974 /* Use platform get_cd function, else try onboard card detect */ 975 if (((mmc->caps & MMC_CAP_NEEDS_POLL) 976 || !mmc_card_is_removable(mmc))) { 977 present = 1; 978 979 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 980 if (mmc->caps & MMC_CAP_NEEDS_POLL) { 981 dev_info(&mmc->class_dev, 982 "card is polling.\n"); 983 } else { 984 dev_info(&mmc->class_dev, 985 "card is non-removable.\n"); 986 } 987 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 988 } 989 990 return present; 991 } else if (gpio_cd >= 0) 992 present = gpio_cd; 993 else 994 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 995 == 0 ? 1 : 0; 996 997 spin_lock_bh(&host->lock); 998 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 999 dev_dbg(&mmc->class_dev, "card is present\n"); 1000 else if (!present && 1001 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 1002 dev_dbg(&mmc->class_dev, "card is not present\n"); 1003 spin_unlock_bh(&host->lock); 1004 1005 return present; 1006 } 1007 1008 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 1009 { 1010 unsigned int blksz = data->blksz; 1011 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 1012 u32 fifo_width = 1 << host->data_shift; 1013 u32 blksz_depth = blksz / fifo_width, fifoth_val; 1014 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 1015 int idx = ARRAY_SIZE(mszs) - 1; 1016 1017 /* pio should ship this scenario */ 1018 if (!host->use_dma) 1019 return; 1020 1021 tx_wmark = (host->fifo_depth) / 2; 1022 tx_wmark_invers = host->fifo_depth - tx_wmark; 1023 1024 /* 1025 * MSIZE is '1', 1026 * if blksz is not a multiple of the FIFO width 1027 */ 1028 if (blksz % fifo_width) 1029 goto done; 1030 1031 do { 1032 if (!((blksz_depth % mszs[idx]) || 1033 (tx_wmark_invers % mszs[idx]))) { 1034 msize = idx; 1035 rx_wmark = mszs[idx] - 1; 1036 break; 1037 } 1038 } while (--idx > 0); 1039 /* 1040 * If idx is '0', it won't be tried 1041 * Thus, initial values are uesed 1042 */ 1043 done: 1044 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 1045 mci_writel(host, FIFOTH, fifoth_val); 1046 } 1047 1048 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1049 { 1050 unsigned int blksz = data->blksz; 1051 u32 blksz_depth, fifo_depth; 1052 u16 thld_size; 1053 u8 enable; 1054 1055 /* 1056 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 1057 * in the FIFO region, so we really shouldn't access it). 1058 */ 1059 if (host->verid < DW_MMC_240A || 1060 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 1061 return; 1062 1063 /* 1064 * Card write Threshold is introduced since 2.80a 1065 * It's used when HS400 mode is enabled. 1066 */ 1067 if (data->flags & MMC_DATA_WRITE && 1068 !(host->timing != MMC_TIMING_MMC_HS400)) 1069 return; 1070 1071 if (data->flags & MMC_DATA_WRITE) 1072 enable = SDMMC_CARD_WR_THR_EN; 1073 else 1074 enable = SDMMC_CARD_RD_THR_EN; 1075 1076 if (host->timing != MMC_TIMING_MMC_HS200 && 1077 host->timing != MMC_TIMING_UHS_SDR104) 1078 goto disable; 1079 1080 blksz_depth = blksz / (1 << host->data_shift); 1081 fifo_depth = host->fifo_depth; 1082 1083 if (blksz_depth > fifo_depth) 1084 goto disable; 1085 1086 /* 1087 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1088 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1089 * Currently just choose blksz. 1090 */ 1091 thld_size = blksz; 1092 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1093 return; 1094 1095 disable: 1096 mci_writel(host, CDTHRCTL, 0); 1097 } 1098 1099 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1100 { 1101 unsigned long irqflags; 1102 int sg_len; 1103 u32 temp; 1104 1105 host->using_dma = 0; 1106 1107 /* If we don't have a channel, we can't do DMA */ 1108 if (!host->use_dma) 1109 return -ENODEV; 1110 1111 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1112 if (sg_len < 0) { 1113 host->dma_ops->stop(host); 1114 return sg_len; 1115 } 1116 1117 host->using_dma = 1; 1118 1119 if (host->use_dma == TRANS_MODE_IDMAC) 1120 dev_vdbg(host->dev, 1121 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1122 (unsigned long)host->sg_cpu, 1123 (unsigned long)host->sg_dma, 1124 sg_len); 1125 1126 /* 1127 * Decide the MSIZE and RX/TX Watermark. 1128 * If current block size is same with previous size, 1129 * no need to update fifoth. 1130 */ 1131 if (host->prev_blksz != data->blksz) 1132 dw_mci_adjust_fifoth(host, data); 1133 1134 /* Enable the DMA interface */ 1135 temp = mci_readl(host, CTRL); 1136 temp |= SDMMC_CTRL_DMA_ENABLE; 1137 mci_writel(host, CTRL, temp); 1138 1139 /* Disable RX/TX IRQs, let DMA handle it */ 1140 spin_lock_irqsave(&host->irq_lock, irqflags); 1141 temp = mci_readl(host, INTMASK); 1142 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1143 mci_writel(host, INTMASK, temp); 1144 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1145 1146 if (host->dma_ops->start(host, sg_len)) { 1147 host->dma_ops->stop(host); 1148 /* We can't do DMA, try PIO for this one */ 1149 dev_dbg(host->dev, 1150 "%s: fall back to PIO mode for current transfer\n", 1151 __func__); 1152 return -ENODEV; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1159 { 1160 unsigned long irqflags; 1161 int flags = SG_MITER_ATOMIC; 1162 u32 temp; 1163 1164 data->error = -EINPROGRESS; 1165 1166 WARN_ON(host->data); 1167 host->sg = NULL; 1168 host->data = data; 1169 1170 if (data->flags & MMC_DATA_READ) 1171 host->dir_status = DW_MCI_RECV_STATUS; 1172 else 1173 host->dir_status = DW_MCI_SEND_STATUS; 1174 1175 dw_mci_ctrl_thld(host, data); 1176 1177 if (dw_mci_submit_data_dma(host, data)) { 1178 if (host->data->flags & MMC_DATA_READ) 1179 flags |= SG_MITER_TO_SG; 1180 else 1181 flags |= SG_MITER_FROM_SG; 1182 1183 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1184 host->sg = data->sg; 1185 host->part_buf_start = 0; 1186 host->part_buf_count = 0; 1187 1188 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1189 1190 spin_lock_irqsave(&host->irq_lock, irqflags); 1191 temp = mci_readl(host, INTMASK); 1192 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1193 mci_writel(host, INTMASK, temp); 1194 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1195 1196 temp = mci_readl(host, CTRL); 1197 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1198 mci_writel(host, CTRL, temp); 1199 1200 /* 1201 * Use the initial fifoth_val for PIO mode. If wm_algined 1202 * is set, we set watermark same as data size. 1203 * If next issued data may be transfered by DMA mode, 1204 * prev_blksz should be invalidated. 1205 */ 1206 if (host->wm_aligned) 1207 dw_mci_adjust_fifoth(host, data); 1208 else 1209 mci_writel(host, FIFOTH, host->fifoth_val); 1210 host->prev_blksz = 0; 1211 } else { 1212 /* 1213 * Keep the current block size. 1214 * It will be used to decide whether to update 1215 * fifoth register next time. 1216 */ 1217 host->prev_blksz = data->blksz; 1218 } 1219 } 1220 1221 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1222 { 1223 struct dw_mci *host = slot->host; 1224 unsigned int clock = slot->clock; 1225 u32 div; 1226 u32 clk_en_a; 1227 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1228 1229 /* We must continue to set bit 28 in CMD until the change is complete */ 1230 if (host->state == STATE_WAITING_CMD11_DONE) 1231 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1232 1233 slot->mmc->actual_clock = 0; 1234 1235 if (!clock) { 1236 mci_writel(host, CLKENA, 0); 1237 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1238 } else if (clock != host->current_speed || force_clkinit) { 1239 div = host->bus_hz / clock; 1240 if (host->bus_hz % clock && host->bus_hz > clock) 1241 /* 1242 * move the + 1 after the divide to prevent 1243 * over-clocking the card. 1244 */ 1245 div += 1; 1246 1247 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1248 1249 if ((clock != slot->__clk_old && 1250 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1251 force_clkinit) { 1252 /* Silent the verbose log if calling from PM context */ 1253 if (!force_clkinit) 1254 dev_info(&slot->mmc->class_dev, 1255 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1256 slot->id, host->bus_hz, clock, 1257 div ? ((host->bus_hz / div) >> 1) : 1258 host->bus_hz, div); 1259 1260 /* 1261 * If card is polling, display the message only 1262 * one time at boot time. 1263 */ 1264 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1265 slot->mmc->f_min == clock) 1266 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1267 } 1268 1269 /* disable clock */ 1270 mci_writel(host, CLKENA, 0); 1271 mci_writel(host, CLKSRC, 0); 1272 1273 /* inform CIU */ 1274 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1275 1276 /* set clock to desired speed */ 1277 mci_writel(host, CLKDIV, div); 1278 1279 /* inform CIU */ 1280 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1281 1282 /* enable clock; only low power if no SDIO */ 1283 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1284 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1285 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1286 mci_writel(host, CLKENA, clk_en_a); 1287 1288 /* inform CIU */ 1289 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1290 1291 /* keep the last clock value that was requested from core */ 1292 slot->__clk_old = clock; 1293 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : 1294 host->bus_hz; 1295 } 1296 1297 host->current_speed = clock; 1298 1299 /* Set the current slot bus width */ 1300 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1301 } 1302 1303 static void __dw_mci_start_request(struct dw_mci *host, 1304 struct dw_mci_slot *slot, 1305 struct mmc_command *cmd) 1306 { 1307 struct mmc_request *mrq; 1308 struct mmc_data *data; 1309 u32 cmdflags; 1310 1311 mrq = slot->mrq; 1312 1313 host->mrq = mrq; 1314 1315 host->pending_events = 0; 1316 host->completed_events = 0; 1317 host->cmd_status = 0; 1318 host->data_status = 0; 1319 host->dir_status = 0; 1320 1321 data = cmd->data; 1322 if (data) { 1323 mci_writel(host, TMOUT, 0xFFFFFFFF); 1324 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1325 mci_writel(host, BLKSIZ, data->blksz); 1326 } 1327 1328 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1329 1330 /* this is the first command, send the initialization clock */ 1331 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1332 cmdflags |= SDMMC_CMD_INIT; 1333 1334 if (data) { 1335 dw_mci_submit_data(host, data); 1336 wmb(); /* drain writebuffer */ 1337 } 1338 1339 dw_mci_start_command(host, cmd, cmdflags); 1340 1341 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1342 unsigned long irqflags; 1343 1344 /* 1345 * Databook says to fail after 2ms w/ no response, but evidence 1346 * shows that sometimes the cmd11 interrupt takes over 130ms. 1347 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1348 * is just about to roll over. 1349 * 1350 * We do this whole thing under spinlock and only if the 1351 * command hasn't already completed (indicating the the irq 1352 * already ran so we don't want the timeout). 1353 */ 1354 spin_lock_irqsave(&host->irq_lock, irqflags); 1355 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1356 mod_timer(&host->cmd11_timer, 1357 jiffies + msecs_to_jiffies(500) + 1); 1358 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1359 } 1360 1361 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1362 } 1363 1364 static void dw_mci_start_request(struct dw_mci *host, 1365 struct dw_mci_slot *slot) 1366 { 1367 struct mmc_request *mrq = slot->mrq; 1368 struct mmc_command *cmd; 1369 1370 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1371 __dw_mci_start_request(host, slot, cmd); 1372 } 1373 1374 /* must be called with host->lock held */ 1375 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1376 struct mmc_request *mrq) 1377 { 1378 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1379 host->state); 1380 1381 slot->mrq = mrq; 1382 1383 if (host->state == STATE_WAITING_CMD11_DONE) { 1384 dev_warn(&slot->mmc->class_dev, 1385 "Voltage change didn't complete\n"); 1386 /* 1387 * this case isn't expected to happen, so we can 1388 * either crash here or just try to continue on 1389 * in the closest possible state 1390 */ 1391 host->state = STATE_IDLE; 1392 } 1393 1394 if (host->state == STATE_IDLE) { 1395 host->state = STATE_SENDING_CMD; 1396 dw_mci_start_request(host, slot); 1397 } else { 1398 list_add_tail(&slot->queue_node, &host->queue); 1399 } 1400 } 1401 1402 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1403 { 1404 struct dw_mci_slot *slot = mmc_priv(mmc); 1405 struct dw_mci *host = slot->host; 1406 1407 WARN_ON(slot->mrq); 1408 1409 /* 1410 * The check for card presence and queueing of the request must be 1411 * atomic, otherwise the card could be removed in between and the 1412 * request wouldn't fail until another card was inserted. 1413 */ 1414 1415 if (!dw_mci_get_cd(mmc)) { 1416 mrq->cmd->error = -ENOMEDIUM; 1417 mmc_request_done(mmc, mrq); 1418 return; 1419 } 1420 1421 spin_lock_bh(&host->lock); 1422 1423 dw_mci_queue_request(host, slot, mrq); 1424 1425 spin_unlock_bh(&host->lock); 1426 } 1427 1428 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1429 { 1430 struct dw_mci_slot *slot = mmc_priv(mmc); 1431 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1432 u32 regs; 1433 int ret; 1434 1435 switch (ios->bus_width) { 1436 case MMC_BUS_WIDTH_4: 1437 slot->ctype = SDMMC_CTYPE_4BIT; 1438 break; 1439 case MMC_BUS_WIDTH_8: 1440 slot->ctype = SDMMC_CTYPE_8BIT; 1441 break; 1442 default: 1443 /* set default 1 bit mode */ 1444 slot->ctype = SDMMC_CTYPE_1BIT; 1445 } 1446 1447 regs = mci_readl(slot->host, UHS_REG); 1448 1449 /* DDR mode set */ 1450 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1451 ios->timing == MMC_TIMING_UHS_DDR50 || 1452 ios->timing == MMC_TIMING_MMC_HS400) 1453 regs |= ((0x1 << slot->id) << 16); 1454 else 1455 regs &= ~((0x1 << slot->id) << 16); 1456 1457 mci_writel(slot->host, UHS_REG, regs); 1458 slot->host->timing = ios->timing; 1459 1460 /* 1461 * Use mirror of ios->clock to prevent race with mmc 1462 * core ios update when finding the minimum. 1463 */ 1464 slot->clock = ios->clock; 1465 1466 if (drv_data && drv_data->set_ios) 1467 drv_data->set_ios(slot->host, ios); 1468 1469 switch (ios->power_mode) { 1470 case MMC_POWER_UP: 1471 if (!IS_ERR(mmc->supply.vmmc)) { 1472 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1473 ios->vdd); 1474 if (ret) { 1475 dev_err(slot->host->dev, 1476 "failed to enable vmmc regulator\n"); 1477 /*return, if failed turn on vmmc*/ 1478 return; 1479 } 1480 } 1481 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1482 regs = mci_readl(slot->host, PWREN); 1483 regs |= (1 << slot->id); 1484 mci_writel(slot->host, PWREN, regs); 1485 break; 1486 case MMC_POWER_ON: 1487 if (!slot->host->vqmmc_enabled) { 1488 if (!IS_ERR(mmc->supply.vqmmc)) { 1489 ret = regulator_enable(mmc->supply.vqmmc); 1490 if (ret < 0) 1491 dev_err(slot->host->dev, 1492 "failed to enable vqmmc\n"); 1493 else 1494 slot->host->vqmmc_enabled = true; 1495 1496 } else { 1497 /* Keep track so we don't reset again */ 1498 slot->host->vqmmc_enabled = true; 1499 } 1500 1501 /* Reset our state machine after powering on */ 1502 dw_mci_ctrl_reset(slot->host, 1503 SDMMC_CTRL_ALL_RESET_FLAGS); 1504 } 1505 1506 /* Adjust clock / bus width after power is up */ 1507 dw_mci_setup_bus(slot, false); 1508 1509 break; 1510 case MMC_POWER_OFF: 1511 /* Turn clock off before power goes down */ 1512 dw_mci_setup_bus(slot, false); 1513 1514 if (!IS_ERR(mmc->supply.vmmc)) 1515 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1516 1517 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1518 regulator_disable(mmc->supply.vqmmc); 1519 slot->host->vqmmc_enabled = false; 1520 1521 regs = mci_readl(slot->host, PWREN); 1522 regs &= ~(1 << slot->id); 1523 mci_writel(slot->host, PWREN, regs); 1524 break; 1525 default: 1526 break; 1527 } 1528 1529 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1530 slot->host->state = STATE_IDLE; 1531 } 1532 1533 static int dw_mci_card_busy(struct mmc_host *mmc) 1534 { 1535 struct dw_mci_slot *slot = mmc_priv(mmc); 1536 u32 status; 1537 1538 /* 1539 * Check the busy bit which is low when DAT[3:0] 1540 * (the data lines) are 0000 1541 */ 1542 status = mci_readl(slot->host, STATUS); 1543 1544 return !!(status & SDMMC_STATUS_BUSY); 1545 } 1546 1547 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1548 { 1549 struct dw_mci_slot *slot = mmc_priv(mmc); 1550 struct dw_mci *host = slot->host; 1551 const struct dw_mci_drv_data *drv_data = host->drv_data; 1552 u32 uhs; 1553 u32 v18 = SDMMC_UHS_18V << slot->id; 1554 int ret; 1555 1556 if (drv_data && drv_data->switch_voltage) 1557 return drv_data->switch_voltage(mmc, ios); 1558 1559 /* 1560 * Program the voltage. Note that some instances of dw_mmc may use 1561 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1562 * does no harm but you need to set the regulator directly. Try both. 1563 */ 1564 uhs = mci_readl(host, UHS_REG); 1565 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1566 uhs &= ~v18; 1567 else 1568 uhs |= v18; 1569 1570 if (!IS_ERR(mmc->supply.vqmmc)) { 1571 ret = mmc_regulator_set_vqmmc(mmc, ios); 1572 1573 if (ret) { 1574 dev_dbg(&mmc->class_dev, 1575 "Regulator set error %d - %s V\n", 1576 ret, uhs & v18 ? "1.8" : "3.3"); 1577 return ret; 1578 } 1579 } 1580 mci_writel(host, UHS_REG, uhs); 1581 1582 return 0; 1583 } 1584 1585 static int dw_mci_get_ro(struct mmc_host *mmc) 1586 { 1587 int read_only; 1588 struct dw_mci_slot *slot = mmc_priv(mmc); 1589 int gpio_ro = mmc_gpio_get_ro(mmc); 1590 1591 /* Use platform get_ro function, else try on board write protect */ 1592 if (gpio_ro >= 0) 1593 read_only = gpio_ro; 1594 else 1595 read_only = 1596 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1597 1598 dev_dbg(&mmc->class_dev, "card is %s\n", 1599 read_only ? "read-only" : "read-write"); 1600 1601 return read_only; 1602 } 1603 1604 static void dw_mci_hw_reset(struct mmc_host *mmc) 1605 { 1606 struct dw_mci_slot *slot = mmc_priv(mmc); 1607 struct dw_mci *host = slot->host; 1608 int reset; 1609 1610 if (host->use_dma == TRANS_MODE_IDMAC) 1611 dw_mci_idmac_reset(host); 1612 1613 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1614 SDMMC_CTRL_FIFO_RESET)) 1615 return; 1616 1617 /* 1618 * According to eMMC spec, card reset procedure: 1619 * tRstW >= 1us: RST_n pulse width 1620 * tRSCA >= 200us: RST_n to Command time 1621 * tRSTH >= 1us: RST_n high period 1622 */ 1623 reset = mci_readl(host, RST_N); 1624 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1625 mci_writel(host, RST_N, reset); 1626 usleep_range(1, 2); 1627 reset |= SDMMC_RST_HWACTIVE << slot->id; 1628 mci_writel(host, RST_N, reset); 1629 usleep_range(200, 300); 1630 } 1631 1632 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1633 { 1634 struct dw_mci_slot *slot = mmc_priv(mmc); 1635 struct dw_mci *host = slot->host; 1636 1637 /* 1638 * Low power mode will stop the card clock when idle. According to the 1639 * description of the CLKENA register we should disable low power mode 1640 * for SDIO cards if we need SDIO interrupts to work. 1641 */ 1642 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1643 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1644 u32 clk_en_a_old; 1645 u32 clk_en_a; 1646 1647 clk_en_a_old = mci_readl(host, CLKENA); 1648 1649 if (card->type == MMC_TYPE_SDIO || 1650 card->type == MMC_TYPE_SD_COMBO) { 1651 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1652 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1653 } else { 1654 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1655 clk_en_a = clk_en_a_old | clken_low_pwr; 1656 } 1657 1658 if (clk_en_a != clk_en_a_old) { 1659 mci_writel(host, CLKENA, clk_en_a); 1660 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1661 SDMMC_CMD_PRV_DAT_WAIT, 0); 1662 } 1663 } 1664 } 1665 1666 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 1667 { 1668 struct dw_mci *host = slot->host; 1669 unsigned long irqflags; 1670 u32 int_mask; 1671 1672 spin_lock_irqsave(&host->irq_lock, irqflags); 1673 1674 /* Enable/disable Slot Specific SDIO interrupt */ 1675 int_mask = mci_readl(host, INTMASK); 1676 if (enb) 1677 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1678 else 1679 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1680 mci_writel(host, INTMASK, int_mask); 1681 1682 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1683 } 1684 1685 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1686 { 1687 struct dw_mci_slot *slot = mmc_priv(mmc); 1688 struct dw_mci *host = slot->host; 1689 1690 __dw_mci_enable_sdio_irq(slot, enb); 1691 1692 /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1693 if (enb) 1694 pm_runtime_get_noresume(host->dev); 1695 else 1696 pm_runtime_put_noidle(host->dev); 1697 } 1698 1699 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 1700 { 1701 struct dw_mci_slot *slot = mmc_priv(mmc); 1702 1703 __dw_mci_enable_sdio_irq(slot, 1); 1704 } 1705 1706 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1707 { 1708 struct dw_mci_slot *slot = mmc_priv(mmc); 1709 struct dw_mci *host = slot->host; 1710 const struct dw_mci_drv_data *drv_data = host->drv_data; 1711 int err = -EINVAL; 1712 1713 if (drv_data && drv_data->execute_tuning) 1714 err = drv_data->execute_tuning(slot, opcode); 1715 return err; 1716 } 1717 1718 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1719 struct mmc_ios *ios) 1720 { 1721 struct dw_mci_slot *slot = mmc_priv(mmc); 1722 struct dw_mci *host = slot->host; 1723 const struct dw_mci_drv_data *drv_data = host->drv_data; 1724 1725 if (drv_data && drv_data->prepare_hs400_tuning) 1726 return drv_data->prepare_hs400_tuning(host, ios); 1727 1728 return 0; 1729 } 1730 1731 static bool dw_mci_reset(struct dw_mci *host) 1732 { 1733 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 1734 bool ret = false; 1735 u32 status = 0; 1736 1737 /* 1738 * Resetting generates a block interrupt, hence setting 1739 * the scatter-gather pointer to NULL. 1740 */ 1741 if (host->sg) { 1742 sg_miter_stop(&host->sg_miter); 1743 host->sg = NULL; 1744 } 1745 1746 if (host->use_dma) 1747 flags |= SDMMC_CTRL_DMA_RESET; 1748 1749 if (dw_mci_ctrl_reset(host, flags)) { 1750 /* 1751 * In all cases we clear the RAWINTS 1752 * register to clear any interrupts. 1753 */ 1754 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1755 1756 if (!host->use_dma) { 1757 ret = true; 1758 goto ciu_out; 1759 } 1760 1761 /* Wait for dma_req to be cleared */ 1762 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 1763 status, 1764 !(status & SDMMC_STATUS_DMA_REQ), 1765 1, 500 * USEC_PER_MSEC)) { 1766 dev_err(host->dev, 1767 "%s: Timeout waiting for dma_req to be cleared\n", 1768 __func__); 1769 goto ciu_out; 1770 } 1771 1772 /* when using DMA next we reset the fifo again */ 1773 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 1774 goto ciu_out; 1775 } else { 1776 /* if the controller reset bit did clear, then set clock regs */ 1777 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 1778 dev_err(host->dev, 1779 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 1780 __func__); 1781 goto ciu_out; 1782 } 1783 } 1784 1785 if (host->use_dma == TRANS_MODE_IDMAC) 1786 /* It is also required that we reinit idmac */ 1787 dw_mci_idmac_init(host); 1788 1789 ret = true; 1790 1791 ciu_out: 1792 /* After a CTRL reset we need to have CIU set clock registers */ 1793 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 1794 1795 return ret; 1796 } 1797 1798 static const struct mmc_host_ops dw_mci_ops = { 1799 .request = dw_mci_request, 1800 .pre_req = dw_mci_pre_req, 1801 .post_req = dw_mci_post_req, 1802 .set_ios = dw_mci_set_ios, 1803 .get_ro = dw_mci_get_ro, 1804 .get_cd = dw_mci_get_cd, 1805 .hw_reset = dw_mci_hw_reset, 1806 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1807 .ack_sdio_irq = dw_mci_ack_sdio_irq, 1808 .execute_tuning = dw_mci_execute_tuning, 1809 .card_busy = dw_mci_card_busy, 1810 .start_signal_voltage_switch = dw_mci_switch_voltage, 1811 .init_card = dw_mci_init_card, 1812 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1813 }; 1814 1815 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1816 __releases(&host->lock) 1817 __acquires(&host->lock) 1818 { 1819 struct dw_mci_slot *slot; 1820 struct mmc_host *prev_mmc = host->slot->mmc; 1821 1822 WARN_ON(host->cmd || host->data); 1823 1824 host->slot->mrq = NULL; 1825 host->mrq = NULL; 1826 if (!list_empty(&host->queue)) { 1827 slot = list_entry(host->queue.next, 1828 struct dw_mci_slot, queue_node); 1829 list_del(&slot->queue_node); 1830 dev_vdbg(host->dev, "list not empty: %s is next\n", 1831 mmc_hostname(slot->mmc)); 1832 host->state = STATE_SENDING_CMD; 1833 dw_mci_start_request(host, slot); 1834 } else { 1835 dev_vdbg(host->dev, "list empty\n"); 1836 1837 if (host->state == STATE_SENDING_CMD11) 1838 host->state = STATE_WAITING_CMD11_DONE; 1839 else 1840 host->state = STATE_IDLE; 1841 } 1842 1843 spin_unlock(&host->lock); 1844 mmc_request_done(prev_mmc, mrq); 1845 spin_lock(&host->lock); 1846 } 1847 1848 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1849 { 1850 u32 status = host->cmd_status; 1851 1852 host->cmd_status = 0; 1853 1854 /* Read the response from the card (up to 16 bytes) */ 1855 if (cmd->flags & MMC_RSP_PRESENT) { 1856 if (cmd->flags & MMC_RSP_136) { 1857 cmd->resp[3] = mci_readl(host, RESP0); 1858 cmd->resp[2] = mci_readl(host, RESP1); 1859 cmd->resp[1] = mci_readl(host, RESP2); 1860 cmd->resp[0] = mci_readl(host, RESP3); 1861 } else { 1862 cmd->resp[0] = mci_readl(host, RESP0); 1863 cmd->resp[1] = 0; 1864 cmd->resp[2] = 0; 1865 cmd->resp[3] = 0; 1866 } 1867 } 1868 1869 if (status & SDMMC_INT_RTO) 1870 cmd->error = -ETIMEDOUT; 1871 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1872 cmd->error = -EILSEQ; 1873 else if (status & SDMMC_INT_RESP_ERR) 1874 cmd->error = -EIO; 1875 else 1876 cmd->error = 0; 1877 1878 return cmd->error; 1879 } 1880 1881 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1882 { 1883 u32 status = host->data_status; 1884 1885 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1886 if (status & SDMMC_INT_DRTO) { 1887 data->error = -ETIMEDOUT; 1888 } else if (status & SDMMC_INT_DCRC) { 1889 data->error = -EILSEQ; 1890 } else if (status & SDMMC_INT_EBE) { 1891 if (host->dir_status == 1892 DW_MCI_SEND_STATUS) { 1893 /* 1894 * No data CRC status was returned. 1895 * The number of bytes transferred 1896 * will be exaggerated in PIO mode. 1897 */ 1898 data->bytes_xfered = 0; 1899 data->error = -ETIMEDOUT; 1900 } else if (host->dir_status == 1901 DW_MCI_RECV_STATUS) { 1902 data->error = -EILSEQ; 1903 } 1904 } else { 1905 /* SDMMC_INT_SBE is included */ 1906 data->error = -EILSEQ; 1907 } 1908 1909 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1910 1911 /* 1912 * After an error, there may be data lingering 1913 * in the FIFO 1914 */ 1915 dw_mci_reset(host); 1916 } else { 1917 data->bytes_xfered = data->blocks * data->blksz; 1918 data->error = 0; 1919 } 1920 1921 return data->error; 1922 } 1923 1924 static void dw_mci_set_drto(struct dw_mci *host) 1925 { 1926 unsigned int drto_clks; 1927 unsigned int drto_div; 1928 unsigned int drto_ms; 1929 unsigned long irqflags; 1930 1931 drto_clks = mci_readl(host, TMOUT) >> 8; 1932 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 1933 if (drto_div == 0) 1934 drto_div = 1; 1935 1936 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 1937 host->bus_hz); 1938 1939 /* add a bit spare time */ 1940 drto_ms += 10; 1941 1942 spin_lock_irqsave(&host->irq_lock, irqflags); 1943 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1944 mod_timer(&host->dto_timer, 1945 jiffies + msecs_to_jiffies(drto_ms)); 1946 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1947 } 1948 1949 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 1950 { 1951 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1952 return false; 1953 1954 /* 1955 * Really be certain that the timer has stopped. This is a bit of 1956 * paranoia and could only really happen if we had really bad 1957 * interrupt latency and the interrupt routine and timeout were 1958 * running concurrently so that the del_timer() in the interrupt 1959 * handler couldn't run. 1960 */ 1961 WARN_ON(del_timer_sync(&host->cto_timer)); 1962 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1963 1964 return true; 1965 } 1966 1967 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 1968 { 1969 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1970 return false; 1971 1972 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 1973 WARN_ON(del_timer_sync(&host->dto_timer)); 1974 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1975 1976 return true; 1977 } 1978 1979 static void dw_mci_tasklet_func(unsigned long priv) 1980 { 1981 struct dw_mci *host = (struct dw_mci *)priv; 1982 struct mmc_data *data; 1983 struct mmc_command *cmd; 1984 struct mmc_request *mrq; 1985 enum dw_mci_state state; 1986 enum dw_mci_state prev_state; 1987 unsigned int err; 1988 1989 spin_lock(&host->lock); 1990 1991 state = host->state; 1992 data = host->data; 1993 mrq = host->mrq; 1994 1995 do { 1996 prev_state = state; 1997 1998 switch (state) { 1999 case STATE_IDLE: 2000 case STATE_WAITING_CMD11_DONE: 2001 break; 2002 2003 case STATE_SENDING_CMD11: 2004 case STATE_SENDING_CMD: 2005 if (!dw_mci_clear_pending_cmd_complete(host)) 2006 break; 2007 2008 cmd = host->cmd; 2009 host->cmd = NULL; 2010 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 2011 err = dw_mci_command_complete(host, cmd); 2012 if (cmd == mrq->sbc && !err) { 2013 __dw_mci_start_request(host, host->slot, 2014 mrq->cmd); 2015 goto unlock; 2016 } 2017 2018 if (cmd->data && err) { 2019 /* 2020 * During UHS tuning sequence, sending the stop 2021 * command after the response CRC error would 2022 * throw the system into a confused state 2023 * causing all future tuning phases to report 2024 * failure. 2025 * 2026 * In such case controller will move into a data 2027 * transfer state after a response error or 2028 * response CRC error. Let's let that finish 2029 * before trying to send a stop, so we'll go to 2030 * STATE_SENDING_DATA. 2031 * 2032 * Although letting the data transfer take place 2033 * will waste a bit of time (we already know 2034 * the command was bad), it can't cause any 2035 * errors since it's possible it would have 2036 * taken place anyway if this tasklet got 2037 * delayed. Allowing the transfer to take place 2038 * avoids races and keeps things simple. 2039 */ 2040 if ((err != -ETIMEDOUT) && 2041 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 2042 state = STATE_SENDING_DATA; 2043 continue; 2044 } 2045 2046 dw_mci_stop_dma(host); 2047 send_stop_abort(host, data); 2048 state = STATE_SENDING_STOP; 2049 break; 2050 } 2051 2052 if (!cmd->data || err) { 2053 dw_mci_request_end(host, mrq); 2054 goto unlock; 2055 } 2056 2057 prev_state = state = STATE_SENDING_DATA; 2058 /* fall through */ 2059 2060 case STATE_SENDING_DATA: 2061 /* 2062 * We could get a data error and never a transfer 2063 * complete so we'd better check for it here. 2064 * 2065 * Note that we don't really care if we also got a 2066 * transfer complete; stopping the DMA and sending an 2067 * abort won't hurt. 2068 */ 2069 if (test_and_clear_bit(EVENT_DATA_ERROR, 2070 &host->pending_events)) { 2071 dw_mci_stop_dma(host); 2072 if (!(host->data_status & (SDMMC_INT_DRTO | 2073 SDMMC_INT_EBE))) 2074 send_stop_abort(host, data); 2075 state = STATE_DATA_ERROR; 2076 break; 2077 } 2078 2079 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2080 &host->pending_events)) { 2081 /* 2082 * If all data-related interrupts don't come 2083 * within the given time in reading data state. 2084 */ 2085 if (host->dir_status == DW_MCI_RECV_STATUS) 2086 dw_mci_set_drto(host); 2087 break; 2088 } 2089 2090 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 2091 2092 /* 2093 * Handle an EVENT_DATA_ERROR that might have shown up 2094 * before the transfer completed. This might not have 2095 * been caught by the check above because the interrupt 2096 * could have gone off between the previous check and 2097 * the check for transfer complete. 2098 * 2099 * Technically this ought not be needed assuming we 2100 * get a DATA_COMPLETE eventually (we'll notice the 2101 * error and end the request), but it shouldn't hurt. 2102 * 2103 * This has the advantage of sending the stop command. 2104 */ 2105 if (test_and_clear_bit(EVENT_DATA_ERROR, 2106 &host->pending_events)) { 2107 dw_mci_stop_dma(host); 2108 if (!(host->data_status & (SDMMC_INT_DRTO | 2109 SDMMC_INT_EBE))) 2110 send_stop_abort(host, data); 2111 state = STATE_DATA_ERROR; 2112 break; 2113 } 2114 prev_state = state = STATE_DATA_BUSY; 2115 2116 /* fall through */ 2117 2118 case STATE_DATA_BUSY: 2119 if (!dw_mci_clear_pending_data_complete(host)) { 2120 /* 2121 * If data error interrupt comes but data over 2122 * interrupt doesn't come within the given time. 2123 * in reading data state. 2124 */ 2125 if (host->dir_status == DW_MCI_RECV_STATUS) 2126 dw_mci_set_drto(host); 2127 break; 2128 } 2129 2130 host->data = NULL; 2131 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2132 err = dw_mci_data_complete(host, data); 2133 2134 if (!err) { 2135 if (!data->stop || mrq->sbc) { 2136 if (mrq->sbc && data->stop) 2137 data->stop->error = 0; 2138 dw_mci_request_end(host, mrq); 2139 goto unlock; 2140 } 2141 2142 /* stop command for open-ended transfer*/ 2143 if (data->stop) 2144 send_stop_abort(host, data); 2145 } else { 2146 /* 2147 * If we don't have a command complete now we'll 2148 * never get one since we just reset everything; 2149 * better end the request. 2150 * 2151 * If we do have a command complete we'll fall 2152 * through to the SENDING_STOP command and 2153 * everything will be peachy keen. 2154 */ 2155 if (!test_bit(EVENT_CMD_COMPLETE, 2156 &host->pending_events)) { 2157 host->cmd = NULL; 2158 dw_mci_request_end(host, mrq); 2159 goto unlock; 2160 } 2161 } 2162 2163 /* 2164 * If err has non-zero, 2165 * stop-abort command has been already issued. 2166 */ 2167 prev_state = state = STATE_SENDING_STOP; 2168 2169 /* fall through */ 2170 2171 case STATE_SENDING_STOP: 2172 if (!dw_mci_clear_pending_cmd_complete(host)) 2173 break; 2174 2175 /* CMD error in data command */ 2176 if (mrq->cmd->error && mrq->data) 2177 dw_mci_reset(host); 2178 2179 host->cmd = NULL; 2180 host->data = NULL; 2181 2182 if (!mrq->sbc && mrq->stop) 2183 dw_mci_command_complete(host, mrq->stop); 2184 else 2185 host->cmd_status = 0; 2186 2187 dw_mci_request_end(host, mrq); 2188 goto unlock; 2189 2190 case STATE_DATA_ERROR: 2191 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2192 &host->pending_events)) 2193 break; 2194 2195 state = STATE_DATA_BUSY; 2196 break; 2197 } 2198 } while (state != prev_state); 2199 2200 host->state = state; 2201 unlock: 2202 spin_unlock(&host->lock); 2203 2204 } 2205 2206 /* push final bytes to part_buf, only use during push */ 2207 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2208 { 2209 memcpy((void *)&host->part_buf, buf, cnt); 2210 host->part_buf_count = cnt; 2211 } 2212 2213 /* append bytes to part_buf, only use during push */ 2214 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2215 { 2216 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2217 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2218 host->part_buf_count += cnt; 2219 return cnt; 2220 } 2221 2222 /* pull first bytes from part_buf, only use during pull */ 2223 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2224 { 2225 cnt = min_t(int, cnt, host->part_buf_count); 2226 if (cnt) { 2227 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2228 cnt); 2229 host->part_buf_count -= cnt; 2230 host->part_buf_start += cnt; 2231 } 2232 return cnt; 2233 } 2234 2235 /* pull final bytes from the part_buf, assuming it's just been filled */ 2236 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2237 { 2238 memcpy(buf, &host->part_buf, cnt); 2239 host->part_buf_start = cnt; 2240 host->part_buf_count = (1 << host->data_shift) - cnt; 2241 } 2242 2243 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2244 { 2245 struct mmc_data *data = host->data; 2246 int init_cnt = cnt; 2247 2248 /* try and push anything in the part_buf */ 2249 if (unlikely(host->part_buf_count)) { 2250 int len = dw_mci_push_part_bytes(host, buf, cnt); 2251 2252 buf += len; 2253 cnt -= len; 2254 if (host->part_buf_count == 2) { 2255 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2256 host->part_buf_count = 0; 2257 } 2258 } 2259 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2260 if (unlikely((unsigned long)buf & 0x1)) { 2261 while (cnt >= 2) { 2262 u16 aligned_buf[64]; 2263 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2264 int items = len >> 1; 2265 int i; 2266 /* memcpy from input buffer into aligned buffer */ 2267 memcpy(aligned_buf, buf, len); 2268 buf += len; 2269 cnt -= len; 2270 /* push data from aligned buffer into fifo */ 2271 for (i = 0; i < items; ++i) 2272 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2273 } 2274 } else 2275 #endif 2276 { 2277 u16 *pdata = buf; 2278 2279 for (; cnt >= 2; cnt -= 2) 2280 mci_fifo_writew(host->fifo_reg, *pdata++); 2281 buf = pdata; 2282 } 2283 /* put anything remaining in the part_buf */ 2284 if (cnt) { 2285 dw_mci_set_part_bytes(host, buf, cnt); 2286 /* Push data if we have reached the expected data length */ 2287 if ((data->bytes_xfered + init_cnt) == 2288 (data->blksz * data->blocks)) 2289 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2290 } 2291 } 2292 2293 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2294 { 2295 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2296 if (unlikely((unsigned long)buf & 0x1)) { 2297 while (cnt >= 2) { 2298 /* pull data from fifo into aligned buffer */ 2299 u16 aligned_buf[64]; 2300 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2301 int items = len >> 1; 2302 int i; 2303 2304 for (i = 0; i < items; ++i) 2305 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2306 /* memcpy from aligned buffer into output buffer */ 2307 memcpy(buf, aligned_buf, len); 2308 buf += len; 2309 cnt -= len; 2310 } 2311 } else 2312 #endif 2313 { 2314 u16 *pdata = buf; 2315 2316 for (; cnt >= 2; cnt -= 2) 2317 *pdata++ = mci_fifo_readw(host->fifo_reg); 2318 buf = pdata; 2319 } 2320 if (cnt) { 2321 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2322 dw_mci_pull_final_bytes(host, buf, cnt); 2323 } 2324 } 2325 2326 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2327 { 2328 struct mmc_data *data = host->data; 2329 int init_cnt = cnt; 2330 2331 /* try and push anything in the part_buf */ 2332 if (unlikely(host->part_buf_count)) { 2333 int len = dw_mci_push_part_bytes(host, buf, cnt); 2334 2335 buf += len; 2336 cnt -= len; 2337 if (host->part_buf_count == 4) { 2338 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2339 host->part_buf_count = 0; 2340 } 2341 } 2342 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2343 if (unlikely((unsigned long)buf & 0x3)) { 2344 while (cnt >= 4) { 2345 u32 aligned_buf[32]; 2346 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2347 int items = len >> 2; 2348 int i; 2349 /* memcpy from input buffer into aligned buffer */ 2350 memcpy(aligned_buf, buf, len); 2351 buf += len; 2352 cnt -= len; 2353 /* push data from aligned buffer into fifo */ 2354 for (i = 0; i < items; ++i) 2355 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2356 } 2357 } else 2358 #endif 2359 { 2360 u32 *pdata = buf; 2361 2362 for (; cnt >= 4; cnt -= 4) 2363 mci_fifo_writel(host->fifo_reg, *pdata++); 2364 buf = pdata; 2365 } 2366 /* put anything remaining in the part_buf */ 2367 if (cnt) { 2368 dw_mci_set_part_bytes(host, buf, cnt); 2369 /* Push data if we have reached the expected data length */ 2370 if ((data->bytes_xfered + init_cnt) == 2371 (data->blksz * data->blocks)) 2372 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2373 } 2374 } 2375 2376 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2377 { 2378 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2379 if (unlikely((unsigned long)buf & 0x3)) { 2380 while (cnt >= 4) { 2381 /* pull data from fifo into aligned buffer */ 2382 u32 aligned_buf[32]; 2383 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2384 int items = len >> 2; 2385 int i; 2386 2387 for (i = 0; i < items; ++i) 2388 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2389 /* memcpy from aligned buffer into output buffer */ 2390 memcpy(buf, aligned_buf, len); 2391 buf += len; 2392 cnt -= len; 2393 } 2394 } else 2395 #endif 2396 { 2397 u32 *pdata = buf; 2398 2399 for (; cnt >= 4; cnt -= 4) 2400 *pdata++ = mci_fifo_readl(host->fifo_reg); 2401 buf = pdata; 2402 } 2403 if (cnt) { 2404 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2405 dw_mci_pull_final_bytes(host, buf, cnt); 2406 } 2407 } 2408 2409 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2410 { 2411 struct mmc_data *data = host->data; 2412 int init_cnt = cnt; 2413 2414 /* try and push anything in the part_buf */ 2415 if (unlikely(host->part_buf_count)) { 2416 int len = dw_mci_push_part_bytes(host, buf, cnt); 2417 2418 buf += len; 2419 cnt -= len; 2420 2421 if (host->part_buf_count == 8) { 2422 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2423 host->part_buf_count = 0; 2424 } 2425 } 2426 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2427 if (unlikely((unsigned long)buf & 0x7)) { 2428 while (cnt >= 8) { 2429 u64 aligned_buf[16]; 2430 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2431 int items = len >> 3; 2432 int i; 2433 /* memcpy from input buffer into aligned buffer */ 2434 memcpy(aligned_buf, buf, len); 2435 buf += len; 2436 cnt -= len; 2437 /* push data from aligned buffer into fifo */ 2438 for (i = 0; i < items; ++i) 2439 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2440 } 2441 } else 2442 #endif 2443 { 2444 u64 *pdata = buf; 2445 2446 for (; cnt >= 8; cnt -= 8) 2447 mci_fifo_writeq(host->fifo_reg, *pdata++); 2448 buf = pdata; 2449 } 2450 /* put anything remaining in the part_buf */ 2451 if (cnt) { 2452 dw_mci_set_part_bytes(host, buf, cnt); 2453 /* Push data if we have reached the expected data length */ 2454 if ((data->bytes_xfered + init_cnt) == 2455 (data->blksz * data->blocks)) 2456 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2457 } 2458 } 2459 2460 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2461 { 2462 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2463 if (unlikely((unsigned long)buf & 0x7)) { 2464 while (cnt >= 8) { 2465 /* pull data from fifo into aligned buffer */ 2466 u64 aligned_buf[16]; 2467 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2468 int items = len >> 3; 2469 int i; 2470 2471 for (i = 0; i < items; ++i) 2472 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2473 2474 /* memcpy from aligned buffer into output buffer */ 2475 memcpy(buf, aligned_buf, len); 2476 buf += len; 2477 cnt -= len; 2478 } 2479 } else 2480 #endif 2481 { 2482 u64 *pdata = buf; 2483 2484 for (; cnt >= 8; cnt -= 8) 2485 *pdata++ = mci_fifo_readq(host->fifo_reg); 2486 buf = pdata; 2487 } 2488 if (cnt) { 2489 host->part_buf = mci_fifo_readq(host->fifo_reg); 2490 dw_mci_pull_final_bytes(host, buf, cnt); 2491 } 2492 } 2493 2494 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2495 { 2496 int len; 2497 2498 /* get remaining partial bytes */ 2499 len = dw_mci_pull_part_bytes(host, buf, cnt); 2500 if (unlikely(len == cnt)) 2501 return; 2502 buf += len; 2503 cnt -= len; 2504 2505 /* get the rest of the data */ 2506 host->pull_data(host, buf, cnt); 2507 } 2508 2509 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2510 { 2511 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2512 void *buf; 2513 unsigned int offset; 2514 struct mmc_data *data = host->data; 2515 int shift = host->data_shift; 2516 u32 status; 2517 unsigned int len; 2518 unsigned int remain, fcnt; 2519 2520 do { 2521 if (!sg_miter_next(sg_miter)) 2522 goto done; 2523 2524 host->sg = sg_miter->piter.sg; 2525 buf = sg_miter->addr; 2526 remain = sg_miter->length; 2527 offset = 0; 2528 2529 do { 2530 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2531 << shift) + host->part_buf_count; 2532 len = min(remain, fcnt); 2533 if (!len) 2534 break; 2535 dw_mci_pull_data(host, (void *)(buf + offset), len); 2536 data->bytes_xfered += len; 2537 offset += len; 2538 remain -= len; 2539 } while (remain); 2540 2541 sg_miter->consumed = offset; 2542 status = mci_readl(host, MINTSTS); 2543 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2544 /* if the RXDR is ready read again */ 2545 } while ((status & SDMMC_INT_RXDR) || 2546 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2547 2548 if (!remain) { 2549 if (!sg_miter_next(sg_miter)) 2550 goto done; 2551 sg_miter->consumed = 0; 2552 } 2553 sg_miter_stop(sg_miter); 2554 return; 2555 2556 done: 2557 sg_miter_stop(sg_miter); 2558 host->sg = NULL; 2559 smp_wmb(); /* drain writebuffer */ 2560 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2561 } 2562 2563 static void dw_mci_write_data_pio(struct dw_mci *host) 2564 { 2565 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2566 void *buf; 2567 unsigned int offset; 2568 struct mmc_data *data = host->data; 2569 int shift = host->data_shift; 2570 u32 status; 2571 unsigned int len; 2572 unsigned int fifo_depth = host->fifo_depth; 2573 unsigned int remain, fcnt; 2574 2575 do { 2576 if (!sg_miter_next(sg_miter)) 2577 goto done; 2578 2579 host->sg = sg_miter->piter.sg; 2580 buf = sg_miter->addr; 2581 remain = sg_miter->length; 2582 offset = 0; 2583 2584 do { 2585 fcnt = ((fifo_depth - 2586 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2587 << shift) - host->part_buf_count; 2588 len = min(remain, fcnt); 2589 if (!len) 2590 break; 2591 host->push_data(host, (void *)(buf + offset), len); 2592 data->bytes_xfered += len; 2593 offset += len; 2594 remain -= len; 2595 } while (remain); 2596 2597 sg_miter->consumed = offset; 2598 status = mci_readl(host, MINTSTS); 2599 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2600 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2601 2602 if (!remain) { 2603 if (!sg_miter_next(sg_miter)) 2604 goto done; 2605 sg_miter->consumed = 0; 2606 } 2607 sg_miter_stop(sg_miter); 2608 return; 2609 2610 done: 2611 sg_miter_stop(sg_miter); 2612 host->sg = NULL; 2613 smp_wmb(); /* drain writebuffer */ 2614 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2615 } 2616 2617 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2618 { 2619 del_timer(&host->cto_timer); 2620 2621 if (!host->cmd_status) 2622 host->cmd_status = status; 2623 2624 smp_wmb(); /* drain writebuffer */ 2625 2626 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2627 tasklet_schedule(&host->tasklet); 2628 } 2629 2630 static void dw_mci_handle_cd(struct dw_mci *host) 2631 { 2632 struct dw_mci_slot *slot = host->slot; 2633 2634 if (slot->mmc->ops->card_event) 2635 slot->mmc->ops->card_event(slot->mmc); 2636 mmc_detect_change(slot->mmc, 2637 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2638 } 2639 2640 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2641 { 2642 struct dw_mci *host = dev_id; 2643 u32 pending; 2644 struct dw_mci_slot *slot = host->slot; 2645 unsigned long irqflags; 2646 2647 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2648 2649 if (pending) { 2650 /* Check volt switch first, since it can look like an error */ 2651 if ((host->state == STATE_SENDING_CMD11) && 2652 (pending & SDMMC_INT_VOLT_SWITCH)) { 2653 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2654 pending &= ~SDMMC_INT_VOLT_SWITCH; 2655 2656 /* 2657 * Hold the lock; we know cmd11_timer can't be kicked 2658 * off after the lock is released, so safe to delete. 2659 */ 2660 spin_lock_irqsave(&host->irq_lock, irqflags); 2661 dw_mci_cmd_interrupt(host, pending); 2662 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2663 2664 del_timer(&host->cmd11_timer); 2665 } 2666 2667 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2668 spin_lock_irqsave(&host->irq_lock, irqflags); 2669 2670 del_timer(&host->cto_timer); 2671 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2672 host->cmd_status = pending; 2673 smp_wmb(); /* drain writebuffer */ 2674 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2675 2676 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2677 } 2678 2679 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2680 /* if there is an error report DATA_ERROR */ 2681 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2682 host->data_status = pending; 2683 smp_wmb(); /* drain writebuffer */ 2684 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2685 tasklet_schedule(&host->tasklet); 2686 } 2687 2688 if (pending & SDMMC_INT_DATA_OVER) { 2689 spin_lock_irqsave(&host->irq_lock, irqflags); 2690 2691 del_timer(&host->dto_timer); 2692 2693 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2694 if (!host->data_status) 2695 host->data_status = pending; 2696 smp_wmb(); /* drain writebuffer */ 2697 if (host->dir_status == DW_MCI_RECV_STATUS) { 2698 if (host->sg != NULL) 2699 dw_mci_read_data_pio(host, true); 2700 } 2701 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2702 tasklet_schedule(&host->tasklet); 2703 2704 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2705 } 2706 2707 if (pending & SDMMC_INT_RXDR) { 2708 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2709 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2710 dw_mci_read_data_pio(host, false); 2711 } 2712 2713 if (pending & SDMMC_INT_TXDR) { 2714 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2715 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2716 dw_mci_write_data_pio(host); 2717 } 2718 2719 if (pending & SDMMC_INT_CMD_DONE) { 2720 spin_lock_irqsave(&host->irq_lock, irqflags); 2721 2722 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2723 dw_mci_cmd_interrupt(host, pending); 2724 2725 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2726 } 2727 2728 if (pending & SDMMC_INT_CD) { 2729 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2730 dw_mci_handle_cd(host); 2731 } 2732 2733 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2734 mci_writel(host, RINTSTS, 2735 SDMMC_INT_SDIO(slot->sdio_id)); 2736 __dw_mci_enable_sdio_irq(slot, 0); 2737 sdio_signal_irq(slot->mmc); 2738 } 2739 2740 } 2741 2742 if (host->use_dma != TRANS_MODE_IDMAC) 2743 return IRQ_HANDLED; 2744 2745 /* Handle IDMA interrupts */ 2746 if (host->dma_64bit_address == 1) { 2747 pending = mci_readl(host, IDSTS64); 2748 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2749 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2750 SDMMC_IDMAC_INT_RI); 2751 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2752 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2753 host->dma_ops->complete((void *)host); 2754 } 2755 } else { 2756 pending = mci_readl(host, IDSTS); 2757 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2758 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2759 SDMMC_IDMAC_INT_RI); 2760 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2761 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2762 host->dma_ops->complete((void *)host); 2763 } 2764 } 2765 2766 return IRQ_HANDLED; 2767 } 2768 2769 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) 2770 { 2771 struct dw_mci *host = slot->host; 2772 const struct dw_mci_drv_data *drv_data = host->drv_data; 2773 struct mmc_host *mmc = slot->mmc; 2774 int ctrl_id; 2775 2776 if (host->pdata->caps) 2777 mmc->caps = host->pdata->caps; 2778 2779 /* 2780 * Support MMC_CAP_ERASE by default. 2781 * It needs to use trim/discard/erase commands. 2782 */ 2783 mmc->caps |= MMC_CAP_ERASE; 2784 2785 if (host->pdata->pm_caps) 2786 mmc->pm_caps = host->pdata->pm_caps; 2787 2788 if (host->dev->of_node) { 2789 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2790 if (ctrl_id < 0) 2791 ctrl_id = 0; 2792 } else { 2793 ctrl_id = to_platform_device(host->dev)->id; 2794 } 2795 2796 if (drv_data && drv_data->caps) { 2797 if (ctrl_id >= drv_data->num_caps) { 2798 dev_err(host->dev, "invalid controller id %d\n", 2799 ctrl_id); 2800 return -EINVAL; 2801 } 2802 mmc->caps |= drv_data->caps[ctrl_id]; 2803 } 2804 2805 if (host->pdata->caps2) 2806 mmc->caps2 = host->pdata->caps2; 2807 2808 mmc->f_min = DW_MCI_FREQ_MIN; 2809 if (!mmc->f_max) 2810 mmc->f_max = DW_MCI_FREQ_MAX; 2811 2812 /* Process SDIO IRQs through the sdio_irq_work. */ 2813 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2814 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2815 2816 return 0; 2817 } 2818 2819 static int dw_mci_init_slot(struct dw_mci *host) 2820 { 2821 struct mmc_host *mmc; 2822 struct dw_mci_slot *slot; 2823 int ret; 2824 2825 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2826 if (!mmc) 2827 return -ENOMEM; 2828 2829 slot = mmc_priv(mmc); 2830 slot->id = 0; 2831 slot->sdio_id = host->sdio_id0 + slot->id; 2832 slot->mmc = mmc; 2833 slot->host = host; 2834 host->slot = slot; 2835 2836 mmc->ops = &dw_mci_ops; 2837 2838 /*if there are external regulators, get them*/ 2839 ret = mmc_regulator_get_supply(mmc); 2840 if (ret) 2841 goto err_host_allocated; 2842 2843 if (!mmc->ocr_avail) 2844 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2845 2846 ret = mmc_of_parse(mmc); 2847 if (ret) 2848 goto err_host_allocated; 2849 2850 ret = dw_mci_init_slot_caps(slot); 2851 if (ret) 2852 goto err_host_allocated; 2853 2854 /* Useful defaults if platform data is unset. */ 2855 if (host->use_dma == TRANS_MODE_IDMAC) { 2856 mmc->max_segs = host->ring_size; 2857 mmc->max_blk_size = 65535; 2858 mmc->max_seg_size = 0x1000; 2859 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2860 mmc->max_blk_count = mmc->max_req_size / 512; 2861 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2862 mmc->max_segs = 64; 2863 mmc->max_blk_size = 65535; 2864 mmc->max_blk_count = 65535; 2865 mmc->max_req_size = 2866 mmc->max_blk_size * mmc->max_blk_count; 2867 mmc->max_seg_size = mmc->max_req_size; 2868 } else { 2869 /* TRANS_MODE_PIO */ 2870 mmc->max_segs = 64; 2871 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2872 mmc->max_blk_count = 512; 2873 mmc->max_req_size = mmc->max_blk_size * 2874 mmc->max_blk_count; 2875 mmc->max_seg_size = mmc->max_req_size; 2876 } 2877 2878 dw_mci_get_cd(mmc); 2879 2880 ret = mmc_add_host(mmc); 2881 if (ret) 2882 goto err_host_allocated; 2883 2884 #if defined(CONFIG_DEBUG_FS) 2885 dw_mci_init_debugfs(slot); 2886 #endif 2887 2888 return 0; 2889 2890 err_host_allocated: 2891 mmc_free_host(mmc); 2892 return ret; 2893 } 2894 2895 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2896 { 2897 /* Debugfs stuff is cleaned up by mmc core */ 2898 mmc_remove_host(slot->mmc); 2899 slot->host->slot = NULL; 2900 mmc_free_host(slot->mmc); 2901 } 2902 2903 static void dw_mci_init_dma(struct dw_mci *host) 2904 { 2905 int addr_config; 2906 struct device *dev = host->dev; 2907 2908 /* 2909 * Check tansfer mode from HCON[17:16] 2910 * Clear the ambiguous description of dw_mmc databook: 2911 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2912 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2913 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2914 * 2b'11: Non DW DMA Interface -> pio only 2915 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2916 * simpler request/acknowledge handshake mechanism and both of them 2917 * are regarded as external dma master for dw_mmc. 2918 */ 2919 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2920 if (host->use_dma == DMA_INTERFACE_IDMA) { 2921 host->use_dma = TRANS_MODE_IDMAC; 2922 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2923 host->use_dma == DMA_INTERFACE_GDMA) { 2924 host->use_dma = TRANS_MODE_EDMAC; 2925 } else { 2926 goto no_dma; 2927 } 2928 2929 /* Determine which DMA interface to use */ 2930 if (host->use_dma == TRANS_MODE_IDMAC) { 2931 /* 2932 * Check ADDR_CONFIG bit in HCON to find 2933 * IDMAC address bus width 2934 */ 2935 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2936 2937 if (addr_config == 1) { 2938 /* host supports IDMAC in 64-bit address mode */ 2939 host->dma_64bit_address = 1; 2940 dev_info(host->dev, 2941 "IDMAC supports 64-bit address mode.\n"); 2942 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2943 dma_set_coherent_mask(host->dev, 2944 DMA_BIT_MASK(64)); 2945 } else { 2946 /* host supports IDMAC in 32-bit address mode */ 2947 host->dma_64bit_address = 0; 2948 dev_info(host->dev, 2949 "IDMAC supports 32-bit address mode.\n"); 2950 } 2951 2952 /* Alloc memory for sg translation */ 2953 host->sg_cpu = dmam_alloc_coherent(host->dev, 2954 DESC_RING_BUF_SZ, 2955 &host->sg_dma, GFP_KERNEL); 2956 if (!host->sg_cpu) { 2957 dev_err(host->dev, 2958 "%s: could not alloc DMA memory\n", 2959 __func__); 2960 goto no_dma; 2961 } 2962 2963 host->dma_ops = &dw_mci_idmac_ops; 2964 dev_info(host->dev, "Using internal DMA controller.\n"); 2965 } else { 2966 /* TRANS_MODE_EDMAC: check dma bindings again */ 2967 if ((device_property_read_string_array(dev, "dma-names", 2968 NULL, 0) < 0) || 2969 !device_property_present(dev, "dmas")) { 2970 goto no_dma; 2971 } 2972 host->dma_ops = &dw_mci_edmac_ops; 2973 dev_info(host->dev, "Using external DMA controller.\n"); 2974 } 2975 2976 if (host->dma_ops->init && host->dma_ops->start && 2977 host->dma_ops->stop && host->dma_ops->cleanup) { 2978 if (host->dma_ops->init(host)) { 2979 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2980 __func__); 2981 goto no_dma; 2982 } 2983 } else { 2984 dev_err(host->dev, "DMA initialization not found.\n"); 2985 goto no_dma; 2986 } 2987 2988 return; 2989 2990 no_dma: 2991 dev_info(host->dev, "Using PIO mode.\n"); 2992 host->use_dma = TRANS_MODE_PIO; 2993 } 2994 2995 static void dw_mci_cmd11_timer(struct timer_list *t) 2996 { 2997 struct dw_mci *host = from_timer(host, t, cmd11_timer); 2998 2999 if (host->state != STATE_SENDING_CMD11) { 3000 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 3001 return; 3002 } 3003 3004 host->cmd_status = SDMMC_INT_RTO; 3005 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3006 tasklet_schedule(&host->tasklet); 3007 } 3008 3009 static void dw_mci_cto_timer(struct timer_list *t) 3010 { 3011 struct dw_mci *host = from_timer(host, t, cto_timer); 3012 unsigned long irqflags; 3013 u32 pending; 3014 3015 spin_lock_irqsave(&host->irq_lock, irqflags); 3016 3017 /* 3018 * If somehow we have very bad interrupt latency it's remotely possible 3019 * that the timer could fire while the interrupt is still pending or 3020 * while the interrupt is midway through running. Let's be paranoid 3021 * and detect those two cases. Note that this is paranoia is somewhat 3022 * justified because in this function we don't actually cancel the 3023 * pending command in the controller--we just assume it will never come. 3024 */ 3025 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3026 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 3027 /* The interrupt should fire; no need to act but we can warn */ 3028 dev_warn(host->dev, "Unexpected interrupt latency\n"); 3029 goto exit; 3030 } 3031 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 3032 /* Presumably interrupt handler couldn't delete the timer */ 3033 dev_warn(host->dev, "CTO timeout when already completed\n"); 3034 goto exit; 3035 } 3036 3037 /* 3038 * Continued paranoia to make sure we're in the state we expect. 3039 * This paranoia isn't really justified but it seems good to be safe. 3040 */ 3041 switch (host->state) { 3042 case STATE_SENDING_CMD11: 3043 case STATE_SENDING_CMD: 3044 case STATE_SENDING_STOP: 3045 /* 3046 * If CMD_DONE interrupt does NOT come in sending command 3047 * state, we should notify the driver to terminate current 3048 * transfer and report a command timeout to the core. 3049 */ 3050 host->cmd_status = SDMMC_INT_RTO; 3051 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3052 tasklet_schedule(&host->tasklet); 3053 break; 3054 default: 3055 dev_warn(host->dev, "Unexpected command timeout, state %d\n", 3056 host->state); 3057 break; 3058 } 3059 3060 exit: 3061 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3062 } 3063 3064 static void dw_mci_dto_timer(struct timer_list *t) 3065 { 3066 struct dw_mci *host = from_timer(host, t, dto_timer); 3067 unsigned long irqflags; 3068 u32 pending; 3069 3070 spin_lock_irqsave(&host->irq_lock, irqflags); 3071 3072 /* 3073 * The DTO timer is much longer than the CTO timer, so it's even less 3074 * likely that we'll these cases, but it pays to be paranoid. 3075 */ 3076 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3077 if (pending & SDMMC_INT_DATA_OVER) { 3078 /* The interrupt should fire; no need to act but we can warn */ 3079 dev_warn(host->dev, "Unexpected data interrupt latency\n"); 3080 goto exit; 3081 } 3082 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 3083 /* Presumably interrupt handler couldn't delete the timer */ 3084 dev_warn(host->dev, "DTO timeout when already completed\n"); 3085 goto exit; 3086 } 3087 3088 /* 3089 * Continued paranoia to make sure we're in the state we expect. 3090 * This paranoia isn't really justified but it seems good to be safe. 3091 */ 3092 switch (host->state) { 3093 case STATE_SENDING_DATA: 3094 case STATE_DATA_BUSY: 3095 /* 3096 * If DTO interrupt does NOT come in sending data state, 3097 * we should notify the driver to terminate current transfer 3098 * and report a data timeout to the core. 3099 */ 3100 host->data_status = SDMMC_INT_DRTO; 3101 set_bit(EVENT_DATA_ERROR, &host->pending_events); 3102 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 3103 tasklet_schedule(&host->tasklet); 3104 break; 3105 default: 3106 dev_warn(host->dev, "Unexpected data timeout, state %d\n", 3107 host->state); 3108 break; 3109 } 3110 3111 exit: 3112 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3113 } 3114 3115 #ifdef CONFIG_OF 3116 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3117 { 3118 struct dw_mci_board *pdata; 3119 struct device *dev = host->dev; 3120 const struct dw_mci_drv_data *drv_data = host->drv_data; 3121 int ret; 3122 u32 clock_frequency; 3123 3124 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3125 if (!pdata) 3126 return ERR_PTR(-ENOMEM); 3127 3128 /* find reset controller when exist */ 3129 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3130 if (IS_ERR(pdata->rstc)) { 3131 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3132 return ERR_PTR(-EPROBE_DEFER); 3133 } 3134 3135 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 3136 dev_info(dev, 3137 "fifo-depth property not found, using value of FIFOTH register as default\n"); 3138 3139 device_property_read_u32(dev, "card-detect-delay", 3140 &pdata->detect_delay_ms); 3141 3142 device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3143 3144 if (device_property_present(dev, "fifo-watermark-aligned")) 3145 host->wm_aligned = true; 3146 3147 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 3148 pdata->bus_hz = clock_frequency; 3149 3150 if (drv_data && drv_data->parse_dt) { 3151 ret = drv_data->parse_dt(host); 3152 if (ret) 3153 return ERR_PTR(ret); 3154 } 3155 3156 return pdata; 3157 } 3158 3159 #else /* CONFIG_OF */ 3160 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3161 { 3162 return ERR_PTR(-EINVAL); 3163 } 3164 #endif /* CONFIG_OF */ 3165 3166 static void dw_mci_enable_cd(struct dw_mci *host) 3167 { 3168 unsigned long irqflags; 3169 u32 temp; 3170 3171 /* 3172 * No need for CD if all slots have a non-error GPIO 3173 * as well as broken card detection is found. 3174 */ 3175 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3176 return; 3177 3178 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3179 spin_lock_irqsave(&host->irq_lock, irqflags); 3180 temp = mci_readl(host, INTMASK); 3181 temp |= SDMMC_INT_CD; 3182 mci_writel(host, INTMASK, temp); 3183 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3184 } 3185 } 3186 3187 int dw_mci_probe(struct dw_mci *host) 3188 { 3189 const struct dw_mci_drv_data *drv_data = host->drv_data; 3190 int width, i, ret = 0; 3191 u32 fifo_size; 3192 3193 if (!host->pdata) { 3194 host->pdata = dw_mci_parse_dt(host); 3195 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3196 return -EPROBE_DEFER; 3197 } else if (IS_ERR(host->pdata)) { 3198 dev_err(host->dev, "platform data not available\n"); 3199 return -EINVAL; 3200 } 3201 } 3202 3203 host->biu_clk = devm_clk_get(host->dev, "biu"); 3204 if (IS_ERR(host->biu_clk)) { 3205 dev_dbg(host->dev, "biu clock not available\n"); 3206 } else { 3207 ret = clk_prepare_enable(host->biu_clk); 3208 if (ret) { 3209 dev_err(host->dev, "failed to enable biu clock\n"); 3210 return ret; 3211 } 3212 } 3213 3214 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3215 if (IS_ERR(host->ciu_clk)) { 3216 dev_dbg(host->dev, "ciu clock not available\n"); 3217 host->bus_hz = host->pdata->bus_hz; 3218 } else { 3219 ret = clk_prepare_enable(host->ciu_clk); 3220 if (ret) { 3221 dev_err(host->dev, "failed to enable ciu clock\n"); 3222 goto err_clk_biu; 3223 } 3224 3225 if (host->pdata->bus_hz) { 3226 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3227 if (ret) 3228 dev_warn(host->dev, 3229 "Unable to set bus rate to %uHz\n", 3230 host->pdata->bus_hz); 3231 } 3232 host->bus_hz = clk_get_rate(host->ciu_clk); 3233 } 3234 3235 if (!host->bus_hz) { 3236 dev_err(host->dev, 3237 "Platform data must supply bus speed\n"); 3238 ret = -ENODEV; 3239 goto err_clk_ciu; 3240 } 3241 3242 if (!IS_ERR(host->pdata->rstc)) { 3243 reset_control_assert(host->pdata->rstc); 3244 usleep_range(10, 50); 3245 reset_control_deassert(host->pdata->rstc); 3246 } 3247 3248 if (drv_data && drv_data->init) { 3249 ret = drv_data->init(host); 3250 if (ret) { 3251 dev_err(host->dev, 3252 "implementation specific init failed\n"); 3253 goto err_clk_ciu; 3254 } 3255 } 3256 3257 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 3258 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 3259 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 3260 3261 spin_lock_init(&host->lock); 3262 spin_lock_init(&host->irq_lock); 3263 INIT_LIST_HEAD(&host->queue); 3264 3265 /* 3266 * Get the host data width - this assumes that HCON has been set with 3267 * the correct values. 3268 */ 3269 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3270 if (!i) { 3271 host->push_data = dw_mci_push_data16; 3272 host->pull_data = dw_mci_pull_data16; 3273 width = 16; 3274 host->data_shift = 1; 3275 } else if (i == 2) { 3276 host->push_data = dw_mci_push_data64; 3277 host->pull_data = dw_mci_pull_data64; 3278 width = 64; 3279 host->data_shift = 3; 3280 } else { 3281 /* Check for a reserved value, and warn if it is */ 3282 WARN((i != 1), 3283 "HCON reports a reserved host data width!\n" 3284 "Defaulting to 32-bit access.\n"); 3285 host->push_data = dw_mci_push_data32; 3286 host->pull_data = dw_mci_pull_data32; 3287 width = 32; 3288 host->data_shift = 2; 3289 } 3290 3291 /* Reset all blocks */ 3292 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3293 ret = -ENODEV; 3294 goto err_clk_ciu; 3295 } 3296 3297 host->dma_ops = host->pdata->dma_ops; 3298 dw_mci_init_dma(host); 3299 3300 /* Clear the interrupts for the host controller */ 3301 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3302 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3303 3304 /* Put in max timeout */ 3305 mci_writel(host, TMOUT, 0xFFFFFFFF); 3306 3307 /* 3308 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3309 * Tx Mark = fifo_size / 2 DMA Size = 8 3310 */ 3311 if (!host->pdata->fifo_depth) { 3312 /* 3313 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3314 * have been overwritten by the bootloader, just like we're 3315 * about to do, so if you know the value for your hardware, you 3316 * should put it in the platform data. 3317 */ 3318 fifo_size = mci_readl(host, FIFOTH); 3319 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3320 } else { 3321 fifo_size = host->pdata->fifo_depth; 3322 } 3323 host->fifo_depth = fifo_size; 3324 host->fifoth_val = 3325 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3326 mci_writel(host, FIFOTH, host->fifoth_val); 3327 3328 /* disable clock to CIU */ 3329 mci_writel(host, CLKENA, 0); 3330 mci_writel(host, CLKSRC, 0); 3331 3332 /* 3333 * In 2.40a spec, Data offset is changed. 3334 * Need to check the version-id and set data-offset for DATA register. 3335 */ 3336 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3337 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3338 3339 if (host->data_addr_override) 3340 host->fifo_reg = host->regs + host->data_addr_override; 3341 else if (host->verid < DW_MMC_240A) 3342 host->fifo_reg = host->regs + DATA_OFFSET; 3343 else 3344 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3345 3346 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3347 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3348 host->irq_flags, "dw-mci", host); 3349 if (ret) 3350 goto err_dmaunmap; 3351 3352 /* 3353 * Enable interrupts for command done, data over, data empty, 3354 * receive ready and error such as transmit, receive timeout, crc error 3355 */ 3356 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3357 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3358 DW_MCI_ERROR_FLAGS); 3359 /* Enable mci interrupt */ 3360 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3361 3362 dev_info(host->dev, 3363 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3364 host->irq, width, fifo_size); 3365 3366 /* We need at least one slot to succeed */ 3367 ret = dw_mci_init_slot(host); 3368 if (ret) { 3369 dev_dbg(host->dev, "slot %d init failed\n", i); 3370 goto err_dmaunmap; 3371 } 3372 3373 /* Now that slots are all setup, we can enable card detect */ 3374 dw_mci_enable_cd(host); 3375 3376 return 0; 3377 3378 err_dmaunmap: 3379 if (host->use_dma && host->dma_ops->exit) 3380 host->dma_ops->exit(host); 3381 3382 if (!IS_ERR(host->pdata->rstc)) 3383 reset_control_assert(host->pdata->rstc); 3384 3385 err_clk_ciu: 3386 clk_disable_unprepare(host->ciu_clk); 3387 3388 err_clk_biu: 3389 clk_disable_unprepare(host->biu_clk); 3390 3391 return ret; 3392 } 3393 EXPORT_SYMBOL(dw_mci_probe); 3394 3395 void dw_mci_remove(struct dw_mci *host) 3396 { 3397 dev_dbg(host->dev, "remove slot\n"); 3398 if (host->slot) 3399 dw_mci_cleanup_slot(host->slot); 3400 3401 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3402 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3403 3404 /* disable clock to CIU */ 3405 mci_writel(host, CLKENA, 0); 3406 mci_writel(host, CLKSRC, 0); 3407 3408 if (host->use_dma && host->dma_ops->exit) 3409 host->dma_ops->exit(host); 3410 3411 if (!IS_ERR(host->pdata->rstc)) 3412 reset_control_assert(host->pdata->rstc); 3413 3414 clk_disable_unprepare(host->ciu_clk); 3415 clk_disable_unprepare(host->biu_clk); 3416 } 3417 EXPORT_SYMBOL(dw_mci_remove); 3418 3419 3420 3421 #ifdef CONFIG_PM 3422 int dw_mci_runtime_suspend(struct device *dev) 3423 { 3424 struct dw_mci *host = dev_get_drvdata(dev); 3425 3426 if (host->use_dma && host->dma_ops->exit) 3427 host->dma_ops->exit(host); 3428 3429 clk_disable_unprepare(host->ciu_clk); 3430 3431 if (host->slot && 3432 (mmc_can_gpio_cd(host->slot->mmc) || 3433 !mmc_card_is_removable(host->slot->mmc))) 3434 clk_disable_unprepare(host->biu_clk); 3435 3436 return 0; 3437 } 3438 EXPORT_SYMBOL(dw_mci_runtime_suspend); 3439 3440 int dw_mci_runtime_resume(struct device *dev) 3441 { 3442 int ret = 0; 3443 struct dw_mci *host = dev_get_drvdata(dev); 3444 3445 if (host->slot && 3446 (mmc_can_gpio_cd(host->slot->mmc) || 3447 !mmc_card_is_removable(host->slot->mmc))) { 3448 ret = clk_prepare_enable(host->biu_clk); 3449 if (ret) 3450 return ret; 3451 } 3452 3453 ret = clk_prepare_enable(host->ciu_clk); 3454 if (ret) 3455 goto err; 3456 3457 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3458 clk_disable_unprepare(host->ciu_clk); 3459 ret = -ENODEV; 3460 goto err; 3461 } 3462 3463 if (host->use_dma && host->dma_ops->init) 3464 host->dma_ops->init(host); 3465 3466 /* 3467 * Restore the initial value at FIFOTH register 3468 * And Invalidate the prev_blksz with zero 3469 */ 3470 mci_writel(host, FIFOTH, host->fifoth_val); 3471 host->prev_blksz = 0; 3472 3473 /* Put in max timeout */ 3474 mci_writel(host, TMOUT, 0xFFFFFFFF); 3475 3476 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3477 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3478 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3479 DW_MCI_ERROR_FLAGS); 3480 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3481 3482 3483 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3484 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3485 3486 /* Force setup bus to guarantee available clock output */ 3487 dw_mci_setup_bus(host->slot, true); 3488 3489 /* Now that slots are all setup, we can enable card detect */ 3490 dw_mci_enable_cd(host); 3491 3492 return 0; 3493 3494 err: 3495 if (host->slot && 3496 (mmc_can_gpio_cd(host->slot->mmc) || 3497 !mmc_card_is_removable(host->slot->mmc))) 3498 clk_disable_unprepare(host->biu_clk); 3499 3500 return ret; 3501 } 3502 EXPORT_SYMBOL(dw_mci_runtime_resume); 3503 #endif /* CONFIG_PM */ 3504 3505 static int __init dw_mci_init(void) 3506 { 3507 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3508 return 0; 3509 } 3510 3511 static void __exit dw_mci_exit(void) 3512 { 3513 } 3514 3515 module_init(dw_mci_init); 3516 module_exit(dw_mci_exit); 3517 3518 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3519 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3520 MODULE_AUTHOR("Imagination Technologies Ltd"); 3521 MODULE_LICENSE("GPL v2"); 3522