1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/iopoll.h> 23 #include <linux/ioport.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/seq_file.h> 28 #include <linux/slab.h> 29 #include <linux/stat.h> 30 #include <linux/delay.h> 31 #include <linux/irq.h> 32 #include <linux/mmc/card.h> 33 #include <linux/mmc/host.h> 34 #include <linux/mmc/mmc.h> 35 #include <linux/mmc/sd.h> 36 #include <linux/mmc/sdio.h> 37 #include <linux/bitops.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/of.h> 40 #include <linux/of_gpio.h> 41 #include <linux/mmc/slot-gpio.h> 42 43 #include "dw_mmc.h" 44 45 /* Common flag combinations */ 46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 47 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 48 SDMMC_INT_EBE | SDMMC_INT_HLE) 49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 52 DW_MCI_CMD_ERROR_FLAGS) 53 #define DW_MCI_SEND_STATUS 1 54 #define DW_MCI_RECV_STATUS 2 55 #define DW_MCI_DMA_THRESHOLD 16 56 57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 59 60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63 SDMMC_IDMAC_INT_TI) 64 65 #define DESC_RING_BUF_SZ PAGE_SIZE 66 67 struct idmac_desc_64addr { 68 u32 des0; /* Control Descriptor */ 69 #define IDMAC_OWN_CLR64(x) \ 70 !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 71 72 u32 des1; /* Reserved */ 73 74 u32 des2; /*Buffer sizes */ 75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 78 79 u32 des3; /* Reserved */ 80 81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 83 84 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 85 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 86 }; 87 88 struct idmac_desc { 89 __le32 des0; /* Control Descriptor */ 90 #define IDMAC_DES0_DIC BIT(1) 91 #define IDMAC_DES0_LD BIT(2) 92 #define IDMAC_DES0_FD BIT(3) 93 #define IDMAC_DES0_CH BIT(4) 94 #define IDMAC_DES0_ER BIT(5) 95 #define IDMAC_DES0_CES BIT(30) 96 #define IDMAC_DES0_OWN BIT(31) 97 98 __le32 des1; /* Buffer sizes */ 99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 101 102 __le32 des2; /* buffer 1 physical address */ 103 104 __le32 des3; /* buffer 2 physical address */ 105 }; 106 107 /* Each descriptor can transfer up to 4KB of data in chained mode */ 108 #define DW_MCI_DESC_DATA_LENGTH 0x1000 109 110 #if defined(CONFIG_DEBUG_FS) 111 static int dw_mci_req_show(struct seq_file *s, void *v) 112 { 113 struct dw_mci_slot *slot = s->private; 114 struct mmc_request *mrq; 115 struct mmc_command *cmd; 116 struct mmc_command *stop; 117 struct mmc_data *data; 118 119 /* Make sure we get a consistent snapshot */ 120 spin_lock_bh(&slot->host->lock); 121 mrq = slot->mrq; 122 123 if (mrq) { 124 cmd = mrq->cmd; 125 data = mrq->data; 126 stop = mrq->stop; 127 128 if (cmd) 129 seq_printf(s, 130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 131 cmd->opcode, cmd->arg, cmd->flags, 132 cmd->resp[0], cmd->resp[1], cmd->resp[2], 133 cmd->resp[2], cmd->error); 134 if (data) 135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 136 data->bytes_xfered, data->blocks, 137 data->blksz, data->flags, data->error); 138 if (stop) 139 seq_printf(s, 140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 141 stop->opcode, stop->arg, stop->flags, 142 stop->resp[0], stop->resp[1], stop->resp[2], 143 stop->resp[2], stop->error); 144 } 145 146 spin_unlock_bh(&slot->host->lock); 147 148 return 0; 149 } 150 151 static int dw_mci_req_open(struct inode *inode, struct file *file) 152 { 153 return single_open(file, dw_mci_req_show, inode->i_private); 154 } 155 156 static const struct file_operations dw_mci_req_fops = { 157 .owner = THIS_MODULE, 158 .open = dw_mci_req_open, 159 .read = seq_read, 160 .llseek = seq_lseek, 161 .release = single_release, 162 }; 163 164 static int dw_mci_regs_show(struct seq_file *s, void *v) 165 { 166 struct dw_mci *host = s->private; 167 168 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 169 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 170 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 171 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 172 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 173 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 174 175 return 0; 176 } 177 178 static int dw_mci_regs_open(struct inode *inode, struct file *file) 179 { 180 return single_open(file, dw_mci_regs_show, inode->i_private); 181 } 182 183 static const struct file_operations dw_mci_regs_fops = { 184 .owner = THIS_MODULE, 185 .open = dw_mci_regs_open, 186 .read = seq_read, 187 .llseek = seq_lseek, 188 .release = single_release, 189 }; 190 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 192 { 193 struct mmc_host *mmc = slot->mmc; 194 struct dw_mci *host = slot->host; 195 struct dentry *root; 196 struct dentry *node; 197 198 root = mmc->debugfs_root; 199 if (!root) 200 return; 201 202 node = debugfs_create_file("regs", S_IRUSR, root, host, 203 &dw_mci_regs_fops); 204 if (!node) 205 goto err; 206 207 node = debugfs_create_file("req", S_IRUSR, root, slot, 208 &dw_mci_req_fops); 209 if (!node) 210 goto err; 211 212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 213 if (!node) 214 goto err; 215 216 node = debugfs_create_x32("pending_events", S_IRUSR, root, 217 (u32 *)&host->pending_events); 218 if (!node) 219 goto err; 220 221 node = debugfs_create_x32("completed_events", S_IRUSR, root, 222 (u32 *)&host->completed_events); 223 if (!node) 224 goto err; 225 226 return; 227 228 err: 229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 230 } 231 #endif /* defined(CONFIG_DEBUG_FS) */ 232 233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 234 { 235 u32 ctrl; 236 237 ctrl = mci_readl(host, CTRL); 238 ctrl |= reset; 239 mci_writel(host, CTRL, ctrl); 240 241 /* wait till resets clear */ 242 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 243 !(ctrl & reset), 244 1, 500 * USEC_PER_MSEC)) { 245 dev_err(host->dev, 246 "Timeout resetting block (ctrl reset %#x)\n", 247 ctrl & reset); 248 return false; 249 } 250 251 return true; 252 } 253 254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 255 { 256 u32 status; 257 258 /* 259 * Databook says that before issuing a new data transfer command 260 * we need to check to see if the card is busy. Data transfer commands 261 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 262 * 263 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 264 * expected. 265 */ 266 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 267 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 268 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 269 status, 270 !(status & SDMMC_STATUS_BUSY), 271 10, 500 * USEC_PER_MSEC)) 272 dev_err(host->dev, "Busy; trying anyway\n"); 273 } 274 } 275 276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 277 { 278 struct dw_mci *host = slot->host; 279 unsigned int cmd_status = 0; 280 281 mci_writel(host, CMDARG, arg); 282 wmb(); /* drain writebuffer */ 283 dw_mci_wait_while_busy(host, cmd); 284 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 285 286 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 287 !(cmd_status & SDMMC_CMD_START), 288 1, 500 * USEC_PER_MSEC)) 289 dev_err(&slot->mmc->class_dev, 290 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 291 cmd, arg, cmd_status); 292 } 293 294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 295 { 296 struct dw_mci_slot *slot = mmc_priv(mmc); 297 struct dw_mci *host = slot->host; 298 u32 cmdr; 299 300 cmd->error = -EINPROGRESS; 301 cmdr = cmd->opcode; 302 303 if (cmd->opcode == MMC_STOP_TRANSMISSION || 304 cmd->opcode == MMC_GO_IDLE_STATE || 305 cmd->opcode == MMC_GO_INACTIVE_STATE || 306 (cmd->opcode == SD_IO_RW_DIRECT && 307 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 308 cmdr |= SDMMC_CMD_STOP; 309 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 310 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 311 312 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 313 u32 clk_en_a; 314 315 /* Special bit makes CMD11 not die */ 316 cmdr |= SDMMC_CMD_VOLT_SWITCH; 317 318 /* Change state to continue to handle CMD11 weirdness */ 319 WARN_ON(slot->host->state != STATE_SENDING_CMD); 320 slot->host->state = STATE_SENDING_CMD11; 321 322 /* 323 * We need to disable low power mode (automatic clock stop) 324 * while doing voltage switch so we don't confuse the card, 325 * since stopping the clock is a specific part of the UHS 326 * voltage change dance. 327 * 328 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 329 * unconditionally turned back on in dw_mci_setup_bus() if it's 330 * ever called with a non-zero clock. That shouldn't happen 331 * until the voltage change is all done. 332 */ 333 clk_en_a = mci_readl(host, CLKENA); 334 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 335 mci_writel(host, CLKENA, clk_en_a); 336 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 337 SDMMC_CMD_PRV_DAT_WAIT, 0); 338 } 339 340 if (cmd->flags & MMC_RSP_PRESENT) { 341 /* We expect a response, so set this bit */ 342 cmdr |= SDMMC_CMD_RESP_EXP; 343 if (cmd->flags & MMC_RSP_136) 344 cmdr |= SDMMC_CMD_RESP_LONG; 345 } 346 347 if (cmd->flags & MMC_RSP_CRC) 348 cmdr |= SDMMC_CMD_RESP_CRC; 349 350 if (cmd->data) { 351 cmdr |= SDMMC_CMD_DAT_EXP; 352 if (cmd->data->flags & MMC_DATA_WRITE) 353 cmdr |= SDMMC_CMD_DAT_WR; 354 } 355 356 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 357 cmdr |= SDMMC_CMD_USE_HOLD_REG; 358 359 return cmdr; 360 } 361 362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 363 { 364 struct mmc_command *stop; 365 u32 cmdr; 366 367 if (!cmd->data) 368 return 0; 369 370 stop = &host->stop_abort; 371 cmdr = cmd->opcode; 372 memset(stop, 0, sizeof(struct mmc_command)); 373 374 if (cmdr == MMC_READ_SINGLE_BLOCK || 375 cmdr == MMC_READ_MULTIPLE_BLOCK || 376 cmdr == MMC_WRITE_BLOCK || 377 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 378 cmdr == MMC_SEND_TUNING_BLOCK || 379 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 380 stop->opcode = MMC_STOP_TRANSMISSION; 381 stop->arg = 0; 382 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 383 } else if (cmdr == SD_IO_RW_EXTENDED) { 384 stop->opcode = SD_IO_RW_DIRECT; 385 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 386 ((cmd->arg >> 28) & 0x7); 387 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 388 } else { 389 return 0; 390 } 391 392 cmdr = stop->opcode | SDMMC_CMD_STOP | 393 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 394 395 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags)) 396 cmdr |= SDMMC_CMD_USE_HOLD_REG; 397 398 return cmdr; 399 } 400 401 static void dw_mci_start_command(struct dw_mci *host, 402 struct mmc_command *cmd, u32 cmd_flags) 403 { 404 host->cmd = cmd; 405 dev_vdbg(host->dev, 406 "start command: ARGR=0x%08x CMDR=0x%08x\n", 407 cmd->arg, cmd_flags); 408 409 mci_writel(host, CMDARG, cmd->arg); 410 wmb(); /* drain writebuffer */ 411 dw_mci_wait_while_busy(host, cmd_flags); 412 413 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 414 } 415 416 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 417 { 418 struct mmc_command *stop = &host->stop_abort; 419 420 dw_mci_start_command(host, stop, host->stop_cmdr); 421 } 422 423 /* DMA interface functions */ 424 static void dw_mci_stop_dma(struct dw_mci *host) 425 { 426 if (host->using_dma) { 427 host->dma_ops->stop(host); 428 host->dma_ops->cleanup(host); 429 } 430 431 /* Data transfer was stopped by the interrupt handler */ 432 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 433 } 434 435 static void dw_mci_dma_cleanup(struct dw_mci *host) 436 { 437 struct mmc_data *data = host->data; 438 439 if (data && data->host_cookie == COOKIE_MAPPED) { 440 dma_unmap_sg(host->dev, 441 data->sg, 442 data->sg_len, 443 mmc_get_dma_dir(data)); 444 data->host_cookie = COOKIE_UNMAPPED; 445 } 446 } 447 448 static void dw_mci_idmac_reset(struct dw_mci *host) 449 { 450 u32 bmod = mci_readl(host, BMOD); 451 /* Software reset of DMA */ 452 bmod |= SDMMC_IDMAC_SWRESET; 453 mci_writel(host, BMOD, bmod); 454 } 455 456 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 457 { 458 u32 temp; 459 460 /* Disable and reset the IDMAC interface */ 461 temp = mci_readl(host, CTRL); 462 temp &= ~SDMMC_CTRL_USE_IDMAC; 463 temp |= SDMMC_CTRL_DMA_RESET; 464 mci_writel(host, CTRL, temp); 465 466 /* Stop the IDMAC running */ 467 temp = mci_readl(host, BMOD); 468 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 469 temp |= SDMMC_IDMAC_SWRESET; 470 mci_writel(host, BMOD, temp); 471 } 472 473 static void dw_mci_dmac_complete_dma(void *arg) 474 { 475 struct dw_mci *host = arg; 476 struct mmc_data *data = host->data; 477 478 dev_vdbg(host->dev, "DMA complete\n"); 479 480 if ((host->use_dma == TRANS_MODE_EDMAC) && 481 data && (data->flags & MMC_DATA_READ)) 482 /* Invalidate cache after read */ 483 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc), 484 data->sg, 485 data->sg_len, 486 DMA_FROM_DEVICE); 487 488 host->dma_ops->cleanup(host); 489 490 /* 491 * If the card was removed, data will be NULL. No point in trying to 492 * send the stop command or waiting for NBUSY in this case. 493 */ 494 if (data) { 495 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 496 tasklet_schedule(&host->tasklet); 497 } 498 } 499 500 static int dw_mci_idmac_init(struct dw_mci *host) 501 { 502 int i; 503 504 if (host->dma_64bit_address == 1) { 505 struct idmac_desc_64addr *p; 506 /* Number of descriptors in the ring buffer */ 507 host->ring_size = 508 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 509 510 /* Forward link the descriptor list */ 511 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 512 i++, p++) { 513 p->des6 = (host->sg_dma + 514 (sizeof(struct idmac_desc_64addr) * 515 (i + 1))) & 0xffffffff; 516 517 p->des7 = (u64)(host->sg_dma + 518 (sizeof(struct idmac_desc_64addr) * 519 (i + 1))) >> 32; 520 /* Initialize reserved and buffer size fields to "0" */ 521 p->des1 = 0; 522 p->des2 = 0; 523 p->des3 = 0; 524 } 525 526 /* Set the last descriptor as the end-of-ring descriptor */ 527 p->des6 = host->sg_dma & 0xffffffff; 528 p->des7 = (u64)host->sg_dma >> 32; 529 p->des0 = IDMAC_DES0_ER; 530 531 } else { 532 struct idmac_desc *p; 533 /* Number of descriptors in the ring buffer */ 534 host->ring_size = 535 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 536 537 /* Forward link the descriptor list */ 538 for (i = 0, p = host->sg_cpu; 539 i < host->ring_size - 1; 540 i++, p++) { 541 p->des3 = cpu_to_le32(host->sg_dma + 542 (sizeof(struct idmac_desc) * (i + 1))); 543 p->des1 = 0; 544 } 545 546 /* Set the last descriptor as the end-of-ring descriptor */ 547 p->des3 = cpu_to_le32(host->sg_dma); 548 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 549 } 550 551 dw_mci_idmac_reset(host); 552 553 if (host->dma_64bit_address == 1) { 554 /* Mask out interrupts - get Tx & Rx complete only */ 555 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 556 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 557 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 558 559 /* Set the descriptor base address */ 560 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 561 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 562 563 } else { 564 /* Mask out interrupts - get Tx & Rx complete only */ 565 mci_writel(host, IDSTS, IDMAC_INT_CLR); 566 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 567 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 568 569 /* Set the descriptor base address */ 570 mci_writel(host, DBADDR, host->sg_dma); 571 } 572 573 return 0; 574 } 575 576 static inline int dw_mci_prepare_desc64(struct dw_mci *host, 577 struct mmc_data *data, 578 unsigned int sg_len) 579 { 580 unsigned int desc_len; 581 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 582 u32 val; 583 int i; 584 585 desc_first = desc_last = desc = host->sg_cpu; 586 587 for (i = 0; i < sg_len; i++) { 588 unsigned int length = sg_dma_len(&data->sg[i]); 589 590 u64 mem_addr = sg_dma_address(&data->sg[i]); 591 592 for ( ; length ; desc++) { 593 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 594 length : DW_MCI_DESC_DATA_LENGTH; 595 596 length -= desc_len; 597 598 /* 599 * Wait for the former clear OWN bit operation 600 * of IDMAC to make sure that this descriptor 601 * isn't still owned by IDMAC as IDMAC's write 602 * ops and CPU's read ops are asynchronous. 603 */ 604 if (readl_poll_timeout_atomic(&desc->des0, val, 605 !(val & IDMAC_DES0_OWN), 606 10, 100 * USEC_PER_MSEC)) 607 goto err_own_bit; 608 609 /* 610 * Set the OWN bit and disable interrupts 611 * for this descriptor 612 */ 613 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 614 IDMAC_DES0_CH; 615 616 /* Buffer length */ 617 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 618 619 /* Physical address to DMA to/from */ 620 desc->des4 = mem_addr & 0xffffffff; 621 desc->des5 = mem_addr >> 32; 622 623 /* Update physical address for the next desc */ 624 mem_addr += desc_len; 625 626 /* Save pointer to the last descriptor */ 627 desc_last = desc; 628 } 629 } 630 631 /* Set first descriptor */ 632 desc_first->des0 |= IDMAC_DES0_FD; 633 634 /* Set last descriptor */ 635 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 636 desc_last->des0 |= IDMAC_DES0_LD; 637 638 return 0; 639 err_own_bit: 640 /* restore the descriptor chain as it's polluted */ 641 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 642 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 643 dw_mci_idmac_init(host); 644 return -EINVAL; 645 } 646 647 648 static inline int dw_mci_prepare_desc32(struct dw_mci *host, 649 struct mmc_data *data, 650 unsigned int sg_len) 651 { 652 unsigned int desc_len; 653 struct idmac_desc *desc_first, *desc_last, *desc; 654 u32 val; 655 int i; 656 657 desc_first = desc_last = desc = host->sg_cpu; 658 659 for (i = 0; i < sg_len; i++) { 660 unsigned int length = sg_dma_len(&data->sg[i]); 661 662 u32 mem_addr = sg_dma_address(&data->sg[i]); 663 664 for ( ; length ; desc++) { 665 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 666 length : DW_MCI_DESC_DATA_LENGTH; 667 668 length -= desc_len; 669 670 /* 671 * Wait for the former clear OWN bit operation 672 * of IDMAC to make sure that this descriptor 673 * isn't still owned by IDMAC as IDMAC's write 674 * ops and CPU's read ops are asynchronous. 675 */ 676 if (readl_poll_timeout_atomic(&desc->des0, val, 677 IDMAC_OWN_CLR64(val), 678 10, 679 100 * USEC_PER_MSEC)) 680 goto err_own_bit; 681 682 /* 683 * Set the OWN bit and disable interrupts 684 * for this descriptor 685 */ 686 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 687 IDMAC_DES0_DIC | 688 IDMAC_DES0_CH); 689 690 /* Buffer length */ 691 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 692 693 /* Physical address to DMA to/from */ 694 desc->des2 = cpu_to_le32(mem_addr); 695 696 /* Update physical address for the next desc */ 697 mem_addr += desc_len; 698 699 /* Save pointer to the last descriptor */ 700 desc_last = desc; 701 } 702 } 703 704 /* Set first descriptor */ 705 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 706 707 /* Set last descriptor */ 708 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 709 IDMAC_DES0_DIC)); 710 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 711 712 return 0; 713 err_own_bit: 714 /* restore the descriptor chain as it's polluted */ 715 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 716 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 717 dw_mci_idmac_init(host); 718 return -EINVAL; 719 } 720 721 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 722 { 723 u32 temp; 724 int ret; 725 726 if (host->dma_64bit_address == 1) 727 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 728 else 729 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 730 731 if (ret) 732 goto out; 733 734 /* drain writebuffer */ 735 wmb(); 736 737 /* Make sure to reset DMA in case we did PIO before this */ 738 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 739 dw_mci_idmac_reset(host); 740 741 /* Select IDMAC interface */ 742 temp = mci_readl(host, CTRL); 743 temp |= SDMMC_CTRL_USE_IDMAC; 744 mci_writel(host, CTRL, temp); 745 746 /* drain writebuffer */ 747 wmb(); 748 749 /* Enable the IDMAC */ 750 temp = mci_readl(host, BMOD); 751 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 752 mci_writel(host, BMOD, temp); 753 754 /* Start it running */ 755 mci_writel(host, PLDMND, 1); 756 757 out: 758 return ret; 759 } 760 761 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 762 .init = dw_mci_idmac_init, 763 .start = dw_mci_idmac_start_dma, 764 .stop = dw_mci_idmac_stop_dma, 765 .complete = dw_mci_dmac_complete_dma, 766 .cleanup = dw_mci_dma_cleanup, 767 }; 768 769 static void dw_mci_edmac_stop_dma(struct dw_mci *host) 770 { 771 dmaengine_terminate_async(host->dms->ch); 772 } 773 774 static int dw_mci_edmac_start_dma(struct dw_mci *host, 775 unsigned int sg_len) 776 { 777 struct dma_slave_config cfg; 778 struct dma_async_tx_descriptor *desc = NULL; 779 struct scatterlist *sgl = host->data->sg; 780 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 781 u32 sg_elems = host->data->sg_len; 782 u32 fifoth_val; 783 u32 fifo_offset = host->fifo_reg - host->regs; 784 int ret = 0; 785 786 /* Set external dma config: burst size, burst width */ 787 cfg.dst_addr = host->phy_regs + fifo_offset; 788 cfg.src_addr = cfg.dst_addr; 789 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 790 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 791 792 /* Match burst msize with external dma config */ 793 fifoth_val = mci_readl(host, FIFOTH); 794 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 795 cfg.src_maxburst = cfg.dst_maxburst; 796 797 if (host->data->flags & MMC_DATA_WRITE) 798 cfg.direction = DMA_MEM_TO_DEV; 799 else 800 cfg.direction = DMA_DEV_TO_MEM; 801 802 ret = dmaengine_slave_config(host->dms->ch, &cfg); 803 if (ret) { 804 dev_err(host->dev, "Failed to config edmac.\n"); 805 return -EBUSY; 806 } 807 808 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 809 sg_len, cfg.direction, 810 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 811 if (!desc) { 812 dev_err(host->dev, "Can't prepare slave sg.\n"); 813 return -EBUSY; 814 } 815 816 /* Set dw_mci_dmac_complete_dma as callback */ 817 desc->callback = dw_mci_dmac_complete_dma; 818 desc->callback_param = (void *)host; 819 dmaengine_submit(desc); 820 821 /* Flush cache before write */ 822 if (host->data->flags & MMC_DATA_WRITE) 823 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl, 824 sg_elems, DMA_TO_DEVICE); 825 826 dma_async_issue_pending(host->dms->ch); 827 828 return 0; 829 } 830 831 static int dw_mci_edmac_init(struct dw_mci *host) 832 { 833 /* Request external dma channel */ 834 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 835 if (!host->dms) 836 return -ENOMEM; 837 838 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx"); 839 if (!host->dms->ch) { 840 dev_err(host->dev, "Failed to get external DMA channel.\n"); 841 kfree(host->dms); 842 host->dms = NULL; 843 return -ENXIO; 844 } 845 846 return 0; 847 } 848 849 static void dw_mci_edmac_exit(struct dw_mci *host) 850 { 851 if (host->dms) { 852 if (host->dms->ch) { 853 dma_release_channel(host->dms->ch); 854 host->dms->ch = NULL; 855 } 856 kfree(host->dms); 857 host->dms = NULL; 858 } 859 } 860 861 static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 862 .init = dw_mci_edmac_init, 863 .exit = dw_mci_edmac_exit, 864 .start = dw_mci_edmac_start_dma, 865 .stop = dw_mci_edmac_stop_dma, 866 .complete = dw_mci_dmac_complete_dma, 867 .cleanup = dw_mci_dma_cleanup, 868 }; 869 870 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 871 struct mmc_data *data, 872 int cookie) 873 { 874 struct scatterlist *sg; 875 unsigned int i, sg_len; 876 877 if (data->host_cookie == COOKIE_PRE_MAPPED) 878 return data->sg_len; 879 880 /* 881 * We don't do DMA on "complex" transfers, i.e. with 882 * non-word-aligned buffers or lengths. Also, we don't bother 883 * with all the DMA setup overhead for short transfers. 884 */ 885 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 886 return -EINVAL; 887 888 if (data->blksz & 3) 889 return -EINVAL; 890 891 for_each_sg(data->sg, sg, data->sg_len, i) { 892 if (sg->offset & 3 || sg->length & 3) 893 return -EINVAL; 894 } 895 896 sg_len = dma_map_sg(host->dev, 897 data->sg, 898 data->sg_len, 899 mmc_get_dma_dir(data)); 900 if (sg_len == 0) 901 return -EINVAL; 902 903 data->host_cookie = cookie; 904 905 return sg_len; 906 } 907 908 static void dw_mci_pre_req(struct mmc_host *mmc, 909 struct mmc_request *mrq) 910 { 911 struct dw_mci_slot *slot = mmc_priv(mmc); 912 struct mmc_data *data = mrq->data; 913 914 if (!slot->host->use_dma || !data) 915 return; 916 917 /* This data might be unmapped at this time */ 918 data->host_cookie = COOKIE_UNMAPPED; 919 920 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 921 COOKIE_PRE_MAPPED) < 0) 922 data->host_cookie = COOKIE_UNMAPPED; 923 } 924 925 static void dw_mci_post_req(struct mmc_host *mmc, 926 struct mmc_request *mrq, 927 int err) 928 { 929 struct dw_mci_slot *slot = mmc_priv(mmc); 930 struct mmc_data *data = mrq->data; 931 932 if (!slot->host->use_dma || !data) 933 return; 934 935 if (data->host_cookie != COOKIE_UNMAPPED) 936 dma_unmap_sg(slot->host->dev, 937 data->sg, 938 data->sg_len, 939 mmc_get_dma_dir(data)); 940 data->host_cookie = COOKIE_UNMAPPED; 941 } 942 943 static int dw_mci_get_cd(struct mmc_host *mmc) 944 { 945 int present; 946 struct dw_mci_slot *slot = mmc_priv(mmc); 947 struct dw_mci *host = slot->host; 948 int gpio_cd = mmc_gpio_get_cd(mmc); 949 950 /* Use platform get_cd function, else try onboard card detect */ 951 if (((mmc->caps & MMC_CAP_NEEDS_POLL) 952 || !mmc_card_is_removable(mmc))) { 953 present = 1; 954 955 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 956 if (mmc->caps & MMC_CAP_NEEDS_POLL) { 957 dev_info(&mmc->class_dev, 958 "card is polling.\n"); 959 } else { 960 dev_info(&mmc->class_dev, 961 "card is non-removable.\n"); 962 } 963 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 964 } 965 966 return present; 967 } else if (gpio_cd >= 0) 968 present = gpio_cd; 969 else 970 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 971 == 0 ? 1 : 0; 972 973 spin_lock_bh(&host->lock); 974 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 975 dev_dbg(&mmc->class_dev, "card is present\n"); 976 else if (!present && 977 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 978 dev_dbg(&mmc->class_dev, "card is not present\n"); 979 spin_unlock_bh(&host->lock); 980 981 return present; 982 } 983 984 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 985 { 986 unsigned int blksz = data->blksz; 987 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 988 u32 fifo_width = 1 << host->data_shift; 989 u32 blksz_depth = blksz / fifo_width, fifoth_val; 990 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 991 int idx = ARRAY_SIZE(mszs) - 1; 992 993 /* pio should ship this scenario */ 994 if (!host->use_dma) 995 return; 996 997 tx_wmark = (host->fifo_depth) / 2; 998 tx_wmark_invers = host->fifo_depth - tx_wmark; 999 1000 /* 1001 * MSIZE is '1', 1002 * if blksz is not a multiple of the FIFO width 1003 */ 1004 if (blksz % fifo_width) 1005 goto done; 1006 1007 do { 1008 if (!((blksz_depth % mszs[idx]) || 1009 (tx_wmark_invers % mszs[idx]))) { 1010 msize = idx; 1011 rx_wmark = mszs[idx] - 1; 1012 break; 1013 } 1014 } while (--idx > 0); 1015 /* 1016 * If idx is '0', it won't be tried 1017 * Thus, initial values are uesed 1018 */ 1019 done: 1020 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 1021 mci_writel(host, FIFOTH, fifoth_val); 1022 } 1023 1024 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1025 { 1026 unsigned int blksz = data->blksz; 1027 u32 blksz_depth, fifo_depth; 1028 u16 thld_size; 1029 u8 enable; 1030 1031 /* 1032 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 1033 * in the FIFO region, so we really shouldn't access it). 1034 */ 1035 if (host->verid < DW_MMC_240A || 1036 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 1037 return; 1038 1039 /* 1040 * Card write Threshold is introduced since 2.80a 1041 * It's used when HS400 mode is enabled. 1042 */ 1043 if (data->flags & MMC_DATA_WRITE && 1044 !(host->timing != MMC_TIMING_MMC_HS400)) 1045 return; 1046 1047 if (data->flags & MMC_DATA_WRITE) 1048 enable = SDMMC_CARD_WR_THR_EN; 1049 else 1050 enable = SDMMC_CARD_RD_THR_EN; 1051 1052 if (host->timing != MMC_TIMING_MMC_HS200 && 1053 host->timing != MMC_TIMING_UHS_SDR104) 1054 goto disable; 1055 1056 blksz_depth = blksz / (1 << host->data_shift); 1057 fifo_depth = host->fifo_depth; 1058 1059 if (blksz_depth > fifo_depth) 1060 goto disable; 1061 1062 /* 1063 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1064 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1065 * Currently just choose blksz. 1066 */ 1067 thld_size = blksz; 1068 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1069 return; 1070 1071 disable: 1072 mci_writel(host, CDTHRCTL, 0); 1073 } 1074 1075 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1076 { 1077 unsigned long irqflags; 1078 int sg_len; 1079 u32 temp; 1080 1081 host->using_dma = 0; 1082 1083 /* If we don't have a channel, we can't do DMA */ 1084 if (!host->use_dma) 1085 return -ENODEV; 1086 1087 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1088 if (sg_len < 0) { 1089 host->dma_ops->stop(host); 1090 return sg_len; 1091 } 1092 1093 host->using_dma = 1; 1094 1095 if (host->use_dma == TRANS_MODE_IDMAC) 1096 dev_vdbg(host->dev, 1097 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1098 (unsigned long)host->sg_cpu, 1099 (unsigned long)host->sg_dma, 1100 sg_len); 1101 1102 /* 1103 * Decide the MSIZE and RX/TX Watermark. 1104 * If current block size is same with previous size, 1105 * no need to update fifoth. 1106 */ 1107 if (host->prev_blksz != data->blksz) 1108 dw_mci_adjust_fifoth(host, data); 1109 1110 /* Enable the DMA interface */ 1111 temp = mci_readl(host, CTRL); 1112 temp |= SDMMC_CTRL_DMA_ENABLE; 1113 mci_writel(host, CTRL, temp); 1114 1115 /* Disable RX/TX IRQs, let DMA handle it */ 1116 spin_lock_irqsave(&host->irq_lock, irqflags); 1117 temp = mci_readl(host, INTMASK); 1118 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1119 mci_writel(host, INTMASK, temp); 1120 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1121 1122 if (host->dma_ops->start(host, sg_len)) { 1123 host->dma_ops->stop(host); 1124 /* We can't do DMA, try PIO for this one */ 1125 dev_dbg(host->dev, 1126 "%s: fall back to PIO mode for current transfer\n", 1127 __func__); 1128 return -ENODEV; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1135 { 1136 unsigned long irqflags; 1137 int flags = SG_MITER_ATOMIC; 1138 u32 temp; 1139 1140 data->error = -EINPROGRESS; 1141 1142 WARN_ON(host->data); 1143 host->sg = NULL; 1144 host->data = data; 1145 1146 if (data->flags & MMC_DATA_READ) 1147 host->dir_status = DW_MCI_RECV_STATUS; 1148 else 1149 host->dir_status = DW_MCI_SEND_STATUS; 1150 1151 dw_mci_ctrl_thld(host, data); 1152 1153 if (dw_mci_submit_data_dma(host, data)) { 1154 if (host->data->flags & MMC_DATA_READ) 1155 flags |= SG_MITER_TO_SG; 1156 else 1157 flags |= SG_MITER_FROM_SG; 1158 1159 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1160 host->sg = data->sg; 1161 host->part_buf_start = 0; 1162 host->part_buf_count = 0; 1163 1164 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1165 1166 spin_lock_irqsave(&host->irq_lock, irqflags); 1167 temp = mci_readl(host, INTMASK); 1168 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1169 mci_writel(host, INTMASK, temp); 1170 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1171 1172 temp = mci_readl(host, CTRL); 1173 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1174 mci_writel(host, CTRL, temp); 1175 1176 /* 1177 * Use the initial fifoth_val for PIO mode. If wm_algined 1178 * is set, we set watermark same as data size. 1179 * If next issued data may be transfered by DMA mode, 1180 * prev_blksz should be invalidated. 1181 */ 1182 if (host->wm_aligned) 1183 dw_mci_adjust_fifoth(host, data); 1184 else 1185 mci_writel(host, FIFOTH, host->fifoth_val); 1186 host->prev_blksz = 0; 1187 } else { 1188 /* 1189 * Keep the current block size. 1190 * It will be used to decide whether to update 1191 * fifoth register next time. 1192 */ 1193 host->prev_blksz = data->blksz; 1194 } 1195 } 1196 1197 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1198 { 1199 struct dw_mci *host = slot->host; 1200 unsigned int clock = slot->clock; 1201 u32 div; 1202 u32 clk_en_a; 1203 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1204 1205 /* We must continue to set bit 28 in CMD until the change is complete */ 1206 if (host->state == STATE_WAITING_CMD11_DONE) 1207 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1208 1209 if (!clock) { 1210 mci_writel(host, CLKENA, 0); 1211 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1212 } else if (clock != host->current_speed || force_clkinit) { 1213 div = host->bus_hz / clock; 1214 if (host->bus_hz % clock && host->bus_hz > clock) 1215 /* 1216 * move the + 1 after the divide to prevent 1217 * over-clocking the card. 1218 */ 1219 div += 1; 1220 1221 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1222 1223 if ((clock != slot->__clk_old && 1224 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1225 force_clkinit) { 1226 /* Silent the verbose log if calling from PM context */ 1227 if (!force_clkinit) 1228 dev_info(&slot->mmc->class_dev, 1229 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1230 slot->id, host->bus_hz, clock, 1231 div ? ((host->bus_hz / div) >> 1) : 1232 host->bus_hz, div); 1233 1234 /* 1235 * If card is polling, display the message only 1236 * one time at boot time. 1237 */ 1238 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1239 slot->mmc->f_min == clock) 1240 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1241 } 1242 1243 /* disable clock */ 1244 mci_writel(host, CLKENA, 0); 1245 mci_writel(host, CLKSRC, 0); 1246 1247 /* inform CIU */ 1248 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1249 1250 /* set clock to desired speed */ 1251 mci_writel(host, CLKDIV, div); 1252 1253 /* inform CIU */ 1254 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1255 1256 /* enable clock; only low power if no SDIO */ 1257 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1258 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1259 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1260 mci_writel(host, CLKENA, clk_en_a); 1261 1262 /* inform CIU */ 1263 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1264 1265 /* keep the last clock value that was requested from core */ 1266 slot->__clk_old = clock; 1267 } 1268 1269 host->current_speed = clock; 1270 1271 /* Set the current slot bus width */ 1272 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1273 } 1274 1275 static void __dw_mci_start_request(struct dw_mci *host, 1276 struct dw_mci_slot *slot, 1277 struct mmc_command *cmd) 1278 { 1279 struct mmc_request *mrq; 1280 struct mmc_data *data; 1281 u32 cmdflags; 1282 1283 mrq = slot->mrq; 1284 1285 host->cur_slot = slot; 1286 host->mrq = mrq; 1287 1288 host->pending_events = 0; 1289 host->completed_events = 0; 1290 host->cmd_status = 0; 1291 host->data_status = 0; 1292 host->dir_status = 0; 1293 1294 data = cmd->data; 1295 if (data) { 1296 mci_writel(host, TMOUT, 0xFFFFFFFF); 1297 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1298 mci_writel(host, BLKSIZ, data->blksz); 1299 } 1300 1301 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1302 1303 /* this is the first command, send the initialization clock */ 1304 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1305 cmdflags |= SDMMC_CMD_INIT; 1306 1307 if (data) { 1308 dw_mci_submit_data(host, data); 1309 wmb(); /* drain writebuffer */ 1310 } 1311 1312 dw_mci_start_command(host, cmd, cmdflags); 1313 1314 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1315 unsigned long irqflags; 1316 1317 /* 1318 * Databook says to fail after 2ms w/ no response, but evidence 1319 * shows that sometimes the cmd11 interrupt takes over 130ms. 1320 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1321 * is just about to roll over. 1322 * 1323 * We do this whole thing under spinlock and only if the 1324 * command hasn't already completed (indicating the the irq 1325 * already ran so we don't want the timeout). 1326 */ 1327 spin_lock_irqsave(&host->irq_lock, irqflags); 1328 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1329 mod_timer(&host->cmd11_timer, 1330 jiffies + msecs_to_jiffies(500) + 1); 1331 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1332 } 1333 1334 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1335 } 1336 1337 static void dw_mci_start_request(struct dw_mci *host, 1338 struct dw_mci_slot *slot) 1339 { 1340 struct mmc_request *mrq = slot->mrq; 1341 struct mmc_command *cmd; 1342 1343 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1344 __dw_mci_start_request(host, slot, cmd); 1345 } 1346 1347 /* must be called with host->lock held */ 1348 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1349 struct mmc_request *mrq) 1350 { 1351 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1352 host->state); 1353 1354 slot->mrq = mrq; 1355 1356 if (host->state == STATE_WAITING_CMD11_DONE) { 1357 dev_warn(&slot->mmc->class_dev, 1358 "Voltage change didn't complete\n"); 1359 /* 1360 * this case isn't expected to happen, so we can 1361 * either crash here or just try to continue on 1362 * in the closest possible state 1363 */ 1364 host->state = STATE_IDLE; 1365 } 1366 1367 if (host->state == STATE_IDLE) { 1368 host->state = STATE_SENDING_CMD; 1369 dw_mci_start_request(host, slot); 1370 } else { 1371 list_add_tail(&slot->queue_node, &host->queue); 1372 } 1373 } 1374 1375 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1376 { 1377 struct dw_mci_slot *slot = mmc_priv(mmc); 1378 struct dw_mci *host = slot->host; 1379 1380 WARN_ON(slot->mrq); 1381 1382 /* 1383 * The check for card presence and queueing of the request must be 1384 * atomic, otherwise the card could be removed in between and the 1385 * request wouldn't fail until another card was inserted. 1386 */ 1387 1388 if (!dw_mci_get_cd(mmc)) { 1389 mrq->cmd->error = -ENOMEDIUM; 1390 mmc_request_done(mmc, mrq); 1391 return; 1392 } 1393 1394 spin_lock_bh(&host->lock); 1395 1396 dw_mci_queue_request(host, slot, mrq); 1397 1398 spin_unlock_bh(&host->lock); 1399 } 1400 1401 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1402 { 1403 struct dw_mci_slot *slot = mmc_priv(mmc); 1404 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1405 u32 regs; 1406 int ret; 1407 1408 switch (ios->bus_width) { 1409 case MMC_BUS_WIDTH_4: 1410 slot->ctype = SDMMC_CTYPE_4BIT; 1411 break; 1412 case MMC_BUS_WIDTH_8: 1413 slot->ctype = SDMMC_CTYPE_8BIT; 1414 break; 1415 default: 1416 /* set default 1 bit mode */ 1417 slot->ctype = SDMMC_CTYPE_1BIT; 1418 } 1419 1420 regs = mci_readl(slot->host, UHS_REG); 1421 1422 /* DDR mode set */ 1423 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1424 ios->timing == MMC_TIMING_UHS_DDR50 || 1425 ios->timing == MMC_TIMING_MMC_HS400) 1426 regs |= ((0x1 << slot->id) << 16); 1427 else 1428 regs &= ~((0x1 << slot->id) << 16); 1429 1430 mci_writel(slot->host, UHS_REG, regs); 1431 slot->host->timing = ios->timing; 1432 1433 /* 1434 * Use mirror of ios->clock to prevent race with mmc 1435 * core ios update when finding the minimum. 1436 */ 1437 slot->clock = ios->clock; 1438 1439 if (drv_data && drv_data->set_ios) 1440 drv_data->set_ios(slot->host, ios); 1441 1442 switch (ios->power_mode) { 1443 case MMC_POWER_UP: 1444 if (!IS_ERR(mmc->supply.vmmc)) { 1445 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1446 ios->vdd); 1447 if (ret) { 1448 dev_err(slot->host->dev, 1449 "failed to enable vmmc regulator\n"); 1450 /*return, if failed turn on vmmc*/ 1451 return; 1452 } 1453 } 1454 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1455 regs = mci_readl(slot->host, PWREN); 1456 regs |= (1 << slot->id); 1457 mci_writel(slot->host, PWREN, regs); 1458 break; 1459 case MMC_POWER_ON: 1460 if (!slot->host->vqmmc_enabled) { 1461 if (!IS_ERR(mmc->supply.vqmmc)) { 1462 ret = regulator_enable(mmc->supply.vqmmc); 1463 if (ret < 0) 1464 dev_err(slot->host->dev, 1465 "failed to enable vqmmc\n"); 1466 else 1467 slot->host->vqmmc_enabled = true; 1468 1469 } else { 1470 /* Keep track so we don't reset again */ 1471 slot->host->vqmmc_enabled = true; 1472 } 1473 1474 /* Reset our state machine after powering on */ 1475 dw_mci_ctrl_reset(slot->host, 1476 SDMMC_CTRL_ALL_RESET_FLAGS); 1477 } 1478 1479 /* Adjust clock / bus width after power is up */ 1480 dw_mci_setup_bus(slot, false); 1481 1482 break; 1483 case MMC_POWER_OFF: 1484 /* Turn clock off before power goes down */ 1485 dw_mci_setup_bus(slot, false); 1486 1487 if (!IS_ERR(mmc->supply.vmmc)) 1488 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1489 1490 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1491 regulator_disable(mmc->supply.vqmmc); 1492 slot->host->vqmmc_enabled = false; 1493 1494 regs = mci_readl(slot->host, PWREN); 1495 regs &= ~(1 << slot->id); 1496 mci_writel(slot->host, PWREN, regs); 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1503 slot->host->state = STATE_IDLE; 1504 } 1505 1506 static int dw_mci_card_busy(struct mmc_host *mmc) 1507 { 1508 struct dw_mci_slot *slot = mmc_priv(mmc); 1509 u32 status; 1510 1511 /* 1512 * Check the busy bit which is low when DAT[3:0] 1513 * (the data lines) are 0000 1514 */ 1515 status = mci_readl(slot->host, STATUS); 1516 1517 return !!(status & SDMMC_STATUS_BUSY); 1518 } 1519 1520 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1521 { 1522 struct dw_mci_slot *slot = mmc_priv(mmc); 1523 struct dw_mci *host = slot->host; 1524 const struct dw_mci_drv_data *drv_data = host->drv_data; 1525 u32 uhs; 1526 u32 v18 = SDMMC_UHS_18V << slot->id; 1527 int ret; 1528 1529 if (drv_data && drv_data->switch_voltage) 1530 return drv_data->switch_voltage(mmc, ios); 1531 1532 /* 1533 * Program the voltage. Note that some instances of dw_mmc may use 1534 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1535 * does no harm but you need to set the regulator directly. Try both. 1536 */ 1537 uhs = mci_readl(host, UHS_REG); 1538 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1539 uhs &= ~v18; 1540 else 1541 uhs |= v18; 1542 1543 if (!IS_ERR(mmc->supply.vqmmc)) { 1544 ret = mmc_regulator_set_vqmmc(mmc, ios); 1545 1546 if (ret) { 1547 dev_dbg(&mmc->class_dev, 1548 "Regulator set error %d - %s V\n", 1549 ret, uhs & v18 ? "1.8" : "3.3"); 1550 return ret; 1551 } 1552 } 1553 mci_writel(host, UHS_REG, uhs); 1554 1555 return 0; 1556 } 1557 1558 static int dw_mci_get_ro(struct mmc_host *mmc) 1559 { 1560 int read_only; 1561 struct dw_mci_slot *slot = mmc_priv(mmc); 1562 int gpio_ro = mmc_gpio_get_ro(mmc); 1563 1564 /* Use platform get_ro function, else try on board write protect */ 1565 if (gpio_ro >= 0) 1566 read_only = gpio_ro; 1567 else 1568 read_only = 1569 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1570 1571 dev_dbg(&mmc->class_dev, "card is %s\n", 1572 read_only ? "read-only" : "read-write"); 1573 1574 return read_only; 1575 } 1576 1577 static void dw_mci_hw_reset(struct mmc_host *mmc) 1578 { 1579 struct dw_mci_slot *slot = mmc_priv(mmc); 1580 struct dw_mci *host = slot->host; 1581 int reset; 1582 1583 if (host->use_dma == TRANS_MODE_IDMAC) 1584 dw_mci_idmac_reset(host); 1585 1586 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1587 SDMMC_CTRL_FIFO_RESET)) 1588 return; 1589 1590 /* 1591 * According to eMMC spec, card reset procedure: 1592 * tRstW >= 1us: RST_n pulse width 1593 * tRSCA >= 200us: RST_n to Command time 1594 * tRSTH >= 1us: RST_n high period 1595 */ 1596 reset = mci_readl(host, RST_N); 1597 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1598 mci_writel(host, RST_N, reset); 1599 usleep_range(1, 2); 1600 reset |= SDMMC_RST_HWACTIVE << slot->id; 1601 mci_writel(host, RST_N, reset); 1602 usleep_range(200, 300); 1603 } 1604 1605 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1606 { 1607 struct dw_mci_slot *slot = mmc_priv(mmc); 1608 struct dw_mci *host = slot->host; 1609 1610 /* 1611 * Low power mode will stop the card clock when idle. According to the 1612 * description of the CLKENA register we should disable low power mode 1613 * for SDIO cards if we need SDIO interrupts to work. 1614 */ 1615 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1616 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1617 u32 clk_en_a_old; 1618 u32 clk_en_a; 1619 1620 clk_en_a_old = mci_readl(host, CLKENA); 1621 1622 if (card->type == MMC_TYPE_SDIO || 1623 card->type == MMC_TYPE_SD_COMBO) { 1624 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) { 1625 pm_runtime_get_noresume(mmc->parent); 1626 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1627 } 1628 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1629 } else { 1630 if (test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) { 1631 pm_runtime_put_noidle(mmc->parent); 1632 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1633 } 1634 clk_en_a = clk_en_a_old | clken_low_pwr; 1635 } 1636 1637 if (clk_en_a != clk_en_a_old) { 1638 mci_writel(host, CLKENA, clk_en_a); 1639 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1640 SDMMC_CMD_PRV_DAT_WAIT, 0); 1641 } 1642 } 1643 } 1644 1645 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1646 { 1647 struct dw_mci_slot *slot = mmc_priv(mmc); 1648 struct dw_mci *host = slot->host; 1649 unsigned long irqflags; 1650 u32 int_mask; 1651 1652 spin_lock_irqsave(&host->irq_lock, irqflags); 1653 1654 /* Enable/disable Slot Specific SDIO interrupt */ 1655 int_mask = mci_readl(host, INTMASK); 1656 if (enb) 1657 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1658 else 1659 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1660 mci_writel(host, INTMASK, int_mask); 1661 1662 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1663 } 1664 1665 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1666 { 1667 struct dw_mci_slot *slot = mmc_priv(mmc); 1668 struct dw_mci *host = slot->host; 1669 const struct dw_mci_drv_data *drv_data = host->drv_data; 1670 int err = -EINVAL; 1671 1672 if (drv_data && drv_data->execute_tuning) 1673 err = drv_data->execute_tuning(slot, opcode); 1674 return err; 1675 } 1676 1677 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1678 struct mmc_ios *ios) 1679 { 1680 struct dw_mci_slot *slot = mmc_priv(mmc); 1681 struct dw_mci *host = slot->host; 1682 const struct dw_mci_drv_data *drv_data = host->drv_data; 1683 1684 if (drv_data && drv_data->prepare_hs400_tuning) 1685 return drv_data->prepare_hs400_tuning(host, ios); 1686 1687 return 0; 1688 } 1689 1690 static bool dw_mci_reset(struct dw_mci *host) 1691 { 1692 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 1693 bool ret = false; 1694 u32 status = 0; 1695 1696 /* 1697 * Resetting generates a block interrupt, hence setting 1698 * the scatter-gather pointer to NULL. 1699 */ 1700 if (host->sg) { 1701 sg_miter_stop(&host->sg_miter); 1702 host->sg = NULL; 1703 } 1704 1705 if (host->use_dma) 1706 flags |= SDMMC_CTRL_DMA_RESET; 1707 1708 if (dw_mci_ctrl_reset(host, flags)) { 1709 /* 1710 * In all cases we clear the RAWINTS 1711 * register to clear any interrupts. 1712 */ 1713 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1714 1715 if (!host->use_dma) { 1716 ret = true; 1717 goto ciu_out; 1718 } 1719 1720 /* Wait for dma_req to be cleared */ 1721 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 1722 status, 1723 !(status & SDMMC_STATUS_DMA_REQ), 1724 1, 500 * USEC_PER_MSEC)) { 1725 dev_err(host->dev, 1726 "%s: Timeout waiting for dma_req to be cleared\n", 1727 __func__); 1728 goto ciu_out; 1729 } 1730 1731 /* when using DMA next we reset the fifo again */ 1732 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 1733 goto ciu_out; 1734 } else { 1735 /* if the controller reset bit did clear, then set clock regs */ 1736 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 1737 dev_err(host->dev, 1738 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 1739 __func__); 1740 goto ciu_out; 1741 } 1742 } 1743 1744 if (host->use_dma == TRANS_MODE_IDMAC) 1745 /* It is also recommended that we reset and reprogram idmac */ 1746 dw_mci_idmac_reset(host); 1747 1748 ret = true; 1749 1750 ciu_out: 1751 /* After a CTRL reset we need to have CIU set clock registers */ 1752 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 1753 1754 return ret; 1755 } 1756 1757 static const struct mmc_host_ops dw_mci_ops = { 1758 .request = dw_mci_request, 1759 .pre_req = dw_mci_pre_req, 1760 .post_req = dw_mci_post_req, 1761 .set_ios = dw_mci_set_ios, 1762 .get_ro = dw_mci_get_ro, 1763 .get_cd = dw_mci_get_cd, 1764 .hw_reset = dw_mci_hw_reset, 1765 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1766 .execute_tuning = dw_mci_execute_tuning, 1767 .card_busy = dw_mci_card_busy, 1768 .start_signal_voltage_switch = dw_mci_switch_voltage, 1769 .init_card = dw_mci_init_card, 1770 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1771 }; 1772 1773 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1774 __releases(&host->lock) 1775 __acquires(&host->lock) 1776 { 1777 struct dw_mci_slot *slot; 1778 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1779 1780 WARN_ON(host->cmd || host->data); 1781 1782 host->cur_slot->mrq = NULL; 1783 host->mrq = NULL; 1784 if (!list_empty(&host->queue)) { 1785 slot = list_entry(host->queue.next, 1786 struct dw_mci_slot, queue_node); 1787 list_del(&slot->queue_node); 1788 dev_vdbg(host->dev, "list not empty: %s is next\n", 1789 mmc_hostname(slot->mmc)); 1790 host->state = STATE_SENDING_CMD; 1791 dw_mci_start_request(host, slot); 1792 } else { 1793 dev_vdbg(host->dev, "list empty\n"); 1794 1795 if (host->state == STATE_SENDING_CMD11) 1796 host->state = STATE_WAITING_CMD11_DONE; 1797 else 1798 host->state = STATE_IDLE; 1799 } 1800 1801 spin_unlock(&host->lock); 1802 mmc_request_done(prev_mmc, mrq); 1803 spin_lock(&host->lock); 1804 } 1805 1806 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1807 { 1808 u32 status = host->cmd_status; 1809 1810 host->cmd_status = 0; 1811 1812 /* Read the response from the card (up to 16 bytes) */ 1813 if (cmd->flags & MMC_RSP_PRESENT) { 1814 if (cmd->flags & MMC_RSP_136) { 1815 cmd->resp[3] = mci_readl(host, RESP0); 1816 cmd->resp[2] = mci_readl(host, RESP1); 1817 cmd->resp[1] = mci_readl(host, RESP2); 1818 cmd->resp[0] = mci_readl(host, RESP3); 1819 } else { 1820 cmd->resp[0] = mci_readl(host, RESP0); 1821 cmd->resp[1] = 0; 1822 cmd->resp[2] = 0; 1823 cmd->resp[3] = 0; 1824 } 1825 } 1826 1827 if (status & SDMMC_INT_RTO) 1828 cmd->error = -ETIMEDOUT; 1829 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1830 cmd->error = -EILSEQ; 1831 else if (status & SDMMC_INT_RESP_ERR) 1832 cmd->error = -EIO; 1833 else 1834 cmd->error = 0; 1835 1836 return cmd->error; 1837 } 1838 1839 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1840 { 1841 u32 status = host->data_status; 1842 1843 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1844 if (status & SDMMC_INT_DRTO) { 1845 data->error = -ETIMEDOUT; 1846 } else if (status & SDMMC_INT_DCRC) { 1847 data->error = -EILSEQ; 1848 } else if (status & SDMMC_INT_EBE) { 1849 if (host->dir_status == 1850 DW_MCI_SEND_STATUS) { 1851 /* 1852 * No data CRC status was returned. 1853 * The number of bytes transferred 1854 * will be exaggerated in PIO mode. 1855 */ 1856 data->bytes_xfered = 0; 1857 data->error = -ETIMEDOUT; 1858 } else if (host->dir_status == 1859 DW_MCI_RECV_STATUS) { 1860 data->error = -EILSEQ; 1861 } 1862 } else { 1863 /* SDMMC_INT_SBE is included */ 1864 data->error = -EILSEQ; 1865 } 1866 1867 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1868 1869 /* 1870 * After an error, there may be data lingering 1871 * in the FIFO 1872 */ 1873 dw_mci_reset(host); 1874 } else { 1875 data->bytes_xfered = data->blocks * data->blksz; 1876 data->error = 0; 1877 } 1878 1879 return data->error; 1880 } 1881 1882 static void dw_mci_set_drto(struct dw_mci *host) 1883 { 1884 unsigned int drto_clks; 1885 unsigned int drto_ms; 1886 1887 drto_clks = mci_readl(host, TMOUT) >> 8; 1888 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 1889 1890 /* add a bit spare time */ 1891 drto_ms += 10; 1892 1893 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 1894 } 1895 1896 static void dw_mci_tasklet_func(unsigned long priv) 1897 { 1898 struct dw_mci *host = (struct dw_mci *)priv; 1899 struct mmc_data *data; 1900 struct mmc_command *cmd; 1901 struct mmc_request *mrq; 1902 enum dw_mci_state state; 1903 enum dw_mci_state prev_state; 1904 unsigned int err; 1905 1906 spin_lock(&host->lock); 1907 1908 state = host->state; 1909 data = host->data; 1910 mrq = host->mrq; 1911 1912 do { 1913 prev_state = state; 1914 1915 switch (state) { 1916 case STATE_IDLE: 1917 case STATE_WAITING_CMD11_DONE: 1918 break; 1919 1920 case STATE_SENDING_CMD11: 1921 case STATE_SENDING_CMD: 1922 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1923 &host->pending_events)) 1924 break; 1925 1926 cmd = host->cmd; 1927 host->cmd = NULL; 1928 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1929 err = dw_mci_command_complete(host, cmd); 1930 if (cmd == mrq->sbc && !err) { 1931 prev_state = state = STATE_SENDING_CMD; 1932 __dw_mci_start_request(host, host->cur_slot, 1933 mrq->cmd); 1934 goto unlock; 1935 } 1936 1937 if (cmd->data && err) { 1938 /* 1939 * During UHS tuning sequence, sending the stop 1940 * command after the response CRC error would 1941 * throw the system into a confused state 1942 * causing all future tuning phases to report 1943 * failure. 1944 * 1945 * In such case controller will move into a data 1946 * transfer state after a response error or 1947 * response CRC error. Let's let that finish 1948 * before trying to send a stop, so we'll go to 1949 * STATE_SENDING_DATA. 1950 * 1951 * Although letting the data transfer take place 1952 * will waste a bit of time (we already know 1953 * the command was bad), it can't cause any 1954 * errors since it's possible it would have 1955 * taken place anyway if this tasklet got 1956 * delayed. Allowing the transfer to take place 1957 * avoids races and keeps things simple. 1958 */ 1959 if ((err != -ETIMEDOUT) && 1960 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) { 1961 state = STATE_SENDING_DATA; 1962 continue; 1963 } 1964 1965 dw_mci_stop_dma(host); 1966 send_stop_abort(host, data); 1967 state = STATE_SENDING_STOP; 1968 break; 1969 } 1970 1971 if (!cmd->data || err) { 1972 dw_mci_request_end(host, mrq); 1973 goto unlock; 1974 } 1975 1976 prev_state = state = STATE_SENDING_DATA; 1977 /* fall through */ 1978 1979 case STATE_SENDING_DATA: 1980 /* 1981 * We could get a data error and never a transfer 1982 * complete so we'd better check for it here. 1983 * 1984 * Note that we don't really care if we also got a 1985 * transfer complete; stopping the DMA and sending an 1986 * abort won't hurt. 1987 */ 1988 if (test_and_clear_bit(EVENT_DATA_ERROR, 1989 &host->pending_events)) { 1990 dw_mci_stop_dma(host); 1991 if (!(host->data_status & (SDMMC_INT_DRTO | 1992 SDMMC_INT_EBE))) 1993 send_stop_abort(host, data); 1994 state = STATE_DATA_ERROR; 1995 break; 1996 } 1997 1998 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1999 &host->pending_events)) { 2000 /* 2001 * If all data-related interrupts don't come 2002 * within the given time in reading data state. 2003 */ 2004 if (host->dir_status == DW_MCI_RECV_STATUS) 2005 dw_mci_set_drto(host); 2006 break; 2007 } 2008 2009 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 2010 2011 /* 2012 * Handle an EVENT_DATA_ERROR that might have shown up 2013 * before the transfer completed. This might not have 2014 * been caught by the check above because the interrupt 2015 * could have gone off between the previous check and 2016 * the check for transfer complete. 2017 * 2018 * Technically this ought not be needed assuming we 2019 * get a DATA_COMPLETE eventually (we'll notice the 2020 * error and end the request), but it shouldn't hurt. 2021 * 2022 * This has the advantage of sending the stop command. 2023 */ 2024 if (test_and_clear_bit(EVENT_DATA_ERROR, 2025 &host->pending_events)) { 2026 dw_mci_stop_dma(host); 2027 if (!(host->data_status & (SDMMC_INT_DRTO | 2028 SDMMC_INT_EBE))) 2029 send_stop_abort(host, data); 2030 state = STATE_DATA_ERROR; 2031 break; 2032 } 2033 prev_state = state = STATE_DATA_BUSY; 2034 2035 /* fall through */ 2036 2037 case STATE_DATA_BUSY: 2038 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 2039 &host->pending_events)) { 2040 /* 2041 * If data error interrupt comes but data over 2042 * interrupt doesn't come within the given time. 2043 * in reading data state. 2044 */ 2045 if (host->dir_status == DW_MCI_RECV_STATUS) 2046 dw_mci_set_drto(host); 2047 break; 2048 } 2049 2050 host->data = NULL; 2051 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2052 err = dw_mci_data_complete(host, data); 2053 2054 if (!err) { 2055 if (!data->stop || mrq->sbc) { 2056 if (mrq->sbc && data->stop) 2057 data->stop->error = 0; 2058 dw_mci_request_end(host, mrq); 2059 goto unlock; 2060 } 2061 2062 /* stop command for open-ended transfer*/ 2063 if (data->stop) 2064 send_stop_abort(host, data); 2065 } else { 2066 /* 2067 * If we don't have a command complete now we'll 2068 * never get one since we just reset everything; 2069 * better end the request. 2070 * 2071 * If we do have a command complete we'll fall 2072 * through to the SENDING_STOP command and 2073 * everything will be peachy keen. 2074 */ 2075 if (!test_bit(EVENT_CMD_COMPLETE, 2076 &host->pending_events)) { 2077 host->cmd = NULL; 2078 dw_mci_request_end(host, mrq); 2079 goto unlock; 2080 } 2081 } 2082 2083 /* 2084 * If err has non-zero, 2085 * stop-abort command has been already issued. 2086 */ 2087 prev_state = state = STATE_SENDING_STOP; 2088 2089 /* fall through */ 2090 2091 case STATE_SENDING_STOP: 2092 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 2093 &host->pending_events)) 2094 break; 2095 2096 /* CMD error in data command */ 2097 if (mrq->cmd->error && mrq->data) 2098 dw_mci_reset(host); 2099 2100 host->cmd = NULL; 2101 host->data = NULL; 2102 2103 if (!mrq->sbc && mrq->stop) 2104 dw_mci_command_complete(host, mrq->stop); 2105 else 2106 host->cmd_status = 0; 2107 2108 dw_mci_request_end(host, mrq); 2109 goto unlock; 2110 2111 case STATE_DATA_ERROR: 2112 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2113 &host->pending_events)) 2114 break; 2115 2116 state = STATE_DATA_BUSY; 2117 break; 2118 } 2119 } while (state != prev_state); 2120 2121 host->state = state; 2122 unlock: 2123 spin_unlock(&host->lock); 2124 2125 } 2126 2127 /* push final bytes to part_buf, only use during push */ 2128 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2129 { 2130 memcpy((void *)&host->part_buf, buf, cnt); 2131 host->part_buf_count = cnt; 2132 } 2133 2134 /* append bytes to part_buf, only use during push */ 2135 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2136 { 2137 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2138 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2139 host->part_buf_count += cnt; 2140 return cnt; 2141 } 2142 2143 /* pull first bytes from part_buf, only use during pull */ 2144 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2145 { 2146 cnt = min_t(int, cnt, host->part_buf_count); 2147 if (cnt) { 2148 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2149 cnt); 2150 host->part_buf_count -= cnt; 2151 host->part_buf_start += cnt; 2152 } 2153 return cnt; 2154 } 2155 2156 /* pull final bytes from the part_buf, assuming it's just been filled */ 2157 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2158 { 2159 memcpy(buf, &host->part_buf, cnt); 2160 host->part_buf_start = cnt; 2161 host->part_buf_count = (1 << host->data_shift) - cnt; 2162 } 2163 2164 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2165 { 2166 struct mmc_data *data = host->data; 2167 int init_cnt = cnt; 2168 2169 /* try and push anything in the part_buf */ 2170 if (unlikely(host->part_buf_count)) { 2171 int len = dw_mci_push_part_bytes(host, buf, cnt); 2172 2173 buf += len; 2174 cnt -= len; 2175 if (host->part_buf_count == 2) { 2176 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2177 host->part_buf_count = 0; 2178 } 2179 } 2180 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2181 if (unlikely((unsigned long)buf & 0x1)) { 2182 while (cnt >= 2) { 2183 u16 aligned_buf[64]; 2184 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2185 int items = len >> 1; 2186 int i; 2187 /* memcpy from input buffer into aligned buffer */ 2188 memcpy(aligned_buf, buf, len); 2189 buf += len; 2190 cnt -= len; 2191 /* push data from aligned buffer into fifo */ 2192 for (i = 0; i < items; ++i) 2193 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2194 } 2195 } else 2196 #endif 2197 { 2198 u16 *pdata = buf; 2199 2200 for (; cnt >= 2; cnt -= 2) 2201 mci_fifo_writew(host->fifo_reg, *pdata++); 2202 buf = pdata; 2203 } 2204 /* put anything remaining in the part_buf */ 2205 if (cnt) { 2206 dw_mci_set_part_bytes(host, buf, cnt); 2207 /* Push data if we have reached the expected data length */ 2208 if ((data->bytes_xfered + init_cnt) == 2209 (data->blksz * data->blocks)) 2210 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2211 } 2212 } 2213 2214 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2215 { 2216 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2217 if (unlikely((unsigned long)buf & 0x1)) { 2218 while (cnt >= 2) { 2219 /* pull data from fifo into aligned buffer */ 2220 u16 aligned_buf[64]; 2221 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2222 int items = len >> 1; 2223 int i; 2224 2225 for (i = 0; i < items; ++i) 2226 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2227 /* memcpy from aligned buffer into output buffer */ 2228 memcpy(buf, aligned_buf, len); 2229 buf += len; 2230 cnt -= len; 2231 } 2232 } else 2233 #endif 2234 { 2235 u16 *pdata = buf; 2236 2237 for (; cnt >= 2; cnt -= 2) 2238 *pdata++ = mci_fifo_readw(host->fifo_reg); 2239 buf = pdata; 2240 } 2241 if (cnt) { 2242 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2243 dw_mci_pull_final_bytes(host, buf, cnt); 2244 } 2245 } 2246 2247 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2248 { 2249 struct mmc_data *data = host->data; 2250 int init_cnt = cnt; 2251 2252 /* try and push anything in the part_buf */ 2253 if (unlikely(host->part_buf_count)) { 2254 int len = dw_mci_push_part_bytes(host, buf, cnt); 2255 2256 buf += len; 2257 cnt -= len; 2258 if (host->part_buf_count == 4) { 2259 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2260 host->part_buf_count = 0; 2261 } 2262 } 2263 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2264 if (unlikely((unsigned long)buf & 0x3)) { 2265 while (cnt >= 4) { 2266 u32 aligned_buf[32]; 2267 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2268 int items = len >> 2; 2269 int i; 2270 /* memcpy from input buffer into aligned buffer */ 2271 memcpy(aligned_buf, buf, len); 2272 buf += len; 2273 cnt -= len; 2274 /* push data from aligned buffer into fifo */ 2275 for (i = 0; i < items; ++i) 2276 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2277 } 2278 } else 2279 #endif 2280 { 2281 u32 *pdata = buf; 2282 2283 for (; cnt >= 4; cnt -= 4) 2284 mci_fifo_writel(host->fifo_reg, *pdata++); 2285 buf = pdata; 2286 } 2287 /* put anything remaining in the part_buf */ 2288 if (cnt) { 2289 dw_mci_set_part_bytes(host, buf, cnt); 2290 /* Push data if we have reached the expected data length */ 2291 if ((data->bytes_xfered + init_cnt) == 2292 (data->blksz * data->blocks)) 2293 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2294 } 2295 } 2296 2297 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2298 { 2299 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2300 if (unlikely((unsigned long)buf & 0x3)) { 2301 while (cnt >= 4) { 2302 /* pull data from fifo into aligned buffer */ 2303 u32 aligned_buf[32]; 2304 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2305 int items = len >> 2; 2306 int i; 2307 2308 for (i = 0; i < items; ++i) 2309 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2310 /* memcpy from aligned buffer into output buffer */ 2311 memcpy(buf, aligned_buf, len); 2312 buf += len; 2313 cnt -= len; 2314 } 2315 } else 2316 #endif 2317 { 2318 u32 *pdata = buf; 2319 2320 for (; cnt >= 4; cnt -= 4) 2321 *pdata++ = mci_fifo_readl(host->fifo_reg); 2322 buf = pdata; 2323 } 2324 if (cnt) { 2325 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2326 dw_mci_pull_final_bytes(host, buf, cnt); 2327 } 2328 } 2329 2330 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2331 { 2332 struct mmc_data *data = host->data; 2333 int init_cnt = cnt; 2334 2335 /* try and push anything in the part_buf */ 2336 if (unlikely(host->part_buf_count)) { 2337 int len = dw_mci_push_part_bytes(host, buf, cnt); 2338 2339 buf += len; 2340 cnt -= len; 2341 2342 if (host->part_buf_count == 8) { 2343 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2344 host->part_buf_count = 0; 2345 } 2346 } 2347 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2348 if (unlikely((unsigned long)buf & 0x7)) { 2349 while (cnt >= 8) { 2350 u64 aligned_buf[16]; 2351 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2352 int items = len >> 3; 2353 int i; 2354 /* memcpy from input buffer into aligned buffer */ 2355 memcpy(aligned_buf, buf, len); 2356 buf += len; 2357 cnt -= len; 2358 /* push data from aligned buffer into fifo */ 2359 for (i = 0; i < items; ++i) 2360 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2361 } 2362 } else 2363 #endif 2364 { 2365 u64 *pdata = buf; 2366 2367 for (; cnt >= 8; cnt -= 8) 2368 mci_fifo_writeq(host->fifo_reg, *pdata++); 2369 buf = pdata; 2370 } 2371 /* put anything remaining in the part_buf */ 2372 if (cnt) { 2373 dw_mci_set_part_bytes(host, buf, cnt); 2374 /* Push data if we have reached the expected data length */ 2375 if ((data->bytes_xfered + init_cnt) == 2376 (data->blksz * data->blocks)) 2377 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2378 } 2379 } 2380 2381 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2382 { 2383 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2384 if (unlikely((unsigned long)buf & 0x7)) { 2385 while (cnt >= 8) { 2386 /* pull data from fifo into aligned buffer */ 2387 u64 aligned_buf[16]; 2388 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2389 int items = len >> 3; 2390 int i; 2391 2392 for (i = 0; i < items; ++i) 2393 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2394 2395 /* memcpy from aligned buffer into output buffer */ 2396 memcpy(buf, aligned_buf, len); 2397 buf += len; 2398 cnt -= len; 2399 } 2400 } else 2401 #endif 2402 { 2403 u64 *pdata = buf; 2404 2405 for (; cnt >= 8; cnt -= 8) 2406 *pdata++ = mci_fifo_readq(host->fifo_reg); 2407 buf = pdata; 2408 } 2409 if (cnt) { 2410 host->part_buf = mci_fifo_readq(host->fifo_reg); 2411 dw_mci_pull_final_bytes(host, buf, cnt); 2412 } 2413 } 2414 2415 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2416 { 2417 int len; 2418 2419 /* get remaining partial bytes */ 2420 len = dw_mci_pull_part_bytes(host, buf, cnt); 2421 if (unlikely(len == cnt)) 2422 return; 2423 buf += len; 2424 cnt -= len; 2425 2426 /* get the rest of the data */ 2427 host->pull_data(host, buf, cnt); 2428 } 2429 2430 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2431 { 2432 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2433 void *buf; 2434 unsigned int offset; 2435 struct mmc_data *data = host->data; 2436 int shift = host->data_shift; 2437 u32 status; 2438 unsigned int len; 2439 unsigned int remain, fcnt; 2440 2441 do { 2442 if (!sg_miter_next(sg_miter)) 2443 goto done; 2444 2445 host->sg = sg_miter->piter.sg; 2446 buf = sg_miter->addr; 2447 remain = sg_miter->length; 2448 offset = 0; 2449 2450 do { 2451 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2452 << shift) + host->part_buf_count; 2453 len = min(remain, fcnt); 2454 if (!len) 2455 break; 2456 dw_mci_pull_data(host, (void *)(buf + offset), len); 2457 data->bytes_xfered += len; 2458 offset += len; 2459 remain -= len; 2460 } while (remain); 2461 2462 sg_miter->consumed = offset; 2463 status = mci_readl(host, MINTSTS); 2464 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2465 /* if the RXDR is ready read again */ 2466 } while ((status & SDMMC_INT_RXDR) || 2467 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2468 2469 if (!remain) { 2470 if (!sg_miter_next(sg_miter)) 2471 goto done; 2472 sg_miter->consumed = 0; 2473 } 2474 sg_miter_stop(sg_miter); 2475 return; 2476 2477 done: 2478 sg_miter_stop(sg_miter); 2479 host->sg = NULL; 2480 smp_wmb(); /* drain writebuffer */ 2481 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2482 } 2483 2484 static void dw_mci_write_data_pio(struct dw_mci *host) 2485 { 2486 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2487 void *buf; 2488 unsigned int offset; 2489 struct mmc_data *data = host->data; 2490 int shift = host->data_shift; 2491 u32 status; 2492 unsigned int len; 2493 unsigned int fifo_depth = host->fifo_depth; 2494 unsigned int remain, fcnt; 2495 2496 do { 2497 if (!sg_miter_next(sg_miter)) 2498 goto done; 2499 2500 host->sg = sg_miter->piter.sg; 2501 buf = sg_miter->addr; 2502 remain = sg_miter->length; 2503 offset = 0; 2504 2505 do { 2506 fcnt = ((fifo_depth - 2507 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2508 << shift) - host->part_buf_count; 2509 len = min(remain, fcnt); 2510 if (!len) 2511 break; 2512 host->push_data(host, (void *)(buf + offset), len); 2513 data->bytes_xfered += len; 2514 offset += len; 2515 remain -= len; 2516 } while (remain); 2517 2518 sg_miter->consumed = offset; 2519 status = mci_readl(host, MINTSTS); 2520 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2521 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2522 2523 if (!remain) { 2524 if (!sg_miter_next(sg_miter)) 2525 goto done; 2526 sg_miter->consumed = 0; 2527 } 2528 sg_miter_stop(sg_miter); 2529 return; 2530 2531 done: 2532 sg_miter_stop(sg_miter); 2533 host->sg = NULL; 2534 smp_wmb(); /* drain writebuffer */ 2535 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2536 } 2537 2538 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2539 { 2540 if (!host->cmd_status) 2541 host->cmd_status = status; 2542 2543 smp_wmb(); /* drain writebuffer */ 2544 2545 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2546 tasklet_schedule(&host->tasklet); 2547 } 2548 2549 static void dw_mci_handle_cd(struct dw_mci *host) 2550 { 2551 int i; 2552 2553 for (i = 0; i < host->num_slots; i++) { 2554 struct dw_mci_slot *slot = host->slot[i]; 2555 2556 if (!slot) 2557 continue; 2558 2559 if (slot->mmc->ops->card_event) 2560 slot->mmc->ops->card_event(slot->mmc); 2561 mmc_detect_change(slot->mmc, 2562 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2563 } 2564 } 2565 2566 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2567 { 2568 struct dw_mci *host = dev_id; 2569 u32 pending; 2570 int i; 2571 2572 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2573 2574 if (pending) { 2575 /* Check volt switch first, since it can look like an error */ 2576 if ((host->state == STATE_SENDING_CMD11) && 2577 (pending & SDMMC_INT_VOLT_SWITCH)) { 2578 unsigned long irqflags; 2579 2580 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2581 pending &= ~SDMMC_INT_VOLT_SWITCH; 2582 2583 /* 2584 * Hold the lock; we know cmd11_timer can't be kicked 2585 * off after the lock is released, so safe to delete. 2586 */ 2587 spin_lock_irqsave(&host->irq_lock, irqflags); 2588 dw_mci_cmd_interrupt(host, pending); 2589 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2590 2591 del_timer(&host->cmd11_timer); 2592 } 2593 2594 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2595 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2596 host->cmd_status = pending; 2597 smp_wmb(); /* drain writebuffer */ 2598 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2599 } 2600 2601 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2602 /* if there is an error report DATA_ERROR */ 2603 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2604 host->data_status = pending; 2605 smp_wmb(); /* drain writebuffer */ 2606 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2607 tasklet_schedule(&host->tasklet); 2608 } 2609 2610 if (pending & SDMMC_INT_DATA_OVER) { 2611 del_timer(&host->dto_timer); 2612 2613 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2614 if (!host->data_status) 2615 host->data_status = pending; 2616 smp_wmb(); /* drain writebuffer */ 2617 if (host->dir_status == DW_MCI_RECV_STATUS) { 2618 if (host->sg != NULL) 2619 dw_mci_read_data_pio(host, true); 2620 } 2621 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2622 tasklet_schedule(&host->tasklet); 2623 } 2624 2625 if (pending & SDMMC_INT_RXDR) { 2626 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2627 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2628 dw_mci_read_data_pio(host, false); 2629 } 2630 2631 if (pending & SDMMC_INT_TXDR) { 2632 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2633 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2634 dw_mci_write_data_pio(host); 2635 } 2636 2637 if (pending & SDMMC_INT_CMD_DONE) { 2638 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2639 dw_mci_cmd_interrupt(host, pending); 2640 } 2641 2642 if (pending & SDMMC_INT_CD) { 2643 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2644 dw_mci_handle_cd(host); 2645 } 2646 2647 /* Handle SDIO Interrupts */ 2648 for (i = 0; i < host->num_slots; i++) { 2649 struct dw_mci_slot *slot = host->slot[i]; 2650 2651 if (!slot) 2652 continue; 2653 2654 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2655 mci_writel(host, RINTSTS, 2656 SDMMC_INT_SDIO(slot->sdio_id)); 2657 mmc_signal_sdio_irq(slot->mmc); 2658 } 2659 } 2660 2661 } 2662 2663 if (host->use_dma != TRANS_MODE_IDMAC) 2664 return IRQ_HANDLED; 2665 2666 /* Handle IDMA interrupts */ 2667 if (host->dma_64bit_address == 1) { 2668 pending = mci_readl(host, IDSTS64); 2669 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2670 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2671 SDMMC_IDMAC_INT_RI); 2672 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2673 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2674 host->dma_ops->complete((void *)host); 2675 } 2676 } else { 2677 pending = mci_readl(host, IDSTS); 2678 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2679 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2680 SDMMC_IDMAC_INT_RI); 2681 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2682 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2683 host->dma_ops->complete((void *)host); 2684 } 2685 } 2686 2687 return IRQ_HANDLED; 2688 } 2689 2690 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2691 { 2692 struct mmc_host *mmc; 2693 struct dw_mci_slot *slot; 2694 const struct dw_mci_drv_data *drv_data = host->drv_data; 2695 int ctrl_id, ret; 2696 u32 freq[2]; 2697 2698 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2699 if (!mmc) 2700 return -ENOMEM; 2701 2702 slot = mmc_priv(mmc); 2703 slot->id = id; 2704 slot->sdio_id = host->sdio_id0 + id; 2705 slot->mmc = mmc; 2706 slot->host = host; 2707 host->slot[id] = slot; 2708 2709 mmc->ops = &dw_mci_ops; 2710 if (of_property_read_u32_array(host->dev->of_node, 2711 "clock-freq-min-max", freq, 2)) { 2712 mmc->f_min = DW_MCI_FREQ_MIN; 2713 mmc->f_max = DW_MCI_FREQ_MAX; 2714 } else { 2715 dev_info(host->dev, 2716 "'clock-freq-min-max' property was deprecated.\n"); 2717 mmc->f_min = freq[0]; 2718 mmc->f_max = freq[1]; 2719 } 2720 2721 /*if there are external regulators, get them*/ 2722 ret = mmc_regulator_get_supply(mmc); 2723 if (ret == -EPROBE_DEFER) 2724 goto err_host_allocated; 2725 2726 if (!mmc->ocr_avail) 2727 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2728 2729 if (host->pdata->caps) 2730 mmc->caps = host->pdata->caps; 2731 2732 /* 2733 * Support MMC_CAP_ERASE by default. 2734 * It needs to use trim/discard/erase commands. 2735 */ 2736 mmc->caps |= MMC_CAP_ERASE; 2737 2738 if (host->pdata->pm_caps) 2739 mmc->pm_caps = host->pdata->pm_caps; 2740 2741 if (host->dev->of_node) { 2742 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2743 if (ctrl_id < 0) 2744 ctrl_id = 0; 2745 } else { 2746 ctrl_id = to_platform_device(host->dev)->id; 2747 } 2748 if (drv_data && drv_data->caps) 2749 mmc->caps |= drv_data->caps[ctrl_id]; 2750 2751 if (host->pdata->caps2) 2752 mmc->caps2 = host->pdata->caps2; 2753 2754 ret = mmc_of_parse(mmc); 2755 if (ret) 2756 goto err_host_allocated; 2757 2758 /* Useful defaults if platform data is unset. */ 2759 if (host->use_dma == TRANS_MODE_IDMAC) { 2760 mmc->max_segs = host->ring_size; 2761 mmc->max_blk_size = 65535; 2762 mmc->max_seg_size = 0x1000; 2763 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2764 mmc->max_blk_count = mmc->max_req_size / 512; 2765 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2766 mmc->max_segs = 64; 2767 mmc->max_blk_size = 65535; 2768 mmc->max_blk_count = 65535; 2769 mmc->max_req_size = 2770 mmc->max_blk_size * mmc->max_blk_count; 2771 mmc->max_seg_size = mmc->max_req_size; 2772 } else { 2773 /* TRANS_MODE_PIO */ 2774 mmc->max_segs = 64; 2775 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2776 mmc->max_blk_count = 512; 2777 mmc->max_req_size = mmc->max_blk_size * 2778 mmc->max_blk_count; 2779 mmc->max_seg_size = mmc->max_req_size; 2780 } 2781 2782 dw_mci_get_cd(mmc); 2783 2784 ret = mmc_add_host(mmc); 2785 if (ret) 2786 goto err_host_allocated; 2787 2788 #if defined(CONFIG_DEBUG_FS) 2789 dw_mci_init_debugfs(slot); 2790 #endif 2791 2792 return 0; 2793 2794 err_host_allocated: 2795 mmc_free_host(mmc); 2796 return ret; 2797 } 2798 2799 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2800 { 2801 /* Debugfs stuff is cleaned up by mmc core */ 2802 mmc_remove_host(slot->mmc); 2803 slot->host->slot[id] = NULL; 2804 mmc_free_host(slot->mmc); 2805 } 2806 2807 static void dw_mci_init_dma(struct dw_mci *host) 2808 { 2809 int addr_config; 2810 struct device *dev = host->dev; 2811 struct device_node *np = dev->of_node; 2812 2813 /* 2814 * Check tansfer mode from HCON[17:16] 2815 * Clear the ambiguous description of dw_mmc databook: 2816 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2817 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2818 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2819 * 2b'11: Non DW DMA Interface -> pio only 2820 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2821 * simpler request/acknowledge handshake mechanism and both of them 2822 * are regarded as external dma master for dw_mmc. 2823 */ 2824 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2825 if (host->use_dma == DMA_INTERFACE_IDMA) { 2826 host->use_dma = TRANS_MODE_IDMAC; 2827 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2828 host->use_dma == DMA_INTERFACE_GDMA) { 2829 host->use_dma = TRANS_MODE_EDMAC; 2830 } else { 2831 goto no_dma; 2832 } 2833 2834 /* Determine which DMA interface to use */ 2835 if (host->use_dma == TRANS_MODE_IDMAC) { 2836 /* 2837 * Check ADDR_CONFIG bit in HCON to find 2838 * IDMAC address bus width 2839 */ 2840 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2841 2842 if (addr_config == 1) { 2843 /* host supports IDMAC in 64-bit address mode */ 2844 host->dma_64bit_address = 1; 2845 dev_info(host->dev, 2846 "IDMAC supports 64-bit address mode.\n"); 2847 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2848 dma_set_coherent_mask(host->dev, 2849 DMA_BIT_MASK(64)); 2850 } else { 2851 /* host supports IDMAC in 32-bit address mode */ 2852 host->dma_64bit_address = 0; 2853 dev_info(host->dev, 2854 "IDMAC supports 32-bit address mode.\n"); 2855 } 2856 2857 /* Alloc memory for sg translation */ 2858 host->sg_cpu = dmam_alloc_coherent(host->dev, 2859 DESC_RING_BUF_SZ, 2860 &host->sg_dma, GFP_KERNEL); 2861 if (!host->sg_cpu) { 2862 dev_err(host->dev, 2863 "%s: could not alloc DMA memory\n", 2864 __func__); 2865 goto no_dma; 2866 } 2867 2868 host->dma_ops = &dw_mci_idmac_ops; 2869 dev_info(host->dev, "Using internal DMA controller.\n"); 2870 } else { 2871 /* TRANS_MODE_EDMAC: check dma bindings again */ 2872 if ((of_property_count_strings(np, "dma-names") < 0) || 2873 (!of_find_property(np, "dmas", NULL))) { 2874 goto no_dma; 2875 } 2876 host->dma_ops = &dw_mci_edmac_ops; 2877 dev_info(host->dev, "Using external DMA controller.\n"); 2878 } 2879 2880 if (host->dma_ops->init && host->dma_ops->start && 2881 host->dma_ops->stop && host->dma_ops->cleanup) { 2882 if (host->dma_ops->init(host)) { 2883 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2884 __func__); 2885 goto no_dma; 2886 } 2887 } else { 2888 dev_err(host->dev, "DMA initialization not found.\n"); 2889 goto no_dma; 2890 } 2891 2892 return; 2893 2894 no_dma: 2895 dev_info(host->dev, "Using PIO mode.\n"); 2896 host->use_dma = TRANS_MODE_PIO; 2897 } 2898 2899 static void dw_mci_cmd11_timer(unsigned long arg) 2900 { 2901 struct dw_mci *host = (struct dw_mci *)arg; 2902 2903 if (host->state != STATE_SENDING_CMD11) { 2904 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2905 return; 2906 } 2907 2908 host->cmd_status = SDMMC_INT_RTO; 2909 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2910 tasklet_schedule(&host->tasklet); 2911 } 2912 2913 static void dw_mci_dto_timer(unsigned long arg) 2914 { 2915 struct dw_mci *host = (struct dw_mci *)arg; 2916 2917 switch (host->state) { 2918 case STATE_SENDING_DATA: 2919 case STATE_DATA_BUSY: 2920 /* 2921 * If DTO interrupt does NOT come in sending data state, 2922 * we should notify the driver to terminate current transfer 2923 * and report a data timeout to the core. 2924 */ 2925 host->data_status = SDMMC_INT_DRTO; 2926 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2927 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2928 tasklet_schedule(&host->tasklet); 2929 break; 2930 default: 2931 break; 2932 } 2933 } 2934 2935 #ifdef CONFIG_OF 2936 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2937 { 2938 struct dw_mci_board *pdata; 2939 struct device *dev = host->dev; 2940 struct device_node *np = dev->of_node; 2941 const struct dw_mci_drv_data *drv_data = host->drv_data; 2942 int ret; 2943 u32 clock_frequency; 2944 2945 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2946 if (!pdata) 2947 return ERR_PTR(-ENOMEM); 2948 2949 /* find reset controller when exist */ 2950 pdata->rstc = devm_reset_control_get_optional(dev, "reset"); 2951 if (IS_ERR(pdata->rstc)) { 2952 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 2953 return ERR_PTR(-EPROBE_DEFER); 2954 } 2955 2956 /* find out number of slots supported */ 2957 of_property_read_u32(np, "num-slots", &pdata->num_slots); 2958 2959 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2960 dev_info(dev, 2961 "fifo-depth property not found, using value of FIFOTH register as default\n"); 2962 2963 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2964 2965 of_property_read_u32(np, "data-addr", &host->data_addr_override); 2966 2967 if (of_get_property(np, "fifo-watermark-aligned", NULL)) 2968 host->wm_aligned = true; 2969 2970 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 2971 pdata->bus_hz = clock_frequency; 2972 2973 if (drv_data && drv_data->parse_dt) { 2974 ret = drv_data->parse_dt(host); 2975 if (ret) 2976 return ERR_PTR(ret); 2977 } 2978 2979 return pdata; 2980 } 2981 2982 #else /* CONFIG_OF */ 2983 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2984 { 2985 return ERR_PTR(-EINVAL); 2986 } 2987 #endif /* CONFIG_OF */ 2988 2989 static void dw_mci_enable_cd(struct dw_mci *host) 2990 { 2991 unsigned long irqflags; 2992 u32 temp; 2993 int i; 2994 struct dw_mci_slot *slot; 2995 2996 /* 2997 * No need for CD if all slots have a non-error GPIO 2998 * as well as broken card detection is found. 2999 */ 3000 for (i = 0; i < host->num_slots; i++) { 3001 slot = host->slot[i]; 3002 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3003 return; 3004 3005 if (mmc_gpio_get_cd(slot->mmc) < 0) 3006 break; 3007 } 3008 if (i == host->num_slots) 3009 return; 3010 3011 spin_lock_irqsave(&host->irq_lock, irqflags); 3012 temp = mci_readl(host, INTMASK); 3013 temp |= SDMMC_INT_CD; 3014 mci_writel(host, INTMASK, temp); 3015 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3016 } 3017 3018 int dw_mci_probe(struct dw_mci *host) 3019 { 3020 const struct dw_mci_drv_data *drv_data = host->drv_data; 3021 int width, i, ret = 0; 3022 u32 fifo_size; 3023 int init_slots = 0; 3024 3025 if (!host->pdata) { 3026 host->pdata = dw_mci_parse_dt(host); 3027 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) { 3028 return -EPROBE_DEFER; 3029 } else if (IS_ERR(host->pdata)) { 3030 dev_err(host->dev, "platform data not available\n"); 3031 return -EINVAL; 3032 } 3033 } 3034 3035 host->biu_clk = devm_clk_get(host->dev, "biu"); 3036 if (IS_ERR(host->biu_clk)) { 3037 dev_dbg(host->dev, "biu clock not available\n"); 3038 } else { 3039 ret = clk_prepare_enable(host->biu_clk); 3040 if (ret) { 3041 dev_err(host->dev, "failed to enable biu clock\n"); 3042 return ret; 3043 } 3044 } 3045 3046 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3047 if (IS_ERR(host->ciu_clk)) { 3048 dev_dbg(host->dev, "ciu clock not available\n"); 3049 host->bus_hz = host->pdata->bus_hz; 3050 } else { 3051 ret = clk_prepare_enable(host->ciu_clk); 3052 if (ret) { 3053 dev_err(host->dev, "failed to enable ciu clock\n"); 3054 goto err_clk_biu; 3055 } 3056 3057 if (host->pdata->bus_hz) { 3058 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3059 if (ret) 3060 dev_warn(host->dev, 3061 "Unable to set bus rate to %uHz\n", 3062 host->pdata->bus_hz); 3063 } 3064 host->bus_hz = clk_get_rate(host->ciu_clk); 3065 } 3066 3067 if (!host->bus_hz) { 3068 dev_err(host->dev, 3069 "Platform data must supply bus speed\n"); 3070 ret = -ENODEV; 3071 goto err_clk_ciu; 3072 } 3073 3074 if (drv_data && drv_data->init) { 3075 ret = drv_data->init(host); 3076 if (ret) { 3077 dev_err(host->dev, 3078 "implementation specific init failed\n"); 3079 goto err_clk_ciu; 3080 } 3081 } 3082 3083 if (!IS_ERR(host->pdata->rstc)) { 3084 reset_control_assert(host->pdata->rstc); 3085 usleep_range(10, 50); 3086 reset_control_deassert(host->pdata->rstc); 3087 } 3088 3089 setup_timer(&host->cmd11_timer, 3090 dw_mci_cmd11_timer, (unsigned long)host); 3091 3092 setup_timer(&host->dto_timer, 3093 dw_mci_dto_timer, (unsigned long)host); 3094 3095 spin_lock_init(&host->lock); 3096 spin_lock_init(&host->irq_lock); 3097 INIT_LIST_HEAD(&host->queue); 3098 3099 /* 3100 * Get the host data width - this assumes that HCON has been set with 3101 * the correct values. 3102 */ 3103 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3104 if (!i) { 3105 host->push_data = dw_mci_push_data16; 3106 host->pull_data = dw_mci_pull_data16; 3107 width = 16; 3108 host->data_shift = 1; 3109 } else if (i == 2) { 3110 host->push_data = dw_mci_push_data64; 3111 host->pull_data = dw_mci_pull_data64; 3112 width = 64; 3113 host->data_shift = 3; 3114 } else { 3115 /* Check for a reserved value, and warn if it is */ 3116 WARN((i != 1), 3117 "HCON reports a reserved host data width!\n" 3118 "Defaulting to 32-bit access.\n"); 3119 host->push_data = dw_mci_push_data32; 3120 host->pull_data = dw_mci_pull_data32; 3121 width = 32; 3122 host->data_shift = 2; 3123 } 3124 3125 /* Reset all blocks */ 3126 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3127 ret = -ENODEV; 3128 goto err_clk_ciu; 3129 } 3130 3131 host->dma_ops = host->pdata->dma_ops; 3132 dw_mci_init_dma(host); 3133 3134 /* Clear the interrupts for the host controller */ 3135 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3136 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3137 3138 /* Put in max timeout */ 3139 mci_writel(host, TMOUT, 0xFFFFFFFF); 3140 3141 /* 3142 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3143 * Tx Mark = fifo_size / 2 DMA Size = 8 3144 */ 3145 if (!host->pdata->fifo_depth) { 3146 /* 3147 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3148 * have been overwritten by the bootloader, just like we're 3149 * about to do, so if you know the value for your hardware, you 3150 * should put it in the platform data. 3151 */ 3152 fifo_size = mci_readl(host, FIFOTH); 3153 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3154 } else { 3155 fifo_size = host->pdata->fifo_depth; 3156 } 3157 host->fifo_depth = fifo_size; 3158 host->fifoth_val = 3159 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3160 mci_writel(host, FIFOTH, host->fifoth_val); 3161 3162 /* disable clock to CIU */ 3163 mci_writel(host, CLKENA, 0); 3164 mci_writel(host, CLKSRC, 0); 3165 3166 /* 3167 * In 2.40a spec, Data offset is changed. 3168 * Need to check the version-id and set data-offset for DATA register. 3169 */ 3170 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3171 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3172 3173 if (host->data_addr_override) 3174 host->fifo_reg = host->regs + host->data_addr_override; 3175 else if (host->verid < DW_MMC_240A) 3176 host->fifo_reg = host->regs + DATA_OFFSET; 3177 else 3178 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3179 3180 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3181 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3182 host->irq_flags, "dw-mci", host); 3183 if (ret) 3184 goto err_dmaunmap; 3185 3186 if (host->pdata->num_slots) 3187 host->num_slots = host->pdata->num_slots; 3188 else 3189 host->num_slots = 1; 3190 3191 if (host->num_slots < 1 || 3192 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) { 3193 dev_err(host->dev, 3194 "Platform data must supply correct num_slots.\n"); 3195 ret = -ENODEV; 3196 goto err_clk_ciu; 3197 } 3198 3199 /* 3200 * Enable interrupts for command done, data over, data empty, 3201 * receive ready and error such as transmit, receive timeout, crc error 3202 */ 3203 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3204 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3205 DW_MCI_ERROR_FLAGS); 3206 /* Enable mci interrupt */ 3207 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3208 3209 dev_info(host->dev, 3210 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3211 host->irq, width, fifo_size); 3212 3213 /* We need at least one slot to succeed */ 3214 for (i = 0; i < host->num_slots; i++) { 3215 ret = dw_mci_init_slot(host, i); 3216 if (ret) 3217 dev_dbg(host->dev, "slot %d init failed\n", i); 3218 else 3219 init_slots++; 3220 } 3221 3222 if (init_slots) { 3223 dev_info(host->dev, "%d slots initialized\n", init_slots); 3224 } else { 3225 dev_dbg(host->dev, 3226 "attempted to initialize %d slots, but failed on all\n", 3227 host->num_slots); 3228 goto err_dmaunmap; 3229 } 3230 3231 /* Now that slots are all setup, we can enable card detect */ 3232 dw_mci_enable_cd(host); 3233 3234 return 0; 3235 3236 err_dmaunmap: 3237 if (host->use_dma && host->dma_ops->exit) 3238 host->dma_ops->exit(host); 3239 3240 if (!IS_ERR(host->pdata->rstc)) 3241 reset_control_assert(host->pdata->rstc); 3242 3243 err_clk_ciu: 3244 clk_disable_unprepare(host->ciu_clk); 3245 3246 err_clk_biu: 3247 clk_disable_unprepare(host->biu_clk); 3248 3249 return ret; 3250 } 3251 EXPORT_SYMBOL(dw_mci_probe); 3252 3253 void dw_mci_remove(struct dw_mci *host) 3254 { 3255 int i; 3256 3257 for (i = 0; i < host->num_slots; i++) { 3258 dev_dbg(host->dev, "remove slot %d\n", i); 3259 if (host->slot[i]) 3260 dw_mci_cleanup_slot(host->slot[i], i); 3261 } 3262 3263 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3264 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3265 3266 /* disable clock to CIU */ 3267 mci_writel(host, CLKENA, 0); 3268 mci_writel(host, CLKSRC, 0); 3269 3270 if (host->use_dma && host->dma_ops->exit) 3271 host->dma_ops->exit(host); 3272 3273 if (!IS_ERR(host->pdata->rstc)) 3274 reset_control_assert(host->pdata->rstc); 3275 3276 clk_disable_unprepare(host->ciu_clk); 3277 clk_disable_unprepare(host->biu_clk); 3278 } 3279 EXPORT_SYMBOL(dw_mci_remove); 3280 3281 3282 3283 #ifdef CONFIG_PM 3284 int dw_mci_runtime_suspend(struct device *dev) 3285 { 3286 struct dw_mci *host = dev_get_drvdata(dev); 3287 3288 if (host->use_dma && host->dma_ops->exit) 3289 host->dma_ops->exit(host); 3290 3291 clk_disable_unprepare(host->ciu_clk); 3292 3293 if (host->cur_slot && 3294 (mmc_can_gpio_cd(host->cur_slot->mmc) || 3295 !mmc_card_is_removable(host->cur_slot->mmc))) 3296 clk_disable_unprepare(host->biu_clk); 3297 3298 return 0; 3299 } 3300 EXPORT_SYMBOL(dw_mci_runtime_suspend); 3301 3302 int dw_mci_runtime_resume(struct device *dev) 3303 { 3304 int i, ret = 0; 3305 struct dw_mci *host = dev_get_drvdata(dev); 3306 3307 if (host->cur_slot && 3308 (mmc_can_gpio_cd(host->cur_slot->mmc) || 3309 !mmc_card_is_removable(host->cur_slot->mmc))) { 3310 ret = clk_prepare_enable(host->biu_clk); 3311 if (ret) 3312 return ret; 3313 } 3314 3315 ret = clk_prepare_enable(host->ciu_clk); 3316 if (ret) 3317 goto err; 3318 3319 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3320 clk_disable_unprepare(host->ciu_clk); 3321 ret = -ENODEV; 3322 goto err; 3323 } 3324 3325 if (host->use_dma && host->dma_ops->init) 3326 host->dma_ops->init(host); 3327 3328 /* 3329 * Restore the initial value at FIFOTH register 3330 * And Invalidate the prev_blksz with zero 3331 */ 3332 mci_writel(host, FIFOTH, host->fifoth_val); 3333 host->prev_blksz = 0; 3334 3335 /* Put in max timeout */ 3336 mci_writel(host, TMOUT, 0xFFFFFFFF); 3337 3338 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3339 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3340 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3341 DW_MCI_ERROR_FLAGS); 3342 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3343 3344 for (i = 0; i < host->num_slots; i++) { 3345 struct dw_mci_slot *slot = host->slot[i]; 3346 3347 if (!slot) 3348 continue; 3349 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3350 dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3351 3352 /* Force setup bus to guarantee available clock output */ 3353 dw_mci_setup_bus(slot, true); 3354 } 3355 3356 /* Now that slots are all setup, we can enable card detect */ 3357 dw_mci_enable_cd(host); 3358 3359 return 0; 3360 3361 err: 3362 if (host->cur_slot && 3363 (mmc_can_gpio_cd(host->cur_slot->mmc) || 3364 !mmc_card_is_removable(host->cur_slot->mmc))) 3365 clk_disable_unprepare(host->biu_clk); 3366 3367 return ret; 3368 } 3369 EXPORT_SYMBOL(dw_mci_runtime_resume); 3370 #endif /* CONFIG_PM */ 3371 3372 static int __init dw_mci_init(void) 3373 { 3374 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3375 return 0; 3376 } 3377 3378 static void __exit dw_mci_exit(void) 3379 { 3380 } 3381 3382 module_init(dw_mci_init); 3383 module_exit(dw_mci_exit); 3384 3385 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3386 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3387 MODULE_AUTHOR("Imagination Technologies Ltd"); 3388 MODULE_LICENSE("GPL v2"); 3389