1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/ioport.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/stat.h> 28 #include <linux/delay.h> 29 #include <linux/irq.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/sd.h> 34 #include <linux/mmc/sdio.h> 35 #include <linux/mmc/dw_mmc.h> 36 #include <linux/bitops.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/of.h> 39 #include <linux/of_gpio.h> 40 #include <linux/mmc/slot-gpio.h> 41 42 #include "dw_mmc.h" 43 44 /* Common flag combinations */ 45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 47 SDMMC_INT_EBE) 48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 49 SDMMC_INT_RESP_ERR) 50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 52 #define DW_MCI_SEND_STATUS 1 53 #define DW_MCI_RECV_STATUS 2 54 #define DW_MCI_DMA_THRESHOLD 16 55 56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ 58 59 #ifdef CONFIG_MMC_DW_IDMAC 60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 63 SDMMC_IDMAC_INT_TI) 64 65 struct idmac_desc_64addr { 66 u32 des0; /* Control Descriptor */ 67 68 u32 des1; /* Reserved */ 69 70 u32 des2; /*Buffer sizes */ 71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 74 75 u32 des3; /* Reserved */ 76 77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 79 80 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 81 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 82 }; 83 84 struct idmac_desc { 85 __le32 des0; /* Control Descriptor */ 86 #define IDMAC_DES0_DIC BIT(1) 87 #define IDMAC_DES0_LD BIT(2) 88 #define IDMAC_DES0_FD BIT(3) 89 #define IDMAC_DES0_CH BIT(4) 90 #define IDMAC_DES0_ER BIT(5) 91 #define IDMAC_DES0_CES BIT(30) 92 #define IDMAC_DES0_OWN BIT(31) 93 94 __le32 des1; /* Buffer sizes */ 95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 96 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 97 98 __le32 des2; /* buffer 1 physical address */ 99 100 __le32 des3; /* buffer 2 physical address */ 101 }; 102 103 /* Each descriptor can transfer up to 4KB of data in chained mode */ 104 #define DW_MCI_DESC_DATA_LENGTH 0x1000 105 #endif /* CONFIG_MMC_DW_IDMAC */ 106 107 static bool dw_mci_reset(struct dw_mci *host); 108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); 109 static int dw_mci_card_busy(struct mmc_host *mmc); 110 111 #if defined(CONFIG_DEBUG_FS) 112 static int dw_mci_req_show(struct seq_file *s, void *v) 113 { 114 struct dw_mci_slot *slot = s->private; 115 struct mmc_request *mrq; 116 struct mmc_command *cmd; 117 struct mmc_command *stop; 118 struct mmc_data *data; 119 120 /* Make sure we get a consistent snapshot */ 121 spin_lock_bh(&slot->host->lock); 122 mrq = slot->mrq; 123 124 if (mrq) { 125 cmd = mrq->cmd; 126 data = mrq->data; 127 stop = mrq->stop; 128 129 if (cmd) 130 seq_printf(s, 131 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 132 cmd->opcode, cmd->arg, cmd->flags, 133 cmd->resp[0], cmd->resp[1], cmd->resp[2], 134 cmd->resp[2], cmd->error); 135 if (data) 136 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 137 data->bytes_xfered, data->blocks, 138 data->blksz, data->flags, data->error); 139 if (stop) 140 seq_printf(s, 141 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 142 stop->opcode, stop->arg, stop->flags, 143 stop->resp[0], stop->resp[1], stop->resp[2], 144 stop->resp[2], stop->error); 145 } 146 147 spin_unlock_bh(&slot->host->lock); 148 149 return 0; 150 } 151 152 static int dw_mci_req_open(struct inode *inode, struct file *file) 153 { 154 return single_open(file, dw_mci_req_show, inode->i_private); 155 } 156 157 static const struct file_operations dw_mci_req_fops = { 158 .owner = THIS_MODULE, 159 .open = dw_mci_req_open, 160 .read = seq_read, 161 .llseek = seq_lseek, 162 .release = single_release, 163 }; 164 165 static int dw_mci_regs_show(struct seq_file *s, void *v) 166 { 167 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 168 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 169 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 170 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 171 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 172 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 173 174 return 0; 175 } 176 177 static int dw_mci_regs_open(struct inode *inode, struct file *file) 178 { 179 return single_open(file, dw_mci_regs_show, inode->i_private); 180 } 181 182 static const struct file_operations dw_mci_regs_fops = { 183 .owner = THIS_MODULE, 184 .open = dw_mci_regs_open, 185 .read = seq_read, 186 .llseek = seq_lseek, 187 .release = single_release, 188 }; 189 190 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 191 { 192 struct mmc_host *mmc = slot->mmc; 193 struct dw_mci *host = slot->host; 194 struct dentry *root; 195 struct dentry *node; 196 197 root = mmc->debugfs_root; 198 if (!root) 199 return; 200 201 node = debugfs_create_file("regs", S_IRUSR, root, host, 202 &dw_mci_regs_fops); 203 if (!node) 204 goto err; 205 206 node = debugfs_create_file("req", S_IRUSR, root, slot, 207 &dw_mci_req_fops); 208 if (!node) 209 goto err; 210 211 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 212 if (!node) 213 goto err; 214 215 node = debugfs_create_x32("pending_events", S_IRUSR, root, 216 (u32 *)&host->pending_events); 217 if (!node) 218 goto err; 219 220 node = debugfs_create_x32("completed_events", S_IRUSR, root, 221 (u32 *)&host->completed_events); 222 if (!node) 223 goto err; 224 225 return; 226 227 err: 228 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 229 } 230 #endif /* defined(CONFIG_DEBUG_FS) */ 231 232 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); 233 234 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 235 { 236 struct mmc_data *data; 237 struct dw_mci_slot *slot = mmc_priv(mmc); 238 struct dw_mci *host = slot->host; 239 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 240 u32 cmdr; 241 242 cmd->error = -EINPROGRESS; 243 cmdr = cmd->opcode; 244 245 if (cmd->opcode == MMC_STOP_TRANSMISSION || 246 cmd->opcode == MMC_GO_IDLE_STATE || 247 cmd->opcode == MMC_GO_INACTIVE_STATE || 248 (cmd->opcode == SD_IO_RW_DIRECT && 249 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 250 cmdr |= SDMMC_CMD_STOP; 251 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 252 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 253 254 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 255 u32 clk_en_a; 256 257 /* Special bit makes CMD11 not die */ 258 cmdr |= SDMMC_CMD_VOLT_SWITCH; 259 260 /* Change state to continue to handle CMD11 weirdness */ 261 WARN_ON(slot->host->state != STATE_SENDING_CMD); 262 slot->host->state = STATE_SENDING_CMD11; 263 264 /* 265 * We need to disable low power mode (automatic clock stop) 266 * while doing voltage switch so we don't confuse the card, 267 * since stopping the clock is a specific part of the UHS 268 * voltage change dance. 269 * 270 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 271 * unconditionally turned back on in dw_mci_setup_bus() if it's 272 * ever called with a non-zero clock. That shouldn't happen 273 * until the voltage change is all done. 274 */ 275 clk_en_a = mci_readl(host, CLKENA); 276 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 277 mci_writel(host, CLKENA, clk_en_a); 278 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 279 SDMMC_CMD_PRV_DAT_WAIT, 0); 280 } 281 282 if (cmd->flags & MMC_RSP_PRESENT) { 283 /* We expect a response, so set this bit */ 284 cmdr |= SDMMC_CMD_RESP_EXP; 285 if (cmd->flags & MMC_RSP_136) 286 cmdr |= SDMMC_CMD_RESP_LONG; 287 } 288 289 if (cmd->flags & MMC_RSP_CRC) 290 cmdr |= SDMMC_CMD_RESP_CRC; 291 292 data = cmd->data; 293 if (data) { 294 cmdr |= SDMMC_CMD_DAT_EXP; 295 if (data->flags & MMC_DATA_STREAM) 296 cmdr |= SDMMC_CMD_STRM_MODE; 297 if (data->flags & MMC_DATA_WRITE) 298 cmdr |= SDMMC_CMD_DAT_WR; 299 } 300 301 if (drv_data && drv_data->prepare_command) 302 drv_data->prepare_command(slot->host, &cmdr); 303 304 return cmdr; 305 } 306 307 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 308 { 309 struct mmc_command *stop; 310 u32 cmdr; 311 312 if (!cmd->data) 313 return 0; 314 315 stop = &host->stop_abort; 316 cmdr = cmd->opcode; 317 memset(stop, 0, sizeof(struct mmc_command)); 318 319 if (cmdr == MMC_READ_SINGLE_BLOCK || 320 cmdr == MMC_READ_MULTIPLE_BLOCK || 321 cmdr == MMC_WRITE_BLOCK || 322 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 323 cmdr == MMC_SEND_TUNING_BLOCK || 324 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 325 stop->opcode = MMC_STOP_TRANSMISSION; 326 stop->arg = 0; 327 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 328 } else if (cmdr == SD_IO_RW_EXTENDED) { 329 stop->opcode = SD_IO_RW_DIRECT; 330 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 331 ((cmd->arg >> 28) & 0x7); 332 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 333 } else { 334 return 0; 335 } 336 337 cmdr = stop->opcode | SDMMC_CMD_STOP | 338 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 339 340 return cmdr; 341 } 342 343 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 344 { 345 unsigned long timeout = jiffies + msecs_to_jiffies(500); 346 347 /* 348 * Databook says that before issuing a new data transfer command 349 * we need to check to see if the card is busy. Data transfer commands 350 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 351 * 352 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 353 * expected. 354 */ 355 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 356 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 357 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { 358 if (time_after(jiffies, timeout)) { 359 /* Command will fail; we'll pass error then */ 360 dev_err(host->dev, "Busy; trying anyway\n"); 361 break; 362 } 363 udelay(10); 364 } 365 } 366 } 367 368 static void dw_mci_start_command(struct dw_mci *host, 369 struct mmc_command *cmd, u32 cmd_flags) 370 { 371 host->cmd = cmd; 372 dev_vdbg(host->dev, 373 "start command: ARGR=0x%08x CMDR=0x%08x\n", 374 cmd->arg, cmd_flags); 375 376 mci_writel(host, CMDARG, cmd->arg); 377 wmb(); /* drain writebuffer */ 378 dw_mci_wait_while_busy(host, cmd_flags); 379 380 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 381 } 382 383 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 384 { 385 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; 386 387 dw_mci_start_command(host, stop, host->stop_cmdr); 388 } 389 390 /* DMA interface functions */ 391 static void dw_mci_stop_dma(struct dw_mci *host) 392 { 393 if (host->using_dma) { 394 host->dma_ops->stop(host); 395 host->dma_ops->cleanup(host); 396 } 397 398 /* Data transfer was stopped by the interrupt handler */ 399 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 400 } 401 402 static int dw_mci_get_dma_dir(struct mmc_data *data) 403 { 404 if (data->flags & MMC_DATA_WRITE) 405 return DMA_TO_DEVICE; 406 else 407 return DMA_FROM_DEVICE; 408 } 409 410 #ifdef CONFIG_MMC_DW_IDMAC 411 static void dw_mci_dma_cleanup(struct dw_mci *host) 412 { 413 struct mmc_data *data = host->data; 414 415 if (data) 416 if (!data->host_cookie) 417 dma_unmap_sg(host->dev, 418 data->sg, 419 data->sg_len, 420 dw_mci_get_dma_dir(data)); 421 } 422 423 static void dw_mci_idmac_reset(struct dw_mci *host) 424 { 425 u32 bmod = mci_readl(host, BMOD); 426 /* Software reset of DMA */ 427 bmod |= SDMMC_IDMAC_SWRESET; 428 mci_writel(host, BMOD, bmod); 429 } 430 431 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 432 { 433 u32 temp; 434 435 /* Disable and reset the IDMAC interface */ 436 temp = mci_readl(host, CTRL); 437 temp &= ~SDMMC_CTRL_USE_IDMAC; 438 temp |= SDMMC_CTRL_DMA_RESET; 439 mci_writel(host, CTRL, temp); 440 441 /* Stop the IDMAC running */ 442 temp = mci_readl(host, BMOD); 443 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 444 temp |= SDMMC_IDMAC_SWRESET; 445 mci_writel(host, BMOD, temp); 446 } 447 448 static void dw_mci_idmac_complete_dma(struct dw_mci *host) 449 { 450 struct mmc_data *data = host->data; 451 452 dev_vdbg(host->dev, "DMA complete\n"); 453 454 host->dma_ops->cleanup(host); 455 456 /* 457 * If the card was removed, data will be NULL. No point in trying to 458 * send the stop command or waiting for NBUSY in this case. 459 */ 460 if (data) { 461 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 462 tasklet_schedule(&host->tasklet); 463 } 464 } 465 466 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 467 unsigned int sg_len) 468 { 469 unsigned int desc_len; 470 int i; 471 472 if (host->dma_64bit_address == 1) { 473 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 474 475 desc_first = desc_last = desc = host->sg_cpu; 476 477 for (i = 0; i < sg_len; i++) { 478 unsigned int length = sg_dma_len(&data->sg[i]); 479 480 u64 mem_addr = sg_dma_address(&data->sg[i]); 481 482 for ( ; length ; desc++) { 483 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 484 length : DW_MCI_DESC_DATA_LENGTH; 485 486 length -= desc_len; 487 488 /* 489 * Set the OWN bit and disable interrupts 490 * for this descriptor 491 */ 492 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 493 IDMAC_DES0_CH; 494 495 /* Buffer length */ 496 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 497 498 /* Physical address to DMA to/from */ 499 desc->des4 = mem_addr & 0xffffffff; 500 desc->des5 = mem_addr >> 32; 501 502 /* Update physical address for the next desc */ 503 mem_addr += desc_len; 504 505 /* Save pointer to the last descriptor */ 506 desc_last = desc; 507 } 508 } 509 510 /* Set first descriptor */ 511 desc_first->des0 |= IDMAC_DES0_FD; 512 513 /* Set last descriptor */ 514 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 515 desc_last->des0 |= IDMAC_DES0_LD; 516 517 } else { 518 struct idmac_desc *desc_first, *desc_last, *desc; 519 520 desc_first = desc_last = desc = host->sg_cpu; 521 522 for (i = 0; i < sg_len; i++) { 523 unsigned int length = sg_dma_len(&data->sg[i]); 524 525 u32 mem_addr = sg_dma_address(&data->sg[i]); 526 527 for ( ; length ; desc++) { 528 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 529 length : DW_MCI_DESC_DATA_LENGTH; 530 531 length -= desc_len; 532 533 /* 534 * Set the OWN bit and disable interrupts 535 * for this descriptor 536 */ 537 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 538 IDMAC_DES0_DIC | 539 IDMAC_DES0_CH); 540 541 /* Buffer length */ 542 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 543 544 /* Physical address to DMA to/from */ 545 desc->des2 = cpu_to_le32(mem_addr); 546 547 /* Update physical address for the next desc */ 548 mem_addr += desc_len; 549 550 /* Save pointer to the last descriptor */ 551 desc_last = desc; 552 } 553 } 554 555 /* Set first descriptor */ 556 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 557 558 /* Set last descriptor */ 559 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 560 IDMAC_DES0_DIC)); 561 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 562 } 563 564 wmb(); /* drain writebuffer */ 565 } 566 567 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 568 { 569 u32 temp; 570 571 dw_mci_translate_sglist(host, host->data, sg_len); 572 573 /* Make sure to reset DMA in case we did PIO before this */ 574 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 575 dw_mci_idmac_reset(host); 576 577 /* Select IDMAC interface */ 578 temp = mci_readl(host, CTRL); 579 temp |= SDMMC_CTRL_USE_IDMAC; 580 mci_writel(host, CTRL, temp); 581 582 /* drain writebuffer */ 583 wmb(); 584 585 /* Enable the IDMAC */ 586 temp = mci_readl(host, BMOD); 587 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 588 mci_writel(host, BMOD, temp); 589 590 /* Start it running */ 591 mci_writel(host, PLDMND, 1); 592 } 593 594 static int dw_mci_idmac_init(struct dw_mci *host) 595 { 596 int i; 597 598 if (host->dma_64bit_address == 1) { 599 struct idmac_desc_64addr *p; 600 /* Number of descriptors in the ring buffer */ 601 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); 602 603 /* Forward link the descriptor list */ 604 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 605 i++, p++) { 606 p->des6 = (host->sg_dma + 607 (sizeof(struct idmac_desc_64addr) * 608 (i + 1))) & 0xffffffff; 609 610 p->des7 = (u64)(host->sg_dma + 611 (sizeof(struct idmac_desc_64addr) * 612 (i + 1))) >> 32; 613 /* Initialize reserved and buffer size fields to "0" */ 614 p->des1 = 0; 615 p->des2 = 0; 616 p->des3 = 0; 617 } 618 619 /* Set the last descriptor as the end-of-ring descriptor */ 620 p->des6 = host->sg_dma & 0xffffffff; 621 p->des7 = (u64)host->sg_dma >> 32; 622 p->des0 = IDMAC_DES0_ER; 623 624 } else { 625 struct idmac_desc *p; 626 /* Number of descriptors in the ring buffer */ 627 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 628 629 /* Forward link the descriptor list */ 630 for (i = 0, p = host->sg_cpu; 631 i < host->ring_size - 1; 632 i++, p++) { 633 p->des3 = cpu_to_le32(host->sg_dma + 634 (sizeof(struct idmac_desc) * (i + 1))); 635 p->des1 = 0; 636 } 637 638 /* Set the last descriptor as the end-of-ring descriptor */ 639 p->des3 = cpu_to_le32(host->sg_dma); 640 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 641 } 642 643 dw_mci_idmac_reset(host); 644 645 if (host->dma_64bit_address == 1) { 646 /* Mask out interrupts - get Tx & Rx complete only */ 647 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 648 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 649 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 650 651 /* Set the descriptor base address */ 652 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 653 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 654 655 } else { 656 /* Mask out interrupts - get Tx & Rx complete only */ 657 mci_writel(host, IDSTS, IDMAC_INT_CLR); 658 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 659 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 660 661 /* Set the descriptor base address */ 662 mci_writel(host, DBADDR, host->sg_dma); 663 } 664 665 return 0; 666 } 667 668 static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 669 .init = dw_mci_idmac_init, 670 .start = dw_mci_idmac_start_dma, 671 .stop = dw_mci_idmac_stop_dma, 672 .complete = dw_mci_idmac_complete_dma, 673 .cleanup = dw_mci_dma_cleanup, 674 }; 675 #endif /* CONFIG_MMC_DW_IDMAC */ 676 677 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 678 struct mmc_data *data, 679 bool next) 680 { 681 struct scatterlist *sg; 682 unsigned int i, sg_len; 683 684 if (!next && data->host_cookie) 685 return data->host_cookie; 686 687 /* 688 * We don't do DMA on "complex" transfers, i.e. with 689 * non-word-aligned buffers or lengths. Also, we don't bother 690 * with all the DMA setup overhead for short transfers. 691 */ 692 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 693 return -EINVAL; 694 695 if (data->blksz & 3) 696 return -EINVAL; 697 698 for_each_sg(data->sg, sg, data->sg_len, i) { 699 if (sg->offset & 3 || sg->length & 3) 700 return -EINVAL; 701 } 702 703 sg_len = dma_map_sg(host->dev, 704 data->sg, 705 data->sg_len, 706 dw_mci_get_dma_dir(data)); 707 if (sg_len == 0) 708 return -EINVAL; 709 710 if (next) 711 data->host_cookie = sg_len; 712 713 return sg_len; 714 } 715 716 static void dw_mci_pre_req(struct mmc_host *mmc, 717 struct mmc_request *mrq, 718 bool is_first_req) 719 { 720 struct dw_mci_slot *slot = mmc_priv(mmc); 721 struct mmc_data *data = mrq->data; 722 723 if (!slot->host->use_dma || !data) 724 return; 725 726 if (data->host_cookie) { 727 data->host_cookie = 0; 728 return; 729 } 730 731 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 732 data->host_cookie = 0; 733 } 734 735 static void dw_mci_post_req(struct mmc_host *mmc, 736 struct mmc_request *mrq, 737 int err) 738 { 739 struct dw_mci_slot *slot = mmc_priv(mmc); 740 struct mmc_data *data = mrq->data; 741 742 if (!slot->host->use_dma || !data) 743 return; 744 745 if (data->host_cookie) 746 dma_unmap_sg(slot->host->dev, 747 data->sg, 748 data->sg_len, 749 dw_mci_get_dma_dir(data)); 750 data->host_cookie = 0; 751 } 752 753 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 754 { 755 #ifdef CONFIG_MMC_DW_IDMAC 756 unsigned int blksz = data->blksz; 757 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 758 u32 fifo_width = 1 << host->data_shift; 759 u32 blksz_depth = blksz / fifo_width, fifoth_val; 760 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 761 int idx = ARRAY_SIZE(mszs) - 1; 762 763 tx_wmark = (host->fifo_depth) / 2; 764 tx_wmark_invers = host->fifo_depth - tx_wmark; 765 766 /* 767 * MSIZE is '1', 768 * if blksz is not a multiple of the FIFO width 769 */ 770 if (blksz % fifo_width) { 771 msize = 0; 772 rx_wmark = 1; 773 goto done; 774 } 775 776 do { 777 if (!((blksz_depth % mszs[idx]) || 778 (tx_wmark_invers % mszs[idx]))) { 779 msize = idx; 780 rx_wmark = mszs[idx] - 1; 781 break; 782 } 783 } while (--idx > 0); 784 /* 785 * If idx is '0', it won't be tried 786 * Thus, initial values are uesed 787 */ 788 done: 789 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 790 mci_writel(host, FIFOTH, fifoth_val); 791 #endif 792 } 793 794 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) 795 { 796 unsigned int blksz = data->blksz; 797 u32 blksz_depth, fifo_depth; 798 u16 thld_size; 799 800 WARN_ON(!(data->flags & MMC_DATA_READ)); 801 802 /* 803 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 804 * in the FIFO region, so we really shouldn't access it). 805 */ 806 if (host->verid < DW_MMC_240A) 807 return; 808 809 if (host->timing != MMC_TIMING_MMC_HS200 && 810 host->timing != MMC_TIMING_MMC_HS400 && 811 host->timing != MMC_TIMING_UHS_SDR104) 812 goto disable; 813 814 blksz_depth = blksz / (1 << host->data_shift); 815 fifo_depth = host->fifo_depth; 816 817 if (blksz_depth > fifo_depth) 818 goto disable; 819 820 /* 821 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 822 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 823 * Currently just choose blksz. 824 */ 825 thld_size = blksz; 826 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); 827 return; 828 829 disable: 830 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); 831 } 832 833 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 834 { 835 unsigned long irqflags; 836 int sg_len; 837 u32 temp; 838 839 host->using_dma = 0; 840 841 /* If we don't have a channel, we can't do DMA */ 842 if (!host->use_dma) 843 return -ENODEV; 844 845 sg_len = dw_mci_pre_dma_transfer(host, data, 0); 846 if (sg_len < 0) { 847 host->dma_ops->stop(host); 848 return sg_len; 849 } 850 851 host->using_dma = 1; 852 853 dev_vdbg(host->dev, 854 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 855 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 856 sg_len); 857 858 /* 859 * Decide the MSIZE and RX/TX Watermark. 860 * If current block size is same with previous size, 861 * no need to update fifoth. 862 */ 863 if (host->prev_blksz != data->blksz) 864 dw_mci_adjust_fifoth(host, data); 865 866 /* Enable the DMA interface */ 867 temp = mci_readl(host, CTRL); 868 temp |= SDMMC_CTRL_DMA_ENABLE; 869 mci_writel(host, CTRL, temp); 870 871 /* Disable RX/TX IRQs, let DMA handle it */ 872 spin_lock_irqsave(&host->irq_lock, irqflags); 873 temp = mci_readl(host, INTMASK); 874 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 875 mci_writel(host, INTMASK, temp); 876 spin_unlock_irqrestore(&host->irq_lock, irqflags); 877 878 host->dma_ops->start(host, sg_len); 879 880 return 0; 881 } 882 883 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 884 { 885 unsigned long irqflags; 886 int flags = SG_MITER_ATOMIC; 887 u32 temp; 888 889 data->error = -EINPROGRESS; 890 891 WARN_ON(host->data); 892 host->sg = NULL; 893 host->data = data; 894 895 if (data->flags & MMC_DATA_READ) { 896 host->dir_status = DW_MCI_RECV_STATUS; 897 dw_mci_ctrl_rd_thld(host, data); 898 } else { 899 host->dir_status = DW_MCI_SEND_STATUS; 900 } 901 902 if (dw_mci_submit_data_dma(host, data)) { 903 if (host->data->flags & MMC_DATA_READ) 904 flags |= SG_MITER_TO_SG; 905 else 906 flags |= SG_MITER_FROM_SG; 907 908 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 909 host->sg = data->sg; 910 host->part_buf_start = 0; 911 host->part_buf_count = 0; 912 913 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 914 915 spin_lock_irqsave(&host->irq_lock, irqflags); 916 temp = mci_readl(host, INTMASK); 917 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 918 mci_writel(host, INTMASK, temp); 919 spin_unlock_irqrestore(&host->irq_lock, irqflags); 920 921 temp = mci_readl(host, CTRL); 922 temp &= ~SDMMC_CTRL_DMA_ENABLE; 923 mci_writel(host, CTRL, temp); 924 925 /* 926 * Use the initial fifoth_val for PIO mode. 927 * If next issued data may be transfered by DMA mode, 928 * prev_blksz should be invalidated. 929 */ 930 mci_writel(host, FIFOTH, host->fifoth_val); 931 host->prev_blksz = 0; 932 } else { 933 /* 934 * Keep the current block size. 935 * It will be used to decide whether to update 936 * fifoth register next time. 937 */ 938 host->prev_blksz = data->blksz; 939 } 940 } 941 942 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 943 { 944 struct dw_mci *host = slot->host; 945 unsigned long timeout = jiffies + msecs_to_jiffies(500); 946 unsigned int cmd_status = 0; 947 948 mci_writel(host, CMDARG, arg); 949 wmb(); /* drain writebuffer */ 950 dw_mci_wait_while_busy(host, cmd); 951 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 952 953 while (time_before(jiffies, timeout)) { 954 cmd_status = mci_readl(host, CMD); 955 if (!(cmd_status & SDMMC_CMD_START)) 956 return; 957 } 958 dev_err(&slot->mmc->class_dev, 959 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 960 cmd, arg, cmd_status); 961 } 962 963 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 964 { 965 struct dw_mci *host = slot->host; 966 unsigned int clock = slot->clock; 967 u32 div; 968 u32 clk_en_a; 969 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 970 971 /* We must continue to set bit 28 in CMD until the change is complete */ 972 if (host->state == STATE_WAITING_CMD11_DONE) 973 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 974 975 if (!clock) { 976 mci_writel(host, CLKENA, 0); 977 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 978 } else if (clock != host->current_speed || force_clkinit) { 979 div = host->bus_hz / clock; 980 if (host->bus_hz % clock && host->bus_hz > clock) 981 /* 982 * move the + 1 after the divide to prevent 983 * over-clocking the card. 984 */ 985 div += 1; 986 987 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 988 989 if ((clock << div) != slot->__clk_old || force_clkinit) 990 dev_info(&slot->mmc->class_dev, 991 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 992 slot->id, host->bus_hz, clock, 993 div ? ((host->bus_hz / div) >> 1) : 994 host->bus_hz, div); 995 996 /* disable clock */ 997 mci_writel(host, CLKENA, 0); 998 mci_writel(host, CLKSRC, 0); 999 1000 /* inform CIU */ 1001 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1002 1003 /* set clock to desired speed */ 1004 mci_writel(host, CLKDIV, div); 1005 1006 /* inform CIU */ 1007 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1008 1009 /* enable clock; only low power if no SDIO */ 1010 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1011 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1012 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1013 mci_writel(host, CLKENA, clk_en_a); 1014 1015 /* inform CIU */ 1016 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1017 1018 /* keep the clock with reflecting clock dividor */ 1019 slot->__clk_old = clock << div; 1020 } 1021 1022 host->current_speed = clock; 1023 1024 /* Set the current slot bus width */ 1025 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1026 } 1027 1028 static void __dw_mci_start_request(struct dw_mci *host, 1029 struct dw_mci_slot *slot, 1030 struct mmc_command *cmd) 1031 { 1032 struct mmc_request *mrq; 1033 struct mmc_data *data; 1034 u32 cmdflags; 1035 1036 mrq = slot->mrq; 1037 1038 host->cur_slot = slot; 1039 host->mrq = mrq; 1040 1041 host->pending_events = 0; 1042 host->completed_events = 0; 1043 host->cmd_status = 0; 1044 host->data_status = 0; 1045 host->dir_status = 0; 1046 1047 data = cmd->data; 1048 if (data) { 1049 mci_writel(host, TMOUT, 0xFFFFFFFF); 1050 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1051 mci_writel(host, BLKSIZ, data->blksz); 1052 } 1053 1054 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1055 1056 /* this is the first command, send the initialization clock */ 1057 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1058 cmdflags |= SDMMC_CMD_INIT; 1059 1060 if (data) { 1061 dw_mci_submit_data(host, data); 1062 wmb(); /* drain writebuffer */ 1063 } 1064 1065 dw_mci_start_command(host, cmd, cmdflags); 1066 1067 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1068 unsigned long irqflags; 1069 1070 /* 1071 * Databook says to fail after 2ms w/ no response, but evidence 1072 * shows that sometimes the cmd11 interrupt takes over 130ms. 1073 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1074 * is just about to roll over. 1075 * 1076 * We do this whole thing under spinlock and only if the 1077 * command hasn't already completed (indicating the the irq 1078 * already ran so we don't want the timeout). 1079 */ 1080 spin_lock_irqsave(&host->irq_lock, irqflags); 1081 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1082 mod_timer(&host->cmd11_timer, 1083 jiffies + msecs_to_jiffies(500) + 1); 1084 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1085 } 1086 1087 if (mrq->stop) 1088 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 1089 else 1090 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1091 } 1092 1093 static void dw_mci_start_request(struct dw_mci *host, 1094 struct dw_mci_slot *slot) 1095 { 1096 struct mmc_request *mrq = slot->mrq; 1097 struct mmc_command *cmd; 1098 1099 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1100 __dw_mci_start_request(host, slot, cmd); 1101 } 1102 1103 /* must be called with host->lock held */ 1104 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1105 struct mmc_request *mrq) 1106 { 1107 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1108 host->state); 1109 1110 slot->mrq = mrq; 1111 1112 if (host->state == STATE_WAITING_CMD11_DONE) { 1113 dev_warn(&slot->mmc->class_dev, 1114 "Voltage change didn't complete\n"); 1115 /* 1116 * this case isn't expected to happen, so we can 1117 * either crash here or just try to continue on 1118 * in the closest possible state 1119 */ 1120 host->state = STATE_IDLE; 1121 } 1122 1123 if (host->state == STATE_IDLE) { 1124 host->state = STATE_SENDING_CMD; 1125 dw_mci_start_request(host, slot); 1126 } else { 1127 list_add_tail(&slot->queue_node, &host->queue); 1128 } 1129 } 1130 1131 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1132 { 1133 struct dw_mci_slot *slot = mmc_priv(mmc); 1134 struct dw_mci *host = slot->host; 1135 1136 WARN_ON(slot->mrq); 1137 1138 /* 1139 * The check for card presence and queueing of the request must be 1140 * atomic, otherwise the card could be removed in between and the 1141 * request wouldn't fail until another card was inserted. 1142 */ 1143 spin_lock_bh(&host->lock); 1144 1145 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 1146 spin_unlock_bh(&host->lock); 1147 mrq->cmd->error = -ENOMEDIUM; 1148 mmc_request_done(mmc, mrq); 1149 return; 1150 } 1151 1152 dw_mci_queue_request(host, slot, mrq); 1153 1154 spin_unlock_bh(&host->lock); 1155 } 1156 1157 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1158 { 1159 struct dw_mci_slot *slot = mmc_priv(mmc); 1160 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1161 u32 regs; 1162 int ret; 1163 1164 switch (ios->bus_width) { 1165 case MMC_BUS_WIDTH_4: 1166 slot->ctype = SDMMC_CTYPE_4BIT; 1167 break; 1168 case MMC_BUS_WIDTH_8: 1169 slot->ctype = SDMMC_CTYPE_8BIT; 1170 break; 1171 default: 1172 /* set default 1 bit mode */ 1173 slot->ctype = SDMMC_CTYPE_1BIT; 1174 } 1175 1176 regs = mci_readl(slot->host, UHS_REG); 1177 1178 /* DDR mode set */ 1179 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1180 ios->timing == MMC_TIMING_MMC_HS400) 1181 regs |= ((0x1 << slot->id) << 16); 1182 else 1183 regs &= ~((0x1 << slot->id) << 16); 1184 1185 mci_writel(slot->host, UHS_REG, regs); 1186 slot->host->timing = ios->timing; 1187 1188 /* 1189 * Use mirror of ios->clock to prevent race with mmc 1190 * core ios update when finding the minimum. 1191 */ 1192 slot->clock = ios->clock; 1193 1194 if (drv_data && drv_data->set_ios) 1195 drv_data->set_ios(slot->host, ios); 1196 1197 switch (ios->power_mode) { 1198 case MMC_POWER_UP: 1199 if (!IS_ERR(mmc->supply.vmmc)) { 1200 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1201 ios->vdd); 1202 if (ret) { 1203 dev_err(slot->host->dev, 1204 "failed to enable vmmc regulator\n"); 1205 /*return, if failed turn on vmmc*/ 1206 return; 1207 } 1208 } 1209 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1210 regs = mci_readl(slot->host, PWREN); 1211 regs |= (1 << slot->id); 1212 mci_writel(slot->host, PWREN, regs); 1213 break; 1214 case MMC_POWER_ON: 1215 if (!slot->host->vqmmc_enabled) { 1216 if (!IS_ERR(mmc->supply.vqmmc)) { 1217 ret = regulator_enable(mmc->supply.vqmmc); 1218 if (ret < 0) 1219 dev_err(slot->host->dev, 1220 "failed to enable vqmmc\n"); 1221 else 1222 slot->host->vqmmc_enabled = true; 1223 1224 } else { 1225 /* Keep track so we don't reset again */ 1226 slot->host->vqmmc_enabled = true; 1227 } 1228 1229 /* Reset our state machine after powering on */ 1230 dw_mci_ctrl_reset(slot->host, 1231 SDMMC_CTRL_ALL_RESET_FLAGS); 1232 } 1233 1234 /* Adjust clock / bus width after power is up */ 1235 dw_mci_setup_bus(slot, false); 1236 1237 break; 1238 case MMC_POWER_OFF: 1239 /* Turn clock off before power goes down */ 1240 dw_mci_setup_bus(slot, false); 1241 1242 if (!IS_ERR(mmc->supply.vmmc)) 1243 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1244 1245 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1246 regulator_disable(mmc->supply.vqmmc); 1247 slot->host->vqmmc_enabled = false; 1248 1249 regs = mci_readl(slot->host, PWREN); 1250 regs &= ~(1 << slot->id); 1251 mci_writel(slot->host, PWREN, regs); 1252 break; 1253 default: 1254 break; 1255 } 1256 1257 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1258 slot->host->state = STATE_IDLE; 1259 } 1260 1261 static int dw_mci_card_busy(struct mmc_host *mmc) 1262 { 1263 struct dw_mci_slot *slot = mmc_priv(mmc); 1264 u32 status; 1265 1266 /* 1267 * Check the busy bit which is low when DAT[3:0] 1268 * (the data lines) are 0000 1269 */ 1270 status = mci_readl(slot->host, STATUS); 1271 1272 return !!(status & SDMMC_STATUS_BUSY); 1273 } 1274 1275 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1276 { 1277 struct dw_mci_slot *slot = mmc_priv(mmc); 1278 struct dw_mci *host = slot->host; 1279 const struct dw_mci_drv_data *drv_data = host->drv_data; 1280 u32 uhs; 1281 u32 v18 = SDMMC_UHS_18V << slot->id; 1282 int min_uv, max_uv; 1283 int ret; 1284 1285 if (drv_data && drv_data->switch_voltage) 1286 return drv_data->switch_voltage(mmc, ios); 1287 1288 /* 1289 * Program the voltage. Note that some instances of dw_mmc may use 1290 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1291 * does no harm but you need to set the regulator directly. Try both. 1292 */ 1293 uhs = mci_readl(host, UHS_REG); 1294 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1295 min_uv = 2700000; 1296 max_uv = 3600000; 1297 uhs &= ~v18; 1298 } else { 1299 min_uv = 1700000; 1300 max_uv = 1950000; 1301 uhs |= v18; 1302 } 1303 if (!IS_ERR(mmc->supply.vqmmc)) { 1304 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 1305 1306 if (ret) { 1307 dev_dbg(&mmc->class_dev, 1308 "Regulator set error %d: %d - %d\n", 1309 ret, min_uv, max_uv); 1310 return ret; 1311 } 1312 } 1313 mci_writel(host, UHS_REG, uhs); 1314 1315 return 0; 1316 } 1317 1318 static int dw_mci_get_ro(struct mmc_host *mmc) 1319 { 1320 int read_only; 1321 struct dw_mci_slot *slot = mmc_priv(mmc); 1322 int gpio_ro = mmc_gpio_get_ro(mmc); 1323 1324 /* Use platform get_ro function, else try on board write protect */ 1325 if (!IS_ERR_VALUE(gpio_ro)) 1326 read_only = gpio_ro; 1327 else 1328 read_only = 1329 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1330 1331 dev_dbg(&mmc->class_dev, "card is %s\n", 1332 read_only ? "read-only" : "read-write"); 1333 1334 return read_only; 1335 } 1336 1337 static int dw_mci_get_cd(struct mmc_host *mmc) 1338 { 1339 int present; 1340 struct dw_mci_slot *slot = mmc_priv(mmc); 1341 struct dw_mci_board *brd = slot->host->pdata; 1342 struct dw_mci *host = slot->host; 1343 int gpio_cd = mmc_gpio_get_cd(mmc); 1344 1345 /* Use platform get_cd function, else try onboard card detect */ 1346 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) || 1347 (mmc->caps & MMC_CAP_NONREMOVABLE)) 1348 present = 1; 1349 else if (!IS_ERR_VALUE(gpio_cd)) 1350 present = gpio_cd; 1351 else 1352 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 1353 == 0 ? 1 : 0; 1354 1355 spin_lock_bh(&host->lock); 1356 if (present) { 1357 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1358 dev_dbg(&mmc->class_dev, "card is present\n"); 1359 } else { 1360 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1361 dev_dbg(&mmc->class_dev, "card is not present\n"); 1362 } 1363 spin_unlock_bh(&host->lock); 1364 1365 return present; 1366 } 1367 1368 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1369 { 1370 struct dw_mci_slot *slot = mmc_priv(mmc); 1371 struct dw_mci *host = slot->host; 1372 1373 /* 1374 * Low power mode will stop the card clock when idle. According to the 1375 * description of the CLKENA register we should disable low power mode 1376 * for SDIO cards if we need SDIO interrupts to work. 1377 */ 1378 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1379 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1380 u32 clk_en_a_old; 1381 u32 clk_en_a; 1382 1383 clk_en_a_old = mci_readl(host, CLKENA); 1384 1385 if (card->type == MMC_TYPE_SDIO || 1386 card->type == MMC_TYPE_SD_COMBO) { 1387 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1388 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1389 } else { 1390 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1391 clk_en_a = clk_en_a_old | clken_low_pwr; 1392 } 1393 1394 if (clk_en_a != clk_en_a_old) { 1395 mci_writel(host, CLKENA, clk_en_a); 1396 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1397 SDMMC_CMD_PRV_DAT_WAIT, 0); 1398 } 1399 } 1400 } 1401 1402 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1403 { 1404 struct dw_mci_slot *slot = mmc_priv(mmc); 1405 struct dw_mci *host = slot->host; 1406 unsigned long irqflags; 1407 u32 int_mask; 1408 1409 spin_lock_irqsave(&host->irq_lock, irqflags); 1410 1411 /* Enable/disable Slot Specific SDIO interrupt */ 1412 int_mask = mci_readl(host, INTMASK); 1413 if (enb) 1414 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1415 else 1416 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1417 mci_writel(host, INTMASK, int_mask); 1418 1419 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1420 } 1421 1422 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1423 { 1424 struct dw_mci_slot *slot = mmc_priv(mmc); 1425 struct dw_mci *host = slot->host; 1426 const struct dw_mci_drv_data *drv_data = host->drv_data; 1427 int err = -EINVAL; 1428 1429 if (drv_data && drv_data->execute_tuning) 1430 err = drv_data->execute_tuning(slot); 1431 return err; 1432 } 1433 1434 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1435 struct mmc_ios *ios) 1436 { 1437 struct dw_mci_slot *slot = mmc_priv(mmc); 1438 struct dw_mci *host = slot->host; 1439 const struct dw_mci_drv_data *drv_data = host->drv_data; 1440 1441 if (drv_data && drv_data->prepare_hs400_tuning) 1442 return drv_data->prepare_hs400_tuning(host, ios); 1443 1444 return 0; 1445 } 1446 1447 static const struct mmc_host_ops dw_mci_ops = { 1448 .request = dw_mci_request, 1449 .pre_req = dw_mci_pre_req, 1450 .post_req = dw_mci_post_req, 1451 .set_ios = dw_mci_set_ios, 1452 .get_ro = dw_mci_get_ro, 1453 .get_cd = dw_mci_get_cd, 1454 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1455 .execute_tuning = dw_mci_execute_tuning, 1456 .card_busy = dw_mci_card_busy, 1457 .start_signal_voltage_switch = dw_mci_switch_voltage, 1458 .init_card = dw_mci_init_card, 1459 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1460 }; 1461 1462 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1463 __releases(&host->lock) 1464 __acquires(&host->lock) 1465 { 1466 struct dw_mci_slot *slot; 1467 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1468 1469 WARN_ON(host->cmd || host->data); 1470 1471 host->cur_slot->mrq = NULL; 1472 host->mrq = NULL; 1473 if (!list_empty(&host->queue)) { 1474 slot = list_entry(host->queue.next, 1475 struct dw_mci_slot, queue_node); 1476 list_del(&slot->queue_node); 1477 dev_vdbg(host->dev, "list not empty: %s is next\n", 1478 mmc_hostname(slot->mmc)); 1479 host->state = STATE_SENDING_CMD; 1480 dw_mci_start_request(host, slot); 1481 } else { 1482 dev_vdbg(host->dev, "list empty\n"); 1483 1484 if (host->state == STATE_SENDING_CMD11) 1485 host->state = STATE_WAITING_CMD11_DONE; 1486 else 1487 host->state = STATE_IDLE; 1488 } 1489 1490 spin_unlock(&host->lock); 1491 mmc_request_done(prev_mmc, mrq); 1492 spin_lock(&host->lock); 1493 } 1494 1495 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1496 { 1497 u32 status = host->cmd_status; 1498 1499 host->cmd_status = 0; 1500 1501 /* Read the response from the card (up to 16 bytes) */ 1502 if (cmd->flags & MMC_RSP_PRESENT) { 1503 if (cmd->flags & MMC_RSP_136) { 1504 cmd->resp[3] = mci_readl(host, RESP0); 1505 cmd->resp[2] = mci_readl(host, RESP1); 1506 cmd->resp[1] = mci_readl(host, RESP2); 1507 cmd->resp[0] = mci_readl(host, RESP3); 1508 } else { 1509 cmd->resp[0] = mci_readl(host, RESP0); 1510 cmd->resp[1] = 0; 1511 cmd->resp[2] = 0; 1512 cmd->resp[3] = 0; 1513 } 1514 } 1515 1516 if (status & SDMMC_INT_RTO) 1517 cmd->error = -ETIMEDOUT; 1518 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1519 cmd->error = -EILSEQ; 1520 else if (status & SDMMC_INT_RESP_ERR) 1521 cmd->error = -EIO; 1522 else 1523 cmd->error = 0; 1524 1525 if (cmd->error) { 1526 /* newer ip versions need a delay between retries */ 1527 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 1528 mdelay(20); 1529 } 1530 1531 return cmd->error; 1532 } 1533 1534 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1535 { 1536 u32 status = host->data_status; 1537 1538 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1539 if (status & SDMMC_INT_DRTO) { 1540 data->error = -ETIMEDOUT; 1541 } else if (status & SDMMC_INT_DCRC) { 1542 data->error = -EILSEQ; 1543 } else if (status & SDMMC_INT_EBE) { 1544 if (host->dir_status == 1545 DW_MCI_SEND_STATUS) { 1546 /* 1547 * No data CRC status was returned. 1548 * The number of bytes transferred 1549 * will be exaggerated in PIO mode. 1550 */ 1551 data->bytes_xfered = 0; 1552 data->error = -ETIMEDOUT; 1553 } else if (host->dir_status == 1554 DW_MCI_RECV_STATUS) { 1555 data->error = -EIO; 1556 } 1557 } else { 1558 /* SDMMC_INT_SBE is included */ 1559 data->error = -EIO; 1560 } 1561 1562 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1563 1564 /* 1565 * After an error, there may be data lingering 1566 * in the FIFO 1567 */ 1568 dw_mci_reset(host); 1569 } else { 1570 data->bytes_xfered = data->blocks * data->blksz; 1571 data->error = 0; 1572 } 1573 1574 return data->error; 1575 } 1576 1577 static void dw_mci_set_drto(struct dw_mci *host) 1578 { 1579 unsigned int drto_clks; 1580 unsigned int drto_ms; 1581 1582 drto_clks = mci_readl(host, TMOUT) >> 8; 1583 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000); 1584 1585 /* add a bit spare time */ 1586 drto_ms += 10; 1587 1588 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms)); 1589 } 1590 1591 static void dw_mci_tasklet_func(unsigned long priv) 1592 { 1593 struct dw_mci *host = (struct dw_mci *)priv; 1594 struct mmc_data *data; 1595 struct mmc_command *cmd; 1596 struct mmc_request *mrq; 1597 enum dw_mci_state state; 1598 enum dw_mci_state prev_state; 1599 unsigned int err; 1600 1601 spin_lock(&host->lock); 1602 1603 state = host->state; 1604 data = host->data; 1605 mrq = host->mrq; 1606 1607 do { 1608 prev_state = state; 1609 1610 switch (state) { 1611 case STATE_IDLE: 1612 case STATE_WAITING_CMD11_DONE: 1613 break; 1614 1615 case STATE_SENDING_CMD11: 1616 case STATE_SENDING_CMD: 1617 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1618 &host->pending_events)) 1619 break; 1620 1621 cmd = host->cmd; 1622 host->cmd = NULL; 1623 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1624 err = dw_mci_command_complete(host, cmd); 1625 if (cmd == mrq->sbc && !err) { 1626 prev_state = state = STATE_SENDING_CMD; 1627 __dw_mci_start_request(host, host->cur_slot, 1628 mrq->cmd); 1629 goto unlock; 1630 } 1631 1632 if (cmd->data && err) { 1633 dw_mci_stop_dma(host); 1634 send_stop_abort(host, data); 1635 state = STATE_SENDING_STOP; 1636 break; 1637 } 1638 1639 if (!cmd->data || err) { 1640 dw_mci_request_end(host, mrq); 1641 goto unlock; 1642 } 1643 1644 prev_state = state = STATE_SENDING_DATA; 1645 /* fall through */ 1646 1647 case STATE_SENDING_DATA: 1648 /* 1649 * We could get a data error and never a transfer 1650 * complete so we'd better check for it here. 1651 * 1652 * Note that we don't really care if we also got a 1653 * transfer complete; stopping the DMA and sending an 1654 * abort won't hurt. 1655 */ 1656 if (test_and_clear_bit(EVENT_DATA_ERROR, 1657 &host->pending_events)) { 1658 dw_mci_stop_dma(host); 1659 if (data->stop || 1660 !(host->data_status & (SDMMC_INT_DRTO | 1661 SDMMC_INT_EBE))) 1662 send_stop_abort(host, data); 1663 state = STATE_DATA_ERROR; 1664 break; 1665 } 1666 1667 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1668 &host->pending_events)) { 1669 /* 1670 * If all data-related interrupts don't come 1671 * within the given time in reading data state. 1672 */ 1673 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 1674 (host->dir_status == DW_MCI_RECV_STATUS)) 1675 dw_mci_set_drto(host); 1676 break; 1677 } 1678 1679 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 1680 1681 /* 1682 * Handle an EVENT_DATA_ERROR that might have shown up 1683 * before the transfer completed. This might not have 1684 * been caught by the check above because the interrupt 1685 * could have gone off between the previous check and 1686 * the check for transfer complete. 1687 * 1688 * Technically this ought not be needed assuming we 1689 * get a DATA_COMPLETE eventually (we'll notice the 1690 * error and end the request), but it shouldn't hurt. 1691 * 1692 * This has the advantage of sending the stop command. 1693 */ 1694 if (test_and_clear_bit(EVENT_DATA_ERROR, 1695 &host->pending_events)) { 1696 dw_mci_stop_dma(host); 1697 if (data->stop || 1698 !(host->data_status & (SDMMC_INT_DRTO | 1699 SDMMC_INT_EBE))) 1700 send_stop_abort(host, data); 1701 state = STATE_DATA_ERROR; 1702 break; 1703 } 1704 prev_state = state = STATE_DATA_BUSY; 1705 1706 /* fall through */ 1707 1708 case STATE_DATA_BUSY: 1709 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1710 &host->pending_events)) { 1711 /* 1712 * If data error interrupt comes but data over 1713 * interrupt doesn't come within the given time. 1714 * in reading data state. 1715 */ 1716 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) && 1717 (host->dir_status == DW_MCI_RECV_STATUS)) 1718 dw_mci_set_drto(host); 1719 break; 1720 } 1721 1722 host->data = NULL; 1723 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1724 err = dw_mci_data_complete(host, data); 1725 1726 if (!err) { 1727 if (!data->stop || mrq->sbc) { 1728 if (mrq->sbc && data->stop) 1729 data->stop->error = 0; 1730 dw_mci_request_end(host, mrq); 1731 goto unlock; 1732 } 1733 1734 /* stop command for open-ended transfer*/ 1735 if (data->stop) 1736 send_stop_abort(host, data); 1737 } else { 1738 /* 1739 * If we don't have a command complete now we'll 1740 * never get one since we just reset everything; 1741 * better end the request. 1742 * 1743 * If we do have a command complete we'll fall 1744 * through to the SENDING_STOP command and 1745 * everything will be peachy keen. 1746 */ 1747 if (!test_bit(EVENT_CMD_COMPLETE, 1748 &host->pending_events)) { 1749 host->cmd = NULL; 1750 dw_mci_request_end(host, mrq); 1751 goto unlock; 1752 } 1753 } 1754 1755 /* 1756 * If err has non-zero, 1757 * stop-abort command has been already issued. 1758 */ 1759 prev_state = state = STATE_SENDING_STOP; 1760 1761 /* fall through */ 1762 1763 case STATE_SENDING_STOP: 1764 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1765 &host->pending_events)) 1766 break; 1767 1768 /* CMD error in data command */ 1769 if (mrq->cmd->error && mrq->data) 1770 dw_mci_reset(host); 1771 1772 host->cmd = NULL; 1773 host->data = NULL; 1774 1775 if (mrq->stop) 1776 dw_mci_command_complete(host, mrq->stop); 1777 else 1778 host->cmd_status = 0; 1779 1780 dw_mci_request_end(host, mrq); 1781 goto unlock; 1782 1783 case STATE_DATA_ERROR: 1784 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1785 &host->pending_events)) 1786 break; 1787 1788 state = STATE_DATA_BUSY; 1789 break; 1790 } 1791 } while (state != prev_state); 1792 1793 host->state = state; 1794 unlock: 1795 spin_unlock(&host->lock); 1796 1797 } 1798 1799 /* push final bytes to part_buf, only use during push */ 1800 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 1801 { 1802 memcpy((void *)&host->part_buf, buf, cnt); 1803 host->part_buf_count = cnt; 1804 } 1805 1806 /* append bytes to part_buf, only use during push */ 1807 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 1808 { 1809 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 1810 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 1811 host->part_buf_count += cnt; 1812 return cnt; 1813 } 1814 1815 /* pull first bytes from part_buf, only use during pull */ 1816 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 1817 { 1818 cnt = min_t(int, cnt, host->part_buf_count); 1819 if (cnt) { 1820 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 1821 cnt); 1822 host->part_buf_count -= cnt; 1823 host->part_buf_start += cnt; 1824 } 1825 return cnt; 1826 } 1827 1828 /* pull final bytes from the part_buf, assuming it's just been filled */ 1829 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 1830 { 1831 memcpy(buf, &host->part_buf, cnt); 1832 host->part_buf_start = cnt; 1833 host->part_buf_count = (1 << host->data_shift) - cnt; 1834 } 1835 1836 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1837 { 1838 struct mmc_data *data = host->data; 1839 int init_cnt = cnt; 1840 1841 /* try and push anything in the part_buf */ 1842 if (unlikely(host->part_buf_count)) { 1843 int len = dw_mci_push_part_bytes(host, buf, cnt); 1844 1845 buf += len; 1846 cnt -= len; 1847 if (host->part_buf_count == 2) { 1848 mci_fifo_writew(host->fifo_reg, host->part_buf16); 1849 host->part_buf_count = 0; 1850 } 1851 } 1852 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1853 if (unlikely((unsigned long)buf & 0x1)) { 1854 while (cnt >= 2) { 1855 u16 aligned_buf[64]; 1856 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1857 int items = len >> 1; 1858 int i; 1859 /* memcpy from input buffer into aligned buffer */ 1860 memcpy(aligned_buf, buf, len); 1861 buf += len; 1862 cnt -= len; 1863 /* push data from aligned buffer into fifo */ 1864 for (i = 0; i < items; ++i) 1865 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 1866 } 1867 } else 1868 #endif 1869 { 1870 u16 *pdata = buf; 1871 1872 for (; cnt >= 2; cnt -= 2) 1873 mci_fifo_writew(host->fifo_reg, *pdata++); 1874 buf = pdata; 1875 } 1876 /* put anything remaining in the part_buf */ 1877 if (cnt) { 1878 dw_mci_set_part_bytes(host, buf, cnt); 1879 /* Push data if we have reached the expected data length */ 1880 if ((data->bytes_xfered + init_cnt) == 1881 (data->blksz * data->blocks)) 1882 mci_fifo_writew(host->fifo_reg, host->part_buf16); 1883 } 1884 } 1885 1886 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1887 { 1888 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1889 if (unlikely((unsigned long)buf & 0x1)) { 1890 while (cnt >= 2) { 1891 /* pull data from fifo into aligned buffer */ 1892 u16 aligned_buf[64]; 1893 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1894 int items = len >> 1; 1895 int i; 1896 1897 for (i = 0; i < items; ++i) 1898 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 1899 /* memcpy from aligned buffer into output buffer */ 1900 memcpy(buf, aligned_buf, len); 1901 buf += len; 1902 cnt -= len; 1903 } 1904 } else 1905 #endif 1906 { 1907 u16 *pdata = buf; 1908 1909 for (; cnt >= 2; cnt -= 2) 1910 *pdata++ = mci_fifo_readw(host->fifo_reg); 1911 buf = pdata; 1912 } 1913 if (cnt) { 1914 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 1915 dw_mci_pull_final_bytes(host, buf, cnt); 1916 } 1917 } 1918 1919 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1920 { 1921 struct mmc_data *data = host->data; 1922 int init_cnt = cnt; 1923 1924 /* try and push anything in the part_buf */ 1925 if (unlikely(host->part_buf_count)) { 1926 int len = dw_mci_push_part_bytes(host, buf, cnt); 1927 1928 buf += len; 1929 cnt -= len; 1930 if (host->part_buf_count == 4) { 1931 mci_fifo_writel(host->fifo_reg, host->part_buf32); 1932 host->part_buf_count = 0; 1933 } 1934 } 1935 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1936 if (unlikely((unsigned long)buf & 0x3)) { 1937 while (cnt >= 4) { 1938 u32 aligned_buf[32]; 1939 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1940 int items = len >> 2; 1941 int i; 1942 /* memcpy from input buffer into aligned buffer */ 1943 memcpy(aligned_buf, buf, len); 1944 buf += len; 1945 cnt -= len; 1946 /* push data from aligned buffer into fifo */ 1947 for (i = 0; i < items; ++i) 1948 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 1949 } 1950 } else 1951 #endif 1952 { 1953 u32 *pdata = buf; 1954 1955 for (; cnt >= 4; cnt -= 4) 1956 mci_fifo_writel(host->fifo_reg, *pdata++); 1957 buf = pdata; 1958 } 1959 /* put anything remaining in the part_buf */ 1960 if (cnt) { 1961 dw_mci_set_part_bytes(host, buf, cnt); 1962 /* Push data if we have reached the expected data length */ 1963 if ((data->bytes_xfered + init_cnt) == 1964 (data->blksz * data->blocks)) 1965 mci_fifo_writel(host->fifo_reg, host->part_buf32); 1966 } 1967 } 1968 1969 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1970 { 1971 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1972 if (unlikely((unsigned long)buf & 0x3)) { 1973 while (cnt >= 4) { 1974 /* pull data from fifo into aligned buffer */ 1975 u32 aligned_buf[32]; 1976 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1977 int items = len >> 2; 1978 int i; 1979 1980 for (i = 0; i < items; ++i) 1981 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 1982 /* memcpy from aligned buffer into output buffer */ 1983 memcpy(buf, aligned_buf, len); 1984 buf += len; 1985 cnt -= len; 1986 } 1987 } else 1988 #endif 1989 { 1990 u32 *pdata = buf; 1991 1992 for (; cnt >= 4; cnt -= 4) 1993 *pdata++ = mci_fifo_readl(host->fifo_reg); 1994 buf = pdata; 1995 } 1996 if (cnt) { 1997 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 1998 dw_mci_pull_final_bytes(host, buf, cnt); 1999 } 2000 } 2001 2002 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2003 { 2004 struct mmc_data *data = host->data; 2005 int init_cnt = cnt; 2006 2007 /* try and push anything in the part_buf */ 2008 if (unlikely(host->part_buf_count)) { 2009 int len = dw_mci_push_part_bytes(host, buf, cnt); 2010 2011 buf += len; 2012 cnt -= len; 2013 2014 if (host->part_buf_count == 8) { 2015 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2016 host->part_buf_count = 0; 2017 } 2018 } 2019 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2020 if (unlikely((unsigned long)buf & 0x7)) { 2021 while (cnt >= 8) { 2022 u64 aligned_buf[16]; 2023 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2024 int items = len >> 3; 2025 int i; 2026 /* memcpy from input buffer into aligned buffer */ 2027 memcpy(aligned_buf, buf, len); 2028 buf += len; 2029 cnt -= len; 2030 /* push data from aligned buffer into fifo */ 2031 for (i = 0; i < items; ++i) 2032 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2033 } 2034 } else 2035 #endif 2036 { 2037 u64 *pdata = buf; 2038 2039 for (; cnt >= 8; cnt -= 8) 2040 mci_fifo_writeq(host->fifo_reg, *pdata++); 2041 buf = pdata; 2042 } 2043 /* put anything remaining in the part_buf */ 2044 if (cnt) { 2045 dw_mci_set_part_bytes(host, buf, cnt); 2046 /* Push data if we have reached the expected data length */ 2047 if ((data->bytes_xfered + init_cnt) == 2048 (data->blksz * data->blocks)) 2049 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2050 } 2051 } 2052 2053 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2054 { 2055 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2056 if (unlikely((unsigned long)buf & 0x7)) { 2057 while (cnt >= 8) { 2058 /* pull data from fifo into aligned buffer */ 2059 u64 aligned_buf[16]; 2060 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2061 int items = len >> 3; 2062 int i; 2063 2064 for (i = 0; i < items; ++i) 2065 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2066 2067 /* memcpy from aligned buffer into output buffer */ 2068 memcpy(buf, aligned_buf, len); 2069 buf += len; 2070 cnt -= len; 2071 } 2072 } else 2073 #endif 2074 { 2075 u64 *pdata = buf; 2076 2077 for (; cnt >= 8; cnt -= 8) 2078 *pdata++ = mci_fifo_readq(host->fifo_reg); 2079 buf = pdata; 2080 } 2081 if (cnt) { 2082 host->part_buf = mci_fifo_readq(host->fifo_reg); 2083 dw_mci_pull_final_bytes(host, buf, cnt); 2084 } 2085 } 2086 2087 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2088 { 2089 int len; 2090 2091 /* get remaining partial bytes */ 2092 len = dw_mci_pull_part_bytes(host, buf, cnt); 2093 if (unlikely(len == cnt)) 2094 return; 2095 buf += len; 2096 cnt -= len; 2097 2098 /* get the rest of the data */ 2099 host->pull_data(host, buf, cnt); 2100 } 2101 2102 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2103 { 2104 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2105 void *buf; 2106 unsigned int offset; 2107 struct mmc_data *data = host->data; 2108 int shift = host->data_shift; 2109 u32 status; 2110 unsigned int len; 2111 unsigned int remain, fcnt; 2112 2113 do { 2114 if (!sg_miter_next(sg_miter)) 2115 goto done; 2116 2117 host->sg = sg_miter->piter.sg; 2118 buf = sg_miter->addr; 2119 remain = sg_miter->length; 2120 offset = 0; 2121 2122 do { 2123 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2124 << shift) + host->part_buf_count; 2125 len = min(remain, fcnt); 2126 if (!len) 2127 break; 2128 dw_mci_pull_data(host, (void *)(buf + offset), len); 2129 data->bytes_xfered += len; 2130 offset += len; 2131 remain -= len; 2132 } while (remain); 2133 2134 sg_miter->consumed = offset; 2135 status = mci_readl(host, MINTSTS); 2136 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2137 /* if the RXDR is ready read again */ 2138 } while ((status & SDMMC_INT_RXDR) || 2139 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2140 2141 if (!remain) { 2142 if (!sg_miter_next(sg_miter)) 2143 goto done; 2144 sg_miter->consumed = 0; 2145 } 2146 sg_miter_stop(sg_miter); 2147 return; 2148 2149 done: 2150 sg_miter_stop(sg_miter); 2151 host->sg = NULL; 2152 smp_wmb(); /* drain writebuffer */ 2153 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2154 } 2155 2156 static void dw_mci_write_data_pio(struct dw_mci *host) 2157 { 2158 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2159 void *buf; 2160 unsigned int offset; 2161 struct mmc_data *data = host->data; 2162 int shift = host->data_shift; 2163 u32 status; 2164 unsigned int len; 2165 unsigned int fifo_depth = host->fifo_depth; 2166 unsigned int remain, fcnt; 2167 2168 do { 2169 if (!sg_miter_next(sg_miter)) 2170 goto done; 2171 2172 host->sg = sg_miter->piter.sg; 2173 buf = sg_miter->addr; 2174 remain = sg_miter->length; 2175 offset = 0; 2176 2177 do { 2178 fcnt = ((fifo_depth - 2179 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2180 << shift) - host->part_buf_count; 2181 len = min(remain, fcnt); 2182 if (!len) 2183 break; 2184 host->push_data(host, (void *)(buf + offset), len); 2185 data->bytes_xfered += len; 2186 offset += len; 2187 remain -= len; 2188 } while (remain); 2189 2190 sg_miter->consumed = offset; 2191 status = mci_readl(host, MINTSTS); 2192 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2193 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2194 2195 if (!remain) { 2196 if (!sg_miter_next(sg_miter)) 2197 goto done; 2198 sg_miter->consumed = 0; 2199 } 2200 sg_miter_stop(sg_miter); 2201 return; 2202 2203 done: 2204 sg_miter_stop(sg_miter); 2205 host->sg = NULL; 2206 smp_wmb(); /* drain writebuffer */ 2207 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2208 } 2209 2210 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2211 { 2212 if (!host->cmd_status) 2213 host->cmd_status = status; 2214 2215 smp_wmb(); /* drain writebuffer */ 2216 2217 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2218 tasklet_schedule(&host->tasklet); 2219 } 2220 2221 static void dw_mci_handle_cd(struct dw_mci *host) 2222 { 2223 int i; 2224 2225 for (i = 0; i < host->num_slots; i++) { 2226 struct dw_mci_slot *slot = host->slot[i]; 2227 2228 if (!slot) 2229 continue; 2230 2231 if (slot->mmc->ops->card_event) 2232 slot->mmc->ops->card_event(slot->mmc); 2233 mmc_detect_change(slot->mmc, 2234 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2235 } 2236 } 2237 2238 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2239 { 2240 struct dw_mci *host = dev_id; 2241 u32 pending; 2242 int i; 2243 2244 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2245 2246 /* 2247 * DTO fix - version 2.10a and below, and only if internal DMA 2248 * is configured. 2249 */ 2250 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 2251 if (!pending && 2252 ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 2253 pending |= SDMMC_INT_DATA_OVER; 2254 } 2255 2256 if (pending) { 2257 /* Check volt switch first, since it can look like an error */ 2258 if ((host->state == STATE_SENDING_CMD11) && 2259 (pending & SDMMC_INT_VOLT_SWITCH)) { 2260 unsigned long irqflags; 2261 2262 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2263 pending &= ~SDMMC_INT_VOLT_SWITCH; 2264 2265 /* 2266 * Hold the lock; we know cmd11_timer can't be kicked 2267 * off after the lock is released, so safe to delete. 2268 */ 2269 spin_lock_irqsave(&host->irq_lock, irqflags); 2270 dw_mci_cmd_interrupt(host, pending); 2271 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2272 2273 del_timer(&host->cmd11_timer); 2274 } 2275 2276 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2277 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2278 host->cmd_status = pending; 2279 smp_wmb(); /* drain writebuffer */ 2280 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2281 } 2282 2283 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2284 /* if there is an error report DATA_ERROR */ 2285 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2286 host->data_status = pending; 2287 smp_wmb(); /* drain writebuffer */ 2288 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2289 tasklet_schedule(&host->tasklet); 2290 } 2291 2292 if (pending & SDMMC_INT_DATA_OVER) { 2293 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO) 2294 del_timer(&host->dto_timer); 2295 2296 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2297 if (!host->data_status) 2298 host->data_status = pending; 2299 smp_wmb(); /* drain writebuffer */ 2300 if (host->dir_status == DW_MCI_RECV_STATUS) { 2301 if (host->sg != NULL) 2302 dw_mci_read_data_pio(host, true); 2303 } 2304 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2305 tasklet_schedule(&host->tasklet); 2306 } 2307 2308 if (pending & SDMMC_INT_RXDR) { 2309 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2310 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2311 dw_mci_read_data_pio(host, false); 2312 } 2313 2314 if (pending & SDMMC_INT_TXDR) { 2315 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2316 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2317 dw_mci_write_data_pio(host); 2318 } 2319 2320 if (pending & SDMMC_INT_CMD_DONE) { 2321 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2322 dw_mci_cmd_interrupt(host, pending); 2323 } 2324 2325 if (pending & SDMMC_INT_CD) { 2326 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2327 dw_mci_handle_cd(host); 2328 } 2329 2330 /* Handle SDIO Interrupts */ 2331 for (i = 0; i < host->num_slots; i++) { 2332 struct dw_mci_slot *slot = host->slot[i]; 2333 2334 if (!slot) 2335 continue; 2336 2337 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2338 mci_writel(host, RINTSTS, 2339 SDMMC_INT_SDIO(slot->sdio_id)); 2340 mmc_signal_sdio_irq(slot->mmc); 2341 } 2342 } 2343 2344 } 2345 2346 #ifdef CONFIG_MMC_DW_IDMAC 2347 /* Handle DMA interrupts */ 2348 if (host->dma_64bit_address == 1) { 2349 pending = mci_readl(host, IDSTS64); 2350 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2351 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2352 SDMMC_IDMAC_INT_RI); 2353 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2354 host->dma_ops->complete(host); 2355 } 2356 } else { 2357 pending = mci_readl(host, IDSTS); 2358 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2359 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2360 SDMMC_IDMAC_INT_RI); 2361 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2362 host->dma_ops->complete(host); 2363 } 2364 } 2365 #endif 2366 2367 return IRQ_HANDLED; 2368 } 2369 2370 #ifdef CONFIG_OF 2371 /* given a slot, find out the device node representing that slot */ 2372 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot) 2373 { 2374 struct device *dev = slot->mmc->parent; 2375 struct device_node *np; 2376 const __be32 *addr; 2377 int len; 2378 2379 if (!dev || !dev->of_node) 2380 return NULL; 2381 2382 for_each_child_of_node(dev->of_node, np) { 2383 addr = of_get_property(np, "reg", &len); 2384 if (!addr || (len < sizeof(int))) 2385 continue; 2386 if (be32_to_cpup(addr) == slot->id) 2387 return np; 2388 } 2389 return NULL; 2390 } 2391 2392 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot) 2393 { 2394 struct device_node *np = dw_mci_of_find_slot_node(slot); 2395 2396 if (!np) 2397 return; 2398 2399 if (of_property_read_bool(np, "disable-wp")) { 2400 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; 2401 dev_warn(slot->mmc->parent, 2402 "Slot quirk 'disable-wp' is deprecated\n"); 2403 } 2404 } 2405 #else /* CONFIG_OF */ 2406 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot) 2407 { 2408 } 2409 #endif /* CONFIG_OF */ 2410 2411 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) 2412 { 2413 struct mmc_host *mmc; 2414 struct dw_mci_slot *slot; 2415 const struct dw_mci_drv_data *drv_data = host->drv_data; 2416 int ctrl_id, ret; 2417 u32 freq[2]; 2418 2419 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2420 if (!mmc) 2421 return -ENOMEM; 2422 2423 slot = mmc_priv(mmc); 2424 slot->id = id; 2425 slot->sdio_id = host->sdio_id0 + id; 2426 slot->mmc = mmc; 2427 slot->host = host; 2428 host->slot[id] = slot; 2429 2430 mmc->ops = &dw_mci_ops; 2431 if (of_property_read_u32_array(host->dev->of_node, 2432 "clock-freq-min-max", freq, 2)) { 2433 mmc->f_min = DW_MCI_FREQ_MIN; 2434 mmc->f_max = DW_MCI_FREQ_MAX; 2435 } else { 2436 mmc->f_min = freq[0]; 2437 mmc->f_max = freq[1]; 2438 } 2439 2440 /*if there are external regulators, get them*/ 2441 ret = mmc_regulator_get_supply(mmc); 2442 if (ret == -EPROBE_DEFER) 2443 goto err_host_allocated; 2444 2445 if (!mmc->ocr_avail) 2446 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2447 2448 if (host->pdata->caps) 2449 mmc->caps = host->pdata->caps; 2450 2451 if (host->pdata->pm_caps) 2452 mmc->pm_caps = host->pdata->pm_caps; 2453 2454 if (host->dev->of_node) { 2455 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2456 if (ctrl_id < 0) 2457 ctrl_id = 0; 2458 } else { 2459 ctrl_id = to_platform_device(host->dev)->id; 2460 } 2461 if (drv_data && drv_data->caps) 2462 mmc->caps |= drv_data->caps[ctrl_id]; 2463 2464 if (host->pdata->caps2) 2465 mmc->caps2 = host->pdata->caps2; 2466 2467 dw_mci_slot_of_parse(slot); 2468 2469 ret = mmc_of_parse(mmc); 2470 if (ret) 2471 goto err_host_allocated; 2472 2473 /* Useful defaults if platform data is unset. */ 2474 if (host->use_dma) { 2475 mmc->max_segs = host->ring_size; 2476 mmc->max_blk_size = 65536; 2477 mmc->max_seg_size = 0x1000; 2478 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2479 mmc->max_blk_count = mmc->max_req_size / 512; 2480 } else { 2481 mmc->max_segs = 64; 2482 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 2483 mmc->max_blk_count = 512; 2484 mmc->max_req_size = mmc->max_blk_size * 2485 mmc->max_blk_count; 2486 mmc->max_seg_size = mmc->max_req_size; 2487 } 2488 2489 if (dw_mci_get_cd(mmc)) 2490 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2491 else 2492 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 2493 2494 ret = mmc_add_host(mmc); 2495 if (ret) 2496 goto err_host_allocated; 2497 2498 #if defined(CONFIG_DEBUG_FS) 2499 dw_mci_init_debugfs(slot); 2500 #endif 2501 2502 return 0; 2503 2504 err_host_allocated: 2505 mmc_free_host(mmc); 2506 return ret; 2507 } 2508 2509 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 2510 { 2511 /* Debugfs stuff is cleaned up by mmc core */ 2512 mmc_remove_host(slot->mmc); 2513 slot->host->slot[id] = NULL; 2514 mmc_free_host(slot->mmc); 2515 } 2516 2517 static void dw_mci_init_dma(struct dw_mci *host) 2518 { 2519 int addr_config; 2520 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ 2521 addr_config = (mci_readl(host, HCON) >> 27) & 0x01; 2522 2523 if (addr_config == 1) { 2524 /* host supports IDMAC in 64-bit address mode */ 2525 host->dma_64bit_address = 1; 2526 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); 2527 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2528 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); 2529 } else { 2530 /* host supports IDMAC in 32-bit address mode */ 2531 host->dma_64bit_address = 0; 2532 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); 2533 } 2534 2535 /* Alloc memory for sg translation */ 2536 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, 2537 &host->sg_dma, GFP_KERNEL); 2538 if (!host->sg_cpu) { 2539 dev_err(host->dev, "%s: could not alloc DMA memory\n", 2540 __func__); 2541 goto no_dma; 2542 } 2543 2544 /* Determine which DMA interface to use */ 2545 #ifdef CONFIG_MMC_DW_IDMAC 2546 host->dma_ops = &dw_mci_idmac_ops; 2547 dev_info(host->dev, "Using internal DMA controller.\n"); 2548 #endif 2549 2550 if (!host->dma_ops) 2551 goto no_dma; 2552 2553 if (host->dma_ops->init && host->dma_ops->start && 2554 host->dma_ops->stop && host->dma_ops->cleanup) { 2555 if (host->dma_ops->init(host)) { 2556 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2557 __func__); 2558 goto no_dma; 2559 } 2560 } else { 2561 dev_err(host->dev, "DMA initialization not found.\n"); 2562 goto no_dma; 2563 } 2564 2565 host->use_dma = 1; 2566 return; 2567 2568 no_dma: 2569 dev_info(host->dev, "Using PIO mode.\n"); 2570 host->use_dma = 0; 2571 } 2572 2573 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 2574 { 2575 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2576 u32 ctrl; 2577 2578 ctrl = mci_readl(host, CTRL); 2579 ctrl |= reset; 2580 mci_writel(host, CTRL, ctrl); 2581 2582 /* wait till resets clear */ 2583 do { 2584 ctrl = mci_readl(host, CTRL); 2585 if (!(ctrl & reset)) 2586 return true; 2587 } while (time_before(jiffies, timeout)); 2588 2589 dev_err(host->dev, 2590 "Timeout resetting block (ctrl reset %#x)\n", 2591 ctrl & reset); 2592 2593 return false; 2594 } 2595 2596 static bool dw_mci_reset(struct dw_mci *host) 2597 { 2598 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 2599 bool ret = false; 2600 2601 /* 2602 * Reseting generates a block interrupt, hence setting 2603 * the scatter-gather pointer to NULL. 2604 */ 2605 if (host->sg) { 2606 sg_miter_stop(&host->sg_miter); 2607 host->sg = NULL; 2608 } 2609 2610 if (host->use_dma) 2611 flags |= SDMMC_CTRL_DMA_RESET; 2612 2613 if (dw_mci_ctrl_reset(host, flags)) { 2614 /* 2615 * In all cases we clear the RAWINTS register to clear any 2616 * interrupts. 2617 */ 2618 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2619 2620 /* if using dma we wait for dma_req to clear */ 2621 if (host->use_dma) { 2622 unsigned long timeout = jiffies + msecs_to_jiffies(500); 2623 u32 status; 2624 2625 do { 2626 status = mci_readl(host, STATUS); 2627 if (!(status & SDMMC_STATUS_DMA_REQ)) 2628 break; 2629 cpu_relax(); 2630 } while (time_before(jiffies, timeout)); 2631 2632 if (status & SDMMC_STATUS_DMA_REQ) { 2633 dev_err(host->dev, 2634 "%s: Timeout waiting for dma_req to clear during reset\n", 2635 __func__); 2636 goto ciu_out; 2637 } 2638 2639 /* when using DMA next we reset the fifo again */ 2640 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 2641 goto ciu_out; 2642 } 2643 } else { 2644 /* if the controller reset bit did clear, then set clock regs */ 2645 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 2646 dev_err(host->dev, 2647 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 2648 __func__); 2649 goto ciu_out; 2650 } 2651 } 2652 2653 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC) 2654 /* It is also recommended that we reset and reprogram idmac */ 2655 dw_mci_idmac_reset(host); 2656 #endif 2657 2658 ret = true; 2659 2660 ciu_out: 2661 /* After a CTRL reset we need to have CIU set clock registers */ 2662 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); 2663 2664 return ret; 2665 } 2666 2667 static void dw_mci_cmd11_timer(unsigned long arg) 2668 { 2669 struct dw_mci *host = (struct dw_mci *)arg; 2670 2671 if (host->state != STATE_SENDING_CMD11) { 2672 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2673 return; 2674 } 2675 2676 host->cmd_status = SDMMC_INT_RTO; 2677 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2678 tasklet_schedule(&host->tasklet); 2679 } 2680 2681 static void dw_mci_dto_timer(unsigned long arg) 2682 { 2683 struct dw_mci *host = (struct dw_mci *)arg; 2684 2685 switch (host->state) { 2686 case STATE_SENDING_DATA: 2687 case STATE_DATA_BUSY: 2688 /* 2689 * If DTO interrupt does NOT come in sending data state, 2690 * we should notify the driver to terminate current transfer 2691 * and report a data timeout to the core. 2692 */ 2693 host->data_status = SDMMC_INT_DRTO; 2694 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2695 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2696 tasklet_schedule(&host->tasklet); 2697 break; 2698 default: 2699 break; 2700 } 2701 } 2702 2703 #ifdef CONFIG_OF 2704 static struct dw_mci_of_quirks { 2705 char *quirk; 2706 int id; 2707 } of_quirks[] = { 2708 { 2709 .quirk = "broken-cd", 2710 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, 2711 }, 2712 }; 2713 2714 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2715 { 2716 struct dw_mci_board *pdata; 2717 struct device *dev = host->dev; 2718 struct device_node *np = dev->of_node; 2719 const struct dw_mci_drv_data *drv_data = host->drv_data; 2720 int idx, ret; 2721 u32 clock_frequency; 2722 2723 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2724 if (!pdata) 2725 return ERR_PTR(-ENOMEM); 2726 2727 /* find out number of slots supported */ 2728 if (of_property_read_u32(dev->of_node, "num-slots", 2729 &pdata->num_slots)) { 2730 dev_info(dev, 2731 "num-slots property not found, assuming 1 slot is available\n"); 2732 pdata->num_slots = 1; 2733 } 2734 2735 /* get quirks */ 2736 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) 2737 if (of_get_property(np, of_quirks[idx].quirk, NULL)) 2738 pdata->quirks |= of_quirks[idx].id; 2739 2740 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) 2741 dev_info(dev, 2742 "fifo-depth property not found, using value of FIFOTH register as default\n"); 2743 2744 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); 2745 2746 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) 2747 pdata->bus_hz = clock_frequency; 2748 2749 if (drv_data && drv_data->parse_dt) { 2750 ret = drv_data->parse_dt(host); 2751 if (ret) 2752 return ERR_PTR(ret); 2753 } 2754 2755 if (of_find_property(np, "supports-highspeed", NULL)) { 2756 dev_info(dev, "supports-highspeed property is deprecated.\n"); 2757 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2758 } 2759 2760 return pdata; 2761 } 2762 2763 #else /* CONFIG_OF */ 2764 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 2765 { 2766 return ERR_PTR(-EINVAL); 2767 } 2768 #endif /* CONFIG_OF */ 2769 2770 static void dw_mci_enable_cd(struct dw_mci *host) 2771 { 2772 struct dw_mci_board *brd = host->pdata; 2773 unsigned long irqflags; 2774 u32 temp; 2775 int i; 2776 2777 /* No need for CD if broken card detection */ 2778 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 2779 return; 2780 2781 /* No need for CD if all slots have a non-error GPIO */ 2782 for (i = 0; i < host->num_slots; i++) { 2783 struct dw_mci_slot *slot = host->slot[i]; 2784 2785 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) 2786 break; 2787 } 2788 if (i == host->num_slots) 2789 return; 2790 2791 spin_lock_irqsave(&host->irq_lock, irqflags); 2792 temp = mci_readl(host, INTMASK); 2793 temp |= SDMMC_INT_CD; 2794 mci_writel(host, INTMASK, temp); 2795 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2796 } 2797 2798 int dw_mci_probe(struct dw_mci *host) 2799 { 2800 const struct dw_mci_drv_data *drv_data = host->drv_data; 2801 int width, i, ret = 0; 2802 u32 fifo_size; 2803 int init_slots = 0; 2804 2805 if (!host->pdata) { 2806 host->pdata = dw_mci_parse_dt(host); 2807 if (IS_ERR(host->pdata)) { 2808 dev_err(host->dev, "platform data not available\n"); 2809 return -EINVAL; 2810 } 2811 } 2812 2813 if (host->pdata->num_slots < 1) { 2814 dev_err(host->dev, 2815 "Platform data must supply num_slots.\n"); 2816 return -ENODEV; 2817 } 2818 2819 host->biu_clk = devm_clk_get(host->dev, "biu"); 2820 if (IS_ERR(host->biu_clk)) { 2821 dev_dbg(host->dev, "biu clock not available\n"); 2822 } else { 2823 ret = clk_prepare_enable(host->biu_clk); 2824 if (ret) { 2825 dev_err(host->dev, "failed to enable biu clock\n"); 2826 return ret; 2827 } 2828 } 2829 2830 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 2831 if (IS_ERR(host->ciu_clk)) { 2832 dev_dbg(host->dev, "ciu clock not available\n"); 2833 host->bus_hz = host->pdata->bus_hz; 2834 } else { 2835 ret = clk_prepare_enable(host->ciu_clk); 2836 if (ret) { 2837 dev_err(host->dev, "failed to enable ciu clock\n"); 2838 goto err_clk_biu; 2839 } 2840 2841 if (host->pdata->bus_hz) { 2842 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 2843 if (ret) 2844 dev_warn(host->dev, 2845 "Unable to set bus rate to %uHz\n", 2846 host->pdata->bus_hz); 2847 } 2848 host->bus_hz = clk_get_rate(host->ciu_clk); 2849 } 2850 2851 if (!host->bus_hz) { 2852 dev_err(host->dev, 2853 "Platform data must supply bus speed\n"); 2854 ret = -ENODEV; 2855 goto err_clk_ciu; 2856 } 2857 2858 if (drv_data && drv_data->init) { 2859 ret = drv_data->init(host); 2860 if (ret) { 2861 dev_err(host->dev, 2862 "implementation specific init failed\n"); 2863 goto err_clk_ciu; 2864 } 2865 } 2866 2867 if (drv_data && drv_data->setup_clock) { 2868 ret = drv_data->setup_clock(host); 2869 if (ret) { 2870 dev_err(host->dev, 2871 "implementation specific clock setup failed\n"); 2872 goto err_clk_ciu; 2873 } 2874 } 2875 2876 setup_timer(&host->cmd11_timer, 2877 dw_mci_cmd11_timer, (unsigned long)host); 2878 2879 host->quirks = host->pdata->quirks; 2880 2881 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO) 2882 setup_timer(&host->dto_timer, 2883 dw_mci_dto_timer, (unsigned long)host); 2884 2885 spin_lock_init(&host->lock); 2886 spin_lock_init(&host->irq_lock); 2887 INIT_LIST_HEAD(&host->queue); 2888 2889 /* 2890 * Get the host data width - this assumes that HCON has been set with 2891 * the correct values. 2892 */ 2893 i = (mci_readl(host, HCON) >> 7) & 0x7; 2894 if (!i) { 2895 host->push_data = dw_mci_push_data16; 2896 host->pull_data = dw_mci_pull_data16; 2897 width = 16; 2898 host->data_shift = 1; 2899 } else if (i == 2) { 2900 host->push_data = dw_mci_push_data64; 2901 host->pull_data = dw_mci_pull_data64; 2902 width = 64; 2903 host->data_shift = 3; 2904 } else { 2905 /* Check for a reserved value, and warn if it is */ 2906 WARN((i != 1), 2907 "HCON reports a reserved host data width!\n" 2908 "Defaulting to 32-bit access.\n"); 2909 host->push_data = dw_mci_push_data32; 2910 host->pull_data = dw_mci_pull_data32; 2911 width = 32; 2912 host->data_shift = 2; 2913 } 2914 2915 /* Reset all blocks */ 2916 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) 2917 return -ENODEV; 2918 2919 host->dma_ops = host->pdata->dma_ops; 2920 dw_mci_init_dma(host); 2921 2922 /* Clear the interrupts for the host controller */ 2923 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2924 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2925 2926 /* Put in max timeout */ 2927 mci_writel(host, TMOUT, 0xFFFFFFFF); 2928 2929 /* 2930 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2931 * Tx Mark = fifo_size / 2 DMA Size = 8 2932 */ 2933 if (!host->pdata->fifo_depth) { 2934 /* 2935 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2936 * have been overwritten by the bootloader, just like we're 2937 * about to do, so if you know the value for your hardware, you 2938 * should put it in the platform data. 2939 */ 2940 fifo_size = mci_readl(host, FIFOTH); 2941 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2942 } else { 2943 fifo_size = host->pdata->fifo_depth; 2944 } 2945 host->fifo_depth = fifo_size; 2946 host->fifoth_val = 2947 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 2948 mci_writel(host, FIFOTH, host->fifoth_val); 2949 2950 /* disable clock to CIU */ 2951 mci_writel(host, CLKENA, 0); 2952 mci_writel(host, CLKSRC, 0); 2953 2954 /* 2955 * In 2.40a spec, Data offset is changed. 2956 * Need to check the version-id and set data-offset for DATA register. 2957 */ 2958 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 2959 dev_info(host->dev, "Version ID is %04x\n", host->verid); 2960 2961 if (host->verid < DW_MMC_240A) 2962 host->fifo_reg = host->regs + DATA_OFFSET; 2963 else 2964 host->fifo_reg = host->regs + DATA_240A_OFFSET; 2965 2966 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2967 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 2968 host->irq_flags, "dw-mci", host); 2969 if (ret) 2970 goto err_dmaunmap; 2971 2972 if (host->pdata->num_slots) 2973 host->num_slots = host->pdata->num_slots; 2974 else 2975 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2976 2977 /* 2978 * Enable interrupts for command done, data over, data empty, 2979 * receive ready and error such as transmit, receive timeout, crc error 2980 */ 2981 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2982 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2983 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2984 DW_MCI_ERROR_FLAGS); 2985 /* Enable mci interrupt */ 2986 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2987 2988 dev_info(host->dev, 2989 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 2990 host->irq, width, fifo_size); 2991 2992 /* We need at least one slot to succeed */ 2993 for (i = 0; i < host->num_slots; i++) { 2994 ret = dw_mci_init_slot(host, i); 2995 if (ret) 2996 dev_dbg(host->dev, "slot %d init failed\n", i); 2997 else 2998 init_slots++; 2999 } 3000 3001 if (init_slots) { 3002 dev_info(host->dev, "%d slots initialized\n", init_slots); 3003 } else { 3004 dev_dbg(host->dev, 3005 "attempted to initialize %d slots, but failed on all\n", 3006 host->num_slots); 3007 goto err_dmaunmap; 3008 } 3009 3010 /* Now that slots are all setup, we can enable card detect */ 3011 dw_mci_enable_cd(host); 3012 3013 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 3014 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); 3015 3016 return 0; 3017 3018 err_dmaunmap: 3019 if (host->use_dma && host->dma_ops->exit) 3020 host->dma_ops->exit(host); 3021 3022 err_clk_ciu: 3023 if (!IS_ERR(host->ciu_clk)) 3024 clk_disable_unprepare(host->ciu_clk); 3025 3026 err_clk_biu: 3027 if (!IS_ERR(host->biu_clk)) 3028 clk_disable_unprepare(host->biu_clk); 3029 3030 return ret; 3031 } 3032 EXPORT_SYMBOL(dw_mci_probe); 3033 3034 void dw_mci_remove(struct dw_mci *host) 3035 { 3036 int i; 3037 3038 for (i = 0; i < host->num_slots; i++) { 3039 dev_dbg(host->dev, "remove slot %d\n", i); 3040 if (host->slot[i]) 3041 dw_mci_cleanup_slot(host->slot[i], i); 3042 } 3043 3044 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3045 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3046 3047 /* disable clock to CIU */ 3048 mci_writel(host, CLKENA, 0); 3049 mci_writel(host, CLKSRC, 0); 3050 3051 if (host->use_dma && host->dma_ops->exit) 3052 host->dma_ops->exit(host); 3053 3054 if (!IS_ERR(host->ciu_clk)) 3055 clk_disable_unprepare(host->ciu_clk); 3056 3057 if (!IS_ERR(host->biu_clk)) 3058 clk_disable_unprepare(host->biu_clk); 3059 } 3060 EXPORT_SYMBOL(dw_mci_remove); 3061 3062 3063 3064 #ifdef CONFIG_PM_SLEEP 3065 /* 3066 * TODO: we should probably disable the clock to the card in the suspend path. 3067 */ 3068 int dw_mci_suspend(struct dw_mci *host) 3069 { 3070 return 0; 3071 } 3072 EXPORT_SYMBOL(dw_mci_suspend); 3073 3074 int dw_mci_resume(struct dw_mci *host) 3075 { 3076 int i, ret; 3077 3078 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3079 ret = -ENODEV; 3080 return ret; 3081 } 3082 3083 if (host->use_dma && host->dma_ops->init) 3084 host->dma_ops->init(host); 3085 3086 /* 3087 * Restore the initial value at FIFOTH register 3088 * And Invalidate the prev_blksz with zero 3089 */ 3090 mci_writel(host, FIFOTH, host->fifoth_val); 3091 host->prev_blksz = 0; 3092 3093 /* Put in max timeout */ 3094 mci_writel(host, TMOUT, 0xFFFFFFFF); 3095 3096 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3097 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3098 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3099 DW_MCI_ERROR_FLAGS); 3100 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3101 3102 for (i = 0; i < host->num_slots; i++) { 3103 struct dw_mci_slot *slot = host->slot[i]; 3104 3105 if (!slot) 3106 continue; 3107 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { 3108 dw_mci_set_ios(slot->mmc, &slot->mmc->ios); 3109 dw_mci_setup_bus(slot, true); 3110 } 3111 } 3112 3113 /* Now that slots are all setup, we can enable card detect */ 3114 dw_mci_enable_cd(host); 3115 3116 return 0; 3117 } 3118 EXPORT_SYMBOL(dw_mci_resume); 3119 #endif /* CONFIG_PM_SLEEP */ 3120 3121 static int __init dw_mci_init(void) 3122 { 3123 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3124 return 0; 3125 } 3126 3127 static void __exit dw_mci_exit(void) 3128 { 3129 } 3130 3131 module_init(dw_mci_init); 3132 module_exit(dw_mci_exit); 3133 3134 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3135 MODULE_AUTHOR("NXP Semiconductor VietNam"); 3136 MODULE_AUTHOR("Imagination Technologies Ltd"); 3137 MODULE_LICENSE("GPL v2"); 3138