1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/blkdev.h> 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/ioport.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/stat.h> 28 #include <linux/delay.h> 29 #include <linux/irq.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/dw_mmc.h> 33 #include <linux/bitops.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/workqueue.h> 36 37 #include "dw_mmc.h" 38 39 /* Common flag combinations */ 40 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \ 41 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 42 SDMMC_INT_EBE) 43 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 44 SDMMC_INT_RESP_ERR) 45 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 47 #define DW_MCI_SEND_STATUS 1 48 #define DW_MCI_RECV_STATUS 2 49 #define DW_MCI_DMA_THRESHOLD 16 50 51 #ifdef CONFIG_MMC_DW_IDMAC 52 struct idmac_desc { 53 u32 des0; /* Control Descriptor */ 54 #define IDMAC_DES0_DIC BIT(1) 55 #define IDMAC_DES0_LD BIT(2) 56 #define IDMAC_DES0_FD BIT(3) 57 #define IDMAC_DES0_CH BIT(4) 58 #define IDMAC_DES0_ER BIT(5) 59 #define IDMAC_DES0_CES BIT(30) 60 #define IDMAC_DES0_OWN BIT(31) 61 62 u32 des1; /* Buffer sizes */ 63 #define IDMAC_SET_BUFFER1_SIZE(d, s) \ 64 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) 65 66 u32 des2; /* buffer 1 physical address */ 67 68 u32 des3; /* buffer 2 physical address */ 69 }; 70 #endif /* CONFIG_MMC_DW_IDMAC */ 71 72 /** 73 * struct dw_mci_slot - MMC slot state 74 * @mmc: The mmc_host representing this slot. 75 * @host: The MMC controller this slot is using. 76 * @ctype: Card type for this slot. 77 * @mrq: mmc_request currently being processed or waiting to be 78 * processed, or NULL when the slot is idle. 79 * @queue_node: List node for placing this node in the @queue list of 80 * &struct dw_mci. 81 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 82 * @flags: Random state bits associated with the slot. 83 * @id: Number of this slot. 84 * @last_detect_state: Most recently observed card detect state. 85 */ 86 struct dw_mci_slot { 87 struct mmc_host *mmc; 88 struct dw_mci *host; 89 90 u32 ctype; 91 92 struct mmc_request *mrq; 93 struct list_head queue_node; 94 95 unsigned int clock; 96 unsigned long flags; 97 #define DW_MMC_CARD_PRESENT 0 98 #define DW_MMC_CARD_NEED_INIT 1 99 int id; 100 int last_detect_state; 101 }; 102 103 #if defined(CONFIG_DEBUG_FS) 104 static int dw_mci_req_show(struct seq_file *s, void *v) 105 { 106 struct dw_mci_slot *slot = s->private; 107 struct mmc_request *mrq; 108 struct mmc_command *cmd; 109 struct mmc_command *stop; 110 struct mmc_data *data; 111 112 /* Make sure we get a consistent snapshot */ 113 spin_lock_bh(&slot->host->lock); 114 mrq = slot->mrq; 115 116 if (mrq) { 117 cmd = mrq->cmd; 118 data = mrq->data; 119 stop = mrq->stop; 120 121 if (cmd) 122 seq_printf(s, 123 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 124 cmd->opcode, cmd->arg, cmd->flags, 125 cmd->resp[0], cmd->resp[1], cmd->resp[2], 126 cmd->resp[2], cmd->error); 127 if (data) 128 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 129 data->bytes_xfered, data->blocks, 130 data->blksz, data->flags, data->error); 131 if (stop) 132 seq_printf(s, 133 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 134 stop->opcode, stop->arg, stop->flags, 135 stop->resp[0], stop->resp[1], stop->resp[2], 136 stop->resp[2], stop->error); 137 } 138 139 spin_unlock_bh(&slot->host->lock); 140 141 return 0; 142 } 143 144 static int dw_mci_req_open(struct inode *inode, struct file *file) 145 { 146 return single_open(file, dw_mci_req_show, inode->i_private); 147 } 148 149 static const struct file_operations dw_mci_req_fops = { 150 .owner = THIS_MODULE, 151 .open = dw_mci_req_open, 152 .read = seq_read, 153 .llseek = seq_lseek, 154 .release = single_release, 155 }; 156 157 static int dw_mci_regs_show(struct seq_file *s, void *v) 158 { 159 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 160 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 161 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 162 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 163 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 164 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 165 166 return 0; 167 } 168 169 static int dw_mci_regs_open(struct inode *inode, struct file *file) 170 { 171 return single_open(file, dw_mci_regs_show, inode->i_private); 172 } 173 174 static const struct file_operations dw_mci_regs_fops = { 175 .owner = THIS_MODULE, 176 .open = dw_mci_regs_open, 177 .read = seq_read, 178 .llseek = seq_lseek, 179 .release = single_release, 180 }; 181 182 static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 183 { 184 struct mmc_host *mmc = slot->mmc; 185 struct dw_mci *host = slot->host; 186 struct dentry *root; 187 struct dentry *node; 188 189 root = mmc->debugfs_root; 190 if (!root) 191 return; 192 193 node = debugfs_create_file("regs", S_IRUSR, root, host, 194 &dw_mci_regs_fops); 195 if (!node) 196 goto err; 197 198 node = debugfs_create_file("req", S_IRUSR, root, slot, 199 &dw_mci_req_fops); 200 if (!node) 201 goto err; 202 203 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 204 if (!node) 205 goto err; 206 207 node = debugfs_create_x32("pending_events", S_IRUSR, root, 208 (u32 *)&host->pending_events); 209 if (!node) 210 goto err; 211 212 node = debugfs_create_x32("completed_events", S_IRUSR, root, 213 (u32 *)&host->completed_events); 214 if (!node) 215 goto err; 216 217 return; 218 219 err: 220 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 221 } 222 #endif /* defined(CONFIG_DEBUG_FS) */ 223 224 static void dw_mci_set_timeout(struct dw_mci *host) 225 { 226 /* timeout (maximum) */ 227 mci_writel(host, TMOUT, 0xffffffff); 228 } 229 230 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 231 { 232 struct mmc_data *data; 233 u32 cmdr; 234 cmd->error = -EINPROGRESS; 235 236 cmdr = cmd->opcode; 237 238 if (cmdr == MMC_STOP_TRANSMISSION) 239 cmdr |= SDMMC_CMD_STOP; 240 else 241 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 242 243 if (cmd->flags & MMC_RSP_PRESENT) { 244 /* We expect a response, so set this bit */ 245 cmdr |= SDMMC_CMD_RESP_EXP; 246 if (cmd->flags & MMC_RSP_136) 247 cmdr |= SDMMC_CMD_RESP_LONG; 248 } 249 250 if (cmd->flags & MMC_RSP_CRC) 251 cmdr |= SDMMC_CMD_RESP_CRC; 252 253 data = cmd->data; 254 if (data) { 255 cmdr |= SDMMC_CMD_DAT_EXP; 256 if (data->flags & MMC_DATA_STREAM) 257 cmdr |= SDMMC_CMD_STRM_MODE; 258 if (data->flags & MMC_DATA_WRITE) 259 cmdr |= SDMMC_CMD_DAT_WR; 260 } 261 262 return cmdr; 263 } 264 265 static void dw_mci_start_command(struct dw_mci *host, 266 struct mmc_command *cmd, u32 cmd_flags) 267 { 268 host->cmd = cmd; 269 dev_vdbg(&host->dev, 270 "start command: ARGR=0x%08x CMDR=0x%08x\n", 271 cmd->arg, cmd_flags); 272 273 mci_writel(host, CMDARG, cmd->arg); 274 wmb(); 275 276 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 277 } 278 279 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data) 280 { 281 dw_mci_start_command(host, data->stop, host->stop_cmdr); 282 } 283 284 /* DMA interface functions */ 285 static void dw_mci_stop_dma(struct dw_mci *host) 286 { 287 if (host->using_dma) { 288 host->dma_ops->stop(host); 289 host->dma_ops->cleanup(host); 290 } else { 291 /* Data transfer was stopped by the interrupt handler */ 292 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 293 } 294 } 295 296 static int dw_mci_get_dma_dir(struct mmc_data *data) 297 { 298 if (data->flags & MMC_DATA_WRITE) 299 return DMA_TO_DEVICE; 300 else 301 return DMA_FROM_DEVICE; 302 } 303 304 #ifdef CONFIG_MMC_DW_IDMAC 305 static void dw_mci_dma_cleanup(struct dw_mci *host) 306 { 307 struct mmc_data *data = host->data; 308 309 if (data) 310 if (!data->host_cookie) 311 dma_unmap_sg(&host->dev, 312 data->sg, 313 data->sg_len, 314 dw_mci_get_dma_dir(data)); 315 } 316 317 static void dw_mci_idmac_stop_dma(struct dw_mci *host) 318 { 319 u32 temp; 320 321 /* Disable and reset the IDMAC interface */ 322 temp = mci_readl(host, CTRL); 323 temp &= ~SDMMC_CTRL_USE_IDMAC; 324 temp |= SDMMC_CTRL_DMA_RESET; 325 mci_writel(host, CTRL, temp); 326 327 /* Stop the IDMAC running */ 328 temp = mci_readl(host, BMOD); 329 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 330 mci_writel(host, BMOD, temp); 331 } 332 333 static void dw_mci_idmac_complete_dma(struct dw_mci *host) 334 { 335 struct mmc_data *data = host->data; 336 337 dev_vdbg(&host->dev, "DMA complete\n"); 338 339 host->dma_ops->cleanup(host); 340 341 /* 342 * If the card was removed, data will be NULL. No point in trying to 343 * send the stop command or waiting for NBUSY in this case. 344 */ 345 if (data) { 346 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 347 tasklet_schedule(&host->tasklet); 348 } 349 } 350 351 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 352 unsigned int sg_len) 353 { 354 int i; 355 struct idmac_desc *desc = host->sg_cpu; 356 357 for (i = 0; i < sg_len; i++, desc++) { 358 unsigned int length = sg_dma_len(&data->sg[i]); 359 u32 mem_addr = sg_dma_address(&data->sg[i]); 360 361 /* Set the OWN bit and disable interrupts for this descriptor */ 362 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; 363 364 /* Buffer length */ 365 IDMAC_SET_BUFFER1_SIZE(desc, length); 366 367 /* Physical address to DMA to/from */ 368 desc->des2 = mem_addr; 369 } 370 371 /* Set first descriptor */ 372 desc = host->sg_cpu; 373 desc->des0 |= IDMAC_DES0_FD; 374 375 /* Set last descriptor */ 376 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 377 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 378 desc->des0 |= IDMAC_DES0_LD; 379 380 wmb(); 381 } 382 383 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 384 { 385 u32 temp; 386 387 dw_mci_translate_sglist(host, host->data, sg_len); 388 389 /* Select IDMAC interface */ 390 temp = mci_readl(host, CTRL); 391 temp |= SDMMC_CTRL_USE_IDMAC; 392 mci_writel(host, CTRL, temp); 393 394 wmb(); 395 396 /* Enable the IDMAC */ 397 temp = mci_readl(host, BMOD); 398 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 399 mci_writel(host, BMOD, temp); 400 401 /* Start it running */ 402 mci_writel(host, PLDMND, 1); 403 } 404 405 static int dw_mci_idmac_init(struct dw_mci *host) 406 { 407 struct idmac_desc *p; 408 int i, dma_support; 409 410 /* Number of descriptors in the ring buffer */ 411 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 412 413 /* Check if Hardware Configuration Register has support for DMA */ 414 dma_support = (mci_readl(host, HCON) >> 16) & 0x3; 415 416 if (!dma_support || dma_support > 2) { 417 dev_err(&host->dev, 418 "Host Controller does not support IDMA Tx.\n"); 419 host->dma_ops = NULL; 420 return -ENODEV; 421 } 422 423 dev_info(&host->dev, "Using internal DMA controller.\n"); 424 425 /* Forward link the descriptor list */ 426 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 427 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1)); 428 429 /* Set the last descriptor as the end-of-ring descriptor */ 430 p->des3 = host->sg_dma; 431 p->des0 = IDMAC_DES0_ER; 432 433 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET); 434 435 /* Mask out interrupts - get Tx & Rx complete only */ 436 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI | 437 SDMMC_IDMAC_INT_TI); 438 439 /* Set the descriptor base address */ 440 mci_writel(host, DBADDR, host->sg_dma); 441 return 0; 442 } 443 444 static struct dw_mci_dma_ops dw_mci_idmac_ops = { 445 .init = dw_mci_idmac_init, 446 .start = dw_mci_idmac_start_dma, 447 .stop = dw_mci_idmac_stop_dma, 448 .complete = dw_mci_idmac_complete_dma, 449 .cleanup = dw_mci_dma_cleanup, 450 }; 451 #endif /* CONFIG_MMC_DW_IDMAC */ 452 453 static int dw_mci_pre_dma_transfer(struct dw_mci *host, 454 struct mmc_data *data, 455 bool next) 456 { 457 struct scatterlist *sg; 458 unsigned int i, sg_len; 459 460 if (!next && data->host_cookie) 461 return data->host_cookie; 462 463 /* 464 * We don't do DMA on "complex" transfers, i.e. with 465 * non-word-aligned buffers or lengths. Also, we don't bother 466 * with all the DMA setup overhead for short transfers. 467 */ 468 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 469 return -EINVAL; 470 471 if (data->blksz & 3) 472 return -EINVAL; 473 474 for_each_sg(data->sg, sg, data->sg_len, i) { 475 if (sg->offset & 3 || sg->length & 3) 476 return -EINVAL; 477 } 478 479 sg_len = dma_map_sg(&host->dev, 480 data->sg, 481 data->sg_len, 482 dw_mci_get_dma_dir(data)); 483 if (sg_len == 0) 484 return -EINVAL; 485 486 if (next) 487 data->host_cookie = sg_len; 488 489 return sg_len; 490 } 491 492 static void dw_mci_pre_req(struct mmc_host *mmc, 493 struct mmc_request *mrq, 494 bool is_first_req) 495 { 496 struct dw_mci_slot *slot = mmc_priv(mmc); 497 struct mmc_data *data = mrq->data; 498 499 if (!slot->host->use_dma || !data) 500 return; 501 502 if (data->host_cookie) { 503 data->host_cookie = 0; 504 return; 505 } 506 507 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) 508 data->host_cookie = 0; 509 } 510 511 static void dw_mci_post_req(struct mmc_host *mmc, 512 struct mmc_request *mrq, 513 int err) 514 { 515 struct dw_mci_slot *slot = mmc_priv(mmc); 516 struct mmc_data *data = mrq->data; 517 518 if (!slot->host->use_dma || !data) 519 return; 520 521 if (data->host_cookie) 522 dma_unmap_sg(&slot->host->dev, 523 data->sg, 524 data->sg_len, 525 dw_mci_get_dma_dir(data)); 526 data->host_cookie = 0; 527 } 528 529 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 530 { 531 int sg_len; 532 u32 temp; 533 534 host->using_dma = 0; 535 536 /* If we don't have a channel, we can't do DMA */ 537 if (!host->use_dma) 538 return -ENODEV; 539 540 sg_len = dw_mci_pre_dma_transfer(host, data, 0); 541 if (sg_len < 0) { 542 host->dma_ops->stop(host); 543 return sg_len; 544 } 545 546 host->using_dma = 1; 547 548 dev_vdbg(&host->dev, 549 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 550 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 551 sg_len); 552 553 /* Enable the DMA interface */ 554 temp = mci_readl(host, CTRL); 555 temp |= SDMMC_CTRL_DMA_ENABLE; 556 mci_writel(host, CTRL, temp); 557 558 /* Disable RX/TX IRQs, let DMA handle it */ 559 temp = mci_readl(host, INTMASK); 560 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 561 mci_writel(host, INTMASK, temp); 562 563 host->dma_ops->start(host, sg_len); 564 565 return 0; 566 } 567 568 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 569 { 570 u32 temp; 571 572 data->error = -EINPROGRESS; 573 574 WARN_ON(host->data); 575 host->sg = NULL; 576 host->data = data; 577 578 if (data->flags & MMC_DATA_READ) 579 host->dir_status = DW_MCI_RECV_STATUS; 580 else 581 host->dir_status = DW_MCI_SEND_STATUS; 582 583 if (dw_mci_submit_data_dma(host, data)) { 584 int flags = SG_MITER_ATOMIC; 585 if (host->data->flags & MMC_DATA_READ) 586 flags |= SG_MITER_TO_SG; 587 else 588 flags |= SG_MITER_FROM_SG; 589 590 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 591 host->sg = data->sg; 592 host->part_buf_start = 0; 593 host->part_buf_count = 0; 594 595 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 596 temp = mci_readl(host, INTMASK); 597 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 598 mci_writel(host, INTMASK, temp); 599 600 temp = mci_readl(host, CTRL); 601 temp &= ~SDMMC_CTRL_DMA_ENABLE; 602 mci_writel(host, CTRL, temp); 603 } 604 } 605 606 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 607 { 608 struct dw_mci *host = slot->host; 609 unsigned long timeout = jiffies + msecs_to_jiffies(500); 610 unsigned int cmd_status = 0; 611 612 mci_writel(host, CMDARG, arg); 613 wmb(); 614 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 615 616 while (time_before(jiffies, timeout)) { 617 cmd_status = mci_readl(host, CMD); 618 if (!(cmd_status & SDMMC_CMD_START)) 619 return; 620 } 621 dev_err(&slot->mmc->class_dev, 622 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 623 cmd, arg, cmd_status); 624 } 625 626 static void dw_mci_setup_bus(struct dw_mci_slot *slot) 627 { 628 struct dw_mci *host = slot->host; 629 u32 div; 630 u32 clk_en_a; 631 632 if (slot->clock != host->current_speed) { 633 div = host->bus_hz / slot->clock; 634 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock) 635 /* 636 * move the + 1 after the divide to prevent 637 * over-clocking the card. 638 */ 639 div += 1; 640 641 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0; 642 643 dev_info(&slot->mmc->class_dev, 644 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ" 645 " div = %d)\n", slot->id, host->bus_hz, slot->clock, 646 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div); 647 648 /* disable clock */ 649 mci_writel(host, CLKENA, 0); 650 mci_writel(host, CLKSRC, 0); 651 652 /* inform CIU */ 653 mci_send_cmd(slot, 654 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 655 656 /* set clock to desired speed */ 657 mci_writel(host, CLKDIV, div); 658 659 /* inform CIU */ 660 mci_send_cmd(slot, 661 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 662 663 /* enable clock; only low power if no SDIO */ 664 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 665 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id))) 666 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 667 mci_writel(host, CLKENA, clk_en_a); 668 669 /* inform CIU */ 670 mci_send_cmd(slot, 671 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 672 673 host->current_speed = slot->clock; 674 } 675 676 /* Set the current slot bus width */ 677 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 678 } 679 680 static void __dw_mci_start_request(struct dw_mci *host, 681 struct dw_mci_slot *slot, 682 struct mmc_command *cmd) 683 { 684 struct mmc_request *mrq; 685 struct mmc_data *data; 686 u32 cmdflags; 687 688 mrq = slot->mrq; 689 if (host->pdata->select_slot) 690 host->pdata->select_slot(slot->id); 691 692 /* Slot specific timing and width adjustment */ 693 dw_mci_setup_bus(slot); 694 695 host->cur_slot = slot; 696 host->mrq = mrq; 697 698 host->pending_events = 0; 699 host->completed_events = 0; 700 host->data_status = 0; 701 702 data = cmd->data; 703 if (data) { 704 dw_mci_set_timeout(host); 705 mci_writel(host, BYTCNT, data->blksz*data->blocks); 706 mci_writel(host, BLKSIZ, data->blksz); 707 } 708 709 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 710 711 /* this is the first command, send the initialization clock */ 712 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 713 cmdflags |= SDMMC_CMD_INIT; 714 715 if (data) { 716 dw_mci_submit_data(host, data); 717 wmb(); 718 } 719 720 dw_mci_start_command(host, cmd, cmdflags); 721 722 if (mrq->stop) 723 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 724 } 725 726 static void dw_mci_start_request(struct dw_mci *host, 727 struct dw_mci_slot *slot) 728 { 729 struct mmc_request *mrq = slot->mrq; 730 struct mmc_command *cmd; 731 732 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 733 __dw_mci_start_request(host, slot, cmd); 734 } 735 736 /* must be called with host->lock held */ 737 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 738 struct mmc_request *mrq) 739 { 740 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 741 host->state); 742 743 slot->mrq = mrq; 744 745 if (host->state == STATE_IDLE) { 746 host->state = STATE_SENDING_CMD; 747 dw_mci_start_request(host, slot); 748 } else { 749 list_add_tail(&slot->queue_node, &host->queue); 750 } 751 } 752 753 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 754 { 755 struct dw_mci_slot *slot = mmc_priv(mmc); 756 struct dw_mci *host = slot->host; 757 758 WARN_ON(slot->mrq); 759 760 /* 761 * The check for card presence and queueing of the request must be 762 * atomic, otherwise the card could be removed in between and the 763 * request wouldn't fail until another card was inserted. 764 */ 765 spin_lock_bh(&host->lock); 766 767 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 768 spin_unlock_bh(&host->lock); 769 mrq->cmd->error = -ENOMEDIUM; 770 mmc_request_done(mmc, mrq); 771 return; 772 } 773 774 dw_mci_queue_request(host, slot, mrq); 775 776 spin_unlock_bh(&host->lock); 777 } 778 779 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 780 { 781 struct dw_mci_slot *slot = mmc_priv(mmc); 782 u32 regs; 783 784 /* set default 1 bit mode */ 785 slot->ctype = SDMMC_CTYPE_1BIT; 786 787 switch (ios->bus_width) { 788 case MMC_BUS_WIDTH_1: 789 slot->ctype = SDMMC_CTYPE_1BIT; 790 break; 791 case MMC_BUS_WIDTH_4: 792 slot->ctype = SDMMC_CTYPE_4BIT; 793 break; 794 case MMC_BUS_WIDTH_8: 795 slot->ctype = SDMMC_CTYPE_8BIT; 796 break; 797 } 798 799 regs = mci_readl(slot->host, UHS_REG); 800 801 /* DDR mode set */ 802 if (ios->timing == MMC_TIMING_UHS_DDR50) 803 regs |= (0x1 << slot->id) << 16; 804 else 805 regs &= ~(0x1 << slot->id) << 16; 806 807 mci_writel(slot->host, UHS_REG, regs); 808 809 if (ios->clock) { 810 /* 811 * Use mirror of ios->clock to prevent race with mmc 812 * core ios update when finding the minimum. 813 */ 814 slot->clock = ios->clock; 815 } 816 817 switch (ios->power_mode) { 818 case MMC_POWER_UP: 819 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 820 break; 821 default: 822 break; 823 } 824 } 825 826 static int dw_mci_get_ro(struct mmc_host *mmc) 827 { 828 int read_only; 829 struct dw_mci_slot *slot = mmc_priv(mmc); 830 struct dw_mci_board *brd = slot->host->pdata; 831 832 /* Use platform get_ro function, else try on board write protect */ 833 if (brd->get_ro) 834 read_only = brd->get_ro(slot->id); 835 else 836 read_only = 837 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 838 839 dev_dbg(&mmc->class_dev, "card is %s\n", 840 read_only ? "read-only" : "read-write"); 841 842 return read_only; 843 } 844 845 static int dw_mci_get_cd(struct mmc_host *mmc) 846 { 847 int present; 848 struct dw_mci_slot *slot = mmc_priv(mmc); 849 struct dw_mci_board *brd = slot->host->pdata; 850 851 /* Use platform get_cd function, else try onboard card detect */ 852 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 853 present = 1; 854 else if (brd->get_cd) 855 present = !brd->get_cd(slot->id); 856 else 857 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 858 == 0 ? 1 : 0; 859 860 if (present) 861 dev_dbg(&mmc->class_dev, "card is present\n"); 862 else 863 dev_dbg(&mmc->class_dev, "card is not present\n"); 864 865 return present; 866 } 867 868 /* 869 * Disable lower power mode. 870 * 871 * Low power mode will stop the card clock when idle. According to the 872 * description of the CLKENA register we should disable low power mode 873 * for SDIO cards if we need SDIO interrupts to work. 874 * 875 * This function is fast if low power mode is already disabled. 876 */ 877 static void dw_mci_disable_low_power(struct dw_mci_slot *slot) 878 { 879 struct dw_mci *host = slot->host; 880 u32 clk_en_a; 881 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 882 883 clk_en_a = mci_readl(host, CLKENA); 884 885 if (clk_en_a & clken_low_pwr) { 886 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr); 887 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 888 SDMMC_CMD_PRV_DAT_WAIT, 0); 889 } 890 } 891 892 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 893 { 894 struct dw_mci_slot *slot = mmc_priv(mmc); 895 struct dw_mci *host = slot->host; 896 u32 int_mask; 897 898 /* Enable/disable Slot Specific SDIO interrupt */ 899 int_mask = mci_readl(host, INTMASK); 900 if (enb) { 901 /* 902 * Turn off low power mode if it was enabled. This is a bit of 903 * a heavy operation and we disable / enable IRQs a lot, so 904 * we'll leave low power mode disabled and it will get 905 * re-enabled again in dw_mci_setup_bus(). 906 */ 907 dw_mci_disable_low_power(slot); 908 909 mci_writel(host, INTMASK, 910 (int_mask | SDMMC_INT_SDIO(slot->id))); 911 } else { 912 mci_writel(host, INTMASK, 913 (int_mask & ~SDMMC_INT_SDIO(slot->id))); 914 } 915 } 916 917 static const struct mmc_host_ops dw_mci_ops = { 918 .request = dw_mci_request, 919 .pre_req = dw_mci_pre_req, 920 .post_req = dw_mci_post_req, 921 .set_ios = dw_mci_set_ios, 922 .get_ro = dw_mci_get_ro, 923 .get_cd = dw_mci_get_cd, 924 .enable_sdio_irq = dw_mci_enable_sdio_irq, 925 }; 926 927 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 928 __releases(&host->lock) 929 __acquires(&host->lock) 930 { 931 struct dw_mci_slot *slot; 932 struct mmc_host *prev_mmc = host->cur_slot->mmc; 933 934 WARN_ON(host->cmd || host->data); 935 936 host->cur_slot->mrq = NULL; 937 host->mrq = NULL; 938 if (!list_empty(&host->queue)) { 939 slot = list_entry(host->queue.next, 940 struct dw_mci_slot, queue_node); 941 list_del(&slot->queue_node); 942 dev_vdbg(&host->dev, "list not empty: %s is next\n", 943 mmc_hostname(slot->mmc)); 944 host->state = STATE_SENDING_CMD; 945 dw_mci_start_request(host, slot); 946 } else { 947 dev_vdbg(&host->dev, "list empty\n"); 948 host->state = STATE_IDLE; 949 } 950 951 spin_unlock(&host->lock); 952 mmc_request_done(prev_mmc, mrq); 953 spin_lock(&host->lock); 954 } 955 956 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 957 { 958 u32 status = host->cmd_status; 959 960 host->cmd_status = 0; 961 962 /* Read the response from the card (up to 16 bytes) */ 963 if (cmd->flags & MMC_RSP_PRESENT) { 964 if (cmd->flags & MMC_RSP_136) { 965 cmd->resp[3] = mci_readl(host, RESP0); 966 cmd->resp[2] = mci_readl(host, RESP1); 967 cmd->resp[1] = mci_readl(host, RESP2); 968 cmd->resp[0] = mci_readl(host, RESP3); 969 } else { 970 cmd->resp[0] = mci_readl(host, RESP0); 971 cmd->resp[1] = 0; 972 cmd->resp[2] = 0; 973 cmd->resp[3] = 0; 974 } 975 } 976 977 if (status & SDMMC_INT_RTO) 978 cmd->error = -ETIMEDOUT; 979 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 980 cmd->error = -EILSEQ; 981 else if (status & SDMMC_INT_RESP_ERR) 982 cmd->error = -EIO; 983 else 984 cmd->error = 0; 985 986 if (cmd->error) { 987 /* newer ip versions need a delay between retries */ 988 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 989 mdelay(20); 990 991 if (cmd->data) { 992 dw_mci_stop_dma(host); 993 host->data = NULL; 994 } 995 } 996 } 997 998 static void dw_mci_tasklet_func(unsigned long priv) 999 { 1000 struct dw_mci *host = (struct dw_mci *)priv; 1001 struct mmc_data *data; 1002 struct mmc_command *cmd; 1003 enum dw_mci_state state; 1004 enum dw_mci_state prev_state; 1005 u32 status, ctrl; 1006 1007 spin_lock(&host->lock); 1008 1009 state = host->state; 1010 data = host->data; 1011 1012 do { 1013 prev_state = state; 1014 1015 switch (state) { 1016 case STATE_IDLE: 1017 break; 1018 1019 case STATE_SENDING_CMD: 1020 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1021 &host->pending_events)) 1022 break; 1023 1024 cmd = host->cmd; 1025 host->cmd = NULL; 1026 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1027 dw_mci_command_complete(host, cmd); 1028 if (cmd == host->mrq->sbc && !cmd->error) { 1029 prev_state = state = STATE_SENDING_CMD; 1030 __dw_mci_start_request(host, host->cur_slot, 1031 host->mrq->cmd); 1032 goto unlock; 1033 } 1034 1035 if (!host->mrq->data || cmd->error) { 1036 dw_mci_request_end(host, host->mrq); 1037 goto unlock; 1038 } 1039 1040 prev_state = state = STATE_SENDING_DATA; 1041 /* fall through */ 1042 1043 case STATE_SENDING_DATA: 1044 if (test_and_clear_bit(EVENT_DATA_ERROR, 1045 &host->pending_events)) { 1046 dw_mci_stop_dma(host); 1047 if (data->stop) 1048 send_stop_cmd(host, data); 1049 state = STATE_DATA_ERROR; 1050 break; 1051 } 1052 1053 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1054 &host->pending_events)) 1055 break; 1056 1057 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 1058 prev_state = state = STATE_DATA_BUSY; 1059 /* fall through */ 1060 1061 case STATE_DATA_BUSY: 1062 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 1063 &host->pending_events)) 1064 break; 1065 1066 host->data = NULL; 1067 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 1068 status = host->data_status; 1069 1070 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1071 if (status & SDMMC_INT_DTO) { 1072 data->error = -ETIMEDOUT; 1073 } else if (status & SDMMC_INT_DCRC) { 1074 data->error = -EILSEQ; 1075 } else if (status & SDMMC_INT_EBE && 1076 host->dir_status == 1077 DW_MCI_SEND_STATUS) { 1078 /* 1079 * No data CRC status was returned. 1080 * The number of bytes transferred will 1081 * be exaggerated in PIO mode. 1082 */ 1083 data->bytes_xfered = 0; 1084 data->error = -ETIMEDOUT; 1085 } else { 1086 dev_err(&host->dev, 1087 "data FIFO error " 1088 "(status=%08x)\n", 1089 status); 1090 data->error = -EIO; 1091 } 1092 /* 1093 * After an error, there may be data lingering 1094 * in the FIFO, so reset it - doing so 1095 * generates a block interrupt, hence setting 1096 * the scatter-gather pointer to NULL. 1097 */ 1098 sg_miter_stop(&host->sg_miter); 1099 host->sg = NULL; 1100 ctrl = mci_readl(host, CTRL); 1101 ctrl |= SDMMC_CTRL_FIFO_RESET; 1102 mci_writel(host, CTRL, ctrl); 1103 } else { 1104 data->bytes_xfered = data->blocks * data->blksz; 1105 data->error = 0; 1106 } 1107 1108 if (!data->stop) { 1109 dw_mci_request_end(host, host->mrq); 1110 goto unlock; 1111 } 1112 1113 if (host->mrq->sbc && !data->error) { 1114 data->stop->error = 0; 1115 dw_mci_request_end(host, host->mrq); 1116 goto unlock; 1117 } 1118 1119 prev_state = state = STATE_SENDING_STOP; 1120 if (!data->error) 1121 send_stop_cmd(host, data); 1122 /* fall through */ 1123 1124 case STATE_SENDING_STOP: 1125 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 1126 &host->pending_events)) 1127 break; 1128 1129 host->cmd = NULL; 1130 dw_mci_command_complete(host, host->mrq->stop); 1131 dw_mci_request_end(host, host->mrq); 1132 goto unlock; 1133 1134 case STATE_DATA_ERROR: 1135 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 1136 &host->pending_events)) 1137 break; 1138 1139 state = STATE_DATA_BUSY; 1140 break; 1141 } 1142 } while (state != prev_state); 1143 1144 host->state = state; 1145 unlock: 1146 spin_unlock(&host->lock); 1147 1148 } 1149 1150 /* push final bytes to part_buf, only use during push */ 1151 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 1152 { 1153 memcpy((void *)&host->part_buf, buf, cnt); 1154 host->part_buf_count = cnt; 1155 } 1156 1157 /* append bytes to part_buf, only use during push */ 1158 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 1159 { 1160 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 1161 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 1162 host->part_buf_count += cnt; 1163 return cnt; 1164 } 1165 1166 /* pull first bytes from part_buf, only use during pull */ 1167 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 1168 { 1169 cnt = min(cnt, (int)host->part_buf_count); 1170 if (cnt) { 1171 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 1172 cnt); 1173 host->part_buf_count -= cnt; 1174 host->part_buf_start += cnt; 1175 } 1176 return cnt; 1177 } 1178 1179 /* pull final bytes from the part_buf, assuming it's just been filled */ 1180 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 1181 { 1182 memcpy(buf, &host->part_buf, cnt); 1183 host->part_buf_start = cnt; 1184 host->part_buf_count = (1 << host->data_shift) - cnt; 1185 } 1186 1187 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1188 { 1189 /* try and push anything in the part_buf */ 1190 if (unlikely(host->part_buf_count)) { 1191 int len = dw_mci_push_part_bytes(host, buf, cnt); 1192 buf += len; 1193 cnt -= len; 1194 if (!sg_next(host->sg) || host->part_buf_count == 2) { 1195 mci_writew(host, DATA(host->data_offset), 1196 host->part_buf16); 1197 host->part_buf_count = 0; 1198 } 1199 } 1200 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1201 if (unlikely((unsigned long)buf & 0x1)) { 1202 while (cnt >= 2) { 1203 u16 aligned_buf[64]; 1204 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1205 int items = len >> 1; 1206 int i; 1207 /* memcpy from input buffer into aligned buffer */ 1208 memcpy(aligned_buf, buf, len); 1209 buf += len; 1210 cnt -= len; 1211 /* push data from aligned buffer into fifo */ 1212 for (i = 0; i < items; ++i) 1213 mci_writew(host, DATA(host->data_offset), 1214 aligned_buf[i]); 1215 } 1216 } else 1217 #endif 1218 { 1219 u16 *pdata = buf; 1220 for (; cnt >= 2; cnt -= 2) 1221 mci_writew(host, DATA(host->data_offset), *pdata++); 1222 buf = pdata; 1223 } 1224 /* put anything remaining in the part_buf */ 1225 if (cnt) { 1226 dw_mci_set_part_bytes(host, buf, cnt); 1227 if (!sg_next(host->sg)) 1228 mci_writew(host, DATA(host->data_offset), 1229 host->part_buf16); 1230 } 1231 } 1232 1233 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1234 { 1235 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1236 if (unlikely((unsigned long)buf & 0x1)) { 1237 while (cnt >= 2) { 1238 /* pull data from fifo into aligned buffer */ 1239 u16 aligned_buf[64]; 1240 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1241 int items = len >> 1; 1242 int i; 1243 for (i = 0; i < items; ++i) 1244 aligned_buf[i] = mci_readw(host, 1245 DATA(host->data_offset)); 1246 /* memcpy from aligned buffer into output buffer */ 1247 memcpy(buf, aligned_buf, len); 1248 buf += len; 1249 cnt -= len; 1250 } 1251 } else 1252 #endif 1253 { 1254 u16 *pdata = buf; 1255 for (; cnt >= 2; cnt -= 2) 1256 *pdata++ = mci_readw(host, DATA(host->data_offset)); 1257 buf = pdata; 1258 } 1259 if (cnt) { 1260 host->part_buf16 = mci_readw(host, DATA(host->data_offset)); 1261 dw_mci_pull_final_bytes(host, buf, cnt); 1262 } 1263 } 1264 1265 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1266 { 1267 /* try and push anything in the part_buf */ 1268 if (unlikely(host->part_buf_count)) { 1269 int len = dw_mci_push_part_bytes(host, buf, cnt); 1270 buf += len; 1271 cnt -= len; 1272 if (!sg_next(host->sg) || host->part_buf_count == 4) { 1273 mci_writel(host, DATA(host->data_offset), 1274 host->part_buf32); 1275 host->part_buf_count = 0; 1276 } 1277 } 1278 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1279 if (unlikely((unsigned long)buf & 0x3)) { 1280 while (cnt >= 4) { 1281 u32 aligned_buf[32]; 1282 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1283 int items = len >> 2; 1284 int i; 1285 /* memcpy from input buffer into aligned buffer */ 1286 memcpy(aligned_buf, buf, len); 1287 buf += len; 1288 cnt -= len; 1289 /* push data from aligned buffer into fifo */ 1290 for (i = 0; i < items; ++i) 1291 mci_writel(host, DATA(host->data_offset), 1292 aligned_buf[i]); 1293 } 1294 } else 1295 #endif 1296 { 1297 u32 *pdata = buf; 1298 for (; cnt >= 4; cnt -= 4) 1299 mci_writel(host, DATA(host->data_offset), *pdata++); 1300 buf = pdata; 1301 } 1302 /* put anything remaining in the part_buf */ 1303 if (cnt) { 1304 dw_mci_set_part_bytes(host, buf, cnt); 1305 if (!sg_next(host->sg)) 1306 mci_writel(host, DATA(host->data_offset), 1307 host->part_buf32); 1308 } 1309 } 1310 1311 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1312 { 1313 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1314 if (unlikely((unsigned long)buf & 0x3)) { 1315 while (cnt >= 4) { 1316 /* pull data from fifo into aligned buffer */ 1317 u32 aligned_buf[32]; 1318 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1319 int items = len >> 2; 1320 int i; 1321 for (i = 0; i < items; ++i) 1322 aligned_buf[i] = mci_readl(host, 1323 DATA(host->data_offset)); 1324 /* memcpy from aligned buffer into output buffer */ 1325 memcpy(buf, aligned_buf, len); 1326 buf += len; 1327 cnt -= len; 1328 } 1329 } else 1330 #endif 1331 { 1332 u32 *pdata = buf; 1333 for (; cnt >= 4; cnt -= 4) 1334 *pdata++ = mci_readl(host, DATA(host->data_offset)); 1335 buf = pdata; 1336 } 1337 if (cnt) { 1338 host->part_buf32 = mci_readl(host, DATA(host->data_offset)); 1339 dw_mci_pull_final_bytes(host, buf, cnt); 1340 } 1341 } 1342 1343 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1344 { 1345 /* try and push anything in the part_buf */ 1346 if (unlikely(host->part_buf_count)) { 1347 int len = dw_mci_push_part_bytes(host, buf, cnt); 1348 buf += len; 1349 cnt -= len; 1350 if (!sg_next(host->sg) || host->part_buf_count == 8) { 1351 mci_writew(host, DATA(host->data_offset), 1352 host->part_buf); 1353 host->part_buf_count = 0; 1354 } 1355 } 1356 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1357 if (unlikely((unsigned long)buf & 0x7)) { 1358 while (cnt >= 8) { 1359 u64 aligned_buf[16]; 1360 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1361 int items = len >> 3; 1362 int i; 1363 /* memcpy from input buffer into aligned buffer */ 1364 memcpy(aligned_buf, buf, len); 1365 buf += len; 1366 cnt -= len; 1367 /* push data from aligned buffer into fifo */ 1368 for (i = 0; i < items; ++i) 1369 mci_writeq(host, DATA(host->data_offset), 1370 aligned_buf[i]); 1371 } 1372 } else 1373 #endif 1374 { 1375 u64 *pdata = buf; 1376 for (; cnt >= 8; cnt -= 8) 1377 mci_writeq(host, DATA(host->data_offset), *pdata++); 1378 buf = pdata; 1379 } 1380 /* put anything remaining in the part_buf */ 1381 if (cnt) { 1382 dw_mci_set_part_bytes(host, buf, cnt); 1383 if (!sg_next(host->sg)) 1384 mci_writeq(host, DATA(host->data_offset), 1385 host->part_buf); 1386 } 1387 } 1388 1389 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1390 { 1391 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1392 if (unlikely((unsigned long)buf & 0x7)) { 1393 while (cnt >= 8) { 1394 /* pull data from fifo into aligned buffer */ 1395 u64 aligned_buf[16]; 1396 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1397 int items = len >> 3; 1398 int i; 1399 for (i = 0; i < items; ++i) 1400 aligned_buf[i] = mci_readq(host, 1401 DATA(host->data_offset)); 1402 /* memcpy from aligned buffer into output buffer */ 1403 memcpy(buf, aligned_buf, len); 1404 buf += len; 1405 cnt -= len; 1406 } 1407 } else 1408 #endif 1409 { 1410 u64 *pdata = buf; 1411 for (; cnt >= 8; cnt -= 8) 1412 *pdata++ = mci_readq(host, DATA(host->data_offset)); 1413 buf = pdata; 1414 } 1415 if (cnt) { 1416 host->part_buf = mci_readq(host, DATA(host->data_offset)); 1417 dw_mci_pull_final_bytes(host, buf, cnt); 1418 } 1419 } 1420 1421 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 1422 { 1423 int len; 1424 1425 /* get remaining partial bytes */ 1426 len = dw_mci_pull_part_bytes(host, buf, cnt); 1427 if (unlikely(len == cnt)) 1428 return; 1429 buf += len; 1430 cnt -= len; 1431 1432 /* get the rest of the data */ 1433 host->pull_data(host, buf, cnt); 1434 } 1435 1436 static void dw_mci_read_data_pio(struct dw_mci *host) 1437 { 1438 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1439 void *buf; 1440 unsigned int offset; 1441 struct mmc_data *data = host->data; 1442 int shift = host->data_shift; 1443 u32 status; 1444 unsigned int nbytes = 0, len; 1445 unsigned int remain, fcnt; 1446 1447 do { 1448 if (!sg_miter_next(sg_miter)) 1449 goto done; 1450 1451 host->sg = sg_miter->__sg; 1452 buf = sg_miter->addr; 1453 remain = sg_miter->length; 1454 offset = 0; 1455 1456 do { 1457 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 1458 << shift) + host->part_buf_count; 1459 len = min(remain, fcnt); 1460 if (!len) 1461 break; 1462 dw_mci_pull_data(host, (void *)(buf + offset), len); 1463 offset += len; 1464 nbytes += len; 1465 remain -= len; 1466 } while (remain); 1467 1468 sg_miter->consumed = offset; 1469 status = mci_readl(host, MINTSTS); 1470 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1471 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/ 1472 data->bytes_xfered += nbytes; 1473 1474 if (!remain) { 1475 if (!sg_miter_next(sg_miter)) 1476 goto done; 1477 sg_miter->consumed = 0; 1478 } 1479 sg_miter_stop(sg_miter); 1480 return; 1481 1482 done: 1483 data->bytes_xfered += nbytes; 1484 sg_miter_stop(sg_miter); 1485 host->sg = NULL; 1486 smp_wmb(); 1487 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1488 } 1489 1490 static void dw_mci_write_data_pio(struct dw_mci *host) 1491 { 1492 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1493 void *buf; 1494 unsigned int offset; 1495 struct mmc_data *data = host->data; 1496 int shift = host->data_shift; 1497 u32 status; 1498 unsigned int nbytes = 0, len; 1499 unsigned int fifo_depth = host->fifo_depth; 1500 unsigned int remain, fcnt; 1501 1502 do { 1503 if (!sg_miter_next(sg_miter)) 1504 goto done; 1505 1506 host->sg = sg_miter->__sg; 1507 buf = sg_miter->addr; 1508 remain = sg_miter->length; 1509 offset = 0; 1510 1511 do { 1512 fcnt = ((fifo_depth - 1513 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 1514 << shift) - host->part_buf_count; 1515 len = min(remain, fcnt); 1516 if (!len) 1517 break; 1518 host->push_data(host, (void *)(buf + offset), len); 1519 offset += len; 1520 nbytes += len; 1521 remain -= len; 1522 } while (remain); 1523 1524 sg_miter->consumed = offset; 1525 status = mci_readl(host, MINTSTS); 1526 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1527 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 1528 data->bytes_xfered += nbytes; 1529 1530 if (!remain) { 1531 if (!sg_miter_next(sg_miter)) 1532 goto done; 1533 sg_miter->consumed = 0; 1534 } 1535 sg_miter_stop(sg_miter); 1536 return; 1537 1538 done: 1539 data->bytes_xfered += nbytes; 1540 sg_miter_stop(sg_miter); 1541 host->sg = NULL; 1542 smp_wmb(); 1543 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1544 } 1545 1546 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 1547 { 1548 if (!host->cmd_status) 1549 host->cmd_status = status; 1550 1551 smp_wmb(); 1552 1553 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1554 tasklet_schedule(&host->tasklet); 1555 } 1556 1557 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 1558 { 1559 struct dw_mci *host = dev_id; 1560 u32 pending; 1561 unsigned int pass_count = 0; 1562 int i; 1563 1564 do { 1565 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 1566 1567 /* 1568 * DTO fix - version 2.10a and below, and only if internal DMA 1569 * is configured. 1570 */ 1571 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 1572 if (!pending && 1573 ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 1574 pending |= SDMMC_INT_DATA_OVER; 1575 } 1576 1577 if (!pending) 1578 break; 1579 1580 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 1581 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 1582 host->cmd_status = pending; 1583 smp_wmb(); 1584 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1585 } 1586 1587 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 1588 /* if there is an error report DATA_ERROR */ 1589 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 1590 host->data_status = pending; 1591 smp_wmb(); 1592 set_bit(EVENT_DATA_ERROR, &host->pending_events); 1593 tasklet_schedule(&host->tasklet); 1594 } 1595 1596 if (pending & SDMMC_INT_DATA_OVER) { 1597 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 1598 if (!host->data_status) 1599 host->data_status = pending; 1600 smp_wmb(); 1601 if (host->dir_status == DW_MCI_RECV_STATUS) { 1602 if (host->sg != NULL) 1603 dw_mci_read_data_pio(host); 1604 } 1605 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1606 tasklet_schedule(&host->tasklet); 1607 } 1608 1609 if (pending & SDMMC_INT_RXDR) { 1610 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1611 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 1612 dw_mci_read_data_pio(host); 1613 } 1614 1615 if (pending & SDMMC_INT_TXDR) { 1616 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1617 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 1618 dw_mci_write_data_pio(host); 1619 } 1620 1621 if (pending & SDMMC_INT_CMD_DONE) { 1622 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 1623 dw_mci_cmd_interrupt(host, pending); 1624 } 1625 1626 if (pending & SDMMC_INT_CD) { 1627 mci_writel(host, RINTSTS, SDMMC_INT_CD); 1628 queue_work(host->card_workqueue, &host->card_work); 1629 } 1630 1631 /* Handle SDIO Interrupts */ 1632 for (i = 0; i < host->num_slots; i++) { 1633 struct dw_mci_slot *slot = host->slot[i]; 1634 if (pending & SDMMC_INT_SDIO(i)) { 1635 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i)); 1636 mmc_signal_sdio_irq(slot->mmc); 1637 } 1638 } 1639 1640 } while (pass_count++ < 5); 1641 1642 #ifdef CONFIG_MMC_DW_IDMAC 1643 /* Handle DMA interrupts */ 1644 pending = mci_readl(host, IDSTS); 1645 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 1646 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI); 1647 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 1648 host->dma_ops->complete(host); 1649 } 1650 #endif 1651 1652 return IRQ_HANDLED; 1653 } 1654 1655 static void dw_mci_work_routine_card(struct work_struct *work) 1656 { 1657 struct dw_mci *host = container_of(work, struct dw_mci, card_work); 1658 int i; 1659 1660 for (i = 0; i < host->num_slots; i++) { 1661 struct dw_mci_slot *slot = host->slot[i]; 1662 struct mmc_host *mmc = slot->mmc; 1663 struct mmc_request *mrq; 1664 int present; 1665 u32 ctrl; 1666 1667 present = dw_mci_get_cd(mmc); 1668 while (present != slot->last_detect_state) { 1669 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1670 present ? "inserted" : "removed"); 1671 1672 /* Power up slot (before spin_lock, may sleep) */ 1673 if (present != 0 && host->pdata->setpower) 1674 host->pdata->setpower(slot->id, mmc->ocr_avail); 1675 1676 spin_lock_bh(&host->lock); 1677 1678 /* Card change detected */ 1679 slot->last_detect_state = present; 1680 1681 /* Mark card as present if applicable */ 1682 if (present != 0) 1683 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1684 1685 /* Clean up queue if present */ 1686 mrq = slot->mrq; 1687 if (mrq) { 1688 if (mrq == host->mrq) { 1689 host->data = NULL; 1690 host->cmd = NULL; 1691 1692 switch (host->state) { 1693 case STATE_IDLE: 1694 break; 1695 case STATE_SENDING_CMD: 1696 mrq->cmd->error = -ENOMEDIUM; 1697 if (!mrq->data) 1698 break; 1699 /* fall through */ 1700 case STATE_SENDING_DATA: 1701 mrq->data->error = -ENOMEDIUM; 1702 dw_mci_stop_dma(host); 1703 break; 1704 case STATE_DATA_BUSY: 1705 case STATE_DATA_ERROR: 1706 if (mrq->data->error == -EINPROGRESS) 1707 mrq->data->error = -ENOMEDIUM; 1708 if (!mrq->stop) 1709 break; 1710 /* fall through */ 1711 case STATE_SENDING_STOP: 1712 mrq->stop->error = -ENOMEDIUM; 1713 break; 1714 } 1715 1716 dw_mci_request_end(host, mrq); 1717 } else { 1718 list_del(&slot->queue_node); 1719 mrq->cmd->error = -ENOMEDIUM; 1720 if (mrq->data) 1721 mrq->data->error = -ENOMEDIUM; 1722 if (mrq->stop) 1723 mrq->stop->error = -ENOMEDIUM; 1724 1725 spin_unlock(&host->lock); 1726 mmc_request_done(slot->mmc, mrq); 1727 spin_lock(&host->lock); 1728 } 1729 } 1730 1731 /* Power down slot */ 1732 if (present == 0) { 1733 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1734 1735 /* 1736 * Clear down the FIFO - doing so generates a 1737 * block interrupt, hence setting the 1738 * scatter-gather pointer to NULL. 1739 */ 1740 sg_miter_stop(&host->sg_miter); 1741 host->sg = NULL; 1742 1743 ctrl = mci_readl(host, CTRL); 1744 ctrl |= SDMMC_CTRL_FIFO_RESET; 1745 mci_writel(host, CTRL, ctrl); 1746 1747 #ifdef CONFIG_MMC_DW_IDMAC 1748 ctrl = mci_readl(host, BMOD); 1749 /* Software reset of DMA */ 1750 ctrl |= SDMMC_IDMAC_SWRESET; 1751 mci_writel(host, BMOD, ctrl); 1752 #endif 1753 1754 } 1755 1756 spin_unlock_bh(&host->lock); 1757 1758 /* Power down slot (after spin_unlock, may sleep) */ 1759 if (present == 0 && host->pdata->setpower) 1760 host->pdata->setpower(slot->id, 0); 1761 1762 present = dw_mci_get_cd(mmc); 1763 } 1764 1765 mmc_detect_change(slot->mmc, 1766 msecs_to_jiffies(host->pdata->detect_delay_ms)); 1767 } 1768 } 1769 1770 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id) 1771 { 1772 struct mmc_host *mmc; 1773 struct dw_mci_slot *slot; 1774 1775 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->dev); 1776 if (!mmc) 1777 return -ENOMEM; 1778 1779 slot = mmc_priv(mmc); 1780 slot->id = id; 1781 slot->mmc = mmc; 1782 slot->host = host; 1783 1784 mmc->ops = &dw_mci_ops; 1785 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); 1786 mmc->f_max = host->bus_hz; 1787 1788 if (host->pdata->get_ocr) 1789 mmc->ocr_avail = host->pdata->get_ocr(id); 1790 else 1791 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1792 1793 /* 1794 * Start with slot power disabled, it will be enabled when a card 1795 * is detected. 1796 */ 1797 if (host->pdata->setpower) 1798 host->pdata->setpower(id, 0); 1799 1800 if (host->pdata->caps) 1801 mmc->caps = host->pdata->caps; 1802 1803 if (host->pdata->caps2) 1804 mmc->caps2 = host->pdata->caps2; 1805 1806 if (host->pdata->get_bus_wd) 1807 if (host->pdata->get_bus_wd(slot->id) >= 4) 1808 mmc->caps |= MMC_CAP_4_BIT_DATA; 1809 1810 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) 1811 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 1812 1813 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY) 1814 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT; 1815 else 1816 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE; 1817 1818 if (host->pdata->blk_settings) { 1819 mmc->max_segs = host->pdata->blk_settings->max_segs; 1820 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 1821 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 1822 mmc->max_req_size = host->pdata->blk_settings->max_req_size; 1823 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 1824 } else { 1825 /* Useful defaults if platform data is unset. */ 1826 #ifdef CONFIG_MMC_DW_IDMAC 1827 mmc->max_segs = host->ring_size; 1828 mmc->max_blk_size = 65536; 1829 mmc->max_blk_count = host->ring_size; 1830 mmc->max_seg_size = 0x1000; 1831 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; 1832 #else 1833 mmc->max_segs = 64; 1834 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 1835 mmc->max_blk_count = 512; 1836 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1837 mmc->max_seg_size = mmc->max_req_size; 1838 #endif /* CONFIG_MMC_DW_IDMAC */ 1839 } 1840 1841 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); 1842 if (IS_ERR(host->vmmc)) { 1843 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc)); 1844 host->vmmc = NULL; 1845 } else 1846 regulator_enable(host->vmmc); 1847 1848 if (dw_mci_get_cd(mmc)) 1849 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1850 else 1851 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1852 1853 host->slot[id] = slot; 1854 mmc_add_host(mmc); 1855 1856 #if defined(CONFIG_DEBUG_FS) 1857 dw_mci_init_debugfs(slot); 1858 #endif 1859 1860 /* Card initially undetected */ 1861 slot->last_detect_state = 0; 1862 1863 /* 1864 * Card may have been plugged in prior to boot so we 1865 * need to run the detect tasklet 1866 */ 1867 queue_work(host->card_workqueue, &host->card_work); 1868 1869 return 0; 1870 } 1871 1872 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 1873 { 1874 /* Shutdown detect IRQ */ 1875 if (slot->host->pdata->exit) 1876 slot->host->pdata->exit(id); 1877 1878 /* Debugfs stuff is cleaned up by mmc core */ 1879 mmc_remove_host(slot->mmc); 1880 slot->host->slot[id] = NULL; 1881 mmc_free_host(slot->mmc); 1882 } 1883 1884 static void dw_mci_init_dma(struct dw_mci *host) 1885 { 1886 /* Alloc memory for sg translation */ 1887 host->sg_cpu = dma_alloc_coherent(&host->dev, PAGE_SIZE, 1888 &host->sg_dma, GFP_KERNEL); 1889 if (!host->sg_cpu) { 1890 dev_err(&host->dev, "%s: could not alloc DMA memory\n", 1891 __func__); 1892 goto no_dma; 1893 } 1894 1895 /* Determine which DMA interface to use */ 1896 #ifdef CONFIG_MMC_DW_IDMAC 1897 host->dma_ops = &dw_mci_idmac_ops; 1898 #endif 1899 1900 if (!host->dma_ops) 1901 goto no_dma; 1902 1903 if (host->dma_ops->init && host->dma_ops->start && 1904 host->dma_ops->stop && host->dma_ops->cleanup) { 1905 if (host->dma_ops->init(host)) { 1906 dev_err(&host->dev, "%s: Unable to initialize " 1907 "DMA Controller.\n", __func__); 1908 goto no_dma; 1909 } 1910 } else { 1911 dev_err(&host->dev, "DMA initialization not found.\n"); 1912 goto no_dma; 1913 } 1914 1915 host->use_dma = 1; 1916 return; 1917 1918 no_dma: 1919 dev_info(&host->dev, "Using PIO mode.\n"); 1920 host->use_dma = 0; 1921 return; 1922 } 1923 1924 static bool mci_wait_reset(struct device *dev, struct dw_mci *host) 1925 { 1926 unsigned long timeout = jiffies + msecs_to_jiffies(500); 1927 unsigned int ctrl; 1928 1929 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 1930 SDMMC_CTRL_DMA_RESET)); 1931 1932 /* wait till resets clear */ 1933 do { 1934 ctrl = mci_readl(host, CTRL); 1935 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 1936 SDMMC_CTRL_DMA_RESET))) 1937 return true; 1938 } while (time_before(jiffies, timeout)); 1939 1940 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl); 1941 1942 return false; 1943 } 1944 1945 int dw_mci_probe(struct dw_mci *host) 1946 { 1947 int width, i, ret = 0; 1948 u32 fifo_size; 1949 1950 if (!host->pdata || !host->pdata->init) { 1951 dev_err(&host->dev, 1952 "Platform data must supply init function\n"); 1953 return -ENODEV; 1954 } 1955 1956 if (!host->pdata->select_slot && host->pdata->num_slots > 1) { 1957 dev_err(&host->dev, 1958 "Platform data must supply select_slot function\n"); 1959 return -ENODEV; 1960 } 1961 1962 if (!host->pdata->bus_hz) { 1963 dev_err(&host->dev, 1964 "Platform data must supply bus speed\n"); 1965 return -ENODEV; 1966 } 1967 1968 host->bus_hz = host->pdata->bus_hz; 1969 host->quirks = host->pdata->quirks; 1970 1971 spin_lock_init(&host->lock); 1972 INIT_LIST_HEAD(&host->queue); 1973 1974 /* 1975 * Get the host data width - this assumes that HCON has been set with 1976 * the correct values. 1977 */ 1978 i = (mci_readl(host, HCON) >> 7) & 0x7; 1979 if (!i) { 1980 host->push_data = dw_mci_push_data16; 1981 host->pull_data = dw_mci_pull_data16; 1982 width = 16; 1983 host->data_shift = 1; 1984 } else if (i == 2) { 1985 host->push_data = dw_mci_push_data64; 1986 host->pull_data = dw_mci_pull_data64; 1987 width = 64; 1988 host->data_shift = 3; 1989 } else { 1990 /* Check for a reserved value, and warn if it is */ 1991 WARN((i != 1), 1992 "HCON reports a reserved host data width!\n" 1993 "Defaulting to 32-bit access.\n"); 1994 host->push_data = dw_mci_push_data32; 1995 host->pull_data = dw_mci_pull_data32; 1996 width = 32; 1997 host->data_shift = 2; 1998 } 1999 2000 /* Reset all blocks */ 2001 if (!mci_wait_reset(&host->dev, host)) 2002 return -ENODEV; 2003 2004 host->dma_ops = host->pdata->dma_ops; 2005 dw_mci_init_dma(host); 2006 2007 /* Clear the interrupts for the host controller */ 2008 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2009 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2010 2011 /* Put in max timeout */ 2012 mci_writel(host, TMOUT, 0xFFFFFFFF); 2013 2014 /* 2015 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 2016 * Tx Mark = fifo_size / 2 DMA Size = 8 2017 */ 2018 if (!host->pdata->fifo_depth) { 2019 /* 2020 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 2021 * have been overwritten by the bootloader, just like we're 2022 * about to do, so if you know the value for your hardware, you 2023 * should put it in the platform data. 2024 */ 2025 fifo_size = mci_readl(host, FIFOTH); 2026 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 2027 } else { 2028 fifo_size = host->pdata->fifo_depth; 2029 } 2030 host->fifo_depth = fifo_size; 2031 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | 2032 ((fifo_size/2) << 0)); 2033 mci_writel(host, FIFOTH, host->fifoth_val); 2034 2035 /* disable clock to CIU */ 2036 mci_writel(host, CLKENA, 0); 2037 mci_writel(host, CLKSRC, 0); 2038 2039 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 2040 host->card_workqueue = alloc_workqueue("dw-mci-card", 2041 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1); 2042 if (!host->card_workqueue) 2043 goto err_dmaunmap; 2044 INIT_WORK(&host->card_work, dw_mci_work_routine_card); 2045 ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host); 2046 if (ret) 2047 goto err_workqueue; 2048 2049 if (host->pdata->num_slots) 2050 host->num_slots = host->pdata->num_slots; 2051 else 2052 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 2053 2054 /* We need at least one slot to succeed */ 2055 for (i = 0; i < host->num_slots; i++) { 2056 ret = dw_mci_init_slot(host, i); 2057 if (ret) { 2058 ret = -ENODEV; 2059 goto err_init_slot; 2060 } 2061 } 2062 2063 /* 2064 * In 2.40a spec, Data offset is changed. 2065 * Need to check the version-id and set data-offset for DATA register. 2066 */ 2067 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 2068 dev_info(&host->dev, "Version ID is %04x\n", host->verid); 2069 2070 if (host->verid < DW_MMC_240A) 2071 host->data_offset = DATA_OFFSET; 2072 else 2073 host->data_offset = DATA_240A_OFFSET; 2074 2075 /* 2076 * Enable interrupts for command done, data over, data empty, card det, 2077 * receive ready and error such as transmit, receive timeout, crc error 2078 */ 2079 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2080 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2081 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2082 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2083 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 2084 2085 dev_info(&host->dev, "DW MMC controller at irq %d, " 2086 "%d bit host data width, " 2087 "%u deep fifo\n", 2088 host->irq, width, fifo_size); 2089 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 2090 dev_info(&host->dev, "Internal DMAC interrupt fix enabled.\n"); 2091 2092 return 0; 2093 2094 err_init_slot: 2095 /* De-init any initialized slots */ 2096 while (i > 0) { 2097 if (host->slot[i]) 2098 dw_mci_cleanup_slot(host->slot[i], i); 2099 i--; 2100 } 2101 free_irq(host->irq, host); 2102 2103 err_workqueue: 2104 destroy_workqueue(host->card_workqueue); 2105 2106 err_dmaunmap: 2107 if (host->use_dma && host->dma_ops->exit) 2108 host->dma_ops->exit(host); 2109 dma_free_coherent(&host->dev, PAGE_SIZE, 2110 host->sg_cpu, host->sg_dma); 2111 2112 if (host->vmmc) { 2113 regulator_disable(host->vmmc); 2114 regulator_put(host->vmmc); 2115 } 2116 return ret; 2117 } 2118 EXPORT_SYMBOL(dw_mci_probe); 2119 2120 void dw_mci_remove(struct dw_mci *host) 2121 { 2122 int i; 2123 2124 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2125 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 2126 2127 for (i = 0; i < host->num_slots; i++) { 2128 dev_dbg(&host->dev, "remove slot %d\n", i); 2129 if (host->slot[i]) 2130 dw_mci_cleanup_slot(host->slot[i], i); 2131 } 2132 2133 /* disable clock to CIU */ 2134 mci_writel(host, CLKENA, 0); 2135 mci_writel(host, CLKSRC, 0); 2136 2137 free_irq(host->irq, host); 2138 destroy_workqueue(host->card_workqueue); 2139 dma_free_coherent(&host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 2140 2141 if (host->use_dma && host->dma_ops->exit) 2142 host->dma_ops->exit(host); 2143 2144 if (host->vmmc) { 2145 regulator_disable(host->vmmc); 2146 regulator_put(host->vmmc); 2147 } 2148 2149 } 2150 EXPORT_SYMBOL(dw_mci_remove); 2151 2152 2153 2154 #ifdef CONFIG_PM_SLEEP 2155 /* 2156 * TODO: we should probably disable the clock to the card in the suspend path. 2157 */ 2158 int dw_mci_suspend(struct dw_mci *host) 2159 { 2160 int i, ret = 0; 2161 2162 for (i = 0; i < host->num_slots; i++) { 2163 struct dw_mci_slot *slot = host->slot[i]; 2164 if (!slot) 2165 continue; 2166 ret = mmc_suspend_host(slot->mmc); 2167 if (ret < 0) { 2168 while (--i >= 0) { 2169 slot = host->slot[i]; 2170 if (slot) 2171 mmc_resume_host(host->slot[i]->mmc); 2172 } 2173 return ret; 2174 } 2175 } 2176 2177 if (host->vmmc) 2178 regulator_disable(host->vmmc); 2179 2180 return 0; 2181 } 2182 EXPORT_SYMBOL(dw_mci_suspend); 2183 2184 int dw_mci_resume(struct dw_mci *host) 2185 { 2186 int i, ret; 2187 2188 if (host->vmmc) 2189 regulator_enable(host->vmmc); 2190 2191 if (!mci_wait_reset(&host->dev, host)) { 2192 ret = -ENODEV; 2193 return ret; 2194 } 2195 2196 if (host->use_dma && host->dma_ops->init) 2197 host->dma_ops->init(host); 2198 2199 /* Restore the old value at FIFOTH register */ 2200 mci_writel(host, FIFOTH, host->fifoth_val); 2201 2202 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2203 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2204 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2205 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2206 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2207 2208 for (i = 0; i < host->num_slots; i++) { 2209 struct dw_mci_slot *slot = host->slot[i]; 2210 if (!slot) 2211 continue; 2212 ret = mmc_resume_host(host->slot[i]->mmc); 2213 if (ret < 0) 2214 return ret; 2215 } 2216 return 0; 2217 } 2218 EXPORT_SYMBOL(dw_mci_resume); 2219 #endif /* CONFIG_PM_SLEEP */ 2220 2221 static int __init dw_mci_init(void) 2222 { 2223 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver"); 2224 return 0; 2225 } 2226 2227 static void __exit dw_mci_exit(void) 2228 { 2229 } 2230 2231 module_init(dw_mci_init); 2232 module_exit(dw_mci_exit); 2233 2234 MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 2235 MODULE_AUTHOR("NXP Semiconductor VietNam"); 2236 MODULE_AUTHOR("Imagination Technologies Ltd"); 2237 MODULE_LICENSE("GPL v2"); 2238